* [PATCH 2/4] drm/i915: Extract skl_set_pipe_chicken()
2019-02-04 18:45 [PATCH 1/4] drm/i915: Fix wm latency==0 disable on skl+ Ville Syrjala
@ 2019-02-04 18:45 ` Ville Syrjala
2019-02-04 20:21 ` [PATCH v2 2/4] drm/i915: Extract icl_set_pipe_chicken() Ville Syrjala
2019-02-04 18:45 ` [PATCH 3/4] drm/i915: Setup PIPE_CHICKEN for fastsets too Ville Syrjala
` (9 subsequent siblings)
10 siblings, 1 reply; 24+ messages in thread
From: Ville Syrjala @ 2019-02-04 18:45 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We need configure PIPE_CHICKEN during fastboot as well. Let's extract
it to a helper.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 32 ++++++++++++++++++----------
1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index df7a7a310f2f..2c867a93903d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3896,6 +3896,25 @@ void intel_finish_reset(struct drm_i915_private *dev_priv)
clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
}
+static void skl_set_pipe_chicken(struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ u32 tmp;
+
+ tmp = I915_READ(PIPE_CHICKEN(pipe));
+
+ /*
+ * Display WA #1153: icl
+ * enable hardware to bypass the alpha math
+ * and rounding for per-pixel values 00 and 0xff
+ */
+ if (INTEL_GEN(dev_priv) >= 11)
+ tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
+
+ I915_WRITE(PIPE_CHICKEN(pipe), tmp);
+}
+
static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
@@ -5782,7 +5801,6 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
struct intel_atomic_state *old_intel_state =
to_intel_atomic_state(old_state);
bool psl_clkgate_wa;
- u32 pipe_chicken;
if (WARN_ON(intel_crtc->active))
return;
@@ -5839,16 +5857,8 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
*/
intel_color_load_luts(pipe_config);
- /*
- * Display WA #1153: enable hardware to bypass the alpha math
- * and rounding for per-pixel values 00 and 0xff
- */
- if (INTEL_GEN(dev_priv) >= 11) {
- pipe_chicken = I915_READ(PIPE_CHICKEN(pipe));
- if (!(pipe_chicken & PER_PIXEL_ALPHA_BYPASS_EN))
- I915_WRITE_FW(PIPE_CHICKEN(pipe),
- pipe_chicken | PER_PIXEL_ALPHA_BYPASS_EN);
- }
+ if (INTEL_GEN(dev_priv) >= 9)
+ skl_set_pipe_chicken(intel_crtc);
intel_ddi_set_pipe_settings(pipe_config);
if (!transcoder_is_dsi(cpu_transcoder))
--
2.19.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v2 2/4] drm/i915: Extract icl_set_pipe_chicken()
2019-02-04 18:45 ` [PATCH 2/4] drm/i915: Extract skl_set_pipe_chicken() Ville Syrjala
@ 2019-02-04 20:21 ` Ville Syrjala
2019-02-04 23:28 ` Matt Roper
0 siblings, 1 reply; 24+ messages in thread
From: Ville Syrjala @ 2019-02-04 20:21 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We need configure PIPE_CHICKEN during fastboot as well. Let's extract
it to a helper.
v2: Apparently PIPE_CHICKEN is icl+ only
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 31 ++++++++++++++++++----------
1 file changed, 20 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index df7a7a310f2f..4087d54ea943 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3896,6 +3896,24 @@ void intel_finish_reset(struct drm_i915_private *dev_priv)
clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
}
+static void icl_set_pipe_chicken(struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ u32 tmp;
+
+ tmp = I915_READ(PIPE_CHICKEN(pipe));
+
+ /*
+ * Display WA #1153: icl
+ * enable hardware to bypass the alpha math
+ * and rounding for per-pixel values 00 and 0xff
+ */
+ tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
+
+ I915_WRITE(PIPE_CHICKEN(pipe), tmp);
+}
+
static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
@@ -5782,7 +5800,6 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
struct intel_atomic_state *old_intel_state =
to_intel_atomic_state(old_state);
bool psl_clkgate_wa;
- u32 pipe_chicken;
if (WARN_ON(intel_crtc->active))
return;
@@ -5839,16 +5856,8 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
*/
intel_color_load_luts(pipe_config);
- /*
- * Display WA #1153: enable hardware to bypass the alpha math
- * and rounding for per-pixel values 00 and 0xff
- */
- if (INTEL_GEN(dev_priv) >= 11) {
- pipe_chicken = I915_READ(PIPE_CHICKEN(pipe));
- if (!(pipe_chicken & PER_PIXEL_ALPHA_BYPASS_EN))
- I915_WRITE_FW(PIPE_CHICKEN(pipe),
- pipe_chicken | PER_PIXEL_ALPHA_BYPASS_EN);
- }
+ if (INTEL_GEN(dev_priv) >= 11)
+ icl_set_pipe_chicken(intel_crtc);
intel_ddi_set_pipe_settings(pipe_config);
if (!transcoder_is_dsi(cpu_transcoder))
--
2.19.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH v2 2/4] drm/i915: Extract icl_set_pipe_chicken()
2019-02-04 20:21 ` [PATCH v2 2/4] drm/i915: Extract icl_set_pipe_chicken() Ville Syrjala
@ 2019-02-04 23:28 ` Matt Roper
0 siblings, 0 replies; 24+ messages in thread
From: Matt Roper @ 2019-02-04 23:28 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Mon, Feb 04, 2019 at 10:21:39PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We need configure PIPE_CHICKEN during fastboot as well. Let's extract
> it to a helper.
>
> v2: Apparently PIPE_CHICKEN is icl+ only
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 31 ++++++++++++++++++----------
> 1 file changed, 20 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index df7a7a310f2f..4087d54ea943 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3896,6 +3896,24 @@ void intel_finish_reset(struct drm_i915_private *dev_priv)
> clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
> }
>
> +static void icl_set_pipe_chicken(struct intel_crtc *crtc)
> +{
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
> + u32 tmp;
> +
> + tmp = I915_READ(PIPE_CHICKEN(pipe));
> +
> + /*
> + * Display WA #1153: icl
> + * enable hardware to bypass the alpha math
> + * and rounding for per-pixel values 00 and 0xff
> + */
> + tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
> +
> + I915_WRITE(PIPE_CHICKEN(pipe), tmp);
> +}
> +
> static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state,
> const struct intel_crtc_state *new_crtc_state)
> {
> @@ -5782,7 +5800,6 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> struct intel_atomic_state *old_intel_state =
> to_intel_atomic_state(old_state);
> bool psl_clkgate_wa;
> - u32 pipe_chicken;
>
> if (WARN_ON(intel_crtc->active))
> return;
> @@ -5839,16 +5856,8 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> */
> intel_color_load_luts(pipe_config);
>
> - /*
> - * Display WA #1153: enable hardware to bypass the alpha math
> - * and rounding for per-pixel values 00 and 0xff
> - */
> - if (INTEL_GEN(dev_priv) >= 11) {
> - pipe_chicken = I915_READ(PIPE_CHICKEN(pipe));
> - if (!(pipe_chicken & PER_PIXEL_ALPHA_BYPASS_EN))
> - I915_WRITE_FW(PIPE_CHICKEN(pipe),
> - pipe_chicken | PER_PIXEL_ALPHA_BYPASS_EN);
> - }
> + if (INTEL_GEN(dev_priv) >= 11)
> + icl_set_pipe_chicken(intel_crtc);
>
> intel_ddi_set_pipe_settings(pipe_config);
> if (!transcoder_is_dsi(cpu_transcoder))
> --
> 2.19.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 3/4] drm/i915: Setup PIPE_CHICKEN for fastsets too
2019-02-04 18:45 [PATCH 1/4] drm/i915: Fix wm latency==0 disable on skl+ Ville Syrjala
2019-02-04 18:45 ` [PATCH 2/4] drm/i915: Extract skl_set_pipe_chicken() Ville Syrjala
@ 2019-02-04 18:45 ` Ville Syrjala
2019-02-04 20:22 ` [PATCH v2 " Ville Syrjala
2019-02-04 18:45 ` [PATCH 4/4] drm/i915: W/A for underruns with WM1+ disabled on icl Ville Syrjala
` (8 subsequent siblings)
10 siblings, 1 reply; 24+ messages in thread
From: Ville Syrjala @ 2019-02-04 18:45 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Configure PIPE_CHICKEN during intel_update_pipe_config() to make
sure we have our chickens in a row with fastboot too.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2c867a93903d..5df035fce2d0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3959,6 +3959,9 @@ static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_sta
I915_WRITE(SKL_BOTTOM_COLOR(crtc->pipe),
SKL_BOTTOM_COLOR_GAMMA_ENABLE |
SKL_BOTTOM_COLOR_CSC_ENABLE);
+
+ if (INTEL_GEN(dev_priv) >= 9)
+ skl_set_pipe_chicken(crtc);
}
static void intel_fdi_normal_train(struct intel_crtc *crtc)
--
2.19.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v2 3/4] drm/i915: Setup PIPE_CHICKEN for fastsets too
2019-02-04 18:45 ` [PATCH 3/4] drm/i915: Setup PIPE_CHICKEN for fastsets too Ville Syrjala
@ 2019-02-04 20:22 ` Ville Syrjala
2019-02-04 23:28 ` Matt Roper
2019-02-05 11:21 ` Maarten Lankhorst
0 siblings, 2 replies; 24+ messages in thread
From: Ville Syrjala @ 2019-02-04 20:22 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Configure PIPE_CHICKEN during intel_update_pipe_config() to make
sure we have our chickens in a row with fastboot too.
v2: Apparently PIPE_CHICKEN is icl+ only
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4087d54ea943..5b9b9791d290 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3958,6 +3958,9 @@ static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_sta
I915_WRITE(SKL_BOTTOM_COLOR(crtc->pipe),
SKL_BOTTOM_COLOR_GAMMA_ENABLE |
SKL_BOTTOM_COLOR_CSC_ENABLE);
+
+ if (INTEL_GEN(dev_priv) >= 11)
+ icl_set_pipe_chicken(crtc);
}
static void intel_fdi_normal_train(struct intel_crtc *crtc)
--
2.19.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v2 3/4] drm/i915: Setup PIPE_CHICKEN for fastsets too
2019-02-04 20:22 ` [PATCH v2 " Ville Syrjala
@ 2019-02-04 23:28 ` Matt Roper
2019-02-05 11:21 ` Maarten Lankhorst
1 sibling, 0 replies; 24+ messages in thread
From: Matt Roper @ 2019-02-04 23:28 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Mon, Feb 04, 2019 at 10:22:14PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Configure PIPE_CHICKEN during intel_update_pipe_config() to make
> sure we have our chickens in a row with fastboot too.
>
> v2: Apparently PIPE_CHICKEN is icl+ only
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 4087d54ea943..5b9b9791d290 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3958,6 +3958,9 @@ static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_sta
> I915_WRITE(SKL_BOTTOM_COLOR(crtc->pipe),
> SKL_BOTTOM_COLOR_GAMMA_ENABLE |
> SKL_BOTTOM_COLOR_CSC_ENABLE);
> +
> + if (INTEL_GEN(dev_priv) >= 11)
> + icl_set_pipe_chicken(crtc);
> }
>
> static void intel_fdi_normal_train(struct intel_crtc *crtc)
> --
> 2.19.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 3/4] drm/i915: Setup PIPE_CHICKEN for fastsets too
2019-02-04 20:22 ` [PATCH v2 " Ville Syrjala
2019-02-04 23:28 ` Matt Roper
@ 2019-02-05 11:21 ` Maarten Lankhorst
2019-02-05 13:39 ` Ville Syrjälä
1 sibling, 1 reply; 24+ messages in thread
From: Maarten Lankhorst @ 2019-02-05 11:21 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
Op 04-02-2019 om 21:22 schreef Ville Syrjala:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Configure PIPE_CHICKEN during intel_update_pipe_config() to make
> sure we have our chickens in a row with fastboot too.
>
> v2: Apparently PIPE_CHICKEN is icl+ only
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 4087d54ea943..5b9b9791d290 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3958,6 +3958,9 @@ static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_sta
> I915_WRITE(SKL_BOTTOM_COLOR(crtc->pipe),
> SKL_BOTTOM_COLOR_GAMMA_ENABLE |
> SKL_BOTTOM_COLOR_CSC_ENABLE);
> +
> + if (INTEL_GEN(dev_priv) >= 11)
> + icl_set_pipe_chicken(crtc);
> }
>
> static void intel_fdi_normal_train(struct intel_crtc *crtc)
Could we set it on the initial watermark sanitization pass somehow? In case userspace doesn't bother setting a mode?
During atomic check we test for distrust_bios_wm, but unfortunately it's cleared before the state is committed to hw.
Hmm there's intel_initial_commit, but that wouldn't work for the s4 resume path..
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 3/4] drm/i915: Setup PIPE_CHICKEN for fastsets too
2019-02-05 11:21 ` Maarten Lankhorst
@ 2019-02-05 13:39 ` Ville Syrjälä
2019-02-05 14:49 ` Maarten Lankhorst
0 siblings, 1 reply; 24+ messages in thread
From: Ville Syrjälä @ 2019-02-05 13:39 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
On Tue, Feb 05, 2019 at 12:21:19PM +0100, Maarten Lankhorst wrote:
> Op 04-02-2019 om 21:22 schreef Ville Syrjala:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Configure PIPE_CHICKEN during intel_update_pipe_config() to make
> > sure we have our chickens in a row with fastboot too.
> >
> > v2: Apparently PIPE_CHICKEN is icl+ only
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 4087d54ea943..5b9b9791d290 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3958,6 +3958,9 @@ static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_sta
> > I915_WRITE(SKL_BOTTOM_COLOR(crtc->pipe),
> > SKL_BOTTOM_COLOR_GAMMA_ENABLE |
> > SKL_BOTTOM_COLOR_CSC_ENABLE);
> > +
> > + if (INTEL_GEN(dev_priv) >= 11)
> > + icl_set_pipe_chicken(crtc);
> > }
> >
> > static void intel_fdi_normal_train(struct intel_crtc *crtc)
>
> Could we set it on the initial watermark sanitization pass somehow? In case userspace doesn't bother setting a mode?
>
> During atomic check we test for distrust_bios_wm, but unfortunately it's cleared before the state is committed to hw.
>
> Hmm there's intel_initial_commit, but that wouldn't work for the s4 resume path..
I think we should just force update_pipe=true for the first commit after
readout. That should fix up everything (tm).
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 3/4] drm/i915: Setup PIPE_CHICKEN for fastsets too
2019-02-05 13:39 ` Ville Syrjälä
@ 2019-02-05 14:49 ` Maarten Lankhorst
2019-02-05 18:30 ` Ville Syrjälä
0 siblings, 1 reply; 24+ messages in thread
From: Maarten Lankhorst @ 2019-02-05 14:49 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
Op 05-02-2019 om 14:39 schreef Ville Syrjälä:
> On Tue, Feb 05, 2019 at 12:21:19PM +0100, Maarten Lankhorst wrote:
>> Op 04-02-2019 om 21:22 schreef Ville Syrjala:
>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>
>>> Configure PIPE_CHICKEN during intel_update_pipe_config() to make
>>> sure we have our chickens in a row with fastboot too.
>>>
>>> v2: Apparently PIPE_CHICKEN is icl+ only
>>>
>>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>> ---
>>> drivers/gpu/drm/i915/intel_display.c | 3 +++
>>> 1 file changed, 3 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>>> index 4087d54ea943..5b9b9791d290 100644
>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>> @@ -3958,6 +3958,9 @@ static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_sta
>>> I915_WRITE(SKL_BOTTOM_COLOR(crtc->pipe),
>>> SKL_BOTTOM_COLOR_GAMMA_ENABLE |
>>> SKL_BOTTOM_COLOR_CSC_ENABLE);
>>> +
>>> + if (INTEL_GEN(dev_priv) >= 11)
>>> + icl_set_pipe_chicken(crtc);
>>> }
>>>
>>> static void intel_fdi_normal_train(struct intel_crtc *crtc)
>> Could we set it on the initial watermark sanitization pass somehow? In case userspace doesn't bother setting a mode?
>>
>> During atomic check we test for distrust_bios_wm, but unfortunately it's cleared before the state is committed to hw.
>>
>> Hmm there's intel_initial_commit, but that wouldn't work for the s4 resume path..
> I think we should just force update_pipe=true for the first commit after
> readout. That should fix up everything (tm).
>
Hmm, resume should already do that by downgrading the modeset if possible.
We could perhaps do it from intel_initial_commit() ?
~Maarten
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v2 3/4] drm/i915: Setup PIPE_CHICKEN for fastsets too
2019-02-05 14:49 ` Maarten Lankhorst
@ 2019-02-05 18:30 ` Ville Syrjälä
0 siblings, 0 replies; 24+ messages in thread
From: Ville Syrjälä @ 2019-02-05 18:30 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
On Tue, Feb 05, 2019 at 03:49:42PM +0100, Maarten Lankhorst wrote:
> Op 05-02-2019 om 14:39 schreef Ville Syrjälä:
> > On Tue, Feb 05, 2019 at 12:21:19PM +0100, Maarten Lankhorst wrote:
> >> Op 04-02-2019 om 21:22 schreef Ville Syrjala:
> >>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>>
> >>> Configure PIPE_CHICKEN during intel_update_pipe_config() to make
> >>> sure we have our chickens in a row with fastboot too.
> >>>
> >>> v2: Apparently PIPE_CHICKEN is icl+ only
> >>>
> >>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>> ---
> >>> drivers/gpu/drm/i915/intel_display.c | 3 +++
> >>> 1 file changed, 3 insertions(+)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> >>> index 4087d54ea943..5b9b9791d290 100644
> >>> --- a/drivers/gpu/drm/i915/intel_display.c
> >>> +++ b/drivers/gpu/drm/i915/intel_display.c
> >>> @@ -3958,6 +3958,9 @@ static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_sta
> >>> I915_WRITE(SKL_BOTTOM_COLOR(crtc->pipe),
> >>> SKL_BOTTOM_COLOR_GAMMA_ENABLE |
> >>> SKL_BOTTOM_COLOR_CSC_ENABLE);
> >>> +
> >>> + if (INTEL_GEN(dev_priv) >= 11)
> >>> + icl_set_pipe_chicken(crtc);
> >>> }
> >>>
> >>> static void intel_fdi_normal_train(struct intel_crtc *crtc)
> >> Could we set it on the initial watermark sanitization pass somehow? In case userspace doesn't bother setting a mode?
> >>
> >> During atomic check we test for distrust_bios_wm, but unfortunately it's cleared before the state is committed to hw.
> >>
> >> Hmm there's intel_initial_commit, but that wouldn't work for the s4 resume path..
> > I think we should just force update_pipe=true for the first commit after
> > readout. That should fix up everything (tm).
> >
> Hmm, resume should already do that by downgrading the modeset if possible.
>
> We could perhaps do it from intel_initial_commit() ?
Eventually I'd like to remove intel_initial_commit() again and replace
it will more full fledged readout. But in the meantime that would work
I suppose.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 4/4] drm/i915: W/A for underruns with WM1+ disabled on icl
2019-02-04 18:45 [PATCH 1/4] drm/i915: Fix wm latency==0 disable on skl+ Ville Syrjala
2019-02-04 18:45 ` [PATCH 2/4] drm/i915: Extract skl_set_pipe_chicken() Ville Syrjala
2019-02-04 18:45 ` [PATCH 3/4] drm/i915: Setup PIPE_CHICKEN for fastsets too Ville Syrjala
@ 2019-02-04 18:45 ` Ville Syrjala
2019-02-04 20:22 ` [PATCH v2 " Ville Syrjala
2019-02-04 19:22 ` ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915: Fix wm latency==0 disable on skl+ Patchwork
` (7 subsequent siblings)
10 siblings, 1 reply; 24+ messages in thread
From: Ville Syrjala @ 2019-02-04 18:45 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Disabling WM1+ on ICL causes tons of underruns with
linear/X-tiled framebuffers. We can avoid this by flipping
on a chicken bit affecting the way the hw fill the FIFO.
This may not be the final solution but should hopefully
avoid some underruns in the meantime.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 7 +++++++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ede54fdc1676..12964b0fbc54 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7618,6 +7618,7 @@ enum {
#define _PIPEB_CHICKEN 0x71038
#define _PIPEC_CHICKEN 0x72038
#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7)
+#define PM_FILL_MAINTAIN_DBUF_FULLNESS (1 << 0)
#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
_PIPEB_CHICKEN)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5df035fce2d0..c5d5309ff789 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3912,6 +3912,13 @@ static void skl_set_pipe_chicken(struct intel_crtc *crtc)
if (INTEL_GEN(dev_priv) >= 11)
tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
+ /*
+ * W/A for underruns with linear/X-tiled with
+ * WM1+ disabled.
+ */
+ if (INTEL_GEN(dev_priv) >= 11)
+ tmp |= PM_FILL_MAINTAIN_DBUF_FULLNESS;
+
I915_WRITE(PIPE_CHICKEN(pipe), tmp);
}
--
2.19.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v2 4/4] drm/i915: W/A for underruns with WM1+ disabled on icl
2019-02-04 18:45 ` [PATCH 4/4] drm/i915: W/A for underruns with WM1+ disabled on icl Ville Syrjala
@ 2019-02-04 20:22 ` Ville Syrjala
2019-02-04 23:29 ` Matt Roper
0 siblings, 1 reply; 24+ messages in thread
From: Ville Syrjala @ 2019-02-04 20:22 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Disabling WM1+ on ICL causes tons of underruns with
linear/X-tiled framebuffers. We can avoid this by flipping
on a chicken bit affecting the way the hw fill the FIFO.
This may not be the final solution but should hopefully
avoid some underruns in the meantime.
v2: Apparently PIPE_CHICKEN is icl+ only
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 6 ++++++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ede54fdc1676..12964b0fbc54 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7618,6 +7618,7 @@ enum {
#define _PIPEB_CHICKEN 0x71038
#define _PIPEC_CHICKEN 0x72038
#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7)
+#define PM_FILL_MAINTAIN_DBUF_FULLNESS (1 << 0)
#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
_PIPEB_CHICKEN)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5b9b9791d290..b825ceed7f1d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3911,6 +3911,12 @@ static void icl_set_pipe_chicken(struct intel_crtc *crtc)
*/
tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
+ /*
+ * W/A for underruns with linear/X-tiled with
+ * WM1+ disabled.
+ */
+ tmp |= PM_FILL_MAINTAIN_DBUF_FULLNESS;
+
I915_WRITE(PIPE_CHICKEN(pipe), tmp);
}
--
2.19.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH v2 4/4] drm/i915: W/A for underruns with WM1+ disabled on icl
2019-02-04 20:22 ` [PATCH v2 " Ville Syrjala
@ 2019-02-04 23:29 ` Matt Roper
0 siblings, 0 replies; 24+ messages in thread
From: Matt Roper @ 2019-02-04 23:29 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Mon, Feb 04, 2019 at 10:22:32PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Disabling WM1+ on ICL causes tons of underruns with
> linear/X-tiled framebuffers. We can avoid this by flipping
> on a chicken bit affecting the way the hw fill the FIFO.
> This may not be the final solution but should hopefully
> avoid some underruns in the meantime.
>
> v2: Apparently PIPE_CHICKEN is icl+ only
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
I can't speak for what this register actually does, but your patch
accurately implements the recommendation from the hardware guys, so
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_display.c | 6 ++++++
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ede54fdc1676..12964b0fbc54 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7618,6 +7618,7 @@ enum {
> #define _PIPEB_CHICKEN 0x71038
> #define _PIPEC_CHICKEN 0x72038
> #define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7)
> +#define PM_FILL_MAINTAIN_DBUF_FULLNESS (1 << 0)
> #define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
> _PIPEB_CHICKEN)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 5b9b9791d290..b825ceed7f1d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3911,6 +3911,12 @@ static void icl_set_pipe_chicken(struct intel_crtc *crtc)
> */
> tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
>
> + /*
> + * W/A for underruns with linear/X-tiled with
> + * WM1+ disabled.
> + */
> + tmp |= PM_FILL_MAINTAIN_DBUF_FULLNESS;
> +
> I915_WRITE(PIPE_CHICKEN(pipe), tmp);
> }
>
> --
> 2.19.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915: Fix wm latency==0 disable on skl+
2019-02-04 18:45 [PATCH 1/4] drm/i915: Fix wm latency==0 disable on skl+ Ville Syrjala
` (2 preceding siblings ...)
2019-02-04 18:45 ` [PATCH 4/4] drm/i915: W/A for underruns with WM1+ disabled on icl Ville Syrjala
@ 2019-02-04 19:22 ` Patchwork
2019-02-04 21:08 ` ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Fix wm latency==0 disable on skl+ (rev4) Patchwork
` (6 subsequent siblings)
10 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2019-02-04 19:22 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm/i915: Fix wm latency==0 disable on skl+
URL : https://patchwork.freedesktop.org/series/56199/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5536 -> Patchwork_12129
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_12129 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12129, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/56199/revisions/1/mbox/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_12129:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_suspend@basic-s3:
- fi-skl-6770hq: PASS -> DMESG-WARN
- fi-cfl-8109u: PASS -> DMESG-WARN
- fi-skl-6260u: PASS -> DMESG-WARN
- fi-cfl-guc: PASS -> DMESG-WARN
- fi-kbl-7567u: PASS -> DMESG-WARN
- fi-skl-guc: PASS -> DMESG-WARN
- fi-glk-j4005: PASS -> DMESG-WARN
- fi-kbl-x1275: PASS -> DMESG-WARN
- fi-cfl-8700k: PASS -> DMESG-WARN
- fi-kbl-7500u: PASS -> DMESG-WARN
- fi-skl-gvtdvm: PASS -> DMESG-WARN
- fi-bxt-j4205: PASS -> DMESG-WARN
- fi-skl-6700k2: PASS -> DMESG-WARN
- fi-apl-guc: PASS -> DMESG-WARN
* igt@gem_exec_suspend@basic-s4-devices:
- fi-skl-iommu: PASS -> DMESG-WARN
- fi-skl-6700hq: PASS -> DMESG-WARN
- fi-skl-6600u: PASS -> DMESG-WARN
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_basic@basic-blt:
- {fi-whl-u}: PASS -> INCOMPLETE
* igt@gem_exec_suspend@basic-s3:
- {fi-whl-u}: PASS -> DMESG-WARN
* {igt@runner@aborted}:
- fi-bxt-j4205: NOTRUN -> FAIL
- {fi-whl-u}: NOTRUN -> FAIL
Known issues
------------
Here are the changes found in Patchwork_12129 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s4-devices:
- fi-kbl-r: PASS -> DMESG-WARN [fdo#107139]
- fi-kbl-7560u: PASS -> DMESG-WARN [fdo#107139]
* igt@i915_module_load@reload:
- fi-blb-e6850: NOTRUN -> INCOMPLETE [fdo#107718]
* igt@i915_selftest@live_evict:
- fi-bsw-kefka: PASS -> DMESG-WARN [fdo#107709]
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
* igt@prime_vgem@basic-fence-flip:
- fi-gdg-551: PASS -> DMESG-FAIL [fdo#103182]
#### Possible fixes ####
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: FAIL [fdo#103182] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
* igt@prime_vgem@basic-fence-flip:
- fi-ilk-650: FAIL [fdo#104008] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#104008]: https://bugs.freedesktop.org/show_bug.cgi?id=104008
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108654]: https://bugs.freedesktop.org/show_bug.cgi?id=108654
[fdo#108756]: https://bugs.freedesktop.org/show_bug.cgi?id=108756
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109383]: https://bugs.freedesktop.org/show_bug.cgi?id=109383
[k.org#201919]: https://bugzilla.kernel.org/show_bug.cgi?id=201919
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (46 -> 44)
------------------------------
Additional (2): fi-byt-j1900 fi-pnv-d510
Missing (4): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
Build changes
-------------
* Linux: CI_DRM_5536 -> Patchwork_12129
CI_DRM_5536: 0a5caf6e62fb99d027b3e6af226abb47be732f15 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4805: cb6610f5a91a08b1d7f8ae910875891003c6f67c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12129: 4b8ca9ecbade242ef033f7d5e39abd865ef22387 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4b8ca9ecbade drm/i915: W/A for underruns with WM1+ disabled on icl
421d5cb064d5 drm/i915: Setup PIPE_CHICKEN for fastsets too
80919556ec88 drm/i915: Extract skl_set_pipe_chicken()
12750c0ded8f drm/i915: Fix wm latency==0 disable on skl+
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12129/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread* ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Fix wm latency==0 disable on skl+ (rev4)
2019-02-04 18:45 [PATCH 1/4] drm/i915: Fix wm latency==0 disable on skl+ Ville Syrjala
` (3 preceding siblings ...)
2019-02-04 19:22 ` ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915: Fix wm latency==0 disable on skl+ Patchwork
@ 2019-02-04 21:08 ` Patchwork
2019-02-04 21:58 ` ✓ Fi.CI.IGT: " Patchwork
` (5 subsequent siblings)
10 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2019-02-04 21:08 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm/i915: Fix wm latency==0 disable on skl+ (rev4)
URL : https://patchwork.freedesktop.org/series/56199/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5536 -> Patchwork_12130
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/56199/revisions/4/mbox/
Known issues
------------
Here are the changes found in Patchwork_12130 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
#### Possible fixes ####
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: FAIL [fdo#103182] -> PASS +1
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: FAIL [fdo#109485] -> PASS
* igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence:
- fi-skl-guc: FAIL [fdo#103191] / [fdo#107362] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
* igt@prime_vgem@basic-fence-flip:
- fi-ilk-650: FAIL [fdo#104008] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#104008]: https://bugs.freedesktop.org/show_bug.cgi?id=104008
[fdo#105998]: https://bugs.freedesktop.org/show_bug.cgi?id=105998
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#109527]: https://bugs.freedesktop.org/show_bug.cgi?id=109527
[fdo#109528]: https://bugs.freedesktop.org/show_bug.cgi?id=109528
[fdo#109530]: https://bugs.freedesktop.org/show_bug.cgi?id=109530
Participating hosts (46 -> 44)
------------------------------
Additional (3): fi-icl-y fi-byt-j1900 fi-pnv-d510
Missing (5): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-kbl-7560u
Build changes
-------------
* Linux: CI_DRM_5536 -> Patchwork_12130
CI_DRM_5536: 0a5caf6e62fb99d027b3e6af226abb47be732f15 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4805: cb6610f5a91a08b1d7f8ae910875891003c6f67c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12130: 842b6e3123756d29c2f40e30ca1e38c0b6a0bd9e @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
842b6e312375 drm/i915: W/A for underruns with WM1+ disabled on icl
f14a675def45 drm/i915: Setup PIPE_CHICKEN for fastsets too
65fdbc2fb2d3 drm/i915: Extract icl_set_pipe_chicken()
b157cc17b7f0 drm/i915: Fix wm latency==0 disable on skl+
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12130/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread* ✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915: Fix wm latency==0 disable on skl+ (rev4)
2019-02-04 18:45 [PATCH 1/4] drm/i915: Fix wm latency==0 disable on skl+ Ville Syrjala
` (4 preceding siblings ...)
2019-02-04 21:08 ` ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Fix wm latency==0 disable on skl+ (rev4) Patchwork
@ 2019-02-04 21:58 ` Patchwork
2019-02-04 23:07 ` [PATCH 1/4] drm/i915: Fix wm latency==0 disable on skl+ Matt Roper
` (4 subsequent siblings)
10 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2019-02-04 21:58 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm/i915: Fix wm latency==0 disable on skl+ (rev4)
URL : https://patchwork.freedesktop.org/series/56199/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5536_full -> Patchwork_12130_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_12130_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_schedule@pi-ringfull-blt:
- shard-kbl: NOTRUN -> FAIL [fdo#103158]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- shard-apl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
- shard-apl: PASS -> FAIL [fdo#106510] / [fdo#108145]
* igt@kms_color@pipe-b-legacy-gamma:
- shard-apl: PASS -> FAIL [fdo#104782]
* igt@kms_cursor_crc@cursor-256x256-sliding:
- shard-glk: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-64x64-dpms:
- shard-apl: PASS -> FAIL [fdo#103232] +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-apl: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
- shard-glk: PASS -> FAIL [fdo#103167] +1
* igt@kms_plane@pixel-format-pipe-b-planes:
- shard-apl: PASS -> FAIL [fdo#103166] +1
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-kbl: NOTRUN -> FAIL [fdo#108145] / [fdo#108590]
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-apl: NOTRUN -> FAIL [fdo#108145] +1
* igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
- shard-glk: PASS -> FAIL [fdo#103166] +1
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-hsw: PASS -> FAIL [fdo#104894]
* igt@perf@blocking:
- shard-hsw: PASS -> FAIL [fdo#102252]
#### Possible fixes ####
* igt@gem_pwrite_pread@uncached-copy-performance:
- shard-apl: INCOMPLETE [fdo#103927] -> PASS
* igt@kms_cursor_crc@cursor-128x128-random:
- shard-apl: FAIL [fdo#103232] -> PASS +1
* igt@kms_cursor_crc@cursor-128x42-sliding:
- shard-glk: FAIL [fdo#103232] -> PASS
* igt@kms_cursor_crc@cursor-256x256-suspend:
- shard-apl: FAIL [fdo#103191] / [fdo#103232] -> PASS
* igt@kms_flip@basic-flip-vs-dpms:
- shard-kbl: DMESG-WARN [fdo#103313] / [fdo#105345] / [fdo#108473] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite:
- shard-apl: FAIL [fdo#103167] -> PASS +2
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt:
- shard-glk: FAIL [fdo#103167] -> PASS +1
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-glk: FAIL [fdo#108145] -> PASS
* igt@kms_setmode@basic:
- shard-apl: FAIL [fdo#99912] -> PASS
- shard-kbl: FAIL [fdo#99912] -> PASS
* igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
- shard-snb: INCOMPLETE [fdo#105411] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102252]: https://bugs.freedesktop.org/show_bug.cgi?id=102252
[fdo#103158]: https://bugs.freedesktop.org/show_bug.cgi?id=103158
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103313]: https://bugs.freedesktop.org/show_bug.cgi?id=103313
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
[fdo#105345]: https://bugs.freedesktop.org/show_bug.cgi?id=105345
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#106510]: https://bugs.freedesktop.org/show_bug.cgi?id=106510
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108473]: https://bugs.freedesktop.org/show_bug.cgi?id=108473
[fdo#108590]: https://bugs.freedesktop.org/show_bug.cgi?id=108590
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (7 -> 5)
------------------------------
Missing (2): shard-skl shard-iclb
Build changes
-------------
* Linux: CI_DRM_5536 -> Patchwork_12130
CI_DRM_5536: 0a5caf6e62fb99d027b3e6af226abb47be732f15 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4805: cb6610f5a91a08b1d7f8ae910875891003c6f67c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12130: 842b6e3123756d29c2f40e30ca1e38c0b6a0bd9e @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12130/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH 1/4] drm/i915: Fix wm latency==0 disable on skl+
2019-02-04 18:45 [PATCH 1/4] drm/i915: Fix wm latency==0 disable on skl+ Ville Syrjala
` (5 preceding siblings ...)
2019-02-04 21:58 ` ✓ Fi.CI.IGT: " Patchwork
@ 2019-02-04 23:07 ` Matt Roper
2019-02-05 13:35 ` Ville Syrjälä
2019-02-05 13:42 ` [PATCH v2 " Ville Syrjala
` (3 subsequent siblings)
10 siblings, 1 reply; 24+ messages in thread
From: Matt Roper @ 2019-02-04 23:07 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Mon, Feb 04, 2019 at 08:45:20PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> When adding the early latency==0 check back I neglected to
> realize that we no longer have a way to return a failure
> from the wm computation like we had in the past (since we
> now calculate wms before ddb allocations). Also plane_en
> being false doesn't actually indicate that the level is
> invalid as it wil also happen when the plane is not
> enabled.
>
> skl_allocate_pipe_ddb() starts scanning from the maximum
> watermark level and it stops as soon as it finds a level
> that is deemed viable. The assumption being that if level
> n+1 is valid then level n is valid as well. Thus if we
> now disable any watermark level by zeroing its latency
> the code will think that level to be actually valid
> and won't confirm whether the actually enabled lower
> watermark level(s) actually fit into the allotted ddb
> space. This results in hilarious watermark values that
> exceed the ddb allocation of the plane.
>
> The way we must now indicate a failure is to assign an
> unreasoanbly big value to min_ddb_alloc which will then
> make skl_allocate_pipe_ddb() reject the entire level.
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Similarly, isn't the
if (res_lines > 31)
return;
farther down the function going to also cause a problem? If we fail the
line requirement then result->min_ddb_alloc and such never get set for
this plane, which screws up the block sum at block allocation time.
Matt
> ---
> drivers/gpu/drm/i915/intel_pm.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ed9786241307..d6186c90bc10 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4694,8 +4694,11 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *cstate,
> uint_fixed_16_16_t selected_result;
> u32 res_blocks, res_lines, min_ddb_alloc = 0;
>
> - if (latency == 0)
> + if (latency == 0) {
> + /* reject it */
> + result->min_ddb_alloc = U16_MAX;
> return;
> + }
>
> /* Display WA #1141: kbl,cfl */
> if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
> --
> 2.19.2
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH 1/4] drm/i915: Fix wm latency==0 disable on skl+
2019-02-04 23:07 ` [PATCH 1/4] drm/i915: Fix wm latency==0 disable on skl+ Matt Roper
@ 2019-02-05 13:35 ` Ville Syrjälä
0 siblings, 0 replies; 24+ messages in thread
From: Ville Syrjälä @ 2019-02-05 13:35 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On Mon, Feb 04, 2019 at 03:07:50PM -0800, Matt Roper wrote:
> On Mon, Feb 04, 2019 at 08:45:20PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > When adding the early latency==0 check back I neglected to
> > realize that we no longer have a way to return a failure
> > from the wm computation like we had in the past (since we
> > now calculate wms before ddb allocations). Also plane_en
> > being false doesn't actually indicate that the level is
> > invalid as it wil also happen when the plane is not
> > enabled.
> >
> > skl_allocate_pipe_ddb() starts scanning from the maximum
> > watermark level and it stops as soon as it finds a level
> > that is deemed viable. The assumption being that if level
> > n+1 is valid then level n is valid as well. Thus if we
> > now disable any watermark level by zeroing its latency
> > the code will think that level to be actually valid
> > and won't confirm whether the actually enabled lower
> > watermark level(s) actually fit into the allotted ddb
> > space. This results in hilarious watermark values that
> > exceed the ddb allocation of the plane.
> >
> > The way we must now indicate a failure is to assign an
> > unreasoanbly big value to min_ddb_alloc which will then
> > make skl_allocate_pipe_ddb() reject the entire level.
> >
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Similarly, isn't the
>
> if (res_lines > 31)
> return;
>
> farther down the function going to also cause a problem? If we fail the
> line requirement then result->min_ddb_alloc and such never get set for
> this plane, which screws up the block sum at block allocation time.
Hmm. Yes, that does seem to be the case. I'll respin.
>
>
> Matt
>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 5 ++++-
> > 1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index ed9786241307..d6186c90bc10 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4694,8 +4694,11 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *cstate,
> > uint_fixed_16_16_t selected_result;
> > u32 res_blocks, res_lines, min_ddb_alloc = 0;
> >
> > - if (latency == 0)
> > + if (latency == 0) {
> > + /* reject it */
> > + result->min_ddb_alloc = U16_MAX;
> > return;
> > + }
> >
> > /* Display WA #1141: kbl,cfl */
> > if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
> > --
> > 2.19.2
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> IoTG Platform Enabling & Development
> Intel Corporation
> (916) 356-2795
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v2 1/4] drm/i915: Fix wm latency==0 disable on skl+
2019-02-04 18:45 [PATCH 1/4] drm/i915: Fix wm latency==0 disable on skl+ Ville Syrjala
` (6 preceding siblings ...)
2019-02-04 23:07 ` [PATCH 1/4] drm/i915: Fix wm latency==0 disable on skl+ Matt Roper
@ 2019-02-05 13:42 ` Ville Syrjala
2019-02-05 15:32 ` Matt Roper
2019-02-05 15:50 ` [PATCH v3 " Ville Syrjala
` (2 subsequent siblings)
10 siblings, 1 reply; 24+ messages in thread
From: Ville Syrjala @ 2019-02-05 13:42 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
When adding the early latency==0 check back I neglected to
realize that we no longer have a way to return a failure
from the wm computation like we had in the past (since we
now calculate wms before ddb allocations). Also plane_en
being false doesn't actually indicate that the level is
invalid as it wil also happen when the plane is not
enabled.
skl_allocate_pipe_ddb() starts scanning from the maximum
watermark level and it stops as soon as it finds a level
that is deemed viable. The assumption being that if level
n+1 is valid then level n is valid as well. Thus if we
now disable any watermark level by zeroing its latency
the code will think that level to be actually valid
and won't confirm whether the actually enabled lower
watermark level(s) actually fit into the allotted ddb
space. This results in hilarious watermark values that
exceed the ddb allocation of the plane.
The way we must now indicate a failure is to assign an
unreasoanbly big value to min_ddb_alloc which will then
make skl_allocate_pipe_ddb() reject the entire level.
v2: Also do the same for the lines>31 case (Matt)
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ed9786241307..92b52bb634ad 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4694,8 +4694,11 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *cstate,
uint_fixed_16_16_t selected_result;
u32 res_blocks, res_lines, min_ddb_alloc = 0;
- if (latency == 0)
+ if (latency == 0) {
+ /* reject it */
+ result->min_ddb_alloc = U16_MAX;
return;
+ }
/* Display WA #1141: kbl,cfl */
if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
@@ -4783,8 +4786,11 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *cstate,
if (!skl_wm_has_lines(dev_priv, level))
res_lines = 0;
- if (res_lines > 31)
+ if (res_lines > 31) {
+ /* reject it */
+ result->min_ddb_alloc = U16_MAX;
return;
+ }
/*
* If res_lines is valid, assume we can use this watermark level
--
2.19.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH v2 1/4] drm/i915: Fix wm latency==0 disable on skl+
2019-02-05 13:42 ` [PATCH v2 " Ville Syrjala
@ 2019-02-05 15:32 ` Matt Roper
0 siblings, 0 replies; 24+ messages in thread
From: Matt Roper @ 2019-02-05 15:32 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Tue, Feb 05, 2019 at 03:42:13PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> When adding the early latency==0 check back I neglected to
> realize that we no longer have a way to return a failure
> from the wm computation like we had in the past (since we
> now calculate wms before ddb allocations). Also plane_en
> being false doesn't actually indicate that the level is
> invalid as it wil also happen when the plane is not
> enabled.
>
> skl_allocate_pipe_ddb() starts scanning from the maximum
> watermark level and it stops as soon as it finds a level
> that is deemed viable. The assumption being that if level
> n+1 is valid then level n is valid as well. Thus if we
> now disable any watermark level by zeroing its latency
> the code will think that level to be actually valid
> and won't confirm whether the actually enabled lower
> watermark level(s) actually fit into the allotted ddb
> space. This results in hilarious watermark values that
> exceed the ddb allocation of the plane.
>
> The way we must now indicate a failure is to assign an
> unreasoanbly big value to min_ddb_alloc which will then
> make skl_allocate_pipe_ddb() reject the entire level.
>
> v2: Also do the same for the lines>31 case (Matt)
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ed9786241307..92b52bb634ad 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4694,8 +4694,11 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *cstate,
> uint_fixed_16_16_t selected_result;
> u32 res_blocks, res_lines, min_ddb_alloc = 0;
>
> - if (latency == 0)
> + if (latency == 0) {
> + /* reject it */
> + result->min_ddb_alloc = U16_MAX;
> return;
> + }
>
> /* Display WA #1141: kbl,cfl */
> if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
> @@ -4783,8 +4786,11 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *cstate,
> if (!skl_wm_has_lines(dev_priv, level))
> res_lines = 0;
>
> - if (res_lines > 31)
> + if (res_lines > 31) {
> + /* reject it */
> + result->min_ddb_alloc = U16_MAX;
> return;
> + }
We might also want to change 'blocks' in skl_allocate_pipe_ddb() to a
u32 so that we don't just overflow our sum. It would be pretty easy for
U16_MAX + real val < alloc_size
given that 'blocks' is stored as a u16 currently.
Aside from that,
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
> /*
> * If res_lines is valid, assume we can use this watermark level
> --
> 2.19.2
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v3 1/4] drm/i915: Fix wm latency==0 disable on skl+
2019-02-04 18:45 [PATCH 1/4] drm/i915: Fix wm latency==0 disable on skl+ Ville Syrjala
` (7 preceding siblings ...)
2019-02-05 13:42 ` [PATCH v2 " Ville Syrjala
@ 2019-02-05 15:50 ` Ville Syrjala
2019-02-05 16:46 ` ✓ Fi.CI.BAT: success for series starting with [v3,1/4] drm/i915: Fix wm latency==0 disable on skl+ (rev6) Patchwork
2019-02-05 19:47 ` ✓ Fi.CI.IGT: " Patchwork
10 siblings, 0 replies; 24+ messages in thread
From: Ville Syrjala @ 2019-02-05 15:50 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
When adding the early latency==0 check back I neglected to
realize that we no longer have a way to return a failure
from the wm computation like we had in the past (since we
now calculate wms before ddb allocations). Also plane_en
being false doesn't actually indicate that the level is
invalid as it wil also happen when the plane is not
enabled.
skl_allocate_pipe_ddb() starts scanning from the maximum
watermark level and it stops as soon as it finds a level
that is deemed viable. The assumption being that if level
n+1 is valid then level n is valid as well. Thus if we
now disable any watermark level by zeroing its latency
the code will think that level to be actually valid
and won't confirm whether the actually enabled lower
watermark level(s) actually fit into the allotted ddb
space. This results in hilarious watermark values that
exceed the ddb allocation of the plane.
The way we must now indicate a failure is to assign an
unreasoanbly big value to min_ddb_alloc which will then
make skl_allocate_pipe_ddb() reject the entire level.
v2: Also do the same for the lines>31 case (Matt)
v3: Make 'blocks' u32 (Matt)
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ed9786241307..737005bf6816 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4319,7 +4319,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
int num_active;
u64 plane_data_rate[I915_MAX_PLANES] = {};
u64 uv_plane_data_rate[I915_MAX_PLANES] = {};
- u16 blocks = 0;
+ u32 blocks;
int level;
/* Clear the partitioning for disabled planes. */
@@ -4694,8 +4694,11 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *cstate,
uint_fixed_16_16_t selected_result;
u32 res_blocks, res_lines, min_ddb_alloc = 0;
- if (latency == 0)
+ if (latency == 0) {
+ /* reject it */
+ result->min_ddb_alloc = U16_MAX;
return;
+ }
/* Display WA #1141: kbl,cfl */
if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
@@ -4783,8 +4786,11 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *cstate,
if (!skl_wm_has_lines(dev_priv, level))
res_lines = 0;
- if (res_lines > 31)
+ if (res_lines > 31) {
+ /* reject it */
+ result->min_ddb_alloc = U16_MAX;
return;
+ }
/*
* If res_lines is valid, assume we can use this watermark level
--
2.19.2
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^ permalink raw reply related [flat|nested] 24+ messages in thread* ✓ Fi.CI.BAT: success for series starting with [v3,1/4] drm/i915: Fix wm latency==0 disable on skl+ (rev6)
2019-02-04 18:45 [PATCH 1/4] drm/i915: Fix wm latency==0 disable on skl+ Ville Syrjala
` (8 preceding siblings ...)
2019-02-05 15:50 ` [PATCH v3 " Ville Syrjala
@ 2019-02-05 16:46 ` Patchwork
2019-02-05 19:47 ` ✓ Fi.CI.IGT: " Patchwork
10 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2019-02-05 16:46 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v3,1/4] drm/i915: Fix wm latency==0 disable on skl+ (rev6)
URL : https://patchwork.freedesktop.org/series/56199/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5541 -> Patchwork_12143
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/56199/revisions/6/mbox/
Known issues
------------
Here are the changes found in Patchwork_12143 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_flip@basic-flip-vs-modeset:
- fi-skl-6700hq: PASS -> DMESG-WARN [fdo#105998]
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
#### Possible fixes ####
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
* igt@pm_rpm@basic-pci-d3-state:
- fi-byt-j1900: {SKIP} [fdo#109271] -> PASS
* igt@pm_rpm@basic-rte:
- fi-byt-j1900: FAIL [fdo#108800] -> PASS
* igt@pm_rpm@module-reload:
- fi-skl-iommu: DMESG-WARN [fdo#109513] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105998]: https://bugs.freedesktop.org/show_bug.cgi?id=105998
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109513]: https://bugs.freedesktop.org/show_bug.cgi?id=109513
[fdo#109527]: https://bugs.freedesktop.org/show_bug.cgi?id=109527
[fdo#109528]: https://bugs.freedesktop.org/show_bug.cgi?id=109528
[fdo#109530]: https://bugs.freedesktop.org/show_bug.cgi?id=109530
Participating hosts (50 -> 46)
------------------------------
Additional (2): fi-icl-y fi-skl-gvtdvm
Missing (6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_5541 -> Patchwork_12143
CI_DRM_5541: 308fc30e2da36a06fd1732e2cb17e158b2df95bd @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4810: 1f89f1a04016cef20aa278ad05508cafdb9976f5 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12143: 7d2545387b70dd1a3742d867d7269b8e41b33e38 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
7d2545387b70 drm/i915: W/A for underruns with WM1+ disabled on icl
7a8974f1c53b drm/i915: Setup PIPE_CHICKEN for fastsets too
7478d40b7d01 drm/i915: Extract icl_set_pipe_chicken()
68cb8f2cd51b drm/i915: Fix wm latency==0 disable on skl+
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12143/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread* ✓ Fi.CI.IGT: success for series starting with [v3,1/4] drm/i915: Fix wm latency==0 disable on skl+ (rev6)
2019-02-04 18:45 [PATCH 1/4] drm/i915: Fix wm latency==0 disable on skl+ Ville Syrjala
` (9 preceding siblings ...)
2019-02-05 16:46 ` ✓ Fi.CI.BAT: success for series starting with [v3,1/4] drm/i915: Fix wm latency==0 disable on skl+ (rev6) Patchwork
@ 2019-02-05 19:47 ` Patchwork
10 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2019-02-05 19:47 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v3,1/4] drm/i915: Fix wm latency==0 disable on skl+ (rev6)
URL : https://patchwork.freedesktop.org/series/56199/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5541_full -> Patchwork_12143_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_12143_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_available_modes_crc@available_mode_test_crc:
- shard-apl: PASS -> FAIL [fdo#106641]
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a:
- shard-snb: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_cursor_crc@cursor-256x85-random:
- shard-apl: PASS -> FAIL [fdo#103232] +3
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232]
* igt@kms_cursor_crc@cursor-alpha-opaque:
- shard-kbl: NOTRUN -> FAIL [fdo#109350]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
- shard-glk: PASS -> FAIL [fdo#103167]
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-apl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-kbl: NOTRUN -> FAIL [fdo#108145] / [fdo#108590]
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-glk: PASS -> FAIL [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-a-tiling-none:
- shard-apl: PASS -> FAIL [fdo#103166]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
- shard-glk: NOTRUN -> FAIL [fdo#103166]
* igt@kms_plane_multiple@atomic-pipe-c-tiling-x:
- shard-glk: PASS -> FAIL [fdo#103166] +1
* igt@kms_setmode@basic:
- shard-kbl: PASS -> FAIL [fdo#99912]
#### Possible fixes ####
* igt@gem_exec_reloc@basic-gtt-wc-noreloc:
- shard-apl: INCOMPLETE [fdo#103927] -> PASS
* igt@gem_workarounds@suspend-resume:
- shard-kbl: INCOMPLETE [fdo#103665] -> PASS
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
- shard-glk: FAIL [fdo#108145] -> PASS
* igt@kms_color@pipe-c-legacy-gamma:
- shard-apl: FAIL [fdo#104782] -> PASS
* igt@kms_cursor_crc@cursor-128x128-onscreen:
- shard-apl: FAIL [fdo#103232] -> PASS +2
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
- shard-glk: FAIL [fdo#103167] -> PASS +1
- shard-apl: FAIL [fdo#103167] -> PASS +1
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-snb: INCOMPLETE [fdo#105411] -> PASS
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-apl: FAIL [fdo#108145] -> PASS
* igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
- shard-glk: FAIL [fdo#103166] -> PASS
* igt@perf@oa-exponents:
- shard-glk: FAIL [fdo#105483] -> PASS
* igt@pm_rc6_residency@rc6-accuracy:
- shard-kbl: {SKIP} [fdo#109271] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#105483]: https://bugs.freedesktop.org/show_bug.cgi?id=105483
[fdo#106641]: https://bugs.freedesktop.org/show_bug.cgi?id=106641
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108590]: https://bugs.freedesktop.org/show_bug.cgi?id=108590
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109350]: https://bugs.freedesktop.org/show_bug.cgi?id=109350
[fdo#109373]: https://bugs.freedesktop.org/show_bug.cgi?id=109373
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (7 -> 5)
------------------------------
Missing (2): shard-skl shard-iclb
Build changes
-------------
* Linux: CI_DRM_5541 -> Patchwork_12143
CI_DRM_5541: 308fc30e2da36a06fd1732e2cb17e158b2df95bd @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4810: 1f89f1a04016cef20aa278ad05508cafdb9976f5 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12143: 7d2545387b70dd1a3742d867d7269b8e41b33e38 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12143/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 24+ messages in thread