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From: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 2/7] riscv: import the supervisor binary interface header file
Date: Mon, 11 Feb 2019 23:13:39 +0100	[thread overview]
Message-ID: <20190211221345.31980-3-lukas.auer@aisec.fraunhofer.de> (raw)
In-Reply-To: <20190211221345.31980-1-lukas.auer@aisec.fraunhofer.de>

Import the supervisor binary interface (SBI) header file from Linux
(arch/riscv/include/asm/sbi.h). The last change to it was in commit
6d60b6ee0c97 ("RISC-V: Device, timer, IRQs, and the SBI").

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
---

 arch/riscv/include/asm/sbi.h | 94 ++++++++++++++++++++++++++++++++++++
 1 file changed, 94 insertions(+)
 create mode 100644 arch/riscv/include/asm/sbi.h

diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
new file mode 100644
index 0000000000..ced57defdd
--- /dev/null
+++ b/arch/riscv/include/asm/sbi.h
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2015 Regents of the University of California
+ *
+ * Taken from Linux arch/riscv/include/asm/sbi.h
+ */
+
+#ifndef _ASM_RISCV_SBI_H
+#define _ASM_RISCV_SBI_H
+
+#include <linux/types.h>
+
+#define SBI_SET_TIMER 0
+#define SBI_CONSOLE_PUTCHAR 1
+#define SBI_CONSOLE_GETCHAR 2
+#define SBI_CLEAR_IPI 3
+#define SBI_SEND_IPI 4
+#define SBI_REMOTE_FENCE_I 5
+#define SBI_REMOTE_SFENCE_VMA 6
+#define SBI_REMOTE_SFENCE_VMA_ASID 7
+#define SBI_SHUTDOWN 8
+
+#define SBI_CALL(which, arg0, arg1, arg2) ({			\
+	register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);	\
+	register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1);	\
+	register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);	\
+	register uintptr_t a7 asm ("a7") = (uintptr_t)(which);	\
+	asm volatile ("ecall"					\
+		      : "+r" (a0)				\
+		      : "r" (a1), "r" (a2), "r" (a7)		\
+		      : "memory");				\
+	a0;							\
+})
+
+/* Lazy implementations until SBI is finalized */
+#define SBI_CALL_0(which) SBI_CALL(which, 0, 0, 0)
+#define SBI_CALL_1(which, arg0) SBI_CALL(which, arg0, 0, 0)
+#define SBI_CALL_2(which, arg0, arg1) SBI_CALL(which, arg0, arg1, 0)
+
+static inline void sbi_console_putchar(int ch)
+{
+	SBI_CALL_1(SBI_CONSOLE_PUTCHAR, ch);
+}
+
+static inline int sbi_console_getchar(void)
+{
+	return SBI_CALL_0(SBI_CONSOLE_GETCHAR);
+}
+
+static inline void sbi_set_timer(uint64_t stime_value)
+{
+#if __riscv_xlen == 32
+	SBI_CALL_2(SBI_SET_TIMER, stime_value, stime_value >> 32);
+#else
+	SBI_CALL_1(SBI_SET_TIMER, stime_value);
+#endif
+}
+
+static inline void sbi_shutdown(void)
+{
+	SBI_CALL_0(SBI_SHUTDOWN);
+}
+
+static inline void sbi_clear_ipi(void)
+{
+	SBI_CALL_0(SBI_CLEAR_IPI);
+}
+
+static inline void sbi_send_ipi(const unsigned long *hart_mask)
+{
+	SBI_CALL_1(SBI_SEND_IPI, hart_mask);
+}
+
+static inline void sbi_remote_fence_i(const unsigned long *hart_mask)
+{
+	SBI_CALL_1(SBI_REMOTE_FENCE_I, hart_mask);
+}
+
+static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask,
+					 unsigned long start,
+					 unsigned long size)
+{
+	SBI_CALL_1(SBI_REMOTE_SFENCE_VMA, hart_mask);
+}
+
+static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
+					      unsigned long start,
+					      unsigned long size,
+					      unsigned long asid)
+{
+	SBI_CALL_1(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask);
+}
+
+#endif
-- 
2.20.1

  parent reply	other threads:[~2019-02-11 22:13 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-11 22:13 [U-Boot] [PATCH 0/7] SMP support for RISC-V Lukas Auer
2019-02-11 22:13 ` [U-Boot] [PATCH 1/7] riscv: add infrastructure for calling functions on other harts Lukas Auer
2019-02-12  1:44   ` Anup Patel
2019-02-17 21:55     ` Auer, Lukas
     [not found]       ` <752D002CFF5D0F4FA35C0100F1D73F3FA4087D3C@ATCPCS16.andestech.com>
2019-02-18  3:24         ` Rick Chen
2019-02-18  3:40           ` Anup Patel
2019-02-18  9:53             ` Auer, Lukas
2019-02-12  3:03   ` Bin Meng
2019-02-17 22:00     ` Auer, Lukas
2019-02-18  4:58   ` Anup Patel
2019-02-18 10:01     ` Auer, Lukas
2019-02-18 11:41       ` Auer, Lukas
2019-02-18 13:16         ` Anup Patel
2019-02-18 16:04           ` Auer, Lukas
2019-02-19  8:16         ` Anup Patel
2019-02-25 11:13           ` Auer, Lukas
2019-02-11 22:13 ` Lukas Auer [this message]
2019-02-12  2:32   ` [U-Boot] [PATCH 2/7] riscv: import the supervisor binary interface header file Anup Patel
2019-02-12  3:03   ` Bin Meng
2019-02-11 22:13 ` [U-Boot] [PATCH 3/7] riscv: implement IPI platform functions using SBI Lukas Auer
2019-02-12  2:32   ` Anup Patel
2019-02-12  3:03   ` Bin Meng
2019-02-11 22:13 ` [U-Boot] [PATCH 4/7] riscv: delay initialization of caches and debug UART Lukas Auer
2019-02-12  2:32   ` Anup Patel
2019-02-12  3:03   ` Bin Meng
2019-02-11 22:13 ` [U-Boot] [PATCH 5/7] riscv: add support for multi-hart systems Lukas Auer
2019-02-12  1:48   ` Anup Patel
2019-02-17 22:02     ` Auer, Lukas
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA408502C@ATCPCS16.andestech.com>
2019-02-15  6:51     ` Rick Chen
2019-02-17 22:06       ` Auer, Lukas
2019-03-07  9:30     ` Rick Chen
2019-03-10 13:58       ` Auer, Lukas
2019-03-10 14:54         ` Anup Patel
2019-03-10 18:12           ` Auer, Lukas
2019-03-10 20:56             ` Anup Patel
2019-03-12  1:15             ` Rick Chen
2019-03-14 21:04               ` Auer, Lukas
2019-02-11 22:13 ` [U-Boot] [PATCH 6/7] riscv: boot images passed to bootm on all harts Lukas Auer
2019-02-12  2:33   ` Anup Patel
2019-02-12  3:04   ` Bin Meng
2019-02-11 22:13 ` [U-Boot] [PATCH 7/7] riscv: qemu: enable SMP Lukas Auer
2019-02-12  2:34   ` Anup Patel
2019-02-12  3:05   ` Bin Meng
2019-02-11 22:16 ` [U-Boot] [PATCH 0/7] SMP support for RISC-V Philipp Tomsich
2019-02-11 22:44   ` Auer, Lukas

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