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From: Boris Brezillon <boris.brezillon@collabora.com>
To: Vignesh R <vigneshr@ti.com>,
	Boris Brezillon <bbrezillon@kernel.org>,
	Tudor.Ambarus@microchip.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	Marek Vasut <marek.vasut@gmail.com>,
	Rob Herring <robh+dt@kernel.org>,
	linux-mtd@lists.infradead.org
Subject: Re: [v6, 2/2] mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller
Date: Thu, 14 Feb 2019 14:00:03 +0100	[thread overview]
Message-ID: <20190214130003.29783-1-boris.brezillon@collabora.com> (raw)
In-Reply-To: <20190212083809.6534-3-vigneshr@ti.com>

From: Boris Brezillon <bbrezillon@kernel.org>

On Tue, 2019-02-12 at 08:38:09 UTC, Vignesh R wrote:
> Cadence OSPI controller IP supports Octal IO (x8 IO lines),
> It also has an integrated PHY. IP register layout is very
> similar to existing QSPI IP except for additional bits to support Octal
> and Octal DDR mode. Therefore, extend current driver to support Octal
> mode. Only Octal SDR read (1-1-8)mode is supported for now.
> 
> Tested with mt35xu512aba Octal flash on TI's AM654 EVM.
> 
> Signed-off-by: Vignesh R <vigneshr@ti.com>
> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>

Applied to http://git.infradead.org/linux-mtd.git spi-nor/next, thanks.

Boris

WARNING: multiple messages have this Message-ID (diff)
From: Boris Brezillon <boris.brezillon@collabora.com>
To: Vignesh R <vigneshr@ti.com>,
	Boris Brezillon <bbrezillon@kernel.org>,
	Tudor.Ambarus@microchip.com
Cc: devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
	linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,
	Marek Vasut <marek.vasut@gmail.com>
Subject: Re: [v6, 2/2] mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller
Date: Thu, 14 Feb 2019 14:00:03 +0100	[thread overview]
Message-ID: <20190214130003.29783-1-boris.brezillon@collabora.com> (raw)
In-Reply-To: <20190212083809.6534-3-vigneshr@ti.com>

From: Boris Brezillon <bbrezillon@kernel.org>

On Tue, 2019-02-12 at 08:38:09 UTC, Vignesh R wrote:
> Cadence OSPI controller IP supports Octal IO (x8 IO lines),
> It also has an integrated PHY. IP register layout is very
> similar to existing QSPI IP except for additional bits to support Octal
> and Octal DDR mode. Therefore, extend current driver to support Octal
> mode. Only Octal SDR read (1-1-8)mode is supported for now.
> 
> Tested with mt35xu512aba Octal flash on TI's AM654 EVM.
> 
> Signed-off-by: Vignesh R <vigneshr@ti.com>
> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>

Applied to http://git.infradead.org/linux-mtd.git spi-nor/next, thanks.

Boris

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Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

  parent reply	other threads:[~2019-02-14 13:00 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-12  8:38 [PATCH v6 0/2] cadence-quadspi: Add Octal mode support Vignesh R
2019-02-12  8:38 ` Vignesh R
2019-02-12  8:38 ` Vignesh R
2019-02-12  8:38 ` [PATCH v6 1/2] dt-bindings: cadence-quadspi: Add new compatible for AM654 SoC Vignesh R
2019-02-12  8:38   ` Vignesh R
2019-02-12  8:38   ` Vignesh R
2019-02-14 13:00   ` [v6, " Boris Brezillon
2019-02-14 13:00     ` Boris Brezillon
2019-02-12  8:38 ` [PATCH v6 2/2] mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller Vignesh R
2019-02-12  8:38   ` Vignesh R
2019-02-12  8:38   ` Vignesh R
2019-02-12  9:12   ` Tudor.Ambarus
2019-02-12  9:12     ` Tudor.Ambarus
2019-02-12  9:12     ` Tudor.Ambarus
2019-02-14 13:00   ` Boris Brezillon [this message]
2019-02-14 13:00     ` [v6, " Boris Brezillon
2019-02-21 10:41   ` [EXT] [PATCH v6 " Bean Huo (beanhuo)
2019-02-21 10:41     ` Bean Huo (beanhuo)
2019-02-21 10:50     ` Boris Brezillon
2019-02-21 10:50       ` Boris Brezillon
2019-02-21 13:11     ` Vignesh R
2019-02-21 13:11       ` Vignesh R

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