* [igt-dev] [PATCH i-g-t] i915/gem_mocs_settings: Add mocs table for icelake
@ 2019-02-09 19:50 Prathap Kumar Valsan
2019-02-09 19:55 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork
` (3 more replies)
0 siblings, 4 replies; 12+ messages in thread
From: Prathap Kumar Valsan @ 2019-02-09 19:50 UTC (permalink / raw)
To: igt-dev
From: "Kumar Valsan, Prathap" <prathap.kumar.valsan@intel.com>
This patch adds mocs table for icelake with expected L3 and eDRAM
control values.
Signed-off-by: Kumar Valsan, Prathap <prathap.kumar.valsan@intel.com>
---
tests/i915/gem_mocs_settings.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/tests/i915/gem_mocs_settings.c b/tests/i915/gem_mocs_settings.c
index 5b3b6bc1..bae245ef 100644
--- a/tests/i915/gem_mocs_settings.c
+++ b/tests/i915/gem_mocs_settings.c
@@ -73,6 +73,18 @@ struct mocs_table {
};
/* The first entries in the MOCS tables are defined by uABI */
+static const struct mocs_entry icelake_mocs_table[] = {
+ { 0x00000005, 0x0010 },
+ { 0x00000004, 0x0030 },
+ { 0x00000037, 0x0030 },
+};
+
+static const struct mocs_entry dirty_icelake_mocs_table[] = {
+ { 0x0007FFFF, 0x003F },
+ { 0x0007FFFF, 0x003F },
+ { 0x0007FFFF, 0x003F },
+};
+
static const struct mocs_entry skylake_mocs_table[] = {
{ 0x00000009, 0x0010 },
{ 0x00000038, 0x0030 },
@@ -127,6 +139,15 @@ static bool get_mocs_settings(int fd, struct mocs_table *table, bool dirty)
table->table = broxton_mocs_table;
}
result = true;
+ } else if (IS_ICELAKE(devid)) {
+ if (dirty) {
+ table->size = ARRAY_SIZE(dirty_icelake_mocs_table);
+ table->table = dirty_icelake_mocs_table;
+ } else {
+ table->size = ARRAY_SIZE(icelake_mocs_table);
+ table->table = icelake_mocs_table;
+ }
+ result = true;
}
return result;
--
2.20.1
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for i915/gem_mocs_settings: Add mocs table for icelake
2019-02-09 19:50 [igt-dev] [PATCH i-g-t] i915/gem_mocs_settings: Add mocs table for icelake Prathap Kumar Valsan
@ 2019-02-09 19:55 ` Patchwork
2019-02-09 21:25 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-02-09 19:55 UTC (permalink / raw)
To: Prathap Kumar Valsan; +Cc: igt-dev
== Series Details ==
Series: i915/gem_mocs_settings: Add mocs table for icelake
URL : https://patchwork.freedesktop.org/series/56459/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5575 -> IGTPW_2369
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/56459/revisions/1/mbox/
Known issues
------------
Here are the changes found in IGTPW_2369 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@pm_rpm@module-reload:
- fi-skl-6770hq: PASS -> FAIL [fdo#108511]
#### Possible fixes ####
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109527]: https://bugs.freedesktop.org/show_bug.cgi?id=109527
[fdo#109567]: https://bugs.freedesktop.org/show_bug.cgi?id=109567
Participating hosts (46 -> 41)
------------------------------
Additional (1): fi-hsw-4770r
Missing (6): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-skl-6700hq fi-bdw-samus
Build changes
-------------
* IGT: IGT_4815 -> IGTPW_2369
CI_DRM_5575: f54ddb76353b218c6731d453cca7dc95b53d5f50 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_2369: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2369/
IGT_4815: 947301563259726b65ce47d3a3fe37931ed42efe @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2369/
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 12+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for i915/gem_mocs_settings: Add mocs table for icelake
2019-02-09 19:50 [igt-dev] [PATCH i-g-t] i915/gem_mocs_settings: Add mocs table for icelake Prathap Kumar Valsan
2019-02-09 19:55 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork
@ 2019-02-09 21:25 ` Patchwork
2019-02-11 18:39 ` [igt-dev] [PATCH i-g-t] " Lucas De Marchi
2019-02-14 15:46 ` [igt-dev] [PATCH i-g-t v2] " Prathap Kumar Valsan via igt-dev
3 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-02-09 21:25 UTC (permalink / raw)
To: Prathap Kumar Valsan; +Cc: igt-dev
== Series Details ==
Series: i915/gem_mocs_settings: Add mocs table for icelake
URL : https://patchwork.freedesktop.org/series/56459/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5575_full -> IGTPW_2369_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/56459/revisions/1/mbox/
Known issues
------------
Here are the changes found in IGTPW_2369_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_flush@basic-uc-pro-default:
- shard-snb: PASS -> INCOMPLETE [fdo#105411]
* igt@gem_softpin@noreloc-s3:
- shard-kbl: PASS -> DMESG-WARN [fdo#108566]
* igt@gem_threaded_access_tiled:
- shard-apl: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-snb: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-render-c:
- shard-kbl: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
- shard-snb: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-glk: PASS -> FAIL [fdo#108145] +1
* igt@kms_color@pipe-a-degamma:
- shard-apl: PASS -> FAIL [fdo#104782] / [fdo#108145]
- shard-kbl: PASS -> FAIL [fdo#104782] / [fdo#108145]
* igt@kms_color@pipe-b-legacy-gamma:
- shard-apl: PASS -> FAIL [fdo#104782]
* igt@kms_cursor_crc@cursor-128x128-sliding:
- shard-kbl: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-kbl: PASS -> FAIL [fdo#103191] / [fdo#103232]
* igt@kms_cursor_crc@cursor-256x85-sliding:
- shard-apl: PASS -> FAIL [fdo#103232] +1
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-hsw: PASS -> FAIL [fdo#105767]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff:
- shard-apl: PASS -> FAIL [fdo#103167] +3
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
- shard-kbl: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
- shard-glk: PASS -> FAIL [fdo#103167] +8
* igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
- shard-apl: PASS -> FAIL [fdo#108948]
* igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-apl: PASS -> FAIL [fdo#103166] +4
* igt@kms_plane_multiple@atomic-pipe-c-tiling-x:
- shard-glk: PASS -> FAIL [fdo#103166] +1
* igt@kms_setmode@basic:
- shard-apl: PASS -> FAIL [fdo#99912]
- shard-kbl: PASS -> FAIL [fdo#99912]
#### Possible fixes ####
* igt@kms_color@pipe-a-legacy-gamma:
- shard-apl: FAIL [fdo#104782] / [fdo#108145] -> PASS
* igt@kms_cursor_crc@cursor-256x256-sliding:
- shard-glk: FAIL [fdo#103232] -> PASS +6
* igt@kms_cursor_crc@cursor-64x21-random:
- shard-apl: FAIL [fdo#103232] -> PASS +7
* igt@kms_cursor_crc@cursor-64x64-onscreen:
- shard-kbl: FAIL [fdo#103232] -> PASS +1
* igt@kms_cursor_crc@cursor-alpha-opaque:
- shard-apl: FAIL [fdo#109350] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
- shard-glk: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
- shard-apl: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbc-farfromfence:
- shard-snb: INCOMPLETE [fdo#105411] -> PASS
* igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
- shard-glk: FAIL [fdo#108948] -> PASS
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-kbl: FAIL [fdo#108145] -> PASS
- shard-apl: FAIL [fdo#108145] -> PASS
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-glk: FAIL [fdo#108145] -> PASS +2
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- shard-glk: FAIL [fdo#103166] -> PASS
- shard-kbl: FAIL [fdo#103166] -> PASS +2
* igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- shard-apl: FAIL [fdo#103166] -> PASS +5
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-kbl: DMESG-FAIL [fdo#105763] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108948]: https://bugs.freedesktop.org/show_bug.cgi?id=108948
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109350]: https://bugs.freedesktop.org/show_bug.cgi?id=109350
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (7 -> 5)
------------------------------
Missing (2): shard-skl shard-iclb
Build changes
-------------
* IGT: IGT_4815 -> IGTPW_2369
* Piglit: piglit_4509 -> None
CI_DRM_5575: f54ddb76353b218c6731d453cca7dc95b53d5f50 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_2369: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2369/
IGT_4815: 947301563259726b65ce47d3a3fe37931ed42efe @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2369/
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] i915/gem_mocs_settings: Add mocs table for icelake
2019-02-09 19:50 [igt-dev] [PATCH i-g-t] i915/gem_mocs_settings: Add mocs table for icelake Prathap Kumar Valsan
2019-02-09 19:55 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork
2019-02-09 21:25 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
@ 2019-02-11 18:39 ` Lucas De Marchi
2019-02-14 15:46 ` [igt-dev] [PATCH i-g-t v2] " Prathap Kumar Valsan via igt-dev
3 siblings, 0 replies; 12+ messages in thread
From: Lucas De Marchi @ 2019-02-11 18:39 UTC (permalink / raw)
To: Prathap Kumar Valsan; +Cc: igt-dev
On Sat, Feb 9, 2019 at 11:37 AM Prathap Kumar Valsan
<prathap.kumar.valsan@intel.com> wrote:
>
> From: "Kumar Valsan, Prathap" <prathap.kumar.valsan@intel.com>
>
> This patch adds mocs table for icelake with expected L3 and eDRAM
> control values.
>
> Signed-off-by: Kumar Valsan, Prathap <prathap.kumar.valsan@intel.com>
> ---
> tests/i915/gem_mocs_settings.c | 21 +++++++++++++++++++++
> 1 file changed, 21 insertions(+)
>
> diff --git a/tests/i915/gem_mocs_settings.c b/tests/i915/gem_mocs_settings.c
> index 5b3b6bc1..bae245ef 100644
> --- a/tests/i915/gem_mocs_settings.c
> +++ b/tests/i915/gem_mocs_settings.c
> @@ -73,6 +73,18 @@ struct mocs_table {
> };
>
> /* The first entries in the MOCS tables are defined by uABI */
> +static const struct mocs_entry icelake_mocs_table[] = {
> + { 0x00000005, 0x0010 },
> + { 0x00000004, 0x0030 },
> + { 0x00000037, 0x0030 },
the table contains 62 entries that we should be checking. What about
the other ones?
We will need to update the other tables as well, as it was changed
from Uncached to PTE. Could you take care of that as well?
thanks
Lucas De Marchi
> +};
> +
> +static const struct mocs_entry dirty_icelake_mocs_table[] = {
> + { 0x0007FFFF, 0x003F },
> + { 0x0007FFFF, 0x003F },
> + { 0x0007FFFF, 0x003F },
> +};
> +
> static const struct mocs_entry skylake_mocs_table[] = {
> { 0x00000009, 0x0010 },
> { 0x00000038, 0x0030 },
> @@ -127,6 +139,15 @@ static bool get_mocs_settings(int fd, struct mocs_table *table, bool dirty)
> table->table = broxton_mocs_table;
> }
> result = true;
> + } else if (IS_ICELAKE(devid)) {
> + if (dirty) {
> + table->size = ARRAY_SIZE(dirty_icelake_mocs_table);
> + table->table = dirty_icelake_mocs_table;
> + } else {
> + table->size = ARRAY_SIZE(icelake_mocs_table);
> + table->table = icelake_mocs_table;
> + }
> + result = true;
> }
>
> return result;
> --
> 2.20.1
>
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
--
Lucas De Marchi
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 12+ messages in thread
* [igt-dev] [PATCH i-g-t v2] i915/gem_mocs_settings: Add mocs table for icelake
2019-02-09 19:50 [igt-dev] [PATCH i-g-t] i915/gem_mocs_settings: Add mocs table for icelake Prathap Kumar Valsan
` (2 preceding siblings ...)
2019-02-11 18:39 ` [igt-dev] [PATCH i-g-t] " Lucas De Marchi
@ 2019-02-14 15:46 ` Prathap Kumar Valsan via igt-dev
3 siblings, 0 replies; 12+ messages in thread
From: Prathap Kumar Valsan via igt-dev @ 2019-02-14 15:46 UTC (permalink / raw)
To: igt-dev
From: "Kumar Valsan, Prathap" <prathap.kumar.valsan@intel.com>
This patch adds mocs table for icelake with expected L3 and eDRAM
control values.
Signed-off-by: Kumar Valsan, Prathap <prathap.kumar.valsan@intel.com>
---
Changes in v2:
- Updated GEN9 mocs table with 62 entries
- Updated GEN11 mocs table with 64 entries
- Set ununsed mocs entries to PTE
tests/i915/gem_mocs_settings.c | 148 +++++++++++++++++++++++++++------
1 file changed, 124 insertions(+), 24 deletions(-)
diff --git a/tests/i915/gem_mocs_settings.c b/tests/i915/gem_mocs_settings.c
index 5b3b6bc1..1ab0d674 100644
--- a/tests/i915/gem_mocs_settings.c
+++ b/tests/i915/gem_mocs_settings.c
@@ -33,6 +33,10 @@
#include "igt_sysfs.h"
#define MAX_NUMBER_MOCS_REGISTERS (64)
+#define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */
+#define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
+#define MOCS_PTE_INDEX (0x1)
+
enum {
NONE,
RESET,
@@ -65,6 +69,7 @@ static const char * const test_modes[] = {
struct mocs_entry {
uint32_t control_value;
uint16_t l3cc_value;
+ uint8_t used;
};
struct mocs_table {
@@ -73,37 +78,113 @@ struct mocs_table {
};
/* The first entries in the MOCS tables are defined by uABI */
-static const struct mocs_entry skylake_mocs_table[] = {
- { 0x00000009, 0x0010 },
- { 0x00000038, 0x0030 },
- { 0x0000003b, 0x0030 },
+static struct mocs_entry icelake_mocs_table[GEN11_NUM_MOCS_ENTRIES] = {
+ [0] = { 0x00000005, 0x0010, 0x1 },
+ [1] = { 0x00000004, 0x0030, 0x1 },
+ [2] = { 0x00000037, 0x0030, 0x1 },
+ [3] = { 0x00000005, 0x0010, 0x1 },
+ [4] = { 0x00000005, 0x0030, 0x1 },
+ [5] = { 0x00000037, 0x0010, 0x1 },
+ [6] = { 0x00000017, 0x0010, 0x1 },
+ [7] = { 0x00000017, 0x0030, 0x1 },
+ [8] = { 0x00000027, 0x0010, 0x1 },
+ [9] = { 0x00000027, 0x0030, 0x1 },
+ [10] = { 0x00000077, 0x0010, 0x1 },
+ [11] = { 0x00000077, 0x0030, 0x1 },
+ [12] = { 0x00000057, 0x0010, 0x1 },
+ [13] = { 0x00000057, 0x0030, 0x1 },
+ [14] = { 0x00000067, 0x0010, 0x1 },
+ [15] = { 0x00000067, 0x0030, 0x1 },
+ [18] = { 0x00060037, 0x0030, 0x1 },
+ [19] = { 0x00000737, 0x0030, 0x1 },
+ [20] = { 0x00000337, 0x0030, 0x1 },
+ [21] = { 0x00000137, 0x0030, 0x1 },
+ [22] = { 0x000003b7, 0x0030, 0x1 },
+ [23] = { 0x000007b7, 0x0030, 0x1 },
+ [62] = { 0x00000037, 0x0010, 0x1 },
+ [63] = { 0x00000037, 0x0010, 0x1 },
+};
+
+static struct mocs_entry dirty_icelake_mocs_table[GEN11_NUM_MOCS_ENTRIES] = {
+ [0] = { 0x0007FFFF, 0x003F },
+ [1] = { 0x0007FFFF, 0x003F },
+ [2] = { 0x0007FFFF, 0x003F },
+ [3] = { 0x0007FFFF, 0x003F },
+ [4] = { 0x0007FFFF, 0x003F },
+ [5] = { 0x0007FFFF, 0x003F },
+ [6] = { 0x0007FFFF, 0x003F },
+ [7] = { 0x0007FFFF, 0x003F },
+ [8] = { 0x0007FFFF, 0x003F },
+ [9] = { 0x0007FFFF, 0x003F },
+ [10] = { 0x0007FFFF, 0x003F },
+ [11] = { 0x0007FFFF, 0x003F },
+ [12] = { 0x0007FFFF, 0x003F },
+ [13] = { 0x0007FFFF, 0x003F },
+ [14] = { 0x0007FFFF, 0x003F },
+ [15] = { 0x0007FFFF, 0x003F },
+ [18] = { 0x0007FFFF, 0x003F },
+ [19] = { 0x0007FFFF, 0x003F },
+ [21] = { 0x0007FFFF, 0x003F },
+ [22] = { 0x0007FFFF, 0x003F },
+ [23] = { 0x0007FFFF, 0x003F },
+ [62] = { 0x0007FFFF, 0x003F },
+ [63] = { 0x0007FFFF, 0x003F },
};
-static const struct mocs_entry dirty_skylake_mocs_table[] = {
- { 0x00003FFF, 0x003F }, /* no snoop bit */
- { 0x00003FFF, 0x003F },
- { 0x00003FFF, 0x003F },
+static struct mocs_entry skylake_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
+ { 0x00000009, 0x0010, 0x1 },
+ { 0x00000038, 0x0030, 0x1 },
+ { 0x0000003b, 0x0030, 0x1 },
};
-static const struct mocs_entry broxton_mocs_table[] = {
- { 0x00000009, 0x0010 },
- { 0x00000038, 0x0030 },
- { 0x00000039, 0x0030 },
+static struct mocs_entry dirty_skylake_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
+ { 0x00003FFF, 0x003F, 0x1 }, /* no snoop bit */
+ { 0x00003FFF, 0x003F, 0x1 },
+ { 0x00003FFF, 0x003F, 0x1 },
};
-static const struct mocs_entry dirty_broxton_mocs_table[] = {
- { 0x00007FFF, 0x003F },
- { 0x00007FFF, 0x003F },
- { 0x00007FFF, 0x003F },
+static struct mocs_entry broxton_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
+ { 0x00000009, 0x0010, 0x1 },
+ { 0x00000038, 0x0030, 0x1 },
+ { 0x00000039, 0x0030, 0x1 },
};
-static const uint32_t write_values[] = {
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF
+static struct mocs_entry dirty_broxton_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
+ { 0x00007FFF, 0x003F, 0x1 },
+ { 0x00007FFF, 0x003F, 0x1 },
+ { 0x00007FFF, 0x003F, 0x1 },
};
+static uint32_t write_values[MAX_NUMBER_MOCS_REGISTERS];
+
+static void set_mocs_settings(void)
+{
+ uint8_t index;
+ /* Set un-used entries to PTE */
+ for (index = 0; index < MAX_NUMBER_MOCS_REGISTERS; index++) {
+ if (index < GEN9_NUM_MOCS_ENTRIES) {
+ if (!skylake_mocs_table[index].used) {
+ skylake_mocs_table[index] = skylake_mocs_table[MOCS_PTE_INDEX];
+ dirty_skylake_mocs_table[index] = dirty_skylake_mocs_table[MOCS_PTE_INDEX];
+ }
+ if (!broxton_mocs_table[index].used) {
+ broxton_mocs_table[index] = broxton_mocs_table[MOCS_PTE_INDEX];
+ dirty_broxton_mocs_table[index] = dirty_broxton_mocs_table[MOCS_PTE_INDEX];
+ }
+ if (!icelake_mocs_table[index].used) {
+ icelake_mocs_table[index] = icelake_mocs_table[MOCS_PTE_INDEX];
+ dirty_icelake_mocs_table[index] = dirty_icelake_mocs_table[MOCS_PTE_INDEX];
+ }
+ } else { /*icelake has 64 entries */
+ if (!icelake_mocs_table[index].used) {
+ icelake_mocs_table[index] = icelake_mocs_table[MOCS_PTE_INDEX];
+ dirty_icelake_mocs_table[index] = dirty_icelake_mocs_table[MOCS_PTE_INDEX];
+ }
+ }
+ }
+ memset((char *)write_values, 0xFF, MAX_NUMBER_MOCS_REGISTERS * sizeof(uint32_t));
+}
+
static bool get_mocs_settings(int fd, struct mocs_table *table, bool dirty)
{
uint32_t devid = intel_get_drm_devid(fd);
@@ -127,6 +208,15 @@ static bool get_mocs_settings(int fd, struct mocs_table *table, bool dirty)
table->table = broxton_mocs_table;
}
result = true;
+ } else if (IS_ICELAKE(devid)) {
+ if (dirty) {
+ table->size = ARRAY_SIZE(dirty_icelake_mocs_table);
+ table->table = dirty_icelake_mocs_table;
+ } else {
+ table->size = ARRAY_SIZE(icelake_mocs_table);
+ table->table = icelake_mocs_table;
+ }
+ result = true;
}
return result;
@@ -283,9 +373,10 @@ static void check_control_registers(int fd,
read_regs = gem_mmap__cpu(fd, dst_handle, 0, 4096, PROT_READ);
gem_set_domain(fd, dst_handle, I915_GEM_DOMAIN_CPU, 0);
- for (int index = 0; index < table.size; index++)
+ for (int index = 0; index < table.size; index++) {
igt_assert_eq_u32(read_regs[index],
table.table[index].control_value);
+ }
munmap(read_regs, 4096);
gem_close(fd, dst_handle);
@@ -374,13 +465,21 @@ static void check_mocs_values(int fd, unsigned engine, uint32_t ctx_id, bool dir
static void write_dirty_mocs(int fd, unsigned engine, uint32_t ctx_id)
{
+ uint32_t devid = intel_get_drm_devid(fd);
+ int num_of_mocs_entries;
+
+ if (IS_ICELAKE(devid))
+ num_of_mocs_entries = GEN11_NUM_MOCS_ENTRIES;
+ else
+ num_of_mocs_entries = GEN9_NUM_MOCS_ENTRIES;
+
write_registers(fd, ctx_id, get_engine_base(engine),
- write_values, ARRAY_SIZE(write_values),
+ write_values, num_of_mocs_entries,
engine);
if (engine == I915_EXEC_RENDER)
write_registers(fd, ctx_id, GEN9_LNCFCMOCS0,
- write_values, ARRAY_SIZE(write_values),
+ write_values, num_of_mocs_entries,
engine);
}
@@ -440,6 +539,7 @@ igt_main
fd = drm_open_driver_master(DRIVER_INTEL); /* for SECURE */
igt_require_gem(fd);
gem_require_mocs_registers(fd);
+ set_mocs_settings();
igt_require(get_mocs_settings(fd, &table, false));
}
--
2.20.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v2] i915/gem_mocs_settings: Add mocs table for icelake
2019-02-22 21:48 ` Chris Wilson
@ 2019-02-25 13:17 ` Lis, Tomasz
0 siblings, 0 replies; 12+ messages in thread
From: Lis, Tomasz @ 2019-02-25 13:17 UTC (permalink / raw)
To: Chris Wilson, Kumar Valsan, Prathap; +Cc: igt-dev, Lucas De Marchi
On 2019-02-22 22:48, Chris Wilson wrote:
> Quoting Kumar Valsan, Prathap (2019-02-22 21:32:55)
>> On Fri, Feb 22, 2019 at 03:21:18PM +0000, Chris Wilson wrote:
>>> Quoting Lis, Tomasz (2019-02-22 15:17:34)
>>>>
>>>> On 2019-02-22 15:17, Prathap Kumar Valsan wrote:
>>>>> From: "Kumar Valsan, Prathap" <prathap.kumar.valsan@intel.com>
>>>>>
>>>>> This patch adds mocs table for icelake with expected L3 and eDRAM
>>>>> control values.
>>>>>
>>>>> Signed-off-by: Kumar Valsan, Prathap <prathap.kumar.valsan@intel.com>
>>>>> ---
>>>>> Changes in v2:
>>>>> - Cleaned up the code based on review comments from Lucas and Chris
>>>>> tests/i915/gem_mocs_settings.c | 96 ++++++++++++++++++++++++++--------
>>>>> 1 file changed, 73 insertions(+), 23 deletions(-)
>>>>>
>>>>> diff --git a/tests/i915/gem_mocs_settings.c b/tests/i915/gem_mocs_settings.c
>>>>> index 5b3b6bc1..6d111076 100644
>>>>> --- a/tests/i915/gem_mocs_settings.c
>>>>> +++ b/tests/i915/gem_mocs_settings.c
>>>>> @@ -33,6 +33,9 @@
>>>>> #include "igt_sysfs.h"
>>>>>
>>>>> #define MAX_NUMBER_MOCS_REGISTERS (64)
>>>>> +#define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */
>>>>> +#define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
>>>>> +
>>>>> enum {
>>>>> NONE,
>>>>> RESET,
>>>>> @@ -72,36 +75,66 @@ struct mocs_table {
>>>>> const struct mocs_entry *table;
>>>>> };
>>>>>
>>>>> +static const struct mocs_entry icelake_mocs_pte = {0x00000004, 0x0030};
>>>>> +static const struct mocs_entry mocs_pte = {0x00000038, 0x0030};
>>>>> +
>>>>> /* The first entries in the MOCS tables are defined by uABI */
>>>>> -static const struct mocs_entry skylake_mocs_table[] = {
>>>>> - { 0x00000009, 0x0010 },
>>>>> - { 0x00000038, 0x0030 },
>>>>> - { 0x0000003b, 0x0030 },
>>>>> +static const struct mocs_entry icelake_mocs_table[GEN11_NUM_MOCS_ENTRIES] = {
>>>>> + [0 ... GEN11_NUM_MOCS_ENTRIES - 1] = icelake_mocs_pte,
>>>>> + [0] = { 0x00000005, 0x0010},
>>>>> + [1] = { 0x00000004, 0x0030},
>>>>> + [2] = { 0x00000037, 0x0030},
>>>>> + [3] = { 0x00000005, 0x0010},
>>>>> + [4] = { 0x00000005, 0x0030},
>>>>> + [5] = { 0x00000037, 0x0010},
>>>>> + [6] = { 0x00000017, 0x0010},
>>>>> + [7] = { 0x00000017, 0x0030},
>>>>> + [8] = { 0x00000027, 0x0010},
>>>>> + [9] = { 0x00000027, 0x0030},
>>>>> + [10] = { 0x00000077, 0x0010},
>>>>> + [11] = { 0x00000077, 0x0030},
>>>>> + [12] = { 0x00000057, 0x0010},
>>>>> + [13] = { 0x00000057, 0x0030},
>>>>> + [14] = { 0x00000067, 0x0010},
>>>>> + [15] = { 0x00000067, 0x0030},
>>>>> + [18] = { 0x00060037, 0x0030},
>>>>> + [19] = { 0x00000737, 0x0030},
>>>>> + [20] = { 0x00000337, 0x0030},
>>>>> + [21] = { 0x00000137, 0x0030},
>>>>> + [22] = { 0x000003b7, 0x0030},
>>>>> + [23] = { 0x000007b7, 0x0030},
>>>>> + [62] = { 0x00000037, 0x0010},
>>>>> + [63] = { 0x00000037, 0x0010},
>>>>> +};
>>>>> +
>>>>> +static const struct mocs_entry dirty_icelake_mocs_table[GEN11_NUM_MOCS_ENTRIES] = {
>>>>> + [0 ... GEN11_NUM_MOCS_ENTRIES - 1] = { 0x0007FFFF, 0x003F },
>>>>> };
>>>>>
>>>>> -static const struct mocs_entry dirty_skylake_mocs_table[] = {
>>>>> - { 0x00003FFF, 0x003F }, /* no snoop bit */
>>>>> - { 0x00003FFF, 0x003F },
>>>>> - { 0x00003FFF, 0x003F },
>>>>> +static const struct mocs_entry skylake_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
>>>>> + [0 ... GEN9_NUM_MOCS_ENTRIES - 1] = mocs_pte,
>>>>> + [0] = { 0x00000009, 0x0010},
>>>>> + [1] = { 0x00000038, 0x0030},
>>>>> + [2] = { 0x0000003b, 0x0030},
>>>>> };
>>>>>
>>>>> -static const struct mocs_entry broxton_mocs_table[] = {
>>>>> - { 0x00000009, 0x0010 },
>>>>> - { 0x00000038, 0x0030 },
>>>>> - { 0x00000039, 0x0030 },
>>>>> +static const struct mocs_entry dirty_skylake_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
>>>>> + [0 ... GEN9_NUM_MOCS_ENTRIES - 1] = { 0x00003FFF, 0x003F },
>>>>> };
>>>>>
>>>>> -static const struct mocs_entry dirty_broxton_mocs_table[] = {
>>>>> - { 0x00007FFF, 0x003F },
>>>>> - { 0x00007FFF, 0x003F },
>>>>> - { 0x00007FFF, 0x003F },
>>>>> +static const struct mocs_entry broxton_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
>>>>> + [0 ... GEN9_NUM_MOCS_ENTRIES - 1] = mocs_pte,
>>>>> + [0] = { 0x00000009, 0x0010},
>>>>> + [1] = { 0x00000038, 0x0030},
>>>>> + [2] = { 0x00000039, 0x0030},
>>>>> };
>>>>>
>>>>> -static const uint32_t write_values[] = {
>>>>> - 0xFFFFFFFF,
>>>>> - 0xFFFFFFFF,
>>>>> - 0xFFFFFFFF,
>>>>> - 0xFFFFFFFF
>>>>> +static const struct mocs_entry dirty_broxton_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
>>>>> + [0 ... GEN9_NUM_MOCS_ENTRIES - 1] = { 0x00007FFF, 0x003F },
>>>>> +};
>>>>> +
>>>>> +static const uint32_t write_values[MAX_NUMBER_MOCS_REGISTERS] = {
>>>>> + [0 ... MAX_NUMBER_MOCS_REGISTERS - 1] = 0xFFFFFFFF,
>>>>> };
>>>>>
>>>>> static bool get_mocs_settings(int fd, struct mocs_table *table, bool dirty)
>>>>> @@ -127,6 +160,15 @@ static bool get_mocs_settings(int fd, struct mocs_table *table, bool dirty)
>>>>> table->table = broxton_mocs_table;
>>>>> }
>>>>> result = true;
>>>>> + } else if (IS_ICELAKE(devid)) {
>>>>> + if (dirty) {
>>>>> + table->size = ARRAY_SIZE(dirty_icelake_mocs_table);
>>>>> + table->table = dirty_icelake_mocs_table;
>>>>> + } else {
>>>>> + table->size = ARRAY_SIZE(icelake_mocs_table);
>>>>> + table->table = icelake_mocs_table;
>>>>> + }
>>>>> + result = true;
>>>>> }
>>>>>
>>>>> return result;
>>>>> @@ -374,13 +416,21 @@ static void check_mocs_values(int fd, unsigned engine, uint32_t ctx_id, bool dir
>>>>>
>>>>> static void write_dirty_mocs(int fd, unsigned engine, uint32_t ctx_id)
>>>>> {
>>>>> + uint32_t devid = intel_get_drm_devid(fd);
>>>>> + int num_of_mocs_entries;
>>>>> +
>>>>> + if (IS_ICELAKE(devid))
>>>>> + num_of_mocs_entries = GEN11_NUM_MOCS_ENTRIES;
>>>>> + else
>>>>> + num_of_mocs_entries = GEN9_NUM_MOCS_ENTRIES;
>>>>> +
>>>>> write_registers(fd, ctx_id, get_engine_base(engine),
>>>>> - write_values, ARRAY_SIZE(write_values),
>>>>> + write_values, num_of_mocs_entries,
>>>>> engine);
>>>>>
>>>>> if (engine == I915_EXEC_RENDER)
>>>>> write_registers(fd, ctx_id, GEN9_LNCFCMOCS0,
>>>>> - write_values, ARRAY_SIZE(write_values),
>>>>> + write_values, num_of_mocs_entries/2,
>>>>> engine);
>>>>> }
>>>>>
>>>> The "-dirty" subcase of the test doesn't seem suitable to current hardware..
>>>>
>>>> The table is now global. So writing it from one context and checking if
>>>> another context is unaffected is bound to fail.
>> As you pointed out On Gen11, "-dirty" subcases are failing.
>> Test is not able to write to registers.
>>> We shouldn't be able to do nonpriv writes to it then. Hopefully those
>>> writes are already being dropped?
>> So probably on latest hardware, test should still try to write and call
>> it pass if the dirty values are not being written?
> Yes, that would be useful confirmation that one context can't shoot
> another in the back, and that our global MOCS table remain invariant.
> -Chris
Don't we have a separate test for privileged registers? I'm not very
familiar with all the tests, but I remember someone told me that.
The scope of this test, as written at its beginning, is:
/** @file gem_mocs_settings.c
*
* Check that the MOCs cache settings are valid.
*/
If we already write to MOCS instead of only checking, the scope should
be expanded.
If we're going to check privileged operations, this should also be
included in the scope.
-Tomasz
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v2] i915/gem_mocs_settings: Add mocs table for icelake
2019-02-22 15:17 ` Lis, Tomasz
2019-02-22 15:21 ` Chris Wilson
@ 2019-02-25 0:26 ` Kumar Valsan, Prathap
1 sibling, 0 replies; 12+ messages in thread
From: Kumar Valsan, Prathap @ 2019-02-25 0:26 UTC (permalink / raw)
To: Lis, Tomasz, Chris Wilson; +Cc: igt-dev, Lucas De Marchi
On Fri, Feb 22, 2019 at 04:17:34PM +0100, Lis, Tomasz wrote:
>
>
> On 2019-02-22 15:17, Prathap Kumar Valsan wrote:
> > From: "Kumar Valsan, Prathap" <prathap.kumar.valsan@intel.com>
> >
> > This patch adds mocs table for icelake with expected L3 and eDRAM
> > control values.
> >
> > Signed-off-by: Kumar Valsan, Prathap <prathap.kumar.valsan@intel.com>
> > ---
> > Changes in v2:
> > - Cleaned up the code based on review comments from Lucas and Chris
> > tests/i915/gem_mocs_settings.c | 96 ++++++++++++++++++++++++++--------
> > 1 file changed, 73 insertions(+), 23 deletions(-)
> >
> > diff --git a/tests/i915/gem_mocs_settings.c b/tests/i915/gem_mocs_settings.c
> > index 5b3b6bc1..6d111076 100644
> > --- a/tests/i915/gem_mocs_settings.c
> > +++ b/tests/i915/gem_mocs_settings.c
> > @@ -33,6 +33,9 @@
> > #include "igt_sysfs.h"
> > #define MAX_NUMBER_MOCS_REGISTERS (64)
> > +#define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */
> > +#define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
> > +
> > enum {
> > NONE,
> > RESET,
> > @@ -72,36 +75,66 @@ struct mocs_table {
> > const struct mocs_entry *table;
> > };
> > +static const struct mocs_entry icelake_mocs_pte = {0x00000004, 0x0030};
> > +static const struct mocs_entry mocs_pte = {0x00000038, 0x0030};
> > +
> > /* The first entries in the MOCS tables are defined by uABI */
> > -static const struct mocs_entry skylake_mocs_table[] = {
> > - { 0x00000009, 0x0010 },
> > - { 0x00000038, 0x0030 },
> > - { 0x0000003b, 0x0030 },
> > +static const struct mocs_entry icelake_mocs_table[GEN11_NUM_MOCS_ENTRIES] = {
> > + [0 ... GEN11_NUM_MOCS_ENTRIES - 1] = icelake_mocs_pte,
> > + [0] = { 0x00000005, 0x0010},
> > + [1] = { 0x00000004, 0x0030},
> > + [2] = { 0x00000037, 0x0030},
> > + [3] = { 0x00000005, 0x0010},
> > + [4] = { 0x00000005, 0x0030},
> > + [5] = { 0x00000037, 0x0010},
> > + [6] = { 0x00000017, 0x0010},
> > + [7] = { 0x00000017, 0x0030},
> > + [8] = { 0x00000027, 0x0010},
> > + [9] = { 0x00000027, 0x0030},
> > + [10] = { 0x00000077, 0x0010},
> > + [11] = { 0x00000077, 0x0030},
> > + [12] = { 0x00000057, 0x0010},
> > + [13] = { 0x00000057, 0x0030},
> > + [14] = { 0x00000067, 0x0010},
> > + [15] = { 0x00000067, 0x0030},
> > + [18] = { 0x00060037, 0x0030},
> > + [19] = { 0x00000737, 0x0030},
> > + [20] = { 0x00000337, 0x0030},
> > + [21] = { 0x00000137, 0x0030},
> > + [22] = { 0x000003b7, 0x0030},
> > + [23] = { 0x000007b7, 0x0030},
> > + [62] = { 0x00000037, 0x0010},
> > + [63] = { 0x00000037, 0x0010},
> > +};
> > +
> > +static const struct mocs_entry dirty_icelake_mocs_table[GEN11_NUM_MOCS_ENTRIES] = {
> > + [0 ... GEN11_NUM_MOCS_ENTRIES - 1] = { 0x0007FFFF, 0x003F },
> > };
> > -static const struct mocs_entry dirty_skylake_mocs_table[] = {
> > - { 0x00003FFF, 0x003F }, /* no snoop bit */
> > - { 0x00003FFF, 0x003F },
> > - { 0x00003FFF, 0x003F },
> > +static const struct mocs_entry skylake_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
> > + [0 ... GEN9_NUM_MOCS_ENTRIES - 1] = mocs_pte,
> > + [0] = { 0x00000009, 0x0010},
> > + [1] = { 0x00000038, 0x0030},
> > + [2] = { 0x0000003b, 0x0030},
> > };
> > -static const struct mocs_entry broxton_mocs_table[] = {
> > - { 0x00000009, 0x0010 },
> > - { 0x00000038, 0x0030 },
> > - { 0x00000039, 0x0030 },
> > +static const struct mocs_entry dirty_skylake_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
> > + [0 ... GEN9_NUM_MOCS_ENTRIES - 1] = { 0x00003FFF, 0x003F },
> > };
> > -static const struct mocs_entry dirty_broxton_mocs_table[] = {
> > - { 0x00007FFF, 0x003F },
> > - { 0x00007FFF, 0x003F },
> > - { 0x00007FFF, 0x003F },
> > +static const struct mocs_entry broxton_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
> > + [0 ... GEN9_NUM_MOCS_ENTRIES - 1] = mocs_pte,
> > + [0] = { 0x00000009, 0x0010},
> > + [1] = { 0x00000038, 0x0030},
> > + [2] = { 0x00000039, 0x0030},
> > };
> > -static const uint32_t write_values[] = {
> > - 0xFFFFFFFF,
> > - 0xFFFFFFFF,
> > - 0xFFFFFFFF,
> > - 0xFFFFFFFF
> > +static const struct mocs_entry dirty_broxton_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
> > + [0 ... GEN9_NUM_MOCS_ENTRIES - 1] = { 0x00007FFF, 0x003F },
> > +};
> > +
> > +static const uint32_t write_values[MAX_NUMBER_MOCS_REGISTERS] = {
> > + [0 ... MAX_NUMBER_MOCS_REGISTERS - 1] = 0xFFFFFFFF,
> > };
> > static bool get_mocs_settings(int fd, struct mocs_table *table, bool dirty)
> > @@ -127,6 +160,15 @@ static bool get_mocs_settings(int fd, struct mocs_table *table, bool dirty)
> > table->table = broxton_mocs_table;
> > }
> > result = true;
> > + } else if (IS_ICELAKE(devid)) {
> > + if (dirty) {
> > + table->size = ARRAY_SIZE(dirty_icelake_mocs_table);
> > + table->table = dirty_icelake_mocs_table;
> > + } else {
> > + table->size = ARRAY_SIZE(icelake_mocs_table);
> > + table->table = icelake_mocs_table;
> > + }
> > + result = true;
> > }
> > return result;
> > @@ -374,13 +416,21 @@ static void check_mocs_values(int fd, unsigned engine, uint32_t ctx_id, bool dir
> > static void write_dirty_mocs(int fd, unsigned engine, uint32_t ctx_id)
> > {
> > + uint32_t devid = intel_get_drm_devid(fd);
> > + int num_of_mocs_entries;
> > +
> > + if (IS_ICELAKE(devid))
> > + num_of_mocs_entries = GEN11_NUM_MOCS_ENTRIES;
> > + else
> > + num_of_mocs_entries = GEN9_NUM_MOCS_ENTRIES;
> > +
> > write_registers(fd, ctx_id, get_engine_base(engine),
> > - write_values, ARRAY_SIZE(write_values),
> > + write_values, num_of_mocs_entries,
> > engine);
> > if (engine == I915_EXEC_RENDER)
> > write_registers(fd, ctx_id, GEN9_LNCFCMOCS0,
> > - write_values, ARRAY_SIZE(write_values),
> > + write_values, num_of_mocs_entries/2,
> > engine);
> > }
> The "-dirty" subcase of the test doesn't seem suitable to current hardware..
>
> The table is now global. So writing it from one context and checking if
> another context is unaffected is bound to fail.
>
> Shouldn't the test for gen11+ be restricted to reading the values and
> checking whether they match pre-defined array?
> (we may still do a test if everything is fine after reset/suspend, that
> won't hurt)
> And if we are writing dirty values, shouldn't there be a restoration to
> original values afterwards?
>
> -Tomasz
I am observing following behaviour on Icelake platform
"-dirty" subcase of the test fails in checking l3 control register.
Tomasz mentioned that the table is now golbal. However, for control
registers(LLC/eDRAM), the context is getting saved and restored
between contexts like the Gen9. If the table was global this shouldn't
be the expected behaviour. Also i don't see a reference in bspec which
stated mocs table is global for GEN11+.
Now for L3 control registers the behaviour is different. This is where
test is failing in "-dirty" subcase. For L3 control registers, writing
dirty values are somehow ignored by the hardware. So checking the L3
Control registers after writing the dirty values fails.
-Prathap
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v2] i915/gem_mocs_settings: Add mocs table for icelake
2019-02-22 21:32 ` Kumar Valsan, Prathap
@ 2019-02-22 21:48 ` Chris Wilson
2019-02-25 13:17 ` Lis, Tomasz
0 siblings, 1 reply; 12+ messages in thread
From: Chris Wilson @ 2019-02-22 21:48 UTC (permalink / raw)
To: Kumar Valsan, Prathap; +Cc: igt-dev, Lucas De Marchi
Quoting Kumar Valsan, Prathap (2019-02-22 21:32:55)
> On Fri, Feb 22, 2019 at 03:21:18PM +0000, Chris Wilson wrote:
> > Quoting Lis, Tomasz (2019-02-22 15:17:34)
> > >
> > >
> > > On 2019-02-22 15:17, Prathap Kumar Valsan wrote:
> > > > From: "Kumar Valsan, Prathap" <prathap.kumar.valsan@intel.com>
> > > >
> > > > This patch adds mocs table for icelake with expected L3 and eDRAM
> > > > control values.
> > > >
> > > > Signed-off-by: Kumar Valsan, Prathap <prathap.kumar.valsan@intel.com>
> > > > ---
> > > > Changes in v2:
> > > > - Cleaned up the code based on review comments from Lucas and Chris
> > > > tests/i915/gem_mocs_settings.c | 96 ++++++++++++++++++++++++++--------
> > > > 1 file changed, 73 insertions(+), 23 deletions(-)
> > > >
> > > > diff --git a/tests/i915/gem_mocs_settings.c b/tests/i915/gem_mocs_settings.c
> > > > index 5b3b6bc1..6d111076 100644
> > > > --- a/tests/i915/gem_mocs_settings.c
> > > > +++ b/tests/i915/gem_mocs_settings.c
> > > > @@ -33,6 +33,9 @@
> > > > #include "igt_sysfs.h"
> > > >
> > > > #define MAX_NUMBER_MOCS_REGISTERS (64)
> > > > +#define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */
> > > > +#define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
> > > > +
> > > > enum {
> > > > NONE,
> > > > RESET,
> > > > @@ -72,36 +75,66 @@ struct mocs_table {
> > > > const struct mocs_entry *table;
> > > > };
> > > >
> > > > +static const struct mocs_entry icelake_mocs_pte = {0x00000004, 0x0030};
> > > > +static const struct mocs_entry mocs_pte = {0x00000038, 0x0030};
> > > > +
> > > > /* The first entries in the MOCS tables are defined by uABI */
> > > > -static const struct mocs_entry skylake_mocs_table[] = {
> > > > - { 0x00000009, 0x0010 },
> > > > - { 0x00000038, 0x0030 },
> > > > - { 0x0000003b, 0x0030 },
> > > > +static const struct mocs_entry icelake_mocs_table[GEN11_NUM_MOCS_ENTRIES] = {
> > > > + [0 ... GEN11_NUM_MOCS_ENTRIES - 1] = icelake_mocs_pte,
> > > > + [0] = { 0x00000005, 0x0010},
> > > > + [1] = { 0x00000004, 0x0030},
> > > > + [2] = { 0x00000037, 0x0030},
> > > > + [3] = { 0x00000005, 0x0010},
> > > > + [4] = { 0x00000005, 0x0030},
> > > > + [5] = { 0x00000037, 0x0010},
> > > > + [6] = { 0x00000017, 0x0010},
> > > > + [7] = { 0x00000017, 0x0030},
> > > > + [8] = { 0x00000027, 0x0010},
> > > > + [9] = { 0x00000027, 0x0030},
> > > > + [10] = { 0x00000077, 0x0010},
> > > > + [11] = { 0x00000077, 0x0030},
> > > > + [12] = { 0x00000057, 0x0010},
> > > > + [13] = { 0x00000057, 0x0030},
> > > > + [14] = { 0x00000067, 0x0010},
> > > > + [15] = { 0x00000067, 0x0030},
> > > > + [18] = { 0x00060037, 0x0030},
> > > > + [19] = { 0x00000737, 0x0030},
> > > > + [20] = { 0x00000337, 0x0030},
> > > > + [21] = { 0x00000137, 0x0030},
> > > > + [22] = { 0x000003b7, 0x0030},
> > > > + [23] = { 0x000007b7, 0x0030},
> > > > + [62] = { 0x00000037, 0x0010},
> > > > + [63] = { 0x00000037, 0x0010},
> > > > +};
> > > > +
> > > > +static const struct mocs_entry dirty_icelake_mocs_table[GEN11_NUM_MOCS_ENTRIES] = {
> > > > + [0 ... GEN11_NUM_MOCS_ENTRIES - 1] = { 0x0007FFFF, 0x003F },
> > > > };
> > > >
> > > > -static const struct mocs_entry dirty_skylake_mocs_table[] = {
> > > > - { 0x00003FFF, 0x003F }, /* no snoop bit */
> > > > - { 0x00003FFF, 0x003F },
> > > > - { 0x00003FFF, 0x003F },
> > > > +static const struct mocs_entry skylake_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
> > > > + [0 ... GEN9_NUM_MOCS_ENTRIES - 1] = mocs_pte,
> > > > + [0] = { 0x00000009, 0x0010},
> > > > + [1] = { 0x00000038, 0x0030},
> > > > + [2] = { 0x0000003b, 0x0030},
> > > > };
> > > >
> > > > -static const struct mocs_entry broxton_mocs_table[] = {
> > > > - { 0x00000009, 0x0010 },
> > > > - { 0x00000038, 0x0030 },
> > > > - { 0x00000039, 0x0030 },
> > > > +static const struct mocs_entry dirty_skylake_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
> > > > + [0 ... GEN9_NUM_MOCS_ENTRIES - 1] = { 0x00003FFF, 0x003F },
> > > > };
> > > >
> > > > -static const struct mocs_entry dirty_broxton_mocs_table[] = {
> > > > - { 0x00007FFF, 0x003F },
> > > > - { 0x00007FFF, 0x003F },
> > > > - { 0x00007FFF, 0x003F },
> > > > +static const struct mocs_entry broxton_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
> > > > + [0 ... GEN9_NUM_MOCS_ENTRIES - 1] = mocs_pte,
> > > > + [0] = { 0x00000009, 0x0010},
> > > > + [1] = { 0x00000038, 0x0030},
> > > > + [2] = { 0x00000039, 0x0030},
> > > > };
> > > >
> > > > -static const uint32_t write_values[] = {
> > > > - 0xFFFFFFFF,
> > > > - 0xFFFFFFFF,
> > > > - 0xFFFFFFFF,
> > > > - 0xFFFFFFFF
> > > > +static const struct mocs_entry dirty_broxton_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
> > > > + [0 ... GEN9_NUM_MOCS_ENTRIES - 1] = { 0x00007FFF, 0x003F },
> > > > +};
> > > > +
> > > > +static const uint32_t write_values[MAX_NUMBER_MOCS_REGISTERS] = {
> > > > + [0 ... MAX_NUMBER_MOCS_REGISTERS - 1] = 0xFFFFFFFF,
> > > > };
> > > >
> > > > static bool get_mocs_settings(int fd, struct mocs_table *table, bool dirty)
> > > > @@ -127,6 +160,15 @@ static bool get_mocs_settings(int fd, struct mocs_table *table, bool dirty)
> > > > table->table = broxton_mocs_table;
> > > > }
> > > > result = true;
> > > > + } else if (IS_ICELAKE(devid)) {
> > > > + if (dirty) {
> > > > + table->size = ARRAY_SIZE(dirty_icelake_mocs_table);
> > > > + table->table = dirty_icelake_mocs_table;
> > > > + } else {
> > > > + table->size = ARRAY_SIZE(icelake_mocs_table);
> > > > + table->table = icelake_mocs_table;
> > > > + }
> > > > + result = true;
> > > > }
> > > >
> > > > return result;
> > > > @@ -374,13 +416,21 @@ static void check_mocs_values(int fd, unsigned engine, uint32_t ctx_id, bool dir
> > > >
> > > > static void write_dirty_mocs(int fd, unsigned engine, uint32_t ctx_id)
> > > > {
> > > > + uint32_t devid = intel_get_drm_devid(fd);
> > > > + int num_of_mocs_entries;
> > > > +
> > > > + if (IS_ICELAKE(devid))
> > > > + num_of_mocs_entries = GEN11_NUM_MOCS_ENTRIES;
> > > > + else
> > > > + num_of_mocs_entries = GEN9_NUM_MOCS_ENTRIES;
> > > > +
> > > > write_registers(fd, ctx_id, get_engine_base(engine),
> > > > - write_values, ARRAY_SIZE(write_values),
> > > > + write_values, num_of_mocs_entries,
> > > > engine);
> > > >
> > > > if (engine == I915_EXEC_RENDER)
> > > > write_registers(fd, ctx_id, GEN9_LNCFCMOCS0,
> > > > - write_values, ARRAY_SIZE(write_values),
> > > > + write_values, num_of_mocs_entries/2,
> > > > engine);
> > > > }
> > > >
> > > The "-dirty" subcase of the test doesn't seem suitable to current hardware..
> > >
> > > The table is now global. So writing it from one context and checking if
> > > another context is unaffected is bound to fail.
> As you pointed out On Gen11, "-dirty" subcases are failing.
> Test is not able to write to registers.
> >
> > We shouldn't be able to do nonpriv writes to it then. Hopefully those
> > writes are already being dropped?
> So probably on latest hardware, test should still try to write and call
> it pass if the dirty values are not being written?
Yes, that would be useful confirmation that one context can't shoot
another in the back, and that our global MOCS table remain invariant.
-Chris
_______________________________________________
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v2] i915/gem_mocs_settings: Add mocs table for icelake
2019-02-22 15:21 ` Chris Wilson
@ 2019-02-22 21:32 ` Kumar Valsan, Prathap
2019-02-22 21:48 ` Chris Wilson
0 siblings, 1 reply; 12+ messages in thread
From: Kumar Valsan, Prathap @ 2019-02-22 21:32 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev, Lucas De Marchi
On Fri, Feb 22, 2019 at 03:21:18PM +0000, Chris Wilson wrote:
> Quoting Lis, Tomasz (2019-02-22 15:17:34)
> >
> >
> > On 2019-02-22 15:17, Prathap Kumar Valsan wrote:
> > > From: "Kumar Valsan, Prathap" <prathap.kumar.valsan@intel.com>
> > >
> > > This patch adds mocs table for icelake with expected L3 and eDRAM
> > > control values.
> > >
> > > Signed-off-by: Kumar Valsan, Prathap <prathap.kumar.valsan@intel.com>
> > > ---
> > > Changes in v2:
> > > - Cleaned up the code based on review comments from Lucas and Chris
> > > tests/i915/gem_mocs_settings.c | 96 ++++++++++++++++++++++++++--------
> > > 1 file changed, 73 insertions(+), 23 deletions(-)
> > >
> > > diff --git a/tests/i915/gem_mocs_settings.c b/tests/i915/gem_mocs_settings.c
> > > index 5b3b6bc1..6d111076 100644
> > > --- a/tests/i915/gem_mocs_settings.c
> > > +++ b/tests/i915/gem_mocs_settings.c
> > > @@ -33,6 +33,9 @@
> > > #include "igt_sysfs.h"
> > >
> > > #define MAX_NUMBER_MOCS_REGISTERS (64)
> > > +#define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */
> > > +#define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
> > > +
> > > enum {
> > > NONE,
> > > RESET,
> > > @@ -72,36 +75,66 @@ struct mocs_table {
> > > const struct mocs_entry *table;
> > > };
> > >
> > > +static const struct mocs_entry icelake_mocs_pte = {0x00000004, 0x0030};
> > > +static const struct mocs_entry mocs_pte = {0x00000038, 0x0030};
> > > +
> > > /* The first entries in the MOCS tables are defined by uABI */
> > > -static const struct mocs_entry skylake_mocs_table[] = {
> > > - { 0x00000009, 0x0010 },
> > > - { 0x00000038, 0x0030 },
> > > - { 0x0000003b, 0x0030 },
> > > +static const struct mocs_entry icelake_mocs_table[GEN11_NUM_MOCS_ENTRIES] = {
> > > + [0 ... GEN11_NUM_MOCS_ENTRIES - 1] = icelake_mocs_pte,
> > > + [0] = { 0x00000005, 0x0010},
> > > + [1] = { 0x00000004, 0x0030},
> > > + [2] = { 0x00000037, 0x0030},
> > > + [3] = { 0x00000005, 0x0010},
> > > + [4] = { 0x00000005, 0x0030},
> > > + [5] = { 0x00000037, 0x0010},
> > > + [6] = { 0x00000017, 0x0010},
> > > + [7] = { 0x00000017, 0x0030},
> > > + [8] = { 0x00000027, 0x0010},
> > > + [9] = { 0x00000027, 0x0030},
> > > + [10] = { 0x00000077, 0x0010},
> > > + [11] = { 0x00000077, 0x0030},
> > > + [12] = { 0x00000057, 0x0010},
> > > + [13] = { 0x00000057, 0x0030},
> > > + [14] = { 0x00000067, 0x0010},
> > > + [15] = { 0x00000067, 0x0030},
> > > + [18] = { 0x00060037, 0x0030},
> > > + [19] = { 0x00000737, 0x0030},
> > > + [20] = { 0x00000337, 0x0030},
> > > + [21] = { 0x00000137, 0x0030},
> > > + [22] = { 0x000003b7, 0x0030},
> > > + [23] = { 0x000007b7, 0x0030},
> > > + [62] = { 0x00000037, 0x0010},
> > > + [63] = { 0x00000037, 0x0010},
> > > +};
> > > +
> > > +static const struct mocs_entry dirty_icelake_mocs_table[GEN11_NUM_MOCS_ENTRIES] = {
> > > + [0 ... GEN11_NUM_MOCS_ENTRIES - 1] = { 0x0007FFFF, 0x003F },
> > > };
> > >
> > > -static const struct mocs_entry dirty_skylake_mocs_table[] = {
> > > - { 0x00003FFF, 0x003F }, /* no snoop bit */
> > > - { 0x00003FFF, 0x003F },
> > > - { 0x00003FFF, 0x003F },
> > > +static const struct mocs_entry skylake_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
> > > + [0 ... GEN9_NUM_MOCS_ENTRIES - 1] = mocs_pte,
> > > + [0] = { 0x00000009, 0x0010},
> > > + [1] = { 0x00000038, 0x0030},
> > > + [2] = { 0x0000003b, 0x0030},
> > > };
> > >
> > > -static const struct mocs_entry broxton_mocs_table[] = {
> > > - { 0x00000009, 0x0010 },
> > > - { 0x00000038, 0x0030 },
> > > - { 0x00000039, 0x0030 },
> > > +static const struct mocs_entry dirty_skylake_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
> > > + [0 ... GEN9_NUM_MOCS_ENTRIES - 1] = { 0x00003FFF, 0x003F },
> > > };
> > >
> > > -static const struct mocs_entry dirty_broxton_mocs_table[] = {
> > > - { 0x00007FFF, 0x003F },
> > > - { 0x00007FFF, 0x003F },
> > > - { 0x00007FFF, 0x003F },
> > > +static const struct mocs_entry broxton_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
> > > + [0 ... GEN9_NUM_MOCS_ENTRIES - 1] = mocs_pte,
> > > + [0] = { 0x00000009, 0x0010},
> > > + [1] = { 0x00000038, 0x0030},
> > > + [2] = { 0x00000039, 0x0030},
> > > };
> > >
> > > -static const uint32_t write_values[] = {
> > > - 0xFFFFFFFF,
> > > - 0xFFFFFFFF,
> > > - 0xFFFFFFFF,
> > > - 0xFFFFFFFF
> > > +static const struct mocs_entry dirty_broxton_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
> > > + [0 ... GEN9_NUM_MOCS_ENTRIES - 1] = { 0x00007FFF, 0x003F },
> > > +};
> > > +
> > > +static const uint32_t write_values[MAX_NUMBER_MOCS_REGISTERS] = {
> > > + [0 ... MAX_NUMBER_MOCS_REGISTERS - 1] = 0xFFFFFFFF,
> > > };
> > >
> > > static bool get_mocs_settings(int fd, struct mocs_table *table, bool dirty)
> > > @@ -127,6 +160,15 @@ static bool get_mocs_settings(int fd, struct mocs_table *table, bool dirty)
> > > table->table = broxton_mocs_table;
> > > }
> > > result = true;
> > > + } else if (IS_ICELAKE(devid)) {
> > > + if (dirty) {
> > > + table->size = ARRAY_SIZE(dirty_icelake_mocs_table);
> > > + table->table = dirty_icelake_mocs_table;
> > > + } else {
> > > + table->size = ARRAY_SIZE(icelake_mocs_table);
> > > + table->table = icelake_mocs_table;
> > > + }
> > > + result = true;
> > > }
> > >
> > > return result;
> > > @@ -374,13 +416,21 @@ static void check_mocs_values(int fd, unsigned engine, uint32_t ctx_id, bool dir
> > >
> > > static void write_dirty_mocs(int fd, unsigned engine, uint32_t ctx_id)
> > > {
> > > + uint32_t devid = intel_get_drm_devid(fd);
> > > + int num_of_mocs_entries;
> > > +
> > > + if (IS_ICELAKE(devid))
> > > + num_of_mocs_entries = GEN11_NUM_MOCS_ENTRIES;
> > > + else
> > > + num_of_mocs_entries = GEN9_NUM_MOCS_ENTRIES;
> > > +
> > > write_registers(fd, ctx_id, get_engine_base(engine),
> > > - write_values, ARRAY_SIZE(write_values),
> > > + write_values, num_of_mocs_entries,
> > > engine);
> > >
> > > if (engine == I915_EXEC_RENDER)
> > > write_registers(fd, ctx_id, GEN9_LNCFCMOCS0,
> > > - write_values, ARRAY_SIZE(write_values),
> > > + write_values, num_of_mocs_entries/2,
> > > engine);
> > > }
> > >
> > The "-dirty" subcase of the test doesn't seem suitable to current hardware..
> >
> > The table is now global. So writing it from one context and checking if
> > another context is unaffected is bound to fail.
As you pointed out On Gen11, "-dirty" subcases are failing.
Test is not able to write to registers.
>
> We shouldn't be able to do nonpriv writes to it then. Hopefully those
> writes are already being dropped?
So probably on latest hardware, test should still try to write and call
it pass if the dirty values are not being written?
> -Chris
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v2] i915/gem_mocs_settings: Add mocs table for icelake
2019-02-22 15:17 ` Lis, Tomasz
@ 2019-02-22 15:21 ` Chris Wilson
2019-02-22 21:32 ` Kumar Valsan, Prathap
2019-02-25 0:26 ` Kumar Valsan, Prathap
1 sibling, 1 reply; 12+ messages in thread
From: Chris Wilson @ 2019-02-22 15:21 UTC (permalink / raw)
To: Lis, Tomasz, Prathap Kumar Valsan, igt-dev; +Cc: Lucas De Marchi
Quoting Lis, Tomasz (2019-02-22 15:17:34)
>
>
> On 2019-02-22 15:17, Prathap Kumar Valsan wrote:
> > From: "Kumar Valsan, Prathap" <prathap.kumar.valsan@intel.com>
> >
> > This patch adds mocs table for icelake with expected L3 and eDRAM
> > control values.
> >
> > Signed-off-by: Kumar Valsan, Prathap <prathap.kumar.valsan@intel.com>
> > ---
> > Changes in v2:
> > - Cleaned up the code based on review comments from Lucas and Chris
> > tests/i915/gem_mocs_settings.c | 96 ++++++++++++++++++++++++++--------
> > 1 file changed, 73 insertions(+), 23 deletions(-)
> >
> > diff --git a/tests/i915/gem_mocs_settings.c b/tests/i915/gem_mocs_settings.c
> > index 5b3b6bc1..6d111076 100644
> > --- a/tests/i915/gem_mocs_settings.c
> > +++ b/tests/i915/gem_mocs_settings.c
> > @@ -33,6 +33,9 @@
> > #include "igt_sysfs.h"
> >
> > #define MAX_NUMBER_MOCS_REGISTERS (64)
> > +#define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */
> > +#define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
> > +
> > enum {
> > NONE,
> > RESET,
> > @@ -72,36 +75,66 @@ struct mocs_table {
> > const struct mocs_entry *table;
> > };
> >
> > +static const struct mocs_entry icelake_mocs_pte = {0x00000004, 0x0030};
> > +static const struct mocs_entry mocs_pte = {0x00000038, 0x0030};
> > +
> > /* The first entries in the MOCS tables are defined by uABI */
> > -static const struct mocs_entry skylake_mocs_table[] = {
> > - { 0x00000009, 0x0010 },
> > - { 0x00000038, 0x0030 },
> > - { 0x0000003b, 0x0030 },
> > +static const struct mocs_entry icelake_mocs_table[GEN11_NUM_MOCS_ENTRIES] = {
> > + [0 ... GEN11_NUM_MOCS_ENTRIES - 1] = icelake_mocs_pte,
> > + [0] = { 0x00000005, 0x0010},
> > + [1] = { 0x00000004, 0x0030},
> > + [2] = { 0x00000037, 0x0030},
> > + [3] = { 0x00000005, 0x0010},
> > + [4] = { 0x00000005, 0x0030},
> > + [5] = { 0x00000037, 0x0010},
> > + [6] = { 0x00000017, 0x0010},
> > + [7] = { 0x00000017, 0x0030},
> > + [8] = { 0x00000027, 0x0010},
> > + [9] = { 0x00000027, 0x0030},
> > + [10] = { 0x00000077, 0x0010},
> > + [11] = { 0x00000077, 0x0030},
> > + [12] = { 0x00000057, 0x0010},
> > + [13] = { 0x00000057, 0x0030},
> > + [14] = { 0x00000067, 0x0010},
> > + [15] = { 0x00000067, 0x0030},
> > + [18] = { 0x00060037, 0x0030},
> > + [19] = { 0x00000737, 0x0030},
> > + [20] = { 0x00000337, 0x0030},
> > + [21] = { 0x00000137, 0x0030},
> > + [22] = { 0x000003b7, 0x0030},
> > + [23] = { 0x000007b7, 0x0030},
> > + [62] = { 0x00000037, 0x0010},
> > + [63] = { 0x00000037, 0x0010},
> > +};
> > +
> > +static const struct mocs_entry dirty_icelake_mocs_table[GEN11_NUM_MOCS_ENTRIES] = {
> > + [0 ... GEN11_NUM_MOCS_ENTRIES - 1] = { 0x0007FFFF, 0x003F },
> > };
> >
> > -static const struct mocs_entry dirty_skylake_mocs_table[] = {
> > - { 0x00003FFF, 0x003F }, /* no snoop bit */
> > - { 0x00003FFF, 0x003F },
> > - { 0x00003FFF, 0x003F },
> > +static const struct mocs_entry skylake_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
> > + [0 ... GEN9_NUM_MOCS_ENTRIES - 1] = mocs_pte,
> > + [0] = { 0x00000009, 0x0010},
> > + [1] = { 0x00000038, 0x0030},
> > + [2] = { 0x0000003b, 0x0030},
> > };
> >
> > -static const struct mocs_entry broxton_mocs_table[] = {
> > - { 0x00000009, 0x0010 },
> > - { 0x00000038, 0x0030 },
> > - { 0x00000039, 0x0030 },
> > +static const struct mocs_entry dirty_skylake_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
> > + [0 ... GEN9_NUM_MOCS_ENTRIES - 1] = { 0x00003FFF, 0x003F },
> > };
> >
> > -static const struct mocs_entry dirty_broxton_mocs_table[] = {
> > - { 0x00007FFF, 0x003F },
> > - { 0x00007FFF, 0x003F },
> > - { 0x00007FFF, 0x003F },
> > +static const struct mocs_entry broxton_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
> > + [0 ... GEN9_NUM_MOCS_ENTRIES - 1] = mocs_pte,
> > + [0] = { 0x00000009, 0x0010},
> > + [1] = { 0x00000038, 0x0030},
> > + [2] = { 0x00000039, 0x0030},
> > };
> >
> > -static const uint32_t write_values[] = {
> > - 0xFFFFFFFF,
> > - 0xFFFFFFFF,
> > - 0xFFFFFFFF,
> > - 0xFFFFFFFF
> > +static const struct mocs_entry dirty_broxton_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
> > + [0 ... GEN9_NUM_MOCS_ENTRIES - 1] = { 0x00007FFF, 0x003F },
> > +};
> > +
> > +static const uint32_t write_values[MAX_NUMBER_MOCS_REGISTERS] = {
> > + [0 ... MAX_NUMBER_MOCS_REGISTERS - 1] = 0xFFFFFFFF,
> > };
> >
> > static bool get_mocs_settings(int fd, struct mocs_table *table, bool dirty)
> > @@ -127,6 +160,15 @@ static bool get_mocs_settings(int fd, struct mocs_table *table, bool dirty)
> > table->table = broxton_mocs_table;
> > }
> > result = true;
> > + } else if (IS_ICELAKE(devid)) {
> > + if (dirty) {
> > + table->size = ARRAY_SIZE(dirty_icelake_mocs_table);
> > + table->table = dirty_icelake_mocs_table;
> > + } else {
> > + table->size = ARRAY_SIZE(icelake_mocs_table);
> > + table->table = icelake_mocs_table;
> > + }
> > + result = true;
> > }
> >
> > return result;
> > @@ -374,13 +416,21 @@ static void check_mocs_values(int fd, unsigned engine, uint32_t ctx_id, bool dir
> >
> > static void write_dirty_mocs(int fd, unsigned engine, uint32_t ctx_id)
> > {
> > + uint32_t devid = intel_get_drm_devid(fd);
> > + int num_of_mocs_entries;
> > +
> > + if (IS_ICELAKE(devid))
> > + num_of_mocs_entries = GEN11_NUM_MOCS_ENTRIES;
> > + else
> > + num_of_mocs_entries = GEN9_NUM_MOCS_ENTRIES;
> > +
> > write_registers(fd, ctx_id, get_engine_base(engine),
> > - write_values, ARRAY_SIZE(write_values),
> > + write_values, num_of_mocs_entries,
> > engine);
> >
> > if (engine == I915_EXEC_RENDER)
> > write_registers(fd, ctx_id, GEN9_LNCFCMOCS0,
> > - write_values, ARRAY_SIZE(write_values),
> > + write_values, num_of_mocs_entries/2,
> > engine);
> > }
> >
> The "-dirty" subcase of the test doesn't seem suitable to current hardware..
>
> The table is now global. So writing it from one context and checking if
> another context is unaffected is bound to fail.
We shouldn't be able to do nonpriv writes to it then. Hopefully those
writes are already being dropped?
-Chris
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v2] i915/gem_mocs_settings: Add mocs table for icelake
2019-02-22 14:17 ` [igt-dev] [PATCH i-g-t v2] " Prathap Kumar Valsan
@ 2019-02-22 15:17 ` Lis, Tomasz
2019-02-22 15:21 ` Chris Wilson
2019-02-25 0:26 ` Kumar Valsan, Prathap
0 siblings, 2 replies; 12+ messages in thread
From: Lis, Tomasz @ 2019-02-22 15:17 UTC (permalink / raw)
To: Prathap Kumar Valsan, igt-dev; +Cc: Lucas De Marchi
On 2019-02-22 15:17, Prathap Kumar Valsan wrote:
> From: "Kumar Valsan, Prathap" <prathap.kumar.valsan@intel.com>
>
> This patch adds mocs table for icelake with expected L3 and eDRAM
> control values.
>
> Signed-off-by: Kumar Valsan, Prathap <prathap.kumar.valsan@intel.com>
> ---
> Changes in v2:
> - Cleaned up the code based on review comments from Lucas and Chris
> tests/i915/gem_mocs_settings.c | 96 ++++++++++++++++++++++++++--------
> 1 file changed, 73 insertions(+), 23 deletions(-)
>
> diff --git a/tests/i915/gem_mocs_settings.c b/tests/i915/gem_mocs_settings.c
> index 5b3b6bc1..6d111076 100644
> --- a/tests/i915/gem_mocs_settings.c
> +++ b/tests/i915/gem_mocs_settings.c
> @@ -33,6 +33,9 @@
> #include "igt_sysfs.h"
>
> #define MAX_NUMBER_MOCS_REGISTERS (64)
> +#define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */
> +#define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
> +
> enum {
> NONE,
> RESET,
> @@ -72,36 +75,66 @@ struct mocs_table {
> const struct mocs_entry *table;
> };
>
> +static const struct mocs_entry icelake_mocs_pte = {0x00000004, 0x0030};
> +static const struct mocs_entry mocs_pte = {0x00000038, 0x0030};
> +
> /* The first entries in the MOCS tables are defined by uABI */
> -static const struct mocs_entry skylake_mocs_table[] = {
> - { 0x00000009, 0x0010 },
> - { 0x00000038, 0x0030 },
> - { 0x0000003b, 0x0030 },
> +static const struct mocs_entry icelake_mocs_table[GEN11_NUM_MOCS_ENTRIES] = {
> + [0 ... GEN11_NUM_MOCS_ENTRIES - 1] = icelake_mocs_pte,
> + [0] = { 0x00000005, 0x0010},
> + [1] = { 0x00000004, 0x0030},
> + [2] = { 0x00000037, 0x0030},
> + [3] = { 0x00000005, 0x0010},
> + [4] = { 0x00000005, 0x0030},
> + [5] = { 0x00000037, 0x0010},
> + [6] = { 0x00000017, 0x0010},
> + [7] = { 0x00000017, 0x0030},
> + [8] = { 0x00000027, 0x0010},
> + [9] = { 0x00000027, 0x0030},
> + [10] = { 0x00000077, 0x0010},
> + [11] = { 0x00000077, 0x0030},
> + [12] = { 0x00000057, 0x0010},
> + [13] = { 0x00000057, 0x0030},
> + [14] = { 0x00000067, 0x0010},
> + [15] = { 0x00000067, 0x0030},
> + [18] = { 0x00060037, 0x0030},
> + [19] = { 0x00000737, 0x0030},
> + [20] = { 0x00000337, 0x0030},
> + [21] = { 0x00000137, 0x0030},
> + [22] = { 0x000003b7, 0x0030},
> + [23] = { 0x000007b7, 0x0030},
> + [62] = { 0x00000037, 0x0010},
> + [63] = { 0x00000037, 0x0010},
> +};
> +
> +static const struct mocs_entry dirty_icelake_mocs_table[GEN11_NUM_MOCS_ENTRIES] = {
> + [0 ... GEN11_NUM_MOCS_ENTRIES - 1] = { 0x0007FFFF, 0x003F },
> };
>
> -static const struct mocs_entry dirty_skylake_mocs_table[] = {
> - { 0x00003FFF, 0x003F }, /* no snoop bit */
> - { 0x00003FFF, 0x003F },
> - { 0x00003FFF, 0x003F },
> +static const struct mocs_entry skylake_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
> + [0 ... GEN9_NUM_MOCS_ENTRIES - 1] = mocs_pte,
> + [0] = { 0x00000009, 0x0010},
> + [1] = { 0x00000038, 0x0030},
> + [2] = { 0x0000003b, 0x0030},
> };
>
> -static const struct mocs_entry broxton_mocs_table[] = {
> - { 0x00000009, 0x0010 },
> - { 0x00000038, 0x0030 },
> - { 0x00000039, 0x0030 },
> +static const struct mocs_entry dirty_skylake_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
> + [0 ... GEN9_NUM_MOCS_ENTRIES - 1] = { 0x00003FFF, 0x003F },
> };
>
> -static const struct mocs_entry dirty_broxton_mocs_table[] = {
> - { 0x00007FFF, 0x003F },
> - { 0x00007FFF, 0x003F },
> - { 0x00007FFF, 0x003F },
> +static const struct mocs_entry broxton_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
> + [0 ... GEN9_NUM_MOCS_ENTRIES - 1] = mocs_pte,
> + [0] = { 0x00000009, 0x0010},
> + [1] = { 0x00000038, 0x0030},
> + [2] = { 0x00000039, 0x0030},
> };
>
> -static const uint32_t write_values[] = {
> - 0xFFFFFFFF,
> - 0xFFFFFFFF,
> - 0xFFFFFFFF,
> - 0xFFFFFFFF
> +static const struct mocs_entry dirty_broxton_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
> + [0 ... GEN9_NUM_MOCS_ENTRIES - 1] = { 0x00007FFF, 0x003F },
> +};
> +
> +static const uint32_t write_values[MAX_NUMBER_MOCS_REGISTERS] = {
> + [0 ... MAX_NUMBER_MOCS_REGISTERS - 1] = 0xFFFFFFFF,
> };
>
> static bool get_mocs_settings(int fd, struct mocs_table *table, bool dirty)
> @@ -127,6 +160,15 @@ static bool get_mocs_settings(int fd, struct mocs_table *table, bool dirty)
> table->table = broxton_mocs_table;
> }
> result = true;
> + } else if (IS_ICELAKE(devid)) {
> + if (dirty) {
> + table->size = ARRAY_SIZE(dirty_icelake_mocs_table);
> + table->table = dirty_icelake_mocs_table;
> + } else {
> + table->size = ARRAY_SIZE(icelake_mocs_table);
> + table->table = icelake_mocs_table;
> + }
> + result = true;
> }
>
> return result;
> @@ -374,13 +416,21 @@ static void check_mocs_values(int fd, unsigned engine, uint32_t ctx_id, bool dir
>
> static void write_dirty_mocs(int fd, unsigned engine, uint32_t ctx_id)
> {
> + uint32_t devid = intel_get_drm_devid(fd);
> + int num_of_mocs_entries;
> +
> + if (IS_ICELAKE(devid))
> + num_of_mocs_entries = GEN11_NUM_MOCS_ENTRIES;
> + else
> + num_of_mocs_entries = GEN9_NUM_MOCS_ENTRIES;
> +
> write_registers(fd, ctx_id, get_engine_base(engine),
> - write_values, ARRAY_SIZE(write_values),
> + write_values, num_of_mocs_entries,
> engine);
>
> if (engine == I915_EXEC_RENDER)
> write_registers(fd, ctx_id, GEN9_LNCFCMOCS0,
> - write_values, ARRAY_SIZE(write_values),
> + write_values, num_of_mocs_entries/2,
> engine);
> }
>
The "-dirty" subcase of the test doesn't seem suitable to current hardware..
The table is now global. So writing it from one context and checking if
another context is unaffected is bound to fail.
Shouldn't the test for gen11+ be restricted to reading the values and
checking whether they match pre-defined array?
(we may still do a test if everything is fine after reset/suspend, that
won't hurt)
And if we are writing dirty values, shouldn't there be a restoration to
original values afterwards?
-Tomasz
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https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 12+ messages in thread
* [igt-dev] [PATCH i-g-t v2] i915/gem_mocs_settings: Add mocs table for icelake
2019-02-15 21:46 [igt-dev] [PATCH i-g-t] " Prathap Kumar Valsan via igt-dev
@ 2019-02-22 14:17 ` Prathap Kumar Valsan
2019-02-22 15:17 ` Lis, Tomasz
0 siblings, 1 reply; 12+ messages in thread
From: Prathap Kumar Valsan @ 2019-02-22 14:17 UTC (permalink / raw)
To: igt-dev; +Cc: Lucas De Marchi
From: "Kumar Valsan, Prathap" <prathap.kumar.valsan@intel.com>
This patch adds mocs table for icelake with expected L3 and eDRAM
control values.
Signed-off-by: Kumar Valsan, Prathap <prathap.kumar.valsan@intel.com>
---
Changes in v2:
- Cleaned up the code based on review comments from Lucas and Chris
tests/i915/gem_mocs_settings.c | 96 ++++++++++++++++++++++++++--------
1 file changed, 73 insertions(+), 23 deletions(-)
diff --git a/tests/i915/gem_mocs_settings.c b/tests/i915/gem_mocs_settings.c
index 5b3b6bc1..6d111076 100644
--- a/tests/i915/gem_mocs_settings.c
+++ b/tests/i915/gem_mocs_settings.c
@@ -33,6 +33,9 @@
#include "igt_sysfs.h"
#define MAX_NUMBER_MOCS_REGISTERS (64)
+#define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */
+#define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
+
enum {
NONE,
RESET,
@@ -72,36 +75,66 @@ struct mocs_table {
const struct mocs_entry *table;
};
+static const struct mocs_entry icelake_mocs_pte = {0x00000004, 0x0030};
+static const struct mocs_entry mocs_pte = {0x00000038, 0x0030};
+
/* The first entries in the MOCS tables are defined by uABI */
-static const struct mocs_entry skylake_mocs_table[] = {
- { 0x00000009, 0x0010 },
- { 0x00000038, 0x0030 },
- { 0x0000003b, 0x0030 },
+static const struct mocs_entry icelake_mocs_table[GEN11_NUM_MOCS_ENTRIES] = {
+ [0 ... GEN11_NUM_MOCS_ENTRIES - 1] = icelake_mocs_pte,
+ [0] = { 0x00000005, 0x0010},
+ [1] = { 0x00000004, 0x0030},
+ [2] = { 0x00000037, 0x0030},
+ [3] = { 0x00000005, 0x0010},
+ [4] = { 0x00000005, 0x0030},
+ [5] = { 0x00000037, 0x0010},
+ [6] = { 0x00000017, 0x0010},
+ [7] = { 0x00000017, 0x0030},
+ [8] = { 0x00000027, 0x0010},
+ [9] = { 0x00000027, 0x0030},
+ [10] = { 0x00000077, 0x0010},
+ [11] = { 0x00000077, 0x0030},
+ [12] = { 0x00000057, 0x0010},
+ [13] = { 0x00000057, 0x0030},
+ [14] = { 0x00000067, 0x0010},
+ [15] = { 0x00000067, 0x0030},
+ [18] = { 0x00060037, 0x0030},
+ [19] = { 0x00000737, 0x0030},
+ [20] = { 0x00000337, 0x0030},
+ [21] = { 0x00000137, 0x0030},
+ [22] = { 0x000003b7, 0x0030},
+ [23] = { 0x000007b7, 0x0030},
+ [62] = { 0x00000037, 0x0010},
+ [63] = { 0x00000037, 0x0010},
+};
+
+static const struct mocs_entry dirty_icelake_mocs_table[GEN11_NUM_MOCS_ENTRIES] = {
+ [0 ... GEN11_NUM_MOCS_ENTRIES - 1] = { 0x0007FFFF, 0x003F },
};
-static const struct mocs_entry dirty_skylake_mocs_table[] = {
- { 0x00003FFF, 0x003F }, /* no snoop bit */
- { 0x00003FFF, 0x003F },
- { 0x00003FFF, 0x003F },
+static const struct mocs_entry skylake_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
+ [0 ... GEN9_NUM_MOCS_ENTRIES - 1] = mocs_pte,
+ [0] = { 0x00000009, 0x0010},
+ [1] = { 0x00000038, 0x0030},
+ [2] = { 0x0000003b, 0x0030},
};
-static const struct mocs_entry broxton_mocs_table[] = {
- { 0x00000009, 0x0010 },
- { 0x00000038, 0x0030 },
- { 0x00000039, 0x0030 },
+static const struct mocs_entry dirty_skylake_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
+ [0 ... GEN9_NUM_MOCS_ENTRIES - 1] = { 0x00003FFF, 0x003F },
};
-static const struct mocs_entry dirty_broxton_mocs_table[] = {
- { 0x00007FFF, 0x003F },
- { 0x00007FFF, 0x003F },
- { 0x00007FFF, 0x003F },
+static const struct mocs_entry broxton_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
+ [0 ... GEN9_NUM_MOCS_ENTRIES - 1] = mocs_pte,
+ [0] = { 0x00000009, 0x0010},
+ [1] = { 0x00000038, 0x0030},
+ [2] = { 0x00000039, 0x0030},
};
-static const uint32_t write_values[] = {
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF,
- 0xFFFFFFFF
+static const struct mocs_entry dirty_broxton_mocs_table[GEN9_NUM_MOCS_ENTRIES] = {
+ [0 ... GEN9_NUM_MOCS_ENTRIES - 1] = { 0x00007FFF, 0x003F },
+};
+
+static const uint32_t write_values[MAX_NUMBER_MOCS_REGISTERS] = {
+ [0 ... MAX_NUMBER_MOCS_REGISTERS - 1] = 0xFFFFFFFF,
};
static bool get_mocs_settings(int fd, struct mocs_table *table, bool dirty)
@@ -127,6 +160,15 @@ static bool get_mocs_settings(int fd, struct mocs_table *table, bool dirty)
table->table = broxton_mocs_table;
}
result = true;
+ } else if (IS_ICELAKE(devid)) {
+ if (dirty) {
+ table->size = ARRAY_SIZE(dirty_icelake_mocs_table);
+ table->table = dirty_icelake_mocs_table;
+ } else {
+ table->size = ARRAY_SIZE(icelake_mocs_table);
+ table->table = icelake_mocs_table;
+ }
+ result = true;
}
return result;
@@ -374,13 +416,21 @@ static void check_mocs_values(int fd, unsigned engine, uint32_t ctx_id, bool dir
static void write_dirty_mocs(int fd, unsigned engine, uint32_t ctx_id)
{
+ uint32_t devid = intel_get_drm_devid(fd);
+ int num_of_mocs_entries;
+
+ if (IS_ICELAKE(devid))
+ num_of_mocs_entries = GEN11_NUM_MOCS_ENTRIES;
+ else
+ num_of_mocs_entries = GEN9_NUM_MOCS_ENTRIES;
+
write_registers(fd, ctx_id, get_engine_base(engine),
- write_values, ARRAY_SIZE(write_values),
+ write_values, num_of_mocs_entries,
engine);
if (engine == I915_EXEC_RENDER)
write_registers(fd, ctx_id, GEN9_LNCFCMOCS0,
- write_values, ARRAY_SIZE(write_values),
+ write_values, num_of_mocs_entries/2,
engine);
}
--
2.20.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
end of thread, other threads:[~2019-02-25 13:17 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-02-09 19:50 [igt-dev] [PATCH i-g-t] i915/gem_mocs_settings: Add mocs table for icelake Prathap Kumar Valsan
2019-02-09 19:55 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork
2019-02-09 21:25 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
2019-02-11 18:39 ` [igt-dev] [PATCH i-g-t] " Lucas De Marchi
2019-02-14 15:46 ` [igt-dev] [PATCH i-g-t v2] " Prathap Kumar Valsan via igt-dev
2019-02-15 21:46 [igt-dev] [PATCH i-g-t] " Prathap Kumar Valsan via igt-dev
2019-02-22 14:17 ` [igt-dev] [PATCH i-g-t v2] " Prathap Kumar Valsan
2019-02-22 15:17 ` Lis, Tomasz
2019-02-22 15:21 ` Chris Wilson
2019-02-22 21:32 ` Kumar Valsan, Prathap
2019-02-22 21:48 ` Chris Wilson
2019-02-25 13:17 ` Lis, Tomasz
2019-02-25 0:26 ` Kumar Valsan, Prathap
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