* [PATCH v3 0/5] PCIE support for i.MX8MQ (DT changes)
@ 2019-02-20 1:58 ` Andrey Smirnov
0 siblings, 0 replies; 14+ messages in thread
From: Andrey Smirnov @ 2019-02-20 1:58 UTC (permalink / raw)
To: Shawn Guo
Cc: A.s. Dong, Richard Zhu, linux-arm-kernel, Andrey Smirnov,
linux-kernel, linux-imx, Fabio Estevam, Leonard Crestez,
Chris Healy, Lucas Stach
Everyone:
This series contains all of the i.MX Device Tree changes I made to
enable support of PCIe on i.MX8MQ EVK.
NOTE: Immutable brach containing imx8mq-reset.h used in "arm64: dts:
Add nodes for PCIe IP blocks" is availible in [reset-imx8mq]
Feedback is welcome!
Changes since [v2]:
- Fixed various nits pointed out by Lucas
- Collected Acked-by and Reviewed-by from Lucas
- Moved EVK's WiFi reset pin configuration into a separate pinmux
entry.
Changes since [v1]:
- Dropped unsupported IRQ from PCIe nodes (a leftover from vendor tree)
- Added "pcie_aux" clock and moved clock configuration to board
file since "pcie_bus" clock is now board specific
Thanks,
Andrey Smirnov
[reset-imx8mq] git://git.pengutronix.de/pza/linux reset/imx8mq
[v1] https://lore.kernel.org/lkml/20190131204333.31846-1-andrew.smirnov@gmail.com/
[v2] https://lore.kernel.org/lkml/20190208002941.30343-1-andrew.smirnov@gmail.com
Andrey Smirnov (5):
arm64: dts: imx8mq: Mark iomuxc_gpr as i.MX6Q compatible
arm64: dts: imx8mq: Add a node for SRC IP block
arm64: dts: imx8mq: Combine PCIE power domains
arm64: dts: imx8mq: Add nodes for PCIe IP blocks
arm64: dts: imx8mq-evk: Enable PCIE0 interface
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 42 ++++++++++
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 84 +++++++++++++++++++-
2 files changed, 124 insertions(+), 2 deletions(-)
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH v3 1/5] arm64: dts: imx8mq: Mark iomuxc_gpr as i.MX6Q compatible
2019-02-20 1:58 ` Andrey Smirnov
@ 2019-02-20 1:58 ` Andrey Smirnov
-1 siblings, 0 replies; 14+ messages in thread
From: Andrey Smirnov @ 2019-02-20 1:58 UTC (permalink / raw)
To: Shawn Guo
Cc: Andrey Smirnov, Lucas Stach, Fabio Estevam, Chris Healy,
Leonard Crestez, A.s. Dong, Richard Zhu, linux-imx,
linux-arm-kernel, linux-kernel
Mark iomuxc_gpr as compatible with "fsl,imx6q-iomuxc-gpr" in order for
to allow i.MX6 PCIe driver to use it.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 892063a7c26c..f6c37bf9cbce 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -230,7 +230,7 @@
};
iomuxc_gpr: syscon@30340000 {
- compatible = "fsl,imx8mq-iomuxc-gpr", "syscon";
+ compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
reg = <0x30340000 0x10000>;
};
--
2.20.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v3 1/5] arm64: dts: imx8mq: Mark iomuxc_gpr as i.MX6Q compatible
@ 2019-02-20 1:58 ` Andrey Smirnov
0 siblings, 0 replies; 14+ messages in thread
From: Andrey Smirnov @ 2019-02-20 1:58 UTC (permalink / raw)
To: Shawn Guo
Cc: A.s. Dong, Richard Zhu, linux-arm-kernel, Andrey Smirnov,
linux-kernel, linux-imx, Fabio Estevam, Leonard Crestez,
Chris Healy, Lucas Stach
Mark iomuxc_gpr as compatible with "fsl,imx6q-iomuxc-gpr" in order for
to allow i.MX6 PCIe driver to use it.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 892063a7c26c..f6c37bf9cbce 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -230,7 +230,7 @@
};
iomuxc_gpr: syscon@30340000 {
- compatible = "fsl,imx8mq-iomuxc-gpr", "syscon";
+ compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
reg = <0x30340000 0x10000>;
};
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v3 2/5] arm64: dts: imx8mq: Add a node for SRC IP block
2019-02-20 1:58 ` Andrey Smirnov
@ 2019-02-20 1:58 ` Andrey Smirnov
-1 siblings, 0 replies; 14+ messages in thread
From: Andrey Smirnov @ 2019-02-20 1:58 UTC (permalink / raw)
To: Shawn Guo
Cc: Andrey Smirnov, Lucas Stach, Fabio Estevam, Chris Healy,
Leonard Crestez, A.s. Dong, Richard Zhu, linux-imx,
linux-arm-kernel, linux-kernel
Add a node for reset controller IP block found on i.MX8MQ.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index f6c37bf9cbce..50436bd393ed 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -254,6 +254,12 @@
"clk_ext3", "clk_ext4";
};
+ src: src@30390000 {
+ compatible = "fsl,imx8mq-src", "syscon";
+ reg = <0x30390000 0x10000>;
+ #reset-cells = <1>;
+ };
+
gpc: gpc@303a0000 {
compatible = "fsl,imx8mq-gpc";
reg = <0x303a0000 0x10000>;
--
2.20.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v3 2/5] arm64: dts: imx8mq: Add a node for SRC IP block
@ 2019-02-20 1:58 ` Andrey Smirnov
0 siblings, 0 replies; 14+ messages in thread
From: Andrey Smirnov @ 2019-02-20 1:58 UTC (permalink / raw)
To: Shawn Guo
Cc: A.s. Dong, Richard Zhu, linux-arm-kernel, Andrey Smirnov,
linux-kernel, linux-imx, Fabio Estevam, Leonard Crestez,
Chris Healy, Lucas Stach
Add a node for reset controller IP block found on i.MX8MQ.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index f6c37bf9cbce..50436bd393ed 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -254,6 +254,12 @@
"clk_ext3", "clk_ext4";
};
+ src: src@30390000 {
+ compatible = "fsl,imx8mq-src", "syscon";
+ reg = <0x30390000 0x10000>;
+ #reset-cells = <1>;
+ };
+
gpc: gpc@303a0000 {
compatible = "fsl,imx8mq-gpc";
reg = <0x303a0000 0x10000>;
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v3 3/5] arm64: dts: imx8mq: Combine PCIE power domains
2019-02-20 1:58 ` Andrey Smirnov
@ 2019-02-20 1:58 ` Andrey Smirnov
-1 siblings, 0 replies; 14+ messages in thread
From: Andrey Smirnov @ 2019-02-20 1:58 UTC (permalink / raw)
To: Shawn Guo
Cc: Andrey Smirnov, Lucas Stach, Fabio Estevam, Chris Healy,
Leonard Crestez, A.s. Dong, Richard Zhu, linux-imx,
linux-arm-kernel, linux-kernel
According to NXP's FAE feedback and a comment in ATF firmware, PCIE1
and PCIE2 power domains can't really be used independently. Due to
shared reset line both power domains have to be turned on at the same
time. Account for that quirk by combining PCIE power domains into a
single 'pgc_pcie' power domain.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 50436bd393ed..fca9b71de94f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -273,9 +273,25 @@
reg = <IMX8M_POWER_DOMAIN_MIPI>;
};
- pgc_pcie1: power-domain@1 {
+ /*
+ * As per comment in ATF source code:
+ *
+ * PCIE1 and PCIE2 share the
+ * same reset signal, if we
+ * power down PCIE2, PCIE1
+ * will be held in reset too.
+ *
+ * So instead of creating two
+ * separate power domains for
+ * PCIE1 and PCIE2 we create a
+ * link between both and use
+ * it as a shared PCIE power
+ * domain.
+ */
+ pgc_pcie: power-domain@1 {
#power-domain-cells = <0>;
reg = <IMX8M_POWER_DOMAIN_PCIE1>;
+ power-domains = <&pgc_pcie2>;
};
pgc_otg1: power-domain@2 {
--
2.20.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v3 3/5] arm64: dts: imx8mq: Combine PCIE power domains
@ 2019-02-20 1:58 ` Andrey Smirnov
0 siblings, 0 replies; 14+ messages in thread
From: Andrey Smirnov @ 2019-02-20 1:58 UTC (permalink / raw)
To: Shawn Guo
Cc: A.s. Dong, Richard Zhu, linux-arm-kernel, Andrey Smirnov,
linux-kernel, linux-imx, Fabio Estevam, Leonard Crestez,
Chris Healy, Lucas Stach
According to NXP's FAE feedback and a comment in ATF firmware, PCIE1
and PCIE2 power domains can't really be used independently. Due to
shared reset line both power domains have to be turned on at the same
time. Account for that quirk by combining PCIE power domains into a
single 'pgc_pcie' power domain.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 50436bd393ed..fca9b71de94f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -273,9 +273,25 @@
reg = <IMX8M_POWER_DOMAIN_MIPI>;
};
- pgc_pcie1: power-domain@1 {
+ /*
+ * As per comment in ATF source code:
+ *
+ * PCIE1 and PCIE2 share the
+ * same reset signal, if we
+ * power down PCIE2, PCIE1
+ * will be held in reset too.
+ *
+ * So instead of creating two
+ * separate power domains for
+ * PCIE1 and PCIE2 we create a
+ * link between both and use
+ * it as a shared PCIE power
+ * domain.
+ */
+ pgc_pcie: power-domain@1 {
#power-domain-cells = <0>;
reg = <IMX8M_POWER_DOMAIN_PCIE1>;
+ power-domains = <&pgc_pcie2>;
};
pgc_otg1: power-domain@2 {
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v3 4/5] arm64: dts: imx8mq: Add nodes for PCIe IP blocks
2019-02-20 1:58 ` Andrey Smirnov
@ 2019-02-20 1:58 ` Andrey Smirnov
-1 siblings, 0 replies; 14+ messages in thread
From: Andrey Smirnov @ 2019-02-20 1:58 UTC (permalink / raw)
To: Shawn Guo
Cc: Andrey Smirnov, Lucas Stach, Fabio Estevam, Chris Healy,
Leonard Crestez, A.s. Dong, Richard Zhu, linux-imx,
linux-arm-kernel, linux-kernel
Add nodes for two PCIe controllers found on i.MX8MQ.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 58 +++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index fca9b71de94f..cae44bcde6f4 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/clock/imx8mq-clock.h>
#include <dt-bindings/power/imx8mq-power.h>
+#include <dt-bindings/reset/imx8mq-reset.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "imx8mq-pinfunc.h"
@@ -536,6 +537,63 @@
};
};
+ pcie0: pcie@33800000 {
+ compatible = "fsl,imx8mq-pcie";
+ reg = <0x33800000 0x400000>,
+ <0x1ff00000 0x80000>;
+ reg-names = "dbi", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
+ 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
+ num-lanes = <1>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,max-link-speed = <2>;
+ power-domains = <&pgc_pcie>;
+ resets = <&src IMX8MQ_RESET_PCIEPHY>,
+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
+ reset-names = "pciephy", "apps", "turnoff";
+ status = "disabled";
+ };
+
+ pcie1: pcie@33c00000 {
+ compatible = "fsl,imx8mq-pcie";
+ reg = <0x33c00000 0x400000>,
+ <0x27f00000 0x80000>;
+ reg-names = "dbi", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */
+ 0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
+ num-lanes = <1>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,max-link-speed = <2>;
+ power-domains = <&pgc_pcie>;
+ resets = <&src IMX8MQ_RESET_PCIEPHY2>,
+ <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
+ <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
+ reset-names = "pciephy", "apps", "turnoff";
+ status = "disabled";
+ };
+
gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3";
reg = <0x38800000 0x10000>, /* GIC Dist */
--
2.20.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v3 4/5] arm64: dts: imx8mq: Add nodes for PCIe IP blocks
@ 2019-02-20 1:58 ` Andrey Smirnov
0 siblings, 0 replies; 14+ messages in thread
From: Andrey Smirnov @ 2019-02-20 1:58 UTC (permalink / raw)
To: Shawn Guo
Cc: A.s. Dong, Richard Zhu, linux-arm-kernel, Andrey Smirnov,
linux-kernel, linux-imx, Fabio Estevam, Leonard Crestez,
Chris Healy, Lucas Stach
Add nodes for two PCIe controllers found on i.MX8MQ.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 58 +++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index fca9b71de94f..cae44bcde6f4 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/clock/imx8mq-clock.h>
#include <dt-bindings/power/imx8mq-power.h>
+#include <dt-bindings/reset/imx8mq-reset.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "imx8mq-pinfunc.h"
@@ -536,6 +537,63 @@
};
};
+ pcie0: pcie@33800000 {
+ compatible = "fsl,imx8mq-pcie";
+ reg = <0x33800000 0x400000>,
+ <0x1ff00000 0x80000>;
+ reg-names = "dbi", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
+ 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
+ num-lanes = <1>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,max-link-speed = <2>;
+ power-domains = <&pgc_pcie>;
+ resets = <&src IMX8MQ_RESET_PCIEPHY>,
+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
+ reset-names = "pciephy", "apps", "turnoff";
+ status = "disabled";
+ };
+
+ pcie1: pcie@33c00000 {
+ compatible = "fsl,imx8mq-pcie";
+ reg = <0x33c00000 0x400000>,
+ <0x27f00000 0x80000>;
+ reg-names = "dbi", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */
+ 0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
+ num-lanes = <1>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,max-link-speed = <2>;
+ power-domains = <&pgc_pcie>;
+ resets = <&src IMX8MQ_RESET_PCIEPHY2>,
+ <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
+ <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
+ reset-names = "pciephy", "apps", "turnoff";
+ status = "disabled";
+ };
+
gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3";
reg = <0x38800000 0x10000>, /* GIC Dist */
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v3 5/5] arm64: dts: imx8mq-evk: Enable PCIE0 interface
2019-02-20 1:58 ` Andrey Smirnov
@ 2019-02-20 1:58 ` Andrey Smirnov
-1 siblings, 0 replies; 14+ messages in thread
From: Andrey Smirnov @ 2019-02-20 1:58 UTC (permalink / raw)
To: Shawn Guo
Cc: Andrey Smirnov, Fabio Estevam, Chris Healy, Lucas Stach,
Leonard Crestez, A.s. Dong, Richard Zhu, linux-imx,
linux-arm-kernel, linux-kernel
Enable PCIE0 interface connected to BCM4356 WiFi/Bluetooth module.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 42 ++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index 64acccc4bfcb..226aeb9791a5 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -31,6 +31,12 @@
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
+
+ pcie0_refclk: pcie0-refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
};
&fec1 {
@@ -40,6 +46,17 @@
status = "okay";
};
+&gpio5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi_reset>;
+
+ wl-reg-on {
+ gpio-hog;
+ gpios = <29 GPIO_ACTIVE_HIGH>;
+ output-high;
+ };
+};
+
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
@@ -131,6 +148,18 @@
};
};
+&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0>;
+ reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
+ clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
+ <&clk IMX8MQ_CLK_PCIE1_AUX>,
+ <&clk IMX8MQ_CLK_PCIE1_PHY>,
+ <&pcie0_refclk>;
+ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+ status = "okay";
+};
+
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
@@ -195,6 +224,13 @@
>;
};
+ pinctrl_pcie0: pcie0grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76
+ MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16
+ >;
+ };
+
pinctrl_reg_usdhc2: regusdhc2grpgpio {
fsl,pins = <
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
@@ -300,4 +336,10 @@
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
+
+ pinctrl_wifi_reset: wifiresetgrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16
+ >;
+ };
};
--
2.20.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v3 5/5] arm64: dts: imx8mq-evk: Enable PCIE0 interface
@ 2019-02-20 1:58 ` Andrey Smirnov
0 siblings, 0 replies; 14+ messages in thread
From: Andrey Smirnov @ 2019-02-20 1:58 UTC (permalink / raw)
To: Shawn Guo
Cc: A.s. Dong, Richard Zhu, linux-arm-kernel, Andrey Smirnov,
linux-kernel, linux-imx, Fabio Estevam, Leonard Crestez,
Chris Healy, Lucas Stach
Enable PCIE0 interface connected to BCM4356 WiFi/Bluetooth module.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 42 ++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index 64acccc4bfcb..226aeb9791a5 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -31,6 +31,12 @@
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
+
+ pcie0_refclk: pcie0-refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
};
&fec1 {
@@ -40,6 +46,17 @@
status = "okay";
};
+&gpio5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi_reset>;
+
+ wl-reg-on {
+ gpio-hog;
+ gpios = <29 GPIO_ACTIVE_HIGH>;
+ output-high;
+ };
+};
+
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
@@ -131,6 +148,18 @@
};
};
+&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0>;
+ reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
+ clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
+ <&clk IMX8MQ_CLK_PCIE1_AUX>,
+ <&clk IMX8MQ_CLK_PCIE1_PHY>,
+ <&pcie0_refclk>;
+ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+ status = "okay";
+};
+
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
@@ -195,6 +224,13 @@
>;
};
+ pinctrl_pcie0: pcie0grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76
+ MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16
+ >;
+ };
+
pinctrl_reg_usdhc2: regusdhc2grpgpio {
fsl,pins = <
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
@@ -300,4 +336,10 @@
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
+
+ pinctrl_wifi_reset: wifiresetgrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16
+ >;
+ };
};
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v3 5/5] arm64: dts: imx8mq-evk: Enable PCIE0 interface
2019-02-20 1:58 ` Andrey Smirnov
@ 2019-02-20 8:18 ` Lucas Stach
-1 siblings, 0 replies; 14+ messages in thread
From: Lucas Stach @ 2019-02-20 8:18 UTC (permalink / raw)
To: Andrey Smirnov, Shawn Guo
Cc: Fabio Estevam, Chris Healy, Leonard Crestez, A.s. Dong,
Richard Zhu, linux-imx, linux-arm-kernel, linux-kernel
Am Dienstag, den 19.02.2019, 17:58 -0800 schrieb Andrey Smirnov:
> Enable PCIE0 interface connected to BCM4356 WiFi/Bluetooth module.
>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Fabio Estevam <fabio.estevam@nxp.com>
> Cc: Chris Healy <cphealy@gmail.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Leonard Crestez <leonard.crestez@nxp.com>
> Cc: "A.s. Dong" <aisheng.dong@nxp.com>
> Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: linux-imx@nxp.com
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
> ---
> arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 42 ++++++++++++++++++++
> 1 file changed, 42 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> index 64acccc4bfcb..226aeb9791a5 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> @@ -31,6 +31,12 @@
> gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> enable-active-high;
> };
> +
> + pcie0_refclk: pcie0-refclk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + };
> };
>
> &fec1 {
> @@ -40,6 +46,17 @@
> status = "okay";
> };
>
> +&gpio5 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_wifi_reset>;
> +
> + wl-reg-on {
> + gpio-hog;
> + gpios = <29 GPIO_ACTIVE_HIGH>;
> + output-high;
> + };
> +};
> +
> &i2c1 {
> clock-frequency = <100000>;
> pinctrl-names = "default";
> @@ -131,6 +148,18 @@
> };
> };
>
> +&pcie0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pcie0>;
> + reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
> + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
> + <&clk IMX8MQ_CLK_PCIE1_AUX>,
> + <&clk IMX8MQ_CLK_PCIE1_PHY>,
> + <&pcie0_refclk>;
> + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> + status = "okay";
> +};
> +
> &uart1 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_uart1>;
> @@ -195,6 +224,13 @@
> >;
> };
>
> + pinctrl_pcie0: pcie0grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76
> + MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16
> + >;
> + };
> +
> pinctrl_reg_usdhc2: regusdhc2grpgpio {
> fsl,pins = <
> MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
> @@ -300,4 +336,10 @@
> MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
> >;
> };
> +
> + pinctrl_wifi_reset: wifiresetgrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16
> + >;
> + };
> };
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v3 5/5] arm64: dts: imx8mq-evk: Enable PCIE0 interface
@ 2019-02-20 8:18 ` Lucas Stach
0 siblings, 0 replies; 14+ messages in thread
From: Lucas Stach @ 2019-02-20 8:18 UTC (permalink / raw)
To: Andrey Smirnov, Shawn Guo
Cc: A.s. Dong, Richard Zhu, linux-kernel, linux-imx, Fabio Estevam,
Leonard Crestez, Chris Healy, linux-arm-kernel
Am Dienstag, den 19.02.2019, 17:58 -0800 schrieb Andrey Smirnov:
> Enable PCIE0 interface connected to BCM4356 WiFi/Bluetooth module.
>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Fabio Estevam <fabio.estevam@nxp.com>
> Cc: Chris Healy <cphealy@gmail.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Leonard Crestez <leonard.crestez@nxp.com>
> Cc: "A.s. Dong" <aisheng.dong@nxp.com>
> Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: linux-imx@nxp.com
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
> ---
> arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 42 ++++++++++++++++++++
> 1 file changed, 42 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> index 64acccc4bfcb..226aeb9791a5 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> @@ -31,6 +31,12 @@
> gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> enable-active-high;
> };
> +
> + pcie0_refclk: pcie0-refclk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + };
> };
>
> &fec1 {
> @@ -40,6 +46,17 @@
> status = "okay";
> };
>
> +&gpio5 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_wifi_reset>;
> +
> + wl-reg-on {
> + gpio-hog;
> + gpios = <29 GPIO_ACTIVE_HIGH>;
> + output-high;
> + };
> +};
> +
> &i2c1 {
> clock-frequency = <100000>;
> pinctrl-names = "default";
> @@ -131,6 +148,18 @@
> };
> };
>
> +&pcie0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pcie0>;
> + reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
> + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
> + <&clk IMX8MQ_CLK_PCIE1_AUX>,
> + <&clk IMX8MQ_CLK_PCIE1_PHY>,
> + <&pcie0_refclk>;
> + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> + status = "okay";
> +};
> +
> &uart1 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_uart1>;
> @@ -195,6 +224,13 @@
> >;
> };
>
> + pinctrl_pcie0: pcie0grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76
> + MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16
> + >;
> + };
> +
> pinctrl_reg_usdhc2: regusdhc2grpgpio {
> fsl,pins = <
> MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
> @@ -300,4 +336,10 @@
> MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
> >;
> };
> +
> + pinctrl_wifi_reset: wifiresetgrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16
> + >;
> + };
> };
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread