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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 09/21] hw/timer/pl031: Allow use as an embedded-struct device
Date: Thu, 21 Feb 2019 18:57:27 +0000	[thread overview]
Message-ID: <20190221185739.25362-10-peter.maydell@linaro.org> (raw)
In-Reply-To: <20190221185739.25362-1-peter.maydell@linaro.org>

Create a new include file for the pl031's device struct,
type macros, etc, so that it can be instantiated using
the "embedded struct" coding style.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/hw/timer/pl031.h | 44 ++++++++++++++++++++++++++++++++++++++++
 hw/timer/pl031.c         | 25 +----------------------
 MAINTAINERS              |  1 +
 3 files changed, 46 insertions(+), 24 deletions(-)
 create mode 100644 include/hw/timer/pl031.h

diff --git a/include/hw/timer/pl031.h b/include/hw/timer/pl031.h
new file mode 100644
index 00000000000..99416d8ba52
--- /dev/null
+++ b/include/hw/timer/pl031.h
@@ -0,0 +1,44 @@
+/*
+ * ARM AMBA PrimeCell PL031 RTC
+ *
+ * Copyright (c) 2007 CodeSourcery
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Contributions after 2012-01-13 are licensed under the terms of the
+ * GNU GPL, version 2 or (at your option) any later version.
+ */
+
+#ifndef HW_TIMER_PL031
+#define HW_TIMER_PL031
+
+#include "hw/sysbus.h"
+
+#define TYPE_PL031 "pl031"
+#define PL031(obj) OBJECT_CHECK(PL031State, (obj), TYPE_PL031)
+
+typedef struct PL031State {
+    SysBusDevice parent_obj;
+
+    MemoryRegion iomem;
+    QEMUTimer *timer;
+    qemu_irq irq;
+
+    /*
+     * Needed to preserve the tick_count across migration, even if the
+     * absolute value of the rtc_clock is different on the source and
+     * destination.
+     */
+    uint32_t tick_offset_vmstate;
+    uint32_t tick_offset;
+
+    uint32_t mr;
+    uint32_t lr;
+    uint32_t cr;
+    uint32_t im;
+    uint32_t is;
+} PL031State;
+
+#endif
diff --git a/hw/timer/pl031.c b/hw/timer/pl031.c
index d3aacce80da..f774dcd5223 100644
--- a/hw/timer/pl031.c
+++ b/hw/timer/pl031.c
@@ -12,6 +12,7 @@
  */
 
 #include "qemu/osdep.h"
+#include "hw/timer/pl031.h"
 #include "hw/sysbus.h"
 #include "qemu/timer.h"
 #include "sysemu/sysemu.h"
@@ -36,30 +37,6 @@ do { printf("pl031: " fmt , ## __VA_ARGS__); } while (0)
 #define RTC_MIS     0x18    /* Masked interrupt status register */
 #define RTC_ICR     0x1c    /* Interrupt clear register */
 
-#define TYPE_PL031 "pl031"
-#define PL031(obj) OBJECT_CHECK(PL031State, (obj), TYPE_PL031)
-
-typedef struct PL031State {
-    SysBusDevice parent_obj;
-
-    MemoryRegion iomem;
-    QEMUTimer *timer;
-    qemu_irq irq;
-
-    /* Needed to preserve the tick_count across migration, even if the
-     * absolute value of the rtc_clock is different on the source and
-     * destination.
-     */
-    uint32_t tick_offset_vmstate;
-    uint32_t tick_offset;
-
-    uint32_t mr;
-    uint32_t lr;
-    uint32_t cr;
-    uint32_t im;
-    uint32_t is;
-} PL031State;
-
 static const unsigned char pl031_id[] = {
     0x31, 0x10, 0x14, 0x00,         /* Device ID        */
     0x0d, 0xf0, 0x05, 0xb1          /* Cell ID      */
diff --git a/MAINTAINERS b/MAINTAINERS
index b1d786cfd87..db31bc4486c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -491,6 +491,7 @@ F: hw/sd/pl181.c
 F: hw/ssi/pl022.c
 F: include/hw/ssi/pl022.h
 F: hw/timer/pl031.c
+F: include/hw/timer/pl031.h
 F: include/hw/arm/primecell.h
 F: hw/timer/cmsdk-apb-timer.c
 F: include/hw/timer/cmsdk-apb-timer.h
-- 
2.20.1

  parent reply	other threads:[~2019-02-21 18:58 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-21 18:57 [Qemu-devel] [PULL 00/21] target-arm queue Peter Maydell
2019-02-21 18:57 ` [Qemu-devel] [PULL 01/21] hw/arm/armsse: Fix memory leak in error-exit path Peter Maydell
2019-02-21 18:57 ` [Qemu-devel] [PULL 02/21] target/arm: v8M MPU should use background region as default, not always Peter Maydell
2019-02-21 18:57 ` [Qemu-devel] [PULL 03/21] target/arm: Stop unintentional sign extension in pmu_init Peter Maydell
2019-02-21 18:57 ` [Qemu-devel] [PULL 04/21] target/arm: Restructure disas_fp_int_conv Peter Maydell
2019-02-21 18:57 ` [Qemu-devel] [PULL 05/21] target/arm: Split out vfp_helper.c Peter Maydell
2019-02-21 18:57 ` [Qemu-devel] [PULL 06/21] target/arm: Rearrange Floating-point data-processing (2 regs) Peter Maydell
2019-02-21 18:57 ` [Qemu-devel] [PULL 07/21] target/arm: Implement ARMv8.3-JSConv Peter Maydell
2019-02-21 18:57 ` [Qemu-devel] [PULL 08/21] hw/misc/tz-ppc: Support having unused ports in the middle of the range Peter Maydell
2019-02-21 18:57 ` Peter Maydell [this message]
2019-02-21 18:57 ` [Qemu-devel] [PULL 10/21] hw/timer/pl031: Convert to using trace events Peter Maydell
2019-02-21 18:57 ` [Qemu-devel] [PULL 11/21] hw/char/pl011: Allow use as an embedded-struct device Peter Maydell
2019-02-21 18:57 ` [Qemu-devel] [PULL 12/21] hw/char/pl011: Support all interrupt lines Peter Maydell
2019-02-21 18:57 ` [Qemu-devel] [PULL 13/21] hw/char/pl011: Use '0x' prefix when logging hex numbers Peter Maydell
2019-02-21 18:57 ` [Qemu-devel] [PULL 14/21] hw/arm/armsse: Document SRAM_ADDR_WIDTH property in header comment Peter Maydell
2019-02-21 18:57 ` [Qemu-devel] [PULL 15/21] hw/arm/armsse: Allow boards to specify init-svtor Peter Maydell
2019-02-21 18:57 ` [Qemu-devel] [PULL 16/21] hw/arm/musca.c: Implement models of the Musca-A and -B1 boards Peter Maydell
2019-02-21 18:57 ` [Qemu-devel] [PULL 17/21] hw/arm/musca: Add PPCs Peter Maydell
2019-02-21 18:57 ` [Qemu-devel] [PULL 18/21] hw/arm/musca: Add MPCs Peter Maydell
2019-02-21 18:57 ` [Qemu-devel] [PULL 19/21] hw/arm/musca: Wire up PL031 RTC Peter Maydell
2019-02-21 18:57 ` [Qemu-devel] [PULL 20/21] hw/arm/musca: Wire up PL011 UARTs Peter Maydell
2019-02-21 18:57 ` [Qemu-devel] [PULL 21/21] hw/arm/armsse: Make 0x5... alias region work for per-CPU devices Peter Maydell
2019-02-22 11:24 ` [Qemu-devel] [PULL 00/21] target-arm queue Peter Maydell

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