* [Qemu-devel] [PATCH 1/9] tcg: Implement tcg_gen_extract2_{i32, i64}
2019-03-07 14:41 [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64} Richard Henderson
@ 2019-03-07 14:41 ` Richard Henderson
2019-03-08 23:19 ` Philippe Mathieu-Daudé
2019-03-07 14:41 ` [Qemu-devel] [PATCH 2/9] tcg: Add INDEX_op_extract2_{i32,i64} Richard Henderson
` (14 subsequent siblings)
15 siblings, 1 reply; 33+ messages in thread
From: Richard Henderson @ 2019-03-07 14:41 UTC (permalink / raw)
To: qemu-devel; +Cc: david
From: David Hildenbrand <david@redhat.com>
Will be helpful for s390x. Input 128 bit and output 64 bit only,
which is sufficient for now.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20190225154204.26751-1-david@redhat.com>
[rth: Add matching tcg_gen_extract2_i32.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg-op.h | 6 ++++++
tcg/tcg-op.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 50 insertions(+)
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index d3e51b15af..1f1824c30a 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -308,6 +308,8 @@ void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg,
unsigned int ofs, unsigned int len);
void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg,
unsigned int ofs, unsigned int len);
+void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah,
+ unsigned int ofs);
void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *);
void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *);
void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
@@ -501,6 +503,8 @@ void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg,
unsigned int ofs, unsigned int len);
void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg,
unsigned int ofs, unsigned int len);
+void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah,
+ unsigned int ofs);
void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *);
void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *);
void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
@@ -1068,6 +1072,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i64
#define tcg_gen_extract_tl tcg_gen_extract_i64
#define tcg_gen_sextract_tl tcg_gen_sextract_i64
+#define tcg_gen_extract2_tl tcg_gen_extract2_i64
#define tcg_const_tl tcg_const_i64
#define tcg_const_local_tl tcg_const_local_i64
#define tcg_gen_movcond_tl tcg_gen_movcond_i64
@@ -1178,6 +1183,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i32
#define tcg_gen_extract_tl tcg_gen_extract_i32
#define tcg_gen_sextract_tl tcg_gen_sextract_i32
+#define tcg_gen_extract2_tl tcg_gen_extract2_i32
#define tcg_const_tl tcg_const_i32
#define tcg_const_local_tl tcg_const_local_i32
#define tcg_gen_movcond_tl tcg_gen_movcond_i32
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 1bd7ef24af..7c56c92c8e 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -809,6 +809,28 @@ void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg,
tcg_gen_sari_i32(ret, ret, 32 - len);
}
+/*
+ * Extract 32-bits from a 64-bit input, ah:al, starting from ofs.
+ * Unlike tcg_gen_extract_i32 above, len is fixed at 32.
+ */
+void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah,
+ unsigned int ofs)
+{
+ tcg_debug_assert(ofs <= 32);
+ if (ofs == 0) {
+ tcg_gen_mov_i32(ret, al);
+ } else if (ofs == 32) {
+ tcg_gen_mov_i32(ret, ah);
+ } else if (al == ah) {
+ tcg_gen_rotri_i32(ret, al, ofs);
+ } else {
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ tcg_gen_shri_i32(t0, al, ofs);
+ tcg_gen_deposit_i32(ret, t0, ah, 32 - ofs, ofs);
+ tcg_temp_free_i32(t0);
+ }
+}
+
void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1,
TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2)
{
@@ -2297,6 +2319,28 @@ void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg,
tcg_gen_sari_i64(ret, ret, 64 - len);
}
+/*
+ * Extract 64 bits from a 128-bit input, ah:al, starting from ofs.
+ * Unlike tcg_gen_extract_i64 above, len is fixed at 64.
+ */
+void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah,
+ unsigned int ofs)
+{
+ tcg_debug_assert(ofs <= 64);
+ if (ofs == 0) {
+ tcg_gen_mov_i64(ret, al);
+ } else if (ofs == 64) {
+ tcg_gen_mov_i64(ret, ah);
+ } else if (al == ah) {
+ tcg_gen_rotri_i64(ret, al, ofs);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ tcg_gen_shri_i64(t0, al, ofs);
+ tcg_gen_deposit_i64(ret, t0, ah, 64 - ofs, ofs);
+ tcg_temp_free_i64(t0);
+ }
+}
+
void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1,
TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2)
{
--
2.17.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 1/9] tcg: Implement tcg_gen_extract2_{i32, i64}
2019-03-07 14:41 ` [Qemu-devel] [PATCH 1/9] tcg: Implement tcg_gen_extract2_{i32, i64} Richard Henderson
@ 2019-03-08 23:19 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-03-08 23:19 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: david
On 3/7/19 3:41 PM, Richard Henderson wrote:
> From: David Hildenbrand <david@redhat.com>
>
> Will be helpful for s390x. Input 128 bit and output 64 bit only,
> which is sufficient for now.
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: David Hildenbrand <david@redhat.com>
> Message-Id: <20190225154204.26751-1-david@redhat.com>
> [rth: Add matching tcg_gen_extract2_i32.]
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/tcg-op.h | 6 ++++++
> tcg/tcg-op.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 50 insertions(+)
>
> diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
> index d3e51b15af..1f1824c30a 100644
> --- a/tcg/tcg-op.h
> +++ b/tcg/tcg-op.h
> @@ -308,6 +308,8 @@ void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg,
> unsigned int ofs, unsigned int len);
> void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg,
> unsigned int ofs, unsigned int len);
> +void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah,
> + unsigned int ofs);
> void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *);
> void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *);
> void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
> @@ -501,6 +503,8 @@ void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg,
> unsigned int ofs, unsigned int len);
> void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg,
> unsigned int ofs, unsigned int len);
> +void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah,
> + unsigned int ofs);
> void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *);
> void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *);
> void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
> @@ -1068,6 +1072,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
> #define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i64
> #define tcg_gen_extract_tl tcg_gen_extract_i64
> #define tcg_gen_sextract_tl tcg_gen_sextract_i64
> +#define tcg_gen_extract2_tl tcg_gen_extract2_i64
> #define tcg_const_tl tcg_const_i64
> #define tcg_const_local_tl tcg_const_local_i64
> #define tcg_gen_movcond_tl tcg_gen_movcond_i64
> @@ -1178,6 +1183,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
> #define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i32
> #define tcg_gen_extract_tl tcg_gen_extract_i32
> #define tcg_gen_sextract_tl tcg_gen_sextract_i32
> +#define tcg_gen_extract2_tl tcg_gen_extract2_i32
> #define tcg_const_tl tcg_const_i32
> #define tcg_const_local_tl tcg_const_local_i32
> #define tcg_gen_movcond_tl tcg_gen_movcond_i32
> diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
> index 1bd7ef24af..7c56c92c8e 100644
> --- a/tcg/tcg-op.c
> +++ b/tcg/tcg-op.c
> @@ -809,6 +809,28 @@ void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg,
> tcg_gen_sari_i32(ret, ret, 32 - len);
> }
>
> +/*
> + * Extract 32-bits from a 64-bit input, ah:al, starting from ofs.
> + * Unlike tcg_gen_extract_i32 above, len is fixed at 32.
> + */
> +void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah,
> + unsigned int ofs)
> +{
> + tcg_debug_assert(ofs <= 32);
> + if (ofs == 0) {
> + tcg_gen_mov_i32(ret, al);
> + } else if (ofs == 32) {
> + tcg_gen_mov_i32(ret, ah);
> + } else if (al == ah) {
> + tcg_gen_rotri_i32(ret, al, ofs);
> + } else {
> + TCGv_i32 t0 = tcg_temp_new_i32();
> + tcg_gen_shri_i32(t0, al, ofs);
> + tcg_gen_deposit_i32(ret, t0, ah, 32 - ofs, ofs);
> + tcg_temp_free_i32(t0);
> + }
> +}
> +
> void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1,
> TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2)
> {
> @@ -2297,6 +2319,28 @@ void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg,
> tcg_gen_sari_i64(ret, ret, 64 - len);
> }
>
> +/*
> + * Extract 64 bits from a 128-bit input, ah:al, starting from ofs.
> + * Unlike tcg_gen_extract_i64 above, len is fixed at 64.
> + */
> +void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah,
> + unsigned int ofs)
> +{
> + tcg_debug_assert(ofs <= 64);
> + if (ofs == 0) {
> + tcg_gen_mov_i64(ret, al);
> + } else if (ofs == 64) {
> + tcg_gen_mov_i64(ret, ah);
> + } else if (al == ah) {
> + tcg_gen_rotri_i64(ret, al, ofs);
> + } else {
> + TCGv_i64 t0 = tcg_temp_new_i64();
> + tcg_gen_shri_i64(t0, al, ofs);
> + tcg_gen_deposit_i64(ret, t0, ah, 64 - ofs, ofs);
> + tcg_temp_free_i64(t0);
> + }
> +}
> +
> void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1,
> TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2)
> {
>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Qemu-devel] [PATCH 2/9] tcg: Add INDEX_op_extract2_{i32,i64}
2019-03-07 14:41 [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64} Richard Henderson
2019-03-07 14:41 ` [Qemu-devel] [PATCH 1/9] tcg: Implement tcg_gen_extract2_{i32, i64} Richard Henderson
@ 2019-03-07 14:41 ` Richard Henderson
2019-03-07 15:19 ` David Hildenbrand
` (2 more replies)
2019-03-07 14:41 ` [Qemu-devel] [PATCH 3/9] tcg: Use extract2 in tcg_gen_shifti_i64 Richard Henderson
` (13 subsequent siblings)
15 siblings, 3 replies; 33+ messages in thread
From: Richard Henderson @ 2019-03-07 14:41 UTC (permalink / raw)
To: qemu-devel; +Cc: david
This will let backends implement the double-word shift operation.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target.h | 2 ++
tcg/arm/tcg-target.h | 1 +
tcg/i386/tcg-target.h | 2 ++
tcg/mips/tcg-target.h | 2 ++
tcg/ppc/tcg-target.h | 2 ++
tcg/riscv/tcg-target.h | 2 ++
tcg/s390/tcg-target.h | 2 ++
tcg/sparc/tcg-target.h | 2 ++
tcg/tcg-opc.h | 2 ++
tcg/tcg.h | 1 +
tcg/tci/tcg-target.h | 2 ++
tcg/optimize.c | 10 ++++++++++
tcg/tcg-op.c | 4 ++++
tcg/tcg.c | 4 ++++
tcg/README | 5 +++++
15 files changed, 43 insertions(+)
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 2d93cf404e..6600a54a02 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -77,6 +77,7 @@ typedef enum {
#define TCG_TARGET_HAS_deposit_i32 1
#define TCG_TARGET_HAS_extract_i32 1
#define TCG_TARGET_HAS_sextract_i32 1
+#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_add2_i32 1
#define TCG_TARGET_HAS_sub2_i32 1
@@ -113,6 +114,7 @@ typedef enum {
#define TCG_TARGET_HAS_deposit_i64 1
#define TCG_TARGET_HAS_extract_i64 1
#define TCG_TARGET_HAS_sextract_i64 1
+#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 16172f73a3..4ee6c98958 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -116,6 +116,7 @@ extern bool use_idiv_instructions;
#define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions
#define TCG_TARGET_HAS_extract_i32 use_armv7_instructions
#define TCG_TARGET_HAS_sextract_i32 use_armv7_instructions
+#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_mulu2_i32 1
#define TCG_TARGET_HAS_muls2_i32 1
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 7995fe3eab..2c58eaa9ed 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -124,6 +124,7 @@ extern bool have_avx2;
#define TCG_TARGET_HAS_deposit_i32 1
#define TCG_TARGET_HAS_extract_i32 1
#define TCG_TARGET_HAS_sextract_i32 1
+#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_add2_i32 1
#define TCG_TARGET_HAS_sub2_i32 1
@@ -162,6 +163,7 @@ extern bool have_avx2;
#define TCG_TARGET_HAS_deposit_i64 1
#define TCG_TARGET_HAS_extract_i64 1
#define TCG_TARGET_HAS_sextract_i64 0
+#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index 5cb8672470..c6b091d849 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -162,6 +162,7 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_deposit_i32 use_mips32r2_instructions
#define TCG_TARGET_HAS_extract_i32 use_mips32r2_instructions
#define TCG_TARGET_HAS_sextract_i32 0
+#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_ext8s_i32 use_mips32r2_instructions
#define TCG_TARGET_HAS_ext16s_i32 use_mips32r2_instructions
#define TCG_TARGET_HAS_rot_i32 use_mips32r2_instructions
@@ -177,6 +178,7 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_deposit_i64 use_mips32r2_instructions
#define TCG_TARGET_HAS_extract_i64 use_mips32r2_instructions
#define TCG_TARGET_HAS_sextract_i64 0
+#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_ext8s_i64 use_mips32r2_instructions
#define TCG_TARGET_HAS_ext16s_i64 use_mips32r2_instructions
#define TCG_TARGET_HAS_rot_i64 use_mips32r2_instructions
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 52c1bb04b1..7627fb62d3 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -77,6 +77,7 @@ extern bool have_isa_3_00;
#define TCG_TARGET_HAS_deposit_i32 1
#define TCG_TARGET_HAS_extract_i32 1
#define TCG_TARGET_HAS_sextract_i32 0
+#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_mulu2_i32 0
#define TCG_TARGET_HAS_muls2_i32 0
@@ -115,6 +116,7 @@ extern bool have_isa_3_00;
#define TCG_TARGET_HAS_deposit_i64 1
#define TCG_TARGET_HAS_extract_i64 1
#define TCG_TARGET_HAS_sextract_i64 0
+#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index 60918cacb4..032439d806 100644
--- a/tcg/riscv/tcg-target.h
+++ b/tcg/riscv/tcg-target.h
@@ -93,6 +93,7 @@ typedef enum {
#define TCG_TARGET_HAS_deposit_i32 0
#define TCG_TARGET_HAS_extract_i32 0
#define TCG_TARGET_HAS_sextract_i32 0
+#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_add2_i32 1
#define TCG_TARGET_HAS_sub2_i32 1
#define TCG_TARGET_HAS_mulu2_i32 0
@@ -128,6 +129,7 @@ typedef enum {
#define TCG_TARGET_HAS_deposit_i64 0
#define TCG_TARGET_HAS_extract_i64 0
#define TCG_TARGET_HAS_sextract_i64 0
+#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_extrl_i64_i32 1
#define TCG_TARGET_HAS_extrh_i64_i32 1
#define TCG_TARGET_HAS_ext8s_i64 1
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index 853ed6e7aa..07accabbd1 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -85,6 +85,7 @@ extern uint64_t s390_facilities;
#define TCG_TARGET_HAS_deposit_i32 (s390_facilities & FACILITY_GEN_INST_EXT)
#define TCG_TARGET_HAS_extract_i32 (s390_facilities & FACILITY_GEN_INST_EXT)
#define TCG_TARGET_HAS_sextract_i32 0
+#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_add2_i32 1
#define TCG_TARGET_HAS_sub2_i32 1
@@ -121,6 +122,7 @@ extern uint64_t s390_facilities;
#define TCG_TARGET_HAS_deposit_i64 (s390_facilities & FACILITY_GEN_INST_EXT)
#define TCG_TARGET_HAS_extract_i64 (s390_facilities & FACILITY_GEN_INST_EXT)
#define TCG_TARGET_HAS_sextract_i64 0
+#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index a0ed2a3342..633841ebf2 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -116,6 +116,7 @@ extern bool use_vis3_instructions;
#define TCG_TARGET_HAS_deposit_i32 0
#define TCG_TARGET_HAS_extract_i32 0
#define TCG_TARGET_HAS_sextract_i32 0
+#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_add2_i32 1
#define TCG_TARGET_HAS_sub2_i32 1
@@ -153,6 +154,7 @@ extern bool use_vis3_instructions;
#define TCG_TARGET_HAS_deposit_i64 0
#define TCG_TARGET_HAS_extract_i64 0
#define TCG_TARGET_HAS_sextract_i64 0
+#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 4e0238ad1a..1bad6e4208 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -79,6 +79,7 @@ DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32))
DEF(extract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_extract_i32))
DEF(sextract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_sextract_i32))
+DEF(extract2_i32, 1, 2, 1, IMPL(TCG_TARGET_HAS_extract2_i32))
DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END)
@@ -146,6 +147,7 @@ DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64))
DEF(extract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_extract_i64))
DEF(sextract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_sextract_i64))
+DEF(extract2_i64, 1, 2, 1, IMPL64 | IMPL(TCG_TARGET_HAS_extract2_i64))
/* size changing ops */
DEF(ext_i32_i64, 1, 1, 0, IMPL64)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 32b7cf3489..7b1c15b40b 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -125,6 +125,7 @@ typedef uint64_t TCGRegSet;
#define TCG_TARGET_HAS_deposit_i64 0
#define TCG_TARGET_HAS_extract_i64 0
#define TCG_TARGET_HAS_sextract_i64 0
+#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_movcond_i64 0
#define TCG_TARGET_HAS_add2_i64 0
#define TCG_TARGET_HAS_sub2_i64 0
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 086f34e69a..8b90ab71cb 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -71,6 +71,7 @@
#define TCG_TARGET_HAS_deposit_i32 1
#define TCG_TARGET_HAS_extract_i32 0
#define TCG_TARGET_HAS_sextract_i32 0
+#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_eqv_i32 0
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0
@@ -97,6 +98,7 @@
#define TCG_TARGET_HAS_deposit_i64 1
#define TCG_TARGET_HAS_extract_i64 0
#define TCG_TARGET_HAS_sextract_i64 0
+#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_div_i64 0
#define TCG_TARGET_HAS_rem_i64 0
#define TCG_TARGET_HAS_ext8s_i64 1
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 01e80c3e46..a5f50a0608 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -1202,6 +1202,16 @@ void tcg_optimize(TCGContext *s)
}
goto do_default;
+ CASE_OP_32_64(extract2):
+ if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
+ TCGArg v1 = arg_info(op->args[1])->val;
+ TCGArg v2 = arg_info(op->args[2])->val;
+ tmp = (v1 >> op->args[3]) | (v2 << (64 - op->args[3]));
+ tcg_opt_gen_movi(s, op, op->args[0], tmp);
+ break;
+ }
+ goto do_default;
+
CASE_OP_32_64(setcond):
tmp = do_constant_folding_cond(opc, op->args[1],
op->args[2], op->args[3]);
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 7c56c92c8e..deacc63e3b 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -823,6 +823,8 @@ void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah,
tcg_gen_mov_i32(ret, ah);
} else if (al == ah) {
tcg_gen_rotri_i32(ret, al, ofs);
+ } else if (TCG_TARGET_HAS_extract2_i32) {
+ tcg_gen_op4i_i32(INDEX_op_extract2_i32, ret, al, ah, ofs);
} else {
TCGv_i32 t0 = tcg_temp_new_i32();
tcg_gen_shri_i32(t0, al, ofs);
@@ -2333,6 +2335,8 @@ void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah,
tcg_gen_mov_i64(ret, ah);
} else if (al == ah) {
tcg_gen_rotri_i64(ret, al, ofs);
+ } else if (TCG_TARGET_HAS_extract2_i64) {
+ tcg_gen_op4i_i64(INDEX_op_extract2_i64, ret, al, ah, ofs);
} else {
TCGv_i64 t0 = tcg_temp_new_i64();
tcg_gen_shri_i64(t0, al, ofs);
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 9b2bf7f439..ade6050982 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1425,6 +1425,8 @@ bool tcg_op_supported(TCGOpcode op)
return TCG_TARGET_HAS_extract_i32;
case INDEX_op_sextract_i32:
return TCG_TARGET_HAS_sextract_i32;
+ case INDEX_op_extract2_i32:
+ return TCG_TARGET_HAS_extract2_i32;
case INDEX_op_add2_i32:
return TCG_TARGET_HAS_add2_i32;
case INDEX_op_sub2_i32:
@@ -1522,6 +1524,8 @@ bool tcg_op_supported(TCGOpcode op)
return TCG_TARGET_HAS_extract_i64;
case INDEX_op_sextract_i64:
return TCG_TARGET_HAS_sextract_i64;
+ case INDEX_op_extract2_i64:
+ return TCG_TARGET_HAS_extract2_i64;
case INDEX_op_extrl_i64_i32:
return TCG_TARGET_HAS_extrl_i64_i32;
case INDEX_op_extrh_i64_i32:
diff --git a/tcg/README b/tcg/README
index 603f4df659..ddabf33017 100644
--- a/tcg/README
+++ b/tcg/README
@@ -343,6 +343,11 @@ at bit 8. This operation would be equivalent to
(using an arithmetic right shift).
+* extract2_i64 dest, t1, t2, pos
+
+Extract a 64-bit quantity from the concatenation of t2:t1,
+beginning at pos.
+
* extrl_i64_i32 t0, t1
For 64-bit hosts only, extract the low 32-bits of input T1 and place it
--
2.17.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 2/9] tcg: Add INDEX_op_extract2_{i32,i64}
2019-03-07 14:41 ` [Qemu-devel] [PATCH 2/9] tcg: Add INDEX_op_extract2_{i32,i64} Richard Henderson
@ 2019-03-07 15:19 ` David Hildenbrand
2019-03-08 23:28 ` Philippe Mathieu-Daudé
[not found] ` <CAFEAcA8JwtiBSgUg_8kg52GETGd3vbX86nvziXa6ZyvqDPLt5g@mail.gmail.com>
2 siblings, 0 replies; 33+ messages in thread
From: David Hildenbrand @ 2019-03-07 15:19 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 07.03.19 15:41, Richard Henderson wrote:
> This will let backends implement the double-word shift operation.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/aarch64/tcg-target.h | 2 ++
> tcg/arm/tcg-target.h | 1 +
> tcg/i386/tcg-target.h | 2 ++
> tcg/mips/tcg-target.h | 2 ++
> tcg/ppc/tcg-target.h | 2 ++
> tcg/riscv/tcg-target.h | 2 ++
> tcg/s390/tcg-target.h | 2 ++
> tcg/sparc/tcg-target.h | 2 ++
> tcg/tcg-opc.h | 2 ++
> tcg/tcg.h | 1 +
> tcg/tci/tcg-target.h | 2 ++
> tcg/optimize.c | 10 ++++++++++
> tcg/tcg-op.c | 4 ++++
> tcg/tcg.c | 4 ++++
> tcg/README | 5 +++++
> 15 files changed, 43 insertions(+)
>
> diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
> index 2d93cf404e..6600a54a02 100644
> --- a/tcg/aarch64/tcg-target.h
> +++ b/tcg/aarch64/tcg-target.h
> @@ -77,6 +77,7 @@ typedef enum {
> #define TCG_TARGET_HAS_deposit_i32 1
> #define TCG_TARGET_HAS_extract_i32 1
> #define TCG_TARGET_HAS_sextract_i32 1
> +#define TCG_TARGET_HAS_extract2_i32 0
> #define TCG_TARGET_HAS_movcond_i32 1
> #define TCG_TARGET_HAS_add2_i32 1
> #define TCG_TARGET_HAS_sub2_i32 1
> @@ -113,6 +114,7 @@ typedef enum {
> #define TCG_TARGET_HAS_deposit_i64 1
> #define TCG_TARGET_HAS_extract_i64 1
> #define TCG_TARGET_HAS_sextract_i64 1
> +#define TCG_TARGET_HAS_extract2_i64 0
> #define TCG_TARGET_HAS_movcond_i64 1
> #define TCG_TARGET_HAS_add2_i64 1
> #define TCG_TARGET_HAS_sub2_i64 1
> diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
> index 16172f73a3..4ee6c98958 100644
> --- a/tcg/arm/tcg-target.h
> +++ b/tcg/arm/tcg-target.h
> @@ -116,6 +116,7 @@ extern bool use_idiv_instructions;
> #define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions
> #define TCG_TARGET_HAS_extract_i32 use_armv7_instructions
> #define TCG_TARGET_HAS_sextract_i32 use_armv7_instructions
> +#define TCG_TARGET_HAS_extract2_i32 0
> #define TCG_TARGET_HAS_movcond_i32 1
> #define TCG_TARGET_HAS_mulu2_i32 1
> #define TCG_TARGET_HAS_muls2_i32 1
> diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
> index 7995fe3eab..2c58eaa9ed 100644
> --- a/tcg/i386/tcg-target.h
> +++ b/tcg/i386/tcg-target.h
> @@ -124,6 +124,7 @@ extern bool have_avx2;
> #define TCG_TARGET_HAS_deposit_i32 1
> #define TCG_TARGET_HAS_extract_i32 1
> #define TCG_TARGET_HAS_sextract_i32 1
> +#define TCG_TARGET_HAS_extract2_i32 0
> #define TCG_TARGET_HAS_movcond_i32 1
> #define TCG_TARGET_HAS_add2_i32 1
> #define TCG_TARGET_HAS_sub2_i32 1
> @@ -162,6 +163,7 @@ extern bool have_avx2;
> #define TCG_TARGET_HAS_deposit_i64 1
> #define TCG_TARGET_HAS_extract_i64 1
> #define TCG_TARGET_HAS_sextract_i64 0
> +#define TCG_TARGET_HAS_extract2_i64 0
> #define TCG_TARGET_HAS_movcond_i64 1
> #define TCG_TARGET_HAS_add2_i64 1
> #define TCG_TARGET_HAS_sub2_i64 1
> diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
> index 5cb8672470..c6b091d849 100644
> --- a/tcg/mips/tcg-target.h
> +++ b/tcg/mips/tcg-target.h
> @@ -162,6 +162,7 @@ extern bool use_mips32r2_instructions;
> #define TCG_TARGET_HAS_deposit_i32 use_mips32r2_instructions
> #define TCG_TARGET_HAS_extract_i32 use_mips32r2_instructions
> #define TCG_TARGET_HAS_sextract_i32 0
> +#define TCG_TARGET_HAS_extract2_i32 0
> #define TCG_TARGET_HAS_ext8s_i32 use_mips32r2_instructions
> #define TCG_TARGET_HAS_ext16s_i32 use_mips32r2_instructions
> #define TCG_TARGET_HAS_rot_i32 use_mips32r2_instructions
> @@ -177,6 +178,7 @@ extern bool use_mips32r2_instructions;
> #define TCG_TARGET_HAS_deposit_i64 use_mips32r2_instructions
> #define TCG_TARGET_HAS_extract_i64 use_mips32r2_instructions
> #define TCG_TARGET_HAS_sextract_i64 0
> +#define TCG_TARGET_HAS_extract2_i64 0
> #define TCG_TARGET_HAS_ext8s_i64 use_mips32r2_instructions
> #define TCG_TARGET_HAS_ext16s_i64 use_mips32r2_instructions
> #define TCG_TARGET_HAS_rot_i64 use_mips32r2_instructions
> diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
> index 52c1bb04b1..7627fb62d3 100644
> --- a/tcg/ppc/tcg-target.h
> +++ b/tcg/ppc/tcg-target.h
> @@ -77,6 +77,7 @@ extern bool have_isa_3_00;
> #define TCG_TARGET_HAS_deposit_i32 1
> #define TCG_TARGET_HAS_extract_i32 1
> #define TCG_TARGET_HAS_sextract_i32 0
> +#define TCG_TARGET_HAS_extract2_i32 0
> #define TCG_TARGET_HAS_movcond_i32 1
> #define TCG_TARGET_HAS_mulu2_i32 0
> #define TCG_TARGET_HAS_muls2_i32 0
> @@ -115,6 +116,7 @@ extern bool have_isa_3_00;
> #define TCG_TARGET_HAS_deposit_i64 1
> #define TCG_TARGET_HAS_extract_i64 1
> #define TCG_TARGET_HAS_sextract_i64 0
> +#define TCG_TARGET_HAS_extract2_i64 0
> #define TCG_TARGET_HAS_movcond_i64 1
> #define TCG_TARGET_HAS_add2_i64 1
> #define TCG_TARGET_HAS_sub2_i64 1
> diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
> index 60918cacb4..032439d806 100644
> --- a/tcg/riscv/tcg-target.h
> +++ b/tcg/riscv/tcg-target.h
> @@ -93,6 +93,7 @@ typedef enum {
> #define TCG_TARGET_HAS_deposit_i32 0
> #define TCG_TARGET_HAS_extract_i32 0
> #define TCG_TARGET_HAS_sextract_i32 0
> +#define TCG_TARGET_HAS_extract2_i32 0
> #define TCG_TARGET_HAS_add2_i32 1
> #define TCG_TARGET_HAS_sub2_i32 1
> #define TCG_TARGET_HAS_mulu2_i32 0
> @@ -128,6 +129,7 @@ typedef enum {
> #define TCG_TARGET_HAS_deposit_i64 0
> #define TCG_TARGET_HAS_extract_i64 0
> #define TCG_TARGET_HAS_sextract_i64 0
> +#define TCG_TARGET_HAS_extract2_i64 0
> #define TCG_TARGET_HAS_extrl_i64_i32 1
> #define TCG_TARGET_HAS_extrh_i64_i32 1
> #define TCG_TARGET_HAS_ext8s_i64 1
> diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
> index 853ed6e7aa..07accabbd1 100644
> --- a/tcg/s390/tcg-target.h
> +++ b/tcg/s390/tcg-target.h
> @@ -85,6 +85,7 @@ extern uint64_t s390_facilities;
> #define TCG_TARGET_HAS_deposit_i32 (s390_facilities & FACILITY_GEN_INST_EXT)
> #define TCG_TARGET_HAS_extract_i32 (s390_facilities & FACILITY_GEN_INST_EXT)
> #define TCG_TARGET_HAS_sextract_i32 0
> +#define TCG_TARGET_HAS_extract2_i32 0
> #define TCG_TARGET_HAS_movcond_i32 1
> #define TCG_TARGET_HAS_add2_i32 1
> #define TCG_TARGET_HAS_sub2_i32 1
> @@ -121,6 +122,7 @@ extern uint64_t s390_facilities;
> #define TCG_TARGET_HAS_deposit_i64 (s390_facilities & FACILITY_GEN_INST_EXT)
> #define TCG_TARGET_HAS_extract_i64 (s390_facilities & FACILITY_GEN_INST_EXT)
> #define TCG_TARGET_HAS_sextract_i64 0
> +#define TCG_TARGET_HAS_extract2_i64 0
> #define TCG_TARGET_HAS_movcond_i64 1
> #define TCG_TARGET_HAS_add2_i64 1
> #define TCG_TARGET_HAS_sub2_i64 1
> diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
> index a0ed2a3342..633841ebf2 100644
> --- a/tcg/sparc/tcg-target.h
> +++ b/tcg/sparc/tcg-target.h
> @@ -116,6 +116,7 @@ extern bool use_vis3_instructions;
> #define TCG_TARGET_HAS_deposit_i32 0
> #define TCG_TARGET_HAS_extract_i32 0
> #define TCG_TARGET_HAS_sextract_i32 0
> +#define TCG_TARGET_HAS_extract2_i32 0
> #define TCG_TARGET_HAS_movcond_i32 1
> #define TCG_TARGET_HAS_add2_i32 1
> #define TCG_TARGET_HAS_sub2_i32 1
> @@ -153,6 +154,7 @@ extern bool use_vis3_instructions;
> #define TCG_TARGET_HAS_deposit_i64 0
> #define TCG_TARGET_HAS_extract_i64 0
> #define TCG_TARGET_HAS_sextract_i64 0
> +#define TCG_TARGET_HAS_extract2_i64 0
> #define TCG_TARGET_HAS_movcond_i64 1
> #define TCG_TARGET_HAS_add2_i64 1
> #define TCG_TARGET_HAS_sub2_i64 1
> diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
> index 4e0238ad1a..1bad6e4208 100644
> --- a/tcg/tcg-opc.h
> +++ b/tcg/tcg-opc.h
> @@ -79,6 +79,7 @@ DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
> DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32))
> DEF(extract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_extract_i32))
> DEF(sextract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_sextract_i32))
> +DEF(extract2_i32, 1, 2, 1, IMPL(TCG_TARGET_HAS_extract2_i32))
>
> DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END)
>
> @@ -146,6 +147,7 @@ DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
> DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64))
> DEF(extract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_extract_i64))
> DEF(sextract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_sextract_i64))
> +DEF(extract2_i64, 1, 2, 1, IMPL64 | IMPL(TCG_TARGET_HAS_extract2_i64))
>
> /* size changing ops */
> DEF(ext_i32_i64, 1, 1, 0, IMPL64)
> diff --git a/tcg/tcg.h b/tcg/tcg.h
> index 32b7cf3489..7b1c15b40b 100644
> --- a/tcg/tcg.h
> +++ b/tcg/tcg.h
> @@ -125,6 +125,7 @@ typedef uint64_t TCGRegSet;
> #define TCG_TARGET_HAS_deposit_i64 0
> #define TCG_TARGET_HAS_extract_i64 0
> #define TCG_TARGET_HAS_sextract_i64 0
> +#define TCG_TARGET_HAS_extract2_i64 0
> #define TCG_TARGET_HAS_movcond_i64 0
> #define TCG_TARGET_HAS_add2_i64 0
> #define TCG_TARGET_HAS_sub2_i64 0
> diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
> index 086f34e69a..8b90ab71cb 100644
> --- a/tcg/tci/tcg-target.h
> +++ b/tcg/tci/tcg-target.h
> @@ -71,6 +71,7 @@
> #define TCG_TARGET_HAS_deposit_i32 1
> #define TCG_TARGET_HAS_extract_i32 0
> #define TCG_TARGET_HAS_sextract_i32 0
> +#define TCG_TARGET_HAS_extract2_i32 0
> #define TCG_TARGET_HAS_eqv_i32 0
> #define TCG_TARGET_HAS_nand_i32 0
> #define TCG_TARGET_HAS_nor_i32 0
> @@ -97,6 +98,7 @@
> #define TCG_TARGET_HAS_deposit_i64 1
> #define TCG_TARGET_HAS_extract_i64 0
> #define TCG_TARGET_HAS_sextract_i64 0
> +#define TCG_TARGET_HAS_extract2_i64 0
> #define TCG_TARGET_HAS_div_i64 0
> #define TCG_TARGET_HAS_rem_i64 0
> #define TCG_TARGET_HAS_ext8s_i64 1
> diff --git a/tcg/optimize.c b/tcg/optimize.c
> index 01e80c3e46..a5f50a0608 100644
> --- a/tcg/optimize.c
> +++ b/tcg/optimize.c
> @@ -1202,6 +1202,16 @@ void tcg_optimize(TCGContext *s)
> }
> goto do_default;
>
> + CASE_OP_32_64(extract2):
> + if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
> + TCGArg v1 = arg_info(op->args[1])->val;
> + TCGArg v2 = arg_info(op->args[2])->val;
> + tmp = (v1 >> op->args[3]) | (v2 << (64 - op->args[3]));> + tcg_opt_gen_movi(s, op, op->args[0], tmp);
> + break;
> + }
> + goto do_default;
> +
> CASE_OP_32_64(setcond):
> tmp = do_constant_folding_cond(opc, op->args[1],
> op->args[2], op->args[3]);
> diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
> index 7c56c92c8e..deacc63e3b 100644
> --- a/tcg/tcg-op.c
> +++ b/tcg/tcg-op.c
> @@ -823,6 +823,8 @@ void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah,
> tcg_gen_mov_i32(ret, ah);
> } else if (al == ah) {
> tcg_gen_rotri_i32(ret, al, ofs);
> + } else if (TCG_TARGET_HAS_extract2_i32) {
> + tcg_gen_op4i_i32(INDEX_op_extract2_i32, ret, al, ah, ofs);
> } else {
> TCGv_i32 t0 = tcg_temp_new_i32();
> tcg_gen_shri_i32(t0, al, ofs);
> @@ -2333,6 +2335,8 @@ void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah,
> tcg_gen_mov_i64(ret, ah);
> } else if (al == ah) {
> tcg_gen_rotri_i64(ret, al, ofs);
> + } else if (TCG_TARGET_HAS_extract2_i64) {
> + tcg_gen_op4i_i64(INDEX_op_extract2_i64, ret, al, ah, ofs);
> } else {
> TCGv_i64 t0 = tcg_temp_new_i64();
> tcg_gen_shri_i64(t0, al, ofs);
> diff --git a/tcg/tcg.c b/tcg/tcg.c
> index 9b2bf7f439..ade6050982 100644
> --- a/tcg/tcg.c
> +++ b/tcg/tcg.c
> @@ -1425,6 +1425,8 @@ bool tcg_op_supported(TCGOpcode op)
> return TCG_TARGET_HAS_extract_i32;
> case INDEX_op_sextract_i32:
> return TCG_TARGET_HAS_sextract_i32;
> + case INDEX_op_extract2_i32:
> + return TCG_TARGET_HAS_extract2_i32;
> case INDEX_op_add2_i32:
> return TCG_TARGET_HAS_add2_i32;
> case INDEX_op_sub2_i32:
> @@ -1522,6 +1524,8 @@ bool tcg_op_supported(TCGOpcode op)
> return TCG_TARGET_HAS_extract_i64;
> case INDEX_op_sextract_i64:
> return TCG_TARGET_HAS_sextract_i64;
> + case INDEX_op_extract2_i64:
> + return TCG_TARGET_HAS_extract2_i64;
> case INDEX_op_extrl_i64_i32:
> return TCG_TARGET_HAS_extrl_i64_i32;
> case INDEX_op_extrh_i64_i32:
> diff --git a/tcg/README b/tcg/README
> index 603f4df659..ddabf33017 100644
> --- a/tcg/README
> +++ b/tcg/README
> @@ -343,6 +343,11 @@ at bit 8. This operation would be equivalent to
>
> (using an arithmetic right shift).
>
> +* extract2_i64 dest, t1, t2, pos
> +
> +Extract a 64-bit quantity from the concatenation of t2:t1,
> +beginning at pos.
> +
> * extrl_i64_i32 t0, t1
>
> For 64-bit hosts only, extract the low 32-bits of input T1 and place it
>
Looks good to me
Reviewed-by: David Hildenbrand <david@redhat.com>
--
Thanks,
David / dhildenb
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 2/9] tcg: Add INDEX_op_extract2_{i32,i64}
2019-03-07 14:41 ` [Qemu-devel] [PATCH 2/9] tcg: Add INDEX_op_extract2_{i32,i64} Richard Henderson
2019-03-07 15:19 ` David Hildenbrand
@ 2019-03-08 23:28 ` Philippe Mathieu-Daudé
2019-03-09 16:37 ` Richard Henderson
[not found] ` <CAFEAcA8JwtiBSgUg_8kg52GETGd3vbX86nvziXa6ZyvqDPLt5g@mail.gmail.com>
2 siblings, 1 reply; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-03-08 23:28 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: david
Hi Richard,
On 3/7/19 3:41 PM, Richard Henderson wrote:
> This will let backends implement the double-word shift operation.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/aarch64/tcg-target.h | 2 ++
> tcg/arm/tcg-target.h | 1 +
> tcg/i386/tcg-target.h | 2 ++
> tcg/mips/tcg-target.h | 2 ++
> tcg/ppc/tcg-target.h | 2 ++
> tcg/riscv/tcg-target.h | 2 ++
> tcg/s390/tcg-target.h | 2 ++
> tcg/sparc/tcg-target.h | 2 ++
> tcg/tcg-opc.h | 2 ++
> tcg/tcg.h | 1 +
> tcg/tci/tcg-target.h | 2 ++
> tcg/optimize.c | 10 ++++++++++
> tcg/tcg-op.c | 4 ++++
> tcg/tcg.c | 4 ++++
> tcg/README | 5 +++++
> 15 files changed, 43 insertions(+)
>
> diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
> index 2d93cf404e..6600a54a02 100644
> --- a/tcg/aarch64/tcg-target.h
> +++ b/tcg/aarch64/tcg-target.h
> @@ -77,6 +77,7 @@ typedef enum {
> #define TCG_TARGET_HAS_deposit_i32 1
> #define TCG_TARGET_HAS_extract_i32 1
> #define TCG_TARGET_HAS_sextract_i32 1
> +#define TCG_TARGET_HAS_extract2_i32 0
> #define TCG_TARGET_HAS_movcond_i32 1
> #define TCG_TARGET_HAS_add2_i32 1
> #define TCG_TARGET_HAS_sub2_i32 1
> @@ -113,6 +114,7 @@ typedef enum {
> #define TCG_TARGET_HAS_deposit_i64 1
> #define TCG_TARGET_HAS_extract_i64 1
> #define TCG_TARGET_HAS_sextract_i64 1
> +#define TCG_TARGET_HAS_extract2_i64 0
> #define TCG_TARGET_HAS_movcond_i64 1
> #define TCG_TARGET_HAS_add2_i64 1
> #define TCG_TARGET_HAS_sub2_i64 1
> diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
> index 16172f73a3..4ee6c98958 100644
> --- a/tcg/arm/tcg-target.h
> +++ b/tcg/arm/tcg-target.h
> @@ -116,6 +116,7 @@ extern bool use_idiv_instructions;
> #define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions
> #define TCG_TARGET_HAS_extract_i32 use_armv7_instructions
> #define TCG_TARGET_HAS_sextract_i32 use_armv7_instructions
> +#define TCG_TARGET_HAS_extract2_i32 0
> #define TCG_TARGET_HAS_movcond_i32 1
> #define TCG_TARGET_HAS_mulu2_i32 1
> #define TCG_TARGET_HAS_muls2_i32 1
> diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
> index 7995fe3eab..2c58eaa9ed 100644
> --- a/tcg/i386/tcg-target.h
> +++ b/tcg/i386/tcg-target.h
> @@ -124,6 +124,7 @@ extern bool have_avx2;
> #define TCG_TARGET_HAS_deposit_i32 1
> #define TCG_TARGET_HAS_extract_i32 1
> #define TCG_TARGET_HAS_sextract_i32 1
> +#define TCG_TARGET_HAS_extract2_i32 0
> #define TCG_TARGET_HAS_movcond_i32 1
> #define TCG_TARGET_HAS_add2_i32 1
> #define TCG_TARGET_HAS_sub2_i32 1
> @@ -162,6 +163,7 @@ extern bool have_avx2;
> #define TCG_TARGET_HAS_deposit_i64 1
> #define TCG_TARGET_HAS_extract_i64 1
> #define TCG_TARGET_HAS_sextract_i64 0
> +#define TCG_TARGET_HAS_extract2_i64 0
> #define TCG_TARGET_HAS_movcond_i64 1
> #define TCG_TARGET_HAS_add2_i64 1
> #define TCG_TARGET_HAS_sub2_i64 1
> diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
> index 5cb8672470..c6b091d849 100644
> --- a/tcg/mips/tcg-target.h
> +++ b/tcg/mips/tcg-target.h
> @@ -162,6 +162,7 @@ extern bool use_mips32r2_instructions;
> #define TCG_TARGET_HAS_deposit_i32 use_mips32r2_instructions
> #define TCG_TARGET_HAS_extract_i32 use_mips32r2_instructions
> #define TCG_TARGET_HAS_sextract_i32 0
> +#define TCG_TARGET_HAS_extract2_i32 0
> #define TCG_TARGET_HAS_ext8s_i32 use_mips32r2_instructions
> #define TCG_TARGET_HAS_ext16s_i32 use_mips32r2_instructions
> #define TCG_TARGET_HAS_rot_i32 use_mips32r2_instructions
> @@ -177,6 +178,7 @@ extern bool use_mips32r2_instructions;
> #define TCG_TARGET_HAS_deposit_i64 use_mips32r2_instructions
> #define TCG_TARGET_HAS_extract_i64 use_mips32r2_instructions
> #define TCG_TARGET_HAS_sextract_i64 0
> +#define TCG_TARGET_HAS_extract2_i64 0
> #define TCG_TARGET_HAS_ext8s_i64 use_mips32r2_instructions
> #define TCG_TARGET_HAS_ext16s_i64 use_mips32r2_instructions
> #define TCG_TARGET_HAS_rot_i64 use_mips32r2_instructions
> diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
> index 52c1bb04b1..7627fb62d3 100644
> --- a/tcg/ppc/tcg-target.h
> +++ b/tcg/ppc/tcg-target.h
> @@ -77,6 +77,7 @@ extern bool have_isa_3_00;
> #define TCG_TARGET_HAS_deposit_i32 1
> #define TCG_TARGET_HAS_extract_i32 1
> #define TCG_TARGET_HAS_sextract_i32 0
> +#define TCG_TARGET_HAS_extract2_i32 0
> #define TCG_TARGET_HAS_movcond_i32 1
> #define TCG_TARGET_HAS_mulu2_i32 0
> #define TCG_TARGET_HAS_muls2_i32 0
> @@ -115,6 +116,7 @@ extern bool have_isa_3_00;
> #define TCG_TARGET_HAS_deposit_i64 1
> #define TCG_TARGET_HAS_extract_i64 1
> #define TCG_TARGET_HAS_sextract_i64 0
> +#define TCG_TARGET_HAS_extract2_i64 0
> #define TCG_TARGET_HAS_movcond_i64 1
> #define TCG_TARGET_HAS_add2_i64 1
> #define TCG_TARGET_HAS_sub2_i64 1
> diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
> index 60918cacb4..032439d806 100644
> --- a/tcg/riscv/tcg-target.h
> +++ b/tcg/riscv/tcg-target.h
> @@ -93,6 +93,7 @@ typedef enum {
> #define TCG_TARGET_HAS_deposit_i32 0
> #define TCG_TARGET_HAS_extract_i32 0
> #define TCG_TARGET_HAS_sextract_i32 0
> +#define TCG_TARGET_HAS_extract2_i32 0
> #define TCG_TARGET_HAS_add2_i32 1
> #define TCG_TARGET_HAS_sub2_i32 1
> #define TCG_TARGET_HAS_mulu2_i32 0
> @@ -128,6 +129,7 @@ typedef enum {
> #define TCG_TARGET_HAS_deposit_i64 0
> #define TCG_TARGET_HAS_extract_i64 0
> #define TCG_TARGET_HAS_sextract_i64 0
> +#define TCG_TARGET_HAS_extract2_i64 0
> #define TCG_TARGET_HAS_extrl_i64_i32 1
> #define TCG_TARGET_HAS_extrh_i64_i32 1
> #define TCG_TARGET_HAS_ext8s_i64 1
> diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
> index 853ed6e7aa..07accabbd1 100644
> --- a/tcg/s390/tcg-target.h
> +++ b/tcg/s390/tcg-target.h
> @@ -85,6 +85,7 @@ extern uint64_t s390_facilities;
> #define TCG_TARGET_HAS_deposit_i32 (s390_facilities & FACILITY_GEN_INST_EXT)
> #define TCG_TARGET_HAS_extract_i32 (s390_facilities & FACILITY_GEN_INST_EXT)
> #define TCG_TARGET_HAS_sextract_i32 0
> +#define TCG_TARGET_HAS_extract2_i32 0
> #define TCG_TARGET_HAS_movcond_i32 1
> #define TCG_TARGET_HAS_add2_i32 1
> #define TCG_TARGET_HAS_sub2_i32 1
> @@ -121,6 +122,7 @@ extern uint64_t s390_facilities;
> #define TCG_TARGET_HAS_deposit_i64 (s390_facilities & FACILITY_GEN_INST_EXT)
> #define TCG_TARGET_HAS_extract_i64 (s390_facilities & FACILITY_GEN_INST_EXT)
> #define TCG_TARGET_HAS_sextract_i64 0
> +#define TCG_TARGET_HAS_extract2_i64 0
> #define TCG_TARGET_HAS_movcond_i64 1
> #define TCG_TARGET_HAS_add2_i64 1
> #define TCG_TARGET_HAS_sub2_i64 1
> diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
> index a0ed2a3342..633841ebf2 100644
> --- a/tcg/sparc/tcg-target.h
> +++ b/tcg/sparc/tcg-target.h
> @@ -116,6 +116,7 @@ extern bool use_vis3_instructions;
> #define TCG_TARGET_HAS_deposit_i32 0
> #define TCG_TARGET_HAS_extract_i32 0
> #define TCG_TARGET_HAS_sextract_i32 0
> +#define TCG_TARGET_HAS_extract2_i32 0
> #define TCG_TARGET_HAS_movcond_i32 1
> #define TCG_TARGET_HAS_add2_i32 1
> #define TCG_TARGET_HAS_sub2_i32 1
> @@ -153,6 +154,7 @@ extern bool use_vis3_instructions;
> #define TCG_TARGET_HAS_deposit_i64 0
> #define TCG_TARGET_HAS_extract_i64 0
> #define TCG_TARGET_HAS_sextract_i64 0
> +#define TCG_TARGET_HAS_extract2_i64 0
> #define TCG_TARGET_HAS_movcond_i64 1
> #define TCG_TARGET_HAS_add2_i64 1
> #define TCG_TARGET_HAS_sub2_i64 1
> diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
> index 4e0238ad1a..1bad6e4208 100644
> --- a/tcg/tcg-opc.h
> +++ b/tcg/tcg-opc.h
> @@ -79,6 +79,7 @@ DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
> DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32))
> DEF(extract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_extract_i32))
> DEF(sextract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_sextract_i32))
> +DEF(extract2_i32, 1, 2, 1, IMPL(TCG_TARGET_HAS_extract2_i32))
>
> DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END)
>
> @@ -146,6 +147,7 @@ DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
> DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64))
> DEF(extract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_extract_i64))
> DEF(sextract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_sextract_i64))
> +DEF(extract2_i64, 1, 2, 1, IMPL64 | IMPL(TCG_TARGET_HAS_extract2_i64))
>
> /* size changing ops */
> DEF(ext_i32_i64, 1, 1, 0, IMPL64)
> diff --git a/tcg/tcg.h b/tcg/tcg.h
> index 32b7cf3489..7b1c15b40b 100644
> --- a/tcg/tcg.h
> +++ b/tcg/tcg.h
> @@ -125,6 +125,7 @@ typedef uint64_t TCGRegSet;
> #define TCG_TARGET_HAS_deposit_i64 0
> #define TCG_TARGET_HAS_extract_i64 0
> #define TCG_TARGET_HAS_sextract_i64 0
> +#define TCG_TARGET_HAS_extract2_i64 0
> #define TCG_TARGET_HAS_movcond_i64 0
> #define TCG_TARGET_HAS_add2_i64 0
> #define TCG_TARGET_HAS_sub2_i64 0
> diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
> index 086f34e69a..8b90ab71cb 100644
> --- a/tcg/tci/tcg-target.h
> +++ b/tcg/tci/tcg-target.h
> @@ -71,6 +71,7 @@
> #define TCG_TARGET_HAS_deposit_i32 1
> #define TCG_TARGET_HAS_extract_i32 0
> #define TCG_TARGET_HAS_sextract_i32 0
> +#define TCG_TARGET_HAS_extract2_i32 0
> #define TCG_TARGET_HAS_eqv_i32 0
> #define TCG_TARGET_HAS_nand_i32 0
> #define TCG_TARGET_HAS_nor_i32 0
> @@ -97,6 +98,7 @@
> #define TCG_TARGET_HAS_deposit_i64 1
> #define TCG_TARGET_HAS_extract_i64 0
> #define TCG_TARGET_HAS_sextract_i64 0
> +#define TCG_TARGET_HAS_extract2_i64 0
> #define TCG_TARGET_HAS_div_i64 0
> #define TCG_TARGET_HAS_rem_i64 0
> #define TCG_TARGET_HAS_ext8s_i64 1
> diff --git a/tcg/optimize.c b/tcg/optimize.c
> index 01e80c3e46..a5f50a0608 100644
> --- a/tcg/optimize.c
> +++ b/tcg/optimize.c
> @@ -1202,6 +1202,16 @@ void tcg_optimize(TCGContext *s)
> }
> goto do_default;
>
> + CASE_OP_32_64(extract2):
> + if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
> + TCGArg v1 = arg_info(op->args[1])->val;
> + TCGArg v2 = arg_info(op->args[2])->val;
> + tmp = (v1 >> op->args[3]) | (v2 << (64 - op->args[3]));
Shouldn't this be:
tmp = (v1 >> op->args[3]) | (v2 << (TCG_TARGET_REG_BITS - op->args[3]));
?
> + tcg_opt_gen_movi(s, op, op->args[0], tmp);
> + break;
> + }
> + goto do_default;
> +
> CASE_OP_32_64(setcond):
> tmp = do_constant_folding_cond(opc, op->args[1],
> op->args[2], op->args[3]);
> diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
> index 7c56c92c8e..deacc63e3b 100644
> --- a/tcg/tcg-op.c
> +++ b/tcg/tcg-op.c
> @@ -823,6 +823,8 @@ void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah,
> tcg_gen_mov_i32(ret, ah);
> } else if (al == ah) {
> tcg_gen_rotri_i32(ret, al, ofs);
> + } else if (TCG_TARGET_HAS_extract2_i32) {
> + tcg_gen_op4i_i32(INDEX_op_extract2_i32, ret, al, ah, ofs);
> } else {
> TCGv_i32 t0 = tcg_temp_new_i32();
> tcg_gen_shri_i32(t0, al, ofs);
> @@ -2333,6 +2335,8 @@ void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah,
> tcg_gen_mov_i64(ret, ah);
> } else if (al == ah) {
> tcg_gen_rotri_i64(ret, al, ofs);
> + } else if (TCG_TARGET_HAS_extract2_i64) {
> + tcg_gen_op4i_i64(INDEX_op_extract2_i64, ret, al, ah, ofs);
> } else {
> TCGv_i64 t0 = tcg_temp_new_i64();
> tcg_gen_shri_i64(t0, al, ofs);
> diff --git a/tcg/tcg.c b/tcg/tcg.c
> index 9b2bf7f439..ade6050982 100644
> --- a/tcg/tcg.c
> +++ b/tcg/tcg.c
> @@ -1425,6 +1425,8 @@ bool tcg_op_supported(TCGOpcode op)
> return TCG_TARGET_HAS_extract_i32;
> case INDEX_op_sextract_i32:
> return TCG_TARGET_HAS_sextract_i32;
> + case INDEX_op_extract2_i32:
> + return TCG_TARGET_HAS_extract2_i32;
> case INDEX_op_add2_i32:
> return TCG_TARGET_HAS_add2_i32;
> case INDEX_op_sub2_i32:
> @@ -1522,6 +1524,8 @@ bool tcg_op_supported(TCGOpcode op)
> return TCG_TARGET_HAS_extract_i64;
> case INDEX_op_sextract_i64:
> return TCG_TARGET_HAS_sextract_i64;
> + case INDEX_op_extract2_i64:
> + return TCG_TARGET_HAS_extract2_i64;
> case INDEX_op_extrl_i64_i32:
> return TCG_TARGET_HAS_extrl_i64_i32;
> case INDEX_op_extrh_i64_i32:
> diff --git a/tcg/README b/tcg/README
> index 603f4df659..ddabf33017 100644
> --- a/tcg/README
> +++ b/tcg/README
> @@ -343,6 +343,11 @@ at bit 8. This operation would be equivalent to
>
> (using an arithmetic right shift).
>
> +* extract2_i64 dest, t1, t2, pos
> +
> +Extract a 64-bit quantity from the concatenation of t2:t1,
> +beginning at pos.
> +
> * extrl_i64_i32 t0, t1
>
> For 64-bit hosts only, extract the low 32-bits of input T1 and place it
>
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 2/9] tcg: Add INDEX_op_extract2_{i32,i64}
2019-03-08 23:28 ` Philippe Mathieu-Daudé
@ 2019-03-09 16:37 ` Richard Henderson
0 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2019-03-09 16:37 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: david
On 3/8/19 3:28 PM, Philippe Mathieu-Daudé wrote:
>> + CASE_OP_32_64(extract2):
>> + if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
>> + TCGArg v1 = arg_info(op->args[1])->val;
>> + TCGArg v2 = arg_info(op->args[2])->val;
>> + tmp = (v1 >> op->args[3]) | (v2 << (64 - op->args[3]));
> Shouldn't this be:
>
> tmp = (v1 >> op->args[3]) | (v2 << (TCG_TARGET_REG_BITS - op->args[3]));
No, but there should be different constants for the two cases.
Thanks.
r~
^ permalink raw reply [flat|nested] 33+ messages in thread
[parent not found: <CAFEAcA8JwtiBSgUg_8kg52GETGd3vbX86nvziXa6ZyvqDPLt5g@mail.gmail.com>]
* Re: [Qemu-devel] [PATCH 2/9] tcg: Add INDEX_op_extract2_{i32,i64}
[not found] ` <CAFEAcA8JwtiBSgUg_8kg52GETGd3vbX86nvziXa6ZyvqDPLt5g@mail.gmail.com>
@ 2019-04-03 11:37 ` Richard Henderson
2019-04-03 11:56 ` Peter Maydell
0 siblings, 1 reply; 33+ messages in thread
From: Richard Henderson @ 2019-04-03 11:37 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers, David Hildenbrand
On 3/26/19 8:35 PM, Peter Maydell wrote:
> On Thu, 7 Mar 2019 at 14:47, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> This will let backends implement the double-word shift operation.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> diff --git a/tcg/README b/tcg/README
>> index 603f4df659..ddabf33017 100644
>> --- a/tcg/README
>> +++ b/tcg/README
>> @@ -343,6 +343,11 @@ at bit 8. This operation would be equivalent to
>>
>> (using an arithmetic right shift).
>>
>> +* extract2_i64 dest, t1, t2, pos
>> +
>> +Extract a 64-bit quantity from the concatenation of t2:t1,
>> +beginning at pos.
>> +
>
> I think we should document the valid values of 'pos'.
> My guess is "0 <= pos <= 63".
How about
----
* extract2_i32/i64 dest, t1, t2, pos
For N = {32,64}, extract an N-bit quantity from the concatenation
of t2:t1, beginning at pos. The tcg_gen_extract2_* expander allows
values 0 <= pos <= N, but will expand 0 and N with mov, so only
1 <= pos <= N-1 will be seen by the host tcg_out_op.
----
?
r~
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 2/9] tcg: Add INDEX_op_extract2_{i32,i64}
2019-04-03 11:37 ` Richard Henderson
@ 2019-04-03 11:56 ` Peter Maydell
2019-04-13 8:31 ` Richard Henderson
0 siblings, 1 reply; 33+ messages in thread
From: Peter Maydell @ 2019-04-03 11:56 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers, David Hildenbrand
On Wed, 3 Apr 2019 at 18:37, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 3/26/19 8:35 PM, Peter Maydell wrote:
> > On Thu, 7 Mar 2019 at 14:47, Richard Henderson
> > <richard.henderson@linaro.org> wrote:
> >>
> >> This will let backends implement the double-word shift operation.
> >>
> >> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> >> diff --git a/tcg/README b/tcg/README
> >> index 603f4df659..ddabf33017 100644
> >> --- a/tcg/README
> >> +++ b/tcg/README
> >> @@ -343,6 +343,11 @@ at bit 8. This operation would be equivalent to
> >>
> >> (using an arithmetic right shift).
> >>
> >> +* extract2_i64 dest, t1, t2, pos
> >> +
> >> +Extract a 64-bit quantity from the concatenation of t2:t1,
> >> +beginning at pos.
> >> +
> >
> > I think we should document the valid values of 'pos'.
> > My guess is "0 <= pos <= 63".
>
> How about
>
> ----
> * extract2_i32/i64 dest, t1, t2, pos
>
> For N = {32,64}, extract an N-bit quantity from the concatenation
> of t2:t1, beginning at pos. The tcg_gen_extract2_* expander allows
> values 0 <= pos <= N, but will expand 0 and N with mov, so only
> 1 <= pos <= N-1 will be seen by the host tcg_out_op.
If I'm reading that correctly, it seems to be combining in one sentence
the behaviour of the TCG API exposed to the front-end (pos can be
between 0 and N inclusive) with a detail of the API that a backend
needs to care about (that it can assume it never sees 0 or N).
I think we should be more careful to keep those separate, because
a reader of this document is almost always going to care only about
one or the other, never both at the same time. Perhaps things that
apply only to the backend end of the interface should go in section 4
of tcg/README? At any rate I think they should at least be in
different sentences :-)
thanks
-- PMM
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 2/9] tcg: Add INDEX_op_extract2_{i32,i64}
2019-04-03 11:56 ` Peter Maydell
@ 2019-04-13 8:31 ` Richard Henderson
0 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2019-04-13 8:31 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers, David Hildenbrand
On 4/3/19 1:56 AM, Peter Maydell wrote:
> On Wed, 3 Apr 2019 at 18:37, Richard Henderson
>> * extract2_i32/i64 dest, t1, t2, pos
>>
>> For N = {32,64}, extract an N-bit quantity from the concatenation
>> of t2:t1, beginning at pos. The tcg_gen_extract2_* expander allows
>> values 0 <= pos <= N, but will expand 0 and N with mov, so only
>> 1 <= pos <= N-1 will be seen by the host tcg_out_op.
>
> If I'm reading that correctly, it seems to be combining in one sentence
> the behaviour of the TCG API exposed to the front-end (pos can be
> between 0 and N inclusive) with a detail of the API that a backend
> needs to care about (that it can assume it never sees 0 or N).
You're not wrong. ;-P
> I think we should be more careful to keep those separate, because
> a reader of this document is almost always going to care only about
> one or the other, never both at the same time. Perhaps things that
> apply only to the backend end of the interface should go in section 4
> of tcg/README?
Sadly, there's a lot of mix up on that count.
Indeed, the very next paragraph,
> * extrl_i64_i32 t0, t1
>
> For 64-bit hosts only, extract the low 32-bits of input T1 and place it
> into 32-bit output T0. Depending on the host, this may be a simple move,
> or may require additional canonicalization.
is entirely about the "section 4" opcode. The "section 2" function,
tcg_gen_extrl_i64_i32, is expanded correctly for 32-bit hosts as a
simple move from the i32 "sub-temp" of the i64 temp.
Clearly the whole thing should be reorganized, but I'm not sure how best that
should be done.
> At any rate I think they should at least be in different sentences :-)
Now that I can do. ;-)
r~
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Qemu-devel] [PATCH 3/9] tcg: Use extract2 in tcg_gen_shifti_i64
2019-03-07 14:41 [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64} Richard Henderson
2019-03-07 14:41 ` [Qemu-devel] [PATCH 1/9] tcg: Implement tcg_gen_extract2_{i32, i64} Richard Henderson
2019-03-07 14:41 ` [Qemu-devel] [PATCH 2/9] tcg: Add INDEX_op_extract2_{i32,i64} Richard Henderson
@ 2019-03-07 14:41 ` Richard Henderson
2019-03-09 1:00 ` Philippe Mathieu-Daudé
2019-03-09 20:30 ` Aleksandar Markovic
2019-03-07 14:41 ` [Qemu-devel] [PATCH 4/9] tcg: Use extract2 in tcg_gen_deposit_{i32, i64} Richard Henderson
` (12 subsequent siblings)
15 siblings, 2 replies; 33+ messages in thread
From: Richard Henderson @ 2019-03-07 14:41 UTC (permalink / raw)
To: qemu-devel; +Cc: david
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg-op.c | 47 ++++++++++++++++++++++++-----------------------
1 file changed, 24 insertions(+), 23 deletions(-)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index deacc63e3b..34e0dbc6e0 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -1355,31 +1355,32 @@ static inline void tcg_gen_shifti_i64(TCGv_i64 ret, TCGv_i64 arg1,
tcg_gen_shli_i32(TCGV_HIGH(ret), TCGV_LOW(arg1), c);
tcg_gen_movi_i32(TCGV_LOW(ret), 0);
}
- } else {
- TCGv_i32 t0, t1;
-
- t0 = tcg_temp_new_i32();
- t1 = tcg_temp_new_i32();
- if (right) {
- tcg_gen_shli_i32(t0, TCGV_HIGH(arg1), 32 - c);
- if (arith) {
- tcg_gen_sari_i32(t1, TCGV_HIGH(arg1), c);
- } else {
- tcg_gen_shri_i32(t1, TCGV_HIGH(arg1), c);
- }
- tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
- tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t0);
- tcg_gen_mov_i32(TCGV_HIGH(ret), t1);
+ } else if (right) {
+ if (TCG_TARGET_HAS_extract2_i32) {
+ tcg_gen_extract2_i32(TCGV_LOW(ret), TCGV_LOW(arg1),
+ TCGV_HIGH(arg1), c);
} else {
- tcg_gen_shri_i32(t0, TCGV_LOW(arg1), 32 - c);
- /* Note: ret can be the same as arg1, so we use t1 */
- tcg_gen_shli_i32(t1, TCGV_LOW(arg1), c);
- tcg_gen_shli_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
- tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t0);
- tcg_gen_mov_i32(TCGV_LOW(ret), t1);
+ tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
+ tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(ret),
+ TCGV_HIGH(arg1), 32 - c, c);
}
- tcg_temp_free_i32(t0);
- tcg_temp_free_i32(t1);
+ if (arith) {
+ tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
+ } else {
+ tcg_gen_shri_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
+ }
+ } else {
+ if (TCG_TARGET_HAS_extract2_i32) {
+ tcg_gen_extract2_i32(TCGV_HIGH(ret), TCGV_LOW(arg1),
+ TCGV_HIGH(arg1), 32 - c);
+ } else {
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ tcg_gen_shri_i32(t0, TCGV_LOW(arg1), 32 - c);
+ tcg_gen_deposit_i32(TCGV_HIGH(ret), t0,
+ TCGV_HIGH(arg1), c, 32 - c);
+ tcg_temp_free_i32(t0);
+ }
+ tcg_gen_shli_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
}
}
--
2.17.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 3/9] tcg: Use extract2 in tcg_gen_shifti_i64
2019-03-07 14:41 ` [Qemu-devel] [PATCH 3/9] tcg: Use extract2 in tcg_gen_shifti_i64 Richard Henderson
@ 2019-03-09 1:00 ` Philippe Mathieu-Daudé
2019-03-09 20:30 ` Aleksandar Markovic
1 sibling, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-03-09 1:00 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: david
Hi Richard,
On 3/7/19 3:41 PM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/tcg-op.c | 47 ++++++++++++++++++++++++-----------------------
> 1 file changed, 24 insertions(+), 23 deletions(-)
>
> diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
> index deacc63e3b..34e0dbc6e0 100644
> --- a/tcg/tcg-op.c
> +++ b/tcg/tcg-op.c
> @@ -1355,31 +1355,32 @@ static inline void tcg_gen_shifti_i64(TCGv_i64 ret, TCGv_i64 arg1,
> tcg_gen_shli_i32(TCGV_HIGH(ret), TCGV_LOW(arg1), c);
> tcg_gen_movi_i32(TCGV_LOW(ret), 0);
> }
> - } else {
> - TCGv_i32 t0, t1;
> -
> - t0 = tcg_temp_new_i32();
> - t1 = tcg_temp_new_i32();
> - if (right) {
> - tcg_gen_shli_i32(t0, TCGV_HIGH(arg1), 32 - c);
> - if (arith) {
> - tcg_gen_sari_i32(t1, TCGV_HIGH(arg1), c);
> - } else {
> - tcg_gen_shri_i32(t1, TCGV_HIGH(arg1), c);
> - }
> - tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
> - tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t0);
> - tcg_gen_mov_i32(TCGV_HIGH(ret), t1);
> + } else if (right) {
> + if (TCG_TARGET_HAS_extract2_i32) {
> + tcg_gen_extract2_i32(TCGV_LOW(ret), TCGV_LOW(arg1),
> + TCGV_HIGH(arg1), c);
> } else {
> - tcg_gen_shri_i32(t0, TCGV_LOW(arg1), 32 - c);
> - /* Note: ret can be the same as arg1, so we use t1 */
> - tcg_gen_shli_i32(t1, TCGV_LOW(arg1), c);
> - tcg_gen_shli_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
> - tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t0);
> - tcg_gen_mov_i32(TCGV_LOW(ret), t1);
> + tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
> + tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(ret),
> + TCGV_HIGH(arg1), 32 - c, c);
> }
> - tcg_temp_free_i32(t0);
> - tcg_temp_free_i32(t1);
> + if (arith) {
> + tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
> + } else {
> + tcg_gen_shri_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
> + }
> + } else {
> + if (TCG_TARGET_HAS_extract2_i32) {
> + tcg_gen_extract2_i32(TCGV_HIGH(ret), TCGV_LOW(arg1),
> + TCGV_HIGH(arg1), 32 - c);
> + } else {
> + TCGv_i32 t0 = tcg_temp_new_i32();
> + tcg_gen_shri_i32(t0, TCGV_LOW(arg1), 32 - c);
> + tcg_gen_deposit_i32(TCGV_HIGH(ret), t0,
> + TCGV_HIGH(arg1), c, 32 - c);
> + tcg_temp_free_i32(t0);
> + }
> + tcg_gen_shli_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
> }
> }
I find this patch quite hard to review because you somehow do more than
simply use extract2, you also reordered part of this function.
I find it easier to review as split in 2 commits:
1/ reorder; the code movement is way easier to follow:
-- >8 --
@@ -1355,31 +1355,22 @@ static inline void tcg_gen_shifti_i64(TCGv_i64
ret, TCGv_i64 arg1,
tcg_gen_shli_i32(TCGV_HIGH(ret), TCGV_LOW(arg1), c);
tcg_gen_movi_i32(TCGV_LOW(ret), 0);
}
- } else {
- TCGv_i32 t0, t1;
-
- t0 = tcg_temp_new_i32();
- t1 = tcg_temp_new_i32();
- if (right) {
- tcg_gen_shli_i32(t0, TCGV_HIGH(arg1), 32 - c);
- if (arith) {
- tcg_gen_sari_i32(t1, TCGV_HIGH(arg1), c);
- } else {
- tcg_gen_shri_i32(t1, TCGV_HIGH(arg1), c);
- }
- tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
- tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t0);
- tcg_gen_mov_i32(TCGV_HIGH(ret), t1);
+ } else if (right) {
+ tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
+ tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(ret),
+ TCGV_HIGH(arg1), 32 - c, c);
+ if (arith) {
+ tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
} else {
- tcg_gen_shri_i32(t0, TCGV_LOW(arg1), 32 - c);
- /* Note: ret can be the same as arg1, so we use t1 */
- tcg_gen_shli_i32(t1, TCGV_LOW(arg1), c);
- tcg_gen_shli_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
- tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t0);
- tcg_gen_mov_i32(TCGV_LOW(ret), t1);
+ tcg_gen_shri_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
}
+ } else {
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ tcg_gen_shri_i32(t0, TCGV_LOW(arg1), 32 - c);
+ tcg_gen_deposit_i32(TCGV_HIGH(ret), t0,
+ TCGV_HIGH(arg1), c, 32 - c);
tcg_temp_free_i32(t0);
- tcg_temp_free_i32(t1);
+ tcg_gen_shli_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
}
}
---
2/ use extract2:
-- >8 --
@@ -1356,20 +1356,30 @@ static inline void tcg_gen_shifti_i64(TCGv_i64
ret, TCGv_i64 arg1,
tcg_gen_movi_i32(TCGV_LOW(ret), 0);
}
} else if (right) {
- tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
- tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(ret),
- TCGV_HIGH(arg1), 32 - c, c);
+ if (TCG_TARGET_HAS_extract2_i32) {
+ tcg_gen_extract2_i32(TCGV_LOW(ret),
+ TCGV_LOW(arg1), TCGV_HIGH(arg1), c);
+ } else {
+ tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
+ tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(ret),
+ TCGV_HIGH(arg1), 32 - c, c);
+ }
if (arith) {
tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
} else {
tcg_gen_shri_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
}
} else {
- TCGv_i32 t0 = tcg_temp_new_i32();
- tcg_gen_shri_i32(t0, TCGV_LOW(arg1), 32 - c);
- tcg_gen_deposit_i32(TCGV_HIGH(ret), t0,
- TCGV_HIGH(arg1), c, 32 - c);
- tcg_temp_free_i32(t0);
+ if (TCG_TARGET_HAS_extract2_i32) {
+ tcg_gen_extract2_i32(TCGV_HIGH(ret),
+ TCGV_LOW(arg1), TCGV_HIGH(arg1), 32 - c);
+ } else {
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ tcg_gen_shri_i32(t0, TCGV_LOW(arg1), 32 - c);
+ tcg_gen_deposit_i32(TCGV_HIGH(ret), t0,
+ TCGV_HIGH(arg1), c, 32 - c);
+ tcg_temp_free_i32(t0);
+ }
tcg_gen_shli_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
}
}
---
Note that I indented the extract2 slighly differently,
TCGV_LOW(arg1) and TCGV_HIGH(arg1) are now together on the same line.
My brain find it more digestible :)
Regards,
Phil.
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 3/9] tcg: Use extract2 in tcg_gen_shifti_i64
2019-03-07 14:41 ` [Qemu-devel] [PATCH 3/9] tcg: Use extract2 in tcg_gen_shifti_i64 Richard Henderson
2019-03-09 1:00 ` Philippe Mathieu-Daudé
@ 2019-03-09 20:30 ` Aleksandar Markovic
2019-03-10 6:43 ` Richard Henderson
1 sibling, 1 reply; 33+ messages in thread
From: Aleksandar Markovic @ 2019-03-09 20:30 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, david
On Thursday, March 7, 2019, Richard Henderson <richard.henderson@linaro.org>
wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/tcg-op.c | 47 ++++++++++++++++++++++++-----------------------
> 1 file changed, 24 insertions(+), 23 deletions(-)
>
>
Extract2 is not a good name for this new function, IMHO.
> diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
> index deacc63e3b..34e0dbc6e0 100644
> --- a/tcg/tcg-op.c
> +++ b/tcg/tcg-op.c
> @@ -1355,31 +1355,32 @@ static inline void tcg_gen_shifti_i64(TCGv_i64
> ret, TCGv_i64 arg1,
> tcg_gen_shli_i32(TCGV_HIGH(ret), TCGV_LOW(arg1), c);
> tcg_gen_movi_i32(TCGV_LOW(ret), 0);
> }
> - } else {
> - TCGv_i32 t0, t1;
> -
> - t0 = tcg_temp_new_i32();
> - t1 = tcg_temp_new_i32();
> - if (right) {
> - tcg_gen_shli_i32(t0, TCGV_HIGH(arg1), 32 - c);
> - if (arith) {
> - tcg_gen_sari_i32(t1, TCGV_HIGH(arg1), c);
> - } else {
> - tcg_gen_shri_i32(t1, TCGV_HIGH(arg1), c);
> - }
> - tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
> - tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t0);
> - tcg_gen_mov_i32(TCGV_HIGH(ret), t1);
> + } else if (right) {
> + if (TCG_TARGET_HAS_extract2_i32) {
> + tcg_gen_extract2_i32(TCGV_LOW(ret), TCGV_LOW(arg1),
> + TCGV_HIGH(arg1), c);
> } else {
> - tcg_gen_shri_i32(t0, TCGV_LOW(arg1), 32 - c);
> - /* Note: ret can be the same as arg1, so we use t1 */
> - tcg_gen_shli_i32(t1, TCGV_LOW(arg1), c);
> - tcg_gen_shli_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
> - tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t0);
> - tcg_gen_mov_i32(TCGV_LOW(ret), t1);
> + tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
> + tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(ret),
> + TCGV_HIGH(arg1), 32 - c, c);
> }
> - tcg_temp_free_i32(t0);
> - tcg_temp_free_i32(t1);
> + if (arith) {
> + tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
> + } else {
> + tcg_gen_shri_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
> + }
> + } else {
> + if (TCG_TARGET_HAS_extract2_i32) {
> + tcg_gen_extract2_i32(TCGV_HIGH(ret), TCGV_LOW(arg1),
> + TCGV_HIGH(arg1), 32 - c);
> + } else {
> + TCGv_i32 t0 = tcg_temp_new_i32();
> + tcg_gen_shri_i32(t0, TCGV_LOW(arg1), 32 - c);
> + tcg_gen_deposit_i32(TCGV_HIGH(ret), t0,
> + TCGV_HIGH(arg1), c, 32 - c);
> + tcg_temp_free_i32(t0);
> + }
> + tcg_gen_shli_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
> }
> }
>
> --
> 2.17.2
>
>
>
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 3/9] tcg: Use extract2 in tcg_gen_shifti_i64
2019-03-09 20:30 ` Aleksandar Markovic
@ 2019-03-10 6:43 ` Richard Henderson
0 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2019-03-10 6:43 UTC (permalink / raw)
To: Aleksandar Markovic; +Cc: qemu-devel, david
On 3/9/19 12:30 PM, Aleksandar Markovic wrote:
>
>
> On Thursday, March 7, 2019, Richard Henderson <richard.henderson@linaro.org
> <mailto:richard.henderson@linaro.org>> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org
> <mailto:richard.henderson@linaro.org>>
> ---
> tcg/tcg-op.c | 47 ++++++++++++++++++++++++-----------------------
> 1 file changed, 24 insertions(+), 23 deletions(-)
>
>
> Extract2 is not a good name for this new function, IMHO.
If you're going to bike shed the name, you should suggest something else.
But I think it's a pretty good name, since it extracts one register output out
of two register inputs.
r~
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Qemu-devel] [PATCH 4/9] tcg: Use extract2 in tcg_gen_deposit_{i32, i64}
2019-03-07 14:41 [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64} Richard Henderson
` (2 preceding siblings ...)
2019-03-07 14:41 ` [Qemu-devel] [PATCH 3/9] tcg: Use extract2 in tcg_gen_shifti_i64 Richard Henderson
@ 2019-03-07 14:41 ` Richard Henderson
2019-03-09 0:36 ` Philippe Mathieu-Daudé
2019-03-07 14:41 ` [Qemu-devel] [PATCH 5/9] tcg/i386: Support INDEX_op_extract2_{i32, i64} Richard Henderson
` (11 subsequent siblings)
15 siblings, 1 reply; 33+ messages in thread
From: Richard Henderson @ 2019-03-07 14:41 UTC (permalink / raw)
To: qemu-devel; +Cc: david
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg-op.c | 28 ++++++++++++++++++++++++++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 34e0dbc6e0..caee80235e 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -614,6 +614,18 @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
mask = (1u << len) - 1;
t1 = tcg_temp_new_i32();
+ if (TCG_TARGET_HAS_extract2_i32) {
+ if (ofs + len == 32) {
+ tcg_gen_shli_i32(t1, arg1, len);
+ tcg_gen_extract2_i32(ret, t1, arg2, len);
+ goto done;
+ }
+ if (ofs == 0) {
+ tcg_gen_extract2_i32(ret, arg1, arg2, len);
+ tcg_gen_rotli_i32(ret, ret, len);
+ goto done;
+ }
+ }
if (ofs + len < 32) {
tcg_gen_andi_i32(t1, arg2, mask);
tcg_gen_shli_i32(t1, t1, ofs);
@@ -622,7 +634,7 @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
}
tcg_gen_andi_i32(ret, arg1, ~(mask << ofs));
tcg_gen_or_i32(ret, ret, t1);
-
+ done:
tcg_temp_free_i32(t1);
}
@@ -2027,6 +2039,18 @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
mask = (1ull << len) - 1;
t1 = tcg_temp_new_i64();
+ if (TCG_TARGET_HAS_extract2_i64) {
+ if (ofs + len == 64) {
+ tcg_gen_shli_i64(t1, arg1, len);
+ tcg_gen_extract2_i64(ret, t1, arg2, len);
+ goto done;
+ }
+ if (ofs == 0) {
+ tcg_gen_extract2_i64(ret, arg1, arg2, len);
+ tcg_gen_rotli_i64(ret, ret, len);
+ goto done;
+ }
+ }
if (ofs + len < 64) {
tcg_gen_andi_i64(t1, arg2, mask);
tcg_gen_shli_i64(t1, t1, ofs);
@@ -2035,7 +2059,7 @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
}
tcg_gen_andi_i64(ret, arg1, ~(mask << ofs));
tcg_gen_or_i64(ret, ret, t1);
-
+ done:
tcg_temp_free_i64(t1);
}
--
2.17.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 4/9] tcg: Use extract2 in tcg_gen_deposit_{i32, i64}
2019-03-07 14:41 ` [Qemu-devel] [PATCH 4/9] tcg: Use extract2 in tcg_gen_deposit_{i32, i64} Richard Henderson
@ 2019-03-09 0:36 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-03-09 0:36 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: david
On 3/7/19 3:41 PM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/tcg-op.c | 28 ++++++++++++++++++++++++++--
> 1 file changed, 26 insertions(+), 2 deletions(-)
>
> diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
> index 34e0dbc6e0..caee80235e 100644
> --- a/tcg/tcg-op.c
> +++ b/tcg/tcg-op.c
> @@ -614,6 +614,18 @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
> mask = (1u << len) - 1;
FWIW you can move 'mask' ...
> t1 = tcg_temp_new_i32();
>
> + if (TCG_TARGET_HAS_extract2_i32) {
> + if (ofs + len == 32) {
> + tcg_gen_shli_i32(t1, arg1, len);
> + tcg_gen_extract2_i32(ret, t1, arg2, len);
> + goto done;
> + }
> + if (ofs == 0) {
> + tcg_gen_extract2_i32(ret, arg1, arg2, len);
> + tcg_gen_rotli_i32(ret, ret, len);
> + goto done;
> + }
> + }
... here, saving few instr if TCG_TARGET_HAS_extract2_i32 ;)
> if (ofs + len < 32) {
> tcg_gen_andi_i32(t1, arg2, mask);
> tcg_gen_shli_i32(t1, t1, ofs);
> @@ -622,7 +634,7 @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
> }
> tcg_gen_andi_i32(ret, arg1, ~(mask << ofs));
> tcg_gen_or_i32(ret, ret, t1);
> -
> + done:
> tcg_temp_free_i32(t1);
> }
>
> @@ -2027,6 +2039,18 @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
> mask = (1ull << len) - 1;
> t1 = tcg_temp_new_i64();
>
> + if (TCG_TARGET_HAS_extract2_i64) {
> + if (ofs + len == 64) {
> + tcg_gen_shli_i64(t1, arg1, len);
> + tcg_gen_extract2_i64(ret, t1, arg2, len);
> + goto done;
> + }
> + if (ofs == 0) {
> + tcg_gen_extract2_i64(ret, arg1, arg2, len);
> + tcg_gen_rotli_i64(ret, ret, len);
> + goto done;
> + }
> + }
Ditto.
> if (ofs + len < 64) {
> tcg_gen_andi_i64(t1, arg2, mask);
> tcg_gen_shli_i64(t1, t1, ofs);
> @@ -2035,7 +2059,7 @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
> }
> tcg_gen_andi_i64(ret, arg1, ~(mask << ofs));
> tcg_gen_or_i64(ret, ret, t1);
> -
> + done:
> tcg_temp_free_i64(t1);
> }
>
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Qemu-devel] [PATCH 5/9] tcg/i386: Support INDEX_op_extract2_{i32, i64}
2019-03-07 14:41 [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64} Richard Henderson
` (3 preceding siblings ...)
2019-03-07 14:41 ` [Qemu-devel] [PATCH 4/9] tcg: Use extract2 in tcg_gen_deposit_{i32, i64} Richard Henderson
@ 2019-03-07 14:41 ` Richard Henderson
2019-03-07 14:41 ` [Qemu-devel] [PATCH 6/9] tcg/arm: Support INDEX_op_extract2_i32 Richard Henderson
` (10 subsequent siblings)
15 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2019-03-07 14:41 UTC (permalink / raw)
To: qemu-devel; +Cc: david
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.h | 4 ++--
tcg/i386/tcg-target.inc.c | 11 +++++++++++
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 2c58eaa9ed..241bf19413 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -124,7 +124,7 @@ extern bool have_avx2;
#define TCG_TARGET_HAS_deposit_i32 1
#define TCG_TARGET_HAS_extract_i32 1
#define TCG_TARGET_HAS_sextract_i32 1
-#define TCG_TARGET_HAS_extract2_i32 0
+#define TCG_TARGET_HAS_extract2_i32 1
#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_add2_i32 1
#define TCG_TARGET_HAS_sub2_i32 1
@@ -163,7 +163,7 @@ extern bool have_avx2;
#define TCG_TARGET_HAS_deposit_i64 1
#define TCG_TARGET_HAS_extract_i64 1
#define TCG_TARGET_HAS_sextract_i64 0
-#define TCG_TARGET_HAS_extract2_i64 0
+#define TCG_TARGET_HAS_extract2_i64 1
#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index e0670e5098..1fa833840e 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -452,6 +452,7 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
#define OPC_SHUFPS (0xc6 | P_EXT)
#define OPC_SHLX (0xf7 | P_EXT38 | P_DATA16)
#define OPC_SHRX (0xf7 | P_EXT38 | P_SIMDF2)
+#define OPC_SHRD_Ib (0xac | P_EXT)
#define OPC_TESTL (0x85)
#define OPC_TZCNT (0xbc | P_EXT | P_SIMDF3)
#define OPC_UD2 (0x0b | P_EXT)
@@ -2587,6 +2588,12 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
break;
+ OP_32_64(extract2):
+ /* Note that SHRD outputs to the r/m operand. */
+ tcg_out_modrm(s, OPC_SHRD_Ib + rexw, a2, a0);
+ tcg_out8(s, args[3]);
+ break;
+
case INDEX_op_mb:
tcg_out_mb(s, a0);
break;
@@ -2845,6 +2852,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
static const TCGTargetOpDef r_0 = { .args_ct_str = { "r", "0" } };
static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
static const TCGTargetOpDef r_r_re = { .args_ct_str = { "r", "r", "re" } };
+ static const TCGTargetOpDef r_0_r = { .args_ct_str = { "r", "0", "r" } };
static const TCGTargetOpDef r_0_re = { .args_ct_str = { "r", "0", "re" } };
static const TCGTargetOpDef r_0_ci = { .args_ct_str = { "r", "0", "ci" } };
static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
@@ -2970,6 +2978,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_ctpop_i32:
case INDEX_op_ctpop_i64:
return &r_r;
+ case INDEX_op_extract2_i32:
+ case INDEX_op_extract2_i64:
+ return &r_0_r;
case INDEX_op_deposit_i32:
case INDEX_op_deposit_i64:
--
2.17.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PATCH 6/9] tcg/arm: Support INDEX_op_extract2_i32
2019-03-07 14:41 [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64} Richard Henderson
` (4 preceding siblings ...)
2019-03-07 14:41 ` [Qemu-devel] [PATCH 5/9] tcg/i386: Support INDEX_op_extract2_{i32, i64} Richard Henderson
@ 2019-03-07 14:41 ` Richard Henderson
2019-03-09 0:11 ` Philippe Mathieu-Daudé
2019-03-07 14:41 ` [Qemu-devel] [PATCH 7/9] tcg/aarch64: Support INDEX_op_extract2_{i32, i64} Richard Henderson
` (9 subsequent siblings)
15 siblings, 1 reply; 33+ messages in thread
From: Richard Henderson @ 2019-03-07 14:41 UTC (permalink / raw)
To: qemu-devel; +Cc: david
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target.h | 2 +-
tcg/arm/tcg-target.inc.c | 25 +++++++++++++++++++++++++
2 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 4ee6c98958..17e771374d 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -116,7 +116,7 @@ extern bool use_idiv_instructions;
#define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions
#define TCG_TARGET_HAS_extract_i32 use_armv7_instructions
#define TCG_TARGET_HAS_sextract_i32 use_armv7_instructions
-#define TCG_TARGET_HAS_extract2_i32 0
+#define TCG_TARGET_HAS_extract2_i32 1
#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_mulu2_i32 1
#define TCG_TARGET_HAS_muls2_i32 1
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index 2245a8aeb9..6873b0cf95 100644
--- a/tcg/arm/tcg-target.inc.c
+++ b/tcg/arm/tcg-target.inc.c
@@ -2064,6 +2064,27 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_sextract_i32:
tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]);
break;
+ case INDEX_op_extract2_i32:
+ /* ??? These optimization vs zero should be generic. */
+ /* ??? But we can't substitute 2 for 1 in the opcode stream yet. */
+ if (const_args[1]) {
+ if (const_args[2]) {
+ tcg_out_movi(s, TCG_TYPE_REG, args[0], 0);
+ } else {
+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0,
+ args[2], SHIFT_IMM_LSL(32 - args[3]));
+ }
+ } else if (const_args[2]) {
+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0,
+ args[1], SHIFT_IMM_LSR(args[3]));
+ } else {
+ /* We can do extract2 in 2 insns, vs the 3 required otherwise. */
+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0,
+ args[2], SHIFT_IMM_LSL(32 - args[3]));
+ tcg_out_dat_reg(s, COND_AL, ARITH_ORR, args[0], TCG_REG_TMP,
+ args[1], SHIFT_IMM_LSR(args[3]));
+ }
+ break;
case INDEX_op_div_i32:
tcg_out_sdiv(s, COND_AL, args[0], args[1], args[2]);
@@ -2108,6 +2129,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
= { .args_ct_str = { "s", "s", "s", "s" } };
static const TCGTargetOpDef br
= { .args_ct_str = { "r", "rIN" } };
+ static const TCGTargetOpDef ext2
+ = { .args_ct_str = { "r", "rZ", "rZ" } };
static const TCGTargetOpDef dep
= { .args_ct_str = { "r", "0", "rZ" } };
static const TCGTargetOpDef movc
@@ -2174,6 +2197,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
return &br;
case INDEX_op_deposit_i32:
return &dep;
+ case INDEX_op_extract2_i32:
+ return &ext2;
case INDEX_op_movcond_i32:
return &movc;
case INDEX_op_add2_i32:
--
2.17.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 6/9] tcg/arm: Support INDEX_op_extract2_i32
2019-03-07 14:41 ` [Qemu-devel] [PATCH 6/9] tcg/arm: Support INDEX_op_extract2_i32 Richard Henderson
@ 2019-03-09 0:11 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-03-09 0:11 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: david
On 3/7/19 3:41 PM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/arm/tcg-target.h | 2 +-
> tcg/arm/tcg-target.inc.c | 25 +++++++++++++++++++++++++
> 2 files changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
> index 4ee6c98958..17e771374d 100644
> --- a/tcg/arm/tcg-target.h
> +++ b/tcg/arm/tcg-target.h
> @@ -116,7 +116,7 @@ extern bool use_idiv_instructions;
> #define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions
> #define TCG_TARGET_HAS_extract_i32 use_armv7_instructions
> #define TCG_TARGET_HAS_sextract_i32 use_armv7_instructions
> -#define TCG_TARGET_HAS_extract2_i32 0
> +#define TCG_TARGET_HAS_extract2_i32 1
> #define TCG_TARGET_HAS_movcond_i32 1
> #define TCG_TARGET_HAS_mulu2_i32 1
> #define TCG_TARGET_HAS_muls2_i32 1
> diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
> index 2245a8aeb9..6873b0cf95 100644
> --- a/tcg/arm/tcg-target.inc.c
> +++ b/tcg/arm/tcg-target.inc.c
> @@ -2064,6 +2064,27 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
> case INDEX_op_sextract_i32:
> tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]);
> break;
> + case INDEX_op_extract2_i32:
> + /* ??? These optimization vs zero should be generic. */
> + /* ??? But we can't substitute 2 for 1 in the opcode stream yet. */
> + if (const_args[1]) {
> + if (const_args[2]) {
> + tcg_out_movi(s, TCG_TYPE_REG, args[0], 0);
> + } else {
> + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0,
> + args[2], SHIFT_IMM_LSL(32 - args[3]));
> + }
> + } else if (const_args[2]) {
> + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0,
> + args[1], SHIFT_IMM_LSR(args[3]));
> + } else {
> + /* We can do extract2 in 2 insns, vs the 3 required otherwise. */
> + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0,
> + args[2], SHIFT_IMM_LSL(32 - args[3]));
> + tcg_out_dat_reg(s, COND_AL, ARITH_ORR, args[0], TCG_REG_TMP,
> + args[1], SHIFT_IMM_LSR(args[3]));
> + }
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> + break;
>
> case INDEX_op_div_i32:
> tcg_out_sdiv(s, COND_AL, args[0], args[1], args[2]);
> @@ -2108,6 +2129,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
> = { .args_ct_str = { "s", "s", "s", "s" } };
> static const TCGTargetOpDef br
> = { .args_ct_str = { "r", "rIN" } };
> + static const TCGTargetOpDef ext2
> + = { .args_ct_str = { "r", "rZ", "rZ" } };
> static const TCGTargetOpDef dep
> = { .args_ct_str = { "r", "0", "rZ" } };
> static const TCGTargetOpDef movc
> @@ -2174,6 +2197,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
> return &br;
> case INDEX_op_deposit_i32:
> return &dep;
> + case INDEX_op_extract2_i32:
> + return &ext2;
> case INDEX_op_movcond_i32:
> return &movc;
> case INDEX_op_add2_i32:
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Qemu-devel] [PATCH 7/9] tcg/aarch64: Support INDEX_op_extract2_{i32, i64}
2019-03-07 14:41 [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64} Richard Henderson
` (5 preceding siblings ...)
2019-03-07 14:41 ` [Qemu-devel] [PATCH 6/9] tcg/arm: Support INDEX_op_extract2_i32 Richard Henderson
@ 2019-03-07 14:41 ` Richard Henderson
2019-03-08 23:41 ` Philippe Mathieu-Daudé
2019-03-07 14:41 ` [Qemu-devel] [PATCH 8/9] target/arm: Use extract2 for EXTR Richard Henderson
` (8 subsequent siblings)
15 siblings, 1 reply; 33+ messages in thread
From: Richard Henderson @ 2019-03-07 14:41 UTC (permalink / raw)
To: qemu-devel; +Cc: david
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target.h | 4 ++--
tcg/aarch64/tcg-target.inc.c | 11 +++++++++++
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 6600a54a02..ce2bb1f90b 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -77,7 +77,7 @@ typedef enum {
#define TCG_TARGET_HAS_deposit_i32 1
#define TCG_TARGET_HAS_extract_i32 1
#define TCG_TARGET_HAS_sextract_i32 1
-#define TCG_TARGET_HAS_extract2_i32 0
+#define TCG_TARGET_HAS_extract2_i32 1
#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_add2_i32 1
#define TCG_TARGET_HAS_sub2_i32 1
@@ -114,7 +114,7 @@ typedef enum {
#define TCG_TARGET_HAS_deposit_i64 1
#define TCG_TARGET_HAS_extract_i64 1
#define TCG_TARGET_HAS_sextract_i64 1
-#define TCG_TARGET_HAS_extract2_i64 0
+#define TCG_TARGET_HAS_extract2_i64 1
#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index d57f9e500f..8b93598bce 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -2058,6 +2058,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_sbfm(s, ext, a0, a1, a2, a2 + args[3] - 1);
break;
+ case INDEX_op_extract2_i64:
+ case INDEX_op_extract2_i32:
+ tcg_out_extr(s, ext, a0, a1, a2, args[3]);
+ break;
+
case INDEX_op_add2_i32:
tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, REG0(2), REG0(3),
(int32_t)args[4], args[5], const_args[4],
@@ -2300,6 +2305,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
= { .args_ct_str = { "r", "r", "rAL" } };
static const TCGTargetOpDef dep
= { .args_ct_str = { "r", "0", "rZ" } };
+ static const TCGTargetOpDef ext2
+ = { .args_ct_str = { "r", "rZ", "rZ" } };
static const TCGTargetOpDef movc
= { .args_ct_str = { "r", "r", "rA", "rZ", "rZ" } };
static const TCGTargetOpDef add2
@@ -2430,6 +2437,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_deposit_i64:
return &dep;
+ case INDEX_op_extract2_i32:
+ case INDEX_op_extract2_i64:
+ return &ext2;
+
case INDEX_op_add2_i32:
case INDEX_op_add2_i64:
case INDEX_op_sub2_i32:
--
2.17.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 7/9] tcg/aarch64: Support INDEX_op_extract2_{i32, i64}
2019-03-07 14:41 ` [Qemu-devel] [PATCH 7/9] tcg/aarch64: Support INDEX_op_extract2_{i32, i64} Richard Henderson
@ 2019-03-08 23:41 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-03-08 23:41 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: david
On 3/7/19 3:41 PM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/aarch64/tcg-target.h | 4 ++--
> tcg/aarch64/tcg-target.inc.c | 11 +++++++++++
> 2 files changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
> index 6600a54a02..ce2bb1f90b 100644
> --- a/tcg/aarch64/tcg-target.h
> +++ b/tcg/aarch64/tcg-target.h
> @@ -77,7 +77,7 @@ typedef enum {
> #define TCG_TARGET_HAS_deposit_i32 1
> #define TCG_TARGET_HAS_extract_i32 1
> #define TCG_TARGET_HAS_sextract_i32 1
> -#define TCG_TARGET_HAS_extract2_i32 0
> +#define TCG_TARGET_HAS_extract2_i32 1
> #define TCG_TARGET_HAS_movcond_i32 1
> #define TCG_TARGET_HAS_add2_i32 1
> #define TCG_TARGET_HAS_sub2_i32 1
> @@ -114,7 +114,7 @@ typedef enum {
> #define TCG_TARGET_HAS_deposit_i64 1
> #define TCG_TARGET_HAS_extract_i64 1
> #define TCG_TARGET_HAS_sextract_i64 1
> -#define TCG_TARGET_HAS_extract2_i64 0
> +#define TCG_TARGET_HAS_extract2_i64 1
> #define TCG_TARGET_HAS_movcond_i64 1
> #define TCG_TARGET_HAS_add2_i64 1
> #define TCG_TARGET_HAS_sub2_i64 1
> diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
> index d57f9e500f..8b93598bce 100644
> --- a/tcg/aarch64/tcg-target.inc.c
> +++ b/tcg/aarch64/tcg-target.inc.c
> @@ -2058,6 +2058,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
> tcg_out_sbfm(s, ext, a0, a1, a2, a2 + args[3] - 1);
> break;
>
> + case INDEX_op_extract2_i64:
> + case INDEX_op_extract2_i32:
> + tcg_out_extr(s, ext, a0, a1, a2, args[3]);
EXTR a0, a1, a2, #args[3] ; OK
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> + break;
> +
> case INDEX_op_add2_i32:
> tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, REG0(2), REG0(3),
> (int32_t)args[4], args[5], const_args[4],
> @@ -2300,6 +2305,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
> = { .args_ct_str = { "r", "r", "rAL" } };
> static const TCGTargetOpDef dep
> = { .args_ct_str = { "r", "0", "rZ" } };
> + static const TCGTargetOpDef ext2
> + = { .args_ct_str = { "r", "rZ", "rZ" } };
> static const TCGTargetOpDef movc
> = { .args_ct_str = { "r", "r", "rA", "rZ", "rZ" } };
> static const TCGTargetOpDef add2
> @@ -2430,6 +2437,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
> case INDEX_op_deposit_i64:
> return &dep;
>
> + case INDEX_op_extract2_i32:
> + case INDEX_op_extract2_i64:
> + return &ext2;
> +
> case INDEX_op_add2_i32:
> case INDEX_op_add2_i64:
> case INDEX_op_sub2_i32:
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* [Qemu-devel] [PATCH 8/9] target/arm: Use extract2 for EXTR
2019-03-07 14:41 [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64} Richard Henderson
` (6 preceding siblings ...)
2019-03-07 14:41 ` [Qemu-devel] [PATCH 7/9] tcg/aarch64: Support INDEX_op_extract2_{i32, i64} Richard Henderson
@ 2019-03-07 14:41 ` Richard Henderson
2019-03-07 14:41 ` [Qemu-devel] [PATCH 9/9] target/arm: Simplify BFXIL expansion Richard Henderson
` (7 subsequent siblings)
15 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2019-03-07 14:41 UTC (permalink / raw)
To: qemu-devel; +Cc: david, qemu-arm, Peter Maydell
This is, after all, how we implement extract2 in tcg/aarc64.
Cc: qemu-arm@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 38 ++++++++++++++++++++------------------
1 file changed, 20 insertions(+), 18 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 1959046343..54fe94c436 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -4114,25 +4114,27 @@ static void disas_extract(DisasContext *s, uint32_t insn)
} else {
tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm));
}
- } else if (rm == rn) { /* ROR */
- tcg_rm = cpu_reg(s, rm);
- if (sf) {
- tcg_gen_rotri_i64(tcg_rd, tcg_rm, imm);
- } else {
- TCGv_i32 tmp = tcg_temp_new_i32();
- tcg_gen_extrl_i64_i32(tmp, tcg_rm);
- tcg_gen_rotri_i32(tmp, tmp, imm);
- tcg_gen_extu_i32_i64(tcg_rd, tmp);
- tcg_temp_free_i32(tmp);
- }
} else {
- tcg_rm = read_cpu_reg(s, rm, sf);
- tcg_rn = read_cpu_reg(s, rn, sf);
- tcg_gen_shri_i64(tcg_rm, tcg_rm, imm);
- tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm);
- tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn);
- if (!sf) {
- tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
+ tcg_rm = cpu_reg(s, rm);
+ tcg_rn = cpu_reg(s, rn);
+
+ if (sf) {
+ /* Specialization to ROR happens in EXTRACT2. */
+ tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, imm);
+ } else {
+ TCGv_i32 t0 = tcg_temp_new_i32();
+
+ tcg_gen_extrl_i64_i32(t0, tcg_rm);
+ if (rm == rn) {
+ tcg_gen_rotri_i32(t0, t0, imm);
+ } else {
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ tcg_gen_extrl_i64_i32(t1, tcg_rn);
+ tcg_gen_extract2_i32(t0, t0, t1, imm);
+ tcg_temp_free_i32(t1);
+ }
+ tcg_gen_extu_i32_i64(tcg_rd, t0);
+ tcg_temp_free_i32(t0);
}
}
}
--
2.17.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* [Qemu-devel] [PATCH 9/9] target/arm: Simplify BFXIL expansion
2019-03-07 14:41 [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64} Richard Henderson
` (7 preceding siblings ...)
2019-03-07 14:41 ` [Qemu-devel] [PATCH 8/9] target/arm: Use extract2 for EXTR Richard Henderson
@ 2019-03-07 14:41 ` Richard Henderson
2019-03-09 0:45 ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2019-03-07 15:23 ` [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64} no-reply
` (6 subsequent siblings)
15 siblings, 1 reply; 33+ messages in thread
From: Richard Henderson @ 2019-03-07 14:41 UTC (permalink / raw)
To: qemu-devel; +Cc: david, qemu-arm, Peter Maydell
The mask implied by the extract is redundant with the one
implied by the deposit. Also, fix spelling of BFXIL.
Cc: qemu-arm@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 54fe94c436..39e0512d21 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -4043,8 +4043,8 @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len);
return;
}
- /* opc == 1, BXFIL fall through to deposit */
- tcg_gen_extract_i64(tcg_tmp, tcg_tmp, ri, len);
+ /* opc == 1, BFXIL fall through to deposit */
+ tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri);
pos = 0;
} else {
/* Handle the ri > si case with a deposit
@@ -4062,7 +4062,7 @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
len = ri;
}
- if (opc == 1) { /* BFM, BXFIL */
+ if (opc == 1) { /* BFM, BFXIL */
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len);
} else {
/* SBFM or UBFM: We start with zero, and we haven't modified
--
2.17.2
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [Qemu-arm] [PATCH 9/9] target/arm: Simplify BFXIL expansion
2019-03-07 14:41 ` [Qemu-devel] [PATCH 9/9] target/arm: Simplify BFXIL expansion Richard Henderson
@ 2019-03-09 0:45 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 33+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-03-09 0:45 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Peter Maydell, qemu-arm, david
On 3/7/19 3:41 PM, Richard Henderson wrote:
> The mask implied by the extract is redundant with the one
> implied by the deposit. Also, fix spelling of BFXIL.
This spelling fix also help understanding the context!
>
> Cc: qemu-arm@nongnu.org
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate-a64.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index 54fe94c436..39e0512d21 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -4043,8 +4043,8 @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
> tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len);
> return;
> }
> - /* opc == 1, BXFIL fall through to deposit */
> - tcg_gen_extract_i64(tcg_tmp, tcg_tmp, ri, len);
> + /* opc == 1, BFXIL fall through to deposit */
> + tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri);
> pos = 0;
> } else {
> /* Handle the ri > si case with a deposit
> @@ -4062,7 +4062,7 @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
> len = ri;
> }
>
> - if (opc == 1) { /* BFM, BXFIL */
> + if (opc == 1) { /* BFM, BFXIL */
> tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len);
Fall through and use deposit of len indeed. So the previous SHRI is enough.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This function uses hardcore optimizations btw, un chef d'oeuvre :)
> } else {
> /* SBFM or UBFM: We start with zero, and we haven't modified
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64}
2019-03-07 14:41 [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64} Richard Henderson
` (8 preceding siblings ...)
2019-03-07 14:41 ` [Qemu-devel] [PATCH 9/9] target/arm: Simplify BFXIL expansion Richard Henderson
@ 2019-03-07 15:23 ` no-reply
2019-03-07 15:47 ` no-reply
` (5 subsequent siblings)
15 siblings, 0 replies; 33+ messages in thread
From: no-reply @ 2019-03-07 15:23 UTC (permalink / raw)
To: richard.henderson; +Cc: fam, qemu-devel, david
Patchew URL: https://patchew.org/QEMU/20190307144126.31847-1-richard.henderson@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190307144126.31847-1-richard.henderson@linaro.org
Subject: [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64}
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/20190307144126.31847-1-richard.henderson@linaro.org -> patchew/20190307144126.31847-1-richard.henderson@linaro.org
Switched to a new branch 'test'
a5ab4c242b target/arm: Simplify BFXIL expansion
d1fcb8aecd target/arm: Use extract2 for EXTR
197413642f tcg/aarch64: Support INDEX_op_extract2_{i32, i64}
65cc26fced tcg/arm: Support INDEX_op_extract2_i32
0f7ffc52ad tcg/i386: Support INDEX_op_extract2_{i32, i64}
f11f5ed5da tcg: Use extract2 in tcg_gen_deposit_{i32, i64}
b51641ae95 tcg: Use extract2 in tcg_gen_shifti_i64
9526239495 tcg: Add INDEX_op_extract2_{i32,i64}
4846d47020 tcg: Implement tcg_gen_extract2_{i32, i64}
=== OUTPUT BEGIN ===
1/9 Checking commit 4846d470202c (tcg: Implement tcg_gen_extract2_{i32, i64})
2/9 Checking commit 9526239495d9 (tcg: Add INDEX_op_extract2_{i32,i64})
ERROR: spaces required around that ':' (ctx:VxE)
#108: FILE: tcg/optimize.c:1205:
+ CASE_OP_32_64(extract2):
^
total: 1 errors, 0 warnings, 199 lines checked
Patch 2/9 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/9 Checking commit b51641ae9525 (tcg: Use extract2 in tcg_gen_shifti_i64)
4/9 Checking commit f11f5ed5da7f (tcg: Use extract2 in tcg_gen_deposit_{i32, i64})
5/9 Checking commit 0f7ffc52ad1b (tcg/i386: Support INDEX_op_extract2_{i32, i64})
ERROR: spaces required around that ':' (ctx:VxE)
#48: FILE: tcg/i386/tcg-target.inc.c:2591:
+ OP_32_64(extract2):
^
total: 1 errors, 0 warnings, 51 lines checked
Patch 5/9 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/9 Checking commit 65cc26fced44 (tcg/arm: Support INDEX_op_extract2_i32)
7/9 Checking commit 197413642f19 (tcg/aarch64: Support INDEX_op_extract2_{i32, i64})
8/9 Checking commit d1fcb8aecd2f (target/arm: Use extract2 for EXTR)
9/9 Checking commit a5ab4c242ba6 (target/arm: Simplify BFXIL expansion)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190307144126.31847-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64}
2019-03-07 14:41 [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64} Richard Henderson
` (9 preceding siblings ...)
2019-03-07 15:23 ` [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64} no-reply
@ 2019-03-07 15:47 ` no-reply
2019-03-08 23:23 ` no-reply
` (4 subsequent siblings)
15 siblings, 0 replies; 33+ messages in thread
From: no-reply @ 2019-03-07 15:47 UTC (permalink / raw)
To: richard.henderson; +Cc: fam, qemu-devel, david
Patchew URL: https://patchew.org/QEMU/20190307144126.31847-1-richard.henderson@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190307144126.31847-1-richard.henderson@linaro.org
Subject: [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64}
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190307144126.31847-1-richard.henderson@linaro.org -> patchew/20190307144126.31847-1-richard.henderson@linaro.org
Switched to a new branch 'test'
172cb1c264 target/arm: Simplify BFXIL expansion
56c87bc882 target/arm: Use extract2 for EXTR
ea8806e468 tcg/aarch64: Support INDEX_op_extract2_{i32, i64}
691d675f4b tcg/arm: Support INDEX_op_extract2_i32
5ec13c83f2 tcg/i386: Support INDEX_op_extract2_{i32, i64}
3c7a3f7506 tcg: Use extract2 in tcg_gen_deposit_{i32, i64}
d3c1df2016 tcg: Use extract2 in tcg_gen_shifti_i64
71cd157f8a tcg: Add INDEX_op_extract2_{i32,i64}
6274d657b3 tcg: Implement tcg_gen_extract2_{i32, i64}
=== OUTPUT BEGIN ===
1/9 Checking commit 6274d657b3ba (tcg: Implement tcg_gen_extract2_{i32, i64})
2/9 Checking commit 71cd157f8a4c (tcg: Add INDEX_op_extract2_{i32,i64})
ERROR: spaces required around that ':' (ctx:VxE)
#109: FILE: tcg/optimize.c:1205:
+ CASE_OP_32_64(extract2):
^
total: 1 errors, 0 warnings, 199 lines checked
Patch 2/9 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/9 Checking commit d3c1df201649 (tcg: Use extract2 in tcg_gen_shifti_i64)
4/9 Checking commit 3c7a3f75068b (tcg: Use extract2 in tcg_gen_deposit_{i32, i64})
5/9 Checking commit 5ec13c83f2f5 (tcg/i386: Support INDEX_op_extract2_{i32, i64})
ERROR: spaces required around that ':' (ctx:VxE)
#48: FILE: tcg/i386/tcg-target.inc.c:2591:
+ OP_32_64(extract2):
^
total: 1 errors, 0 warnings, 51 lines checked
Patch 5/9 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/9 Checking commit 691d675f4b74 (tcg/arm: Support INDEX_op_extract2_i32)
7/9 Checking commit ea8806e468a7 (tcg/aarch64: Support INDEX_op_extract2_{i32, i64})
8/9 Checking commit 56c87bc882dc (target/arm: Use extract2 for EXTR)
9/9 Checking commit 172cb1c264ae (target/arm: Simplify BFXIL expansion)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190307144126.31847-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64}
2019-03-07 14:41 [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64} Richard Henderson
` (10 preceding siblings ...)
2019-03-07 15:47 ` no-reply
@ 2019-03-08 23:23 ` no-reply
2019-03-08 23:45 ` no-reply
` (3 subsequent siblings)
15 siblings, 0 replies; 33+ messages in thread
From: no-reply @ 2019-03-08 23:23 UTC (permalink / raw)
To: richard.henderson; +Cc: fam, qemu-devel, david
Patchew URL: https://patchew.org/QEMU/20190307144126.31847-1-richard.henderson@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190307144126.31847-1-richard.henderson@linaro.org
Subject: [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64}
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190307144126.31847-1-richard.henderson@linaro.org -> patchew/20190307144126.31847-1-richard.henderson@linaro.org
Switched to a new branch 'test'
3292d7b43c target/arm: Simplify BFXIL expansion
ff6ac2e56f target/arm: Use extract2 for EXTR
cf32404712 tcg/aarch64: Support INDEX_op_extract2_{i32, i64}
7bb2bf5b2f tcg/arm: Support INDEX_op_extract2_i32
77cd89c565 tcg/i386: Support INDEX_op_extract2_{i32, i64}
c74535f601 tcg: Use extract2 in tcg_gen_deposit_{i32, i64}
bf3e4eb1b5 tcg: Use extract2 in tcg_gen_shifti_i64
7880a5be65 tcg: Add INDEX_op_extract2_{i32,i64}
6f428742fe tcg: Implement tcg_gen_extract2_{i32, i64}
=== OUTPUT BEGIN ===
1/9 Checking commit 6f428742fe41 (tcg: Implement tcg_gen_extract2_{i32, i64})
2/9 Checking commit 7880a5be6520 (tcg: Add INDEX_op_extract2_{i32,i64})
ERROR: spaces required around that ':' (ctx:VxE)
#109: FILE: tcg/optimize.c:1205:
+ CASE_OP_32_64(extract2):
^
total: 1 errors, 0 warnings, 199 lines checked
Patch 2/9 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/9 Checking commit bf3e4eb1b5b0 (tcg: Use extract2 in tcg_gen_shifti_i64)
4/9 Checking commit c74535f601dc (tcg: Use extract2 in tcg_gen_deposit_{i32, i64})
5/9 Checking commit 77cd89c565b5 (tcg/i386: Support INDEX_op_extract2_{i32, i64})
ERROR: spaces required around that ':' (ctx:VxE)
#48: FILE: tcg/i386/tcg-target.inc.c:2591:
+ OP_32_64(extract2):
^
total: 1 errors, 0 warnings, 51 lines checked
Patch 5/9 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/9 Checking commit 7bb2bf5b2fa4 (tcg/arm: Support INDEX_op_extract2_i32)
7/9 Checking commit cf324047128d (tcg/aarch64: Support INDEX_op_extract2_{i32, i64})
8/9 Checking commit ff6ac2e56f23 (target/arm: Use extract2 for EXTR)
9/9 Checking commit 3292d7b43c8b (target/arm: Simplify BFXIL expansion)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190307144126.31847-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64}
2019-03-07 14:41 [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64} Richard Henderson
` (11 preceding siblings ...)
2019-03-08 23:23 ` no-reply
@ 2019-03-08 23:45 ` no-reply
2019-03-09 0:16 ` no-reply
` (2 subsequent siblings)
15 siblings, 0 replies; 33+ messages in thread
From: no-reply @ 2019-03-08 23:45 UTC (permalink / raw)
To: richard.henderson; +Cc: fam, qemu-devel, david
Patchew URL: https://patchew.org/QEMU/20190307144126.31847-1-richard.henderson@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190307144126.31847-1-richard.henderson@linaro.org
Subject: [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64}
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190307144126.31847-1-richard.henderson@linaro.org -> patchew/20190307144126.31847-1-richard.henderson@linaro.org
Switched to a new branch 'test'
3898cccde9 target/arm: Simplify BFXIL expansion
2ada5d316c target/arm: Use extract2 for EXTR
49b4870227 tcg/aarch64: Support INDEX_op_extract2_{i32, i64}
92cd638e55 tcg/arm: Support INDEX_op_extract2_i32
9b93a7bdeb tcg/i386: Support INDEX_op_extract2_{i32, i64}
d5d7cc7750 tcg: Use extract2 in tcg_gen_deposit_{i32, i64}
67a6356446 tcg: Use extract2 in tcg_gen_shifti_i64
17714e10e2 tcg: Add INDEX_op_extract2_{i32,i64}
c7936c5b94 tcg: Implement tcg_gen_extract2_{i32, i64}
=== OUTPUT BEGIN ===
1/9 Checking commit c7936c5b9404 (tcg: Implement tcg_gen_extract2_{i32, i64})
2/9 Checking commit 17714e10e223 (tcg: Add INDEX_op_extract2_{i32,i64})
ERROR: spaces required around that ':' (ctx:VxE)
#109: FILE: tcg/optimize.c:1205:
+ CASE_OP_32_64(extract2):
^
total: 1 errors, 0 warnings, 199 lines checked
Patch 2/9 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/9 Checking commit 67a63564468a (tcg: Use extract2 in tcg_gen_shifti_i64)
4/9 Checking commit d5d7cc7750e3 (tcg: Use extract2 in tcg_gen_deposit_{i32, i64})
5/9 Checking commit 9b93a7bdebcd (tcg/i386: Support INDEX_op_extract2_{i32, i64})
ERROR: spaces required around that ':' (ctx:VxE)
#48: FILE: tcg/i386/tcg-target.inc.c:2591:
+ OP_32_64(extract2):
^
total: 1 errors, 0 warnings, 51 lines checked
Patch 5/9 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/9 Checking commit 92cd638e55c0 (tcg/arm: Support INDEX_op_extract2_i32)
7/9 Checking commit 49b4870227e8 (tcg/aarch64: Support INDEX_op_extract2_{i32, i64})
8/9 Checking commit 2ada5d316ccb (target/arm: Use extract2 for EXTR)
9/9 Checking commit 3898cccde939 (target/arm: Simplify BFXIL expansion)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190307144126.31847-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64}
2019-03-07 14:41 [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64} Richard Henderson
` (12 preceding siblings ...)
2019-03-08 23:45 ` no-reply
@ 2019-03-09 0:16 ` no-reply
2019-03-09 0:49 ` no-reply
2019-04-09 18:53 ` David Hildenbrand
15 siblings, 0 replies; 33+ messages in thread
From: no-reply @ 2019-03-09 0:16 UTC (permalink / raw)
To: richard.henderson; +Cc: fam, qemu-devel, david
Patchew URL: https://patchew.org/QEMU/20190307144126.31847-1-richard.henderson@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190307144126.31847-1-richard.henderson@linaro.org
Subject: [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64}
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190307144126.31847-1-richard.henderson@linaro.org -> patchew/20190307144126.31847-1-richard.henderson@linaro.org
Switched to a new branch 'test'
fd5c8534d8 target/arm: Simplify BFXIL expansion
ff97eff064 target/arm: Use extract2 for EXTR
14907a5cdf tcg/aarch64: Support INDEX_op_extract2_{i32, i64}
571ce62802 tcg/arm: Support INDEX_op_extract2_i32
47322e4359 tcg/i386: Support INDEX_op_extract2_{i32, i64}
71c243e0b1 tcg: Use extract2 in tcg_gen_deposit_{i32, i64}
7f01d6944a tcg: Use extract2 in tcg_gen_shifti_i64
6040cdd72c tcg: Add INDEX_op_extract2_{i32,i64}
fd5a59c277 tcg: Implement tcg_gen_extract2_{i32, i64}
=== OUTPUT BEGIN ===
1/9 Checking commit fd5a59c277d1 (tcg: Implement tcg_gen_extract2_{i32, i64})
2/9 Checking commit 6040cdd72c14 (tcg: Add INDEX_op_extract2_{i32,i64})
ERROR: spaces required around that ':' (ctx:VxE)
#109: FILE: tcg/optimize.c:1205:
+ CASE_OP_32_64(extract2):
^
total: 1 errors, 0 warnings, 199 lines checked
Patch 2/9 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/9 Checking commit 7f01d6944a7a (tcg: Use extract2 in tcg_gen_shifti_i64)
4/9 Checking commit 71c243e0b1d7 (tcg: Use extract2 in tcg_gen_deposit_{i32, i64})
5/9 Checking commit 47322e435956 (tcg/i386: Support INDEX_op_extract2_{i32, i64})
ERROR: spaces required around that ':' (ctx:VxE)
#48: FILE: tcg/i386/tcg-target.inc.c:2591:
+ OP_32_64(extract2):
^
total: 1 errors, 0 warnings, 51 lines checked
Patch 5/9 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/9 Checking commit 571ce62802b8 (tcg/arm: Support INDEX_op_extract2_i32)
7/9 Checking commit 14907a5cdf13 (tcg/aarch64: Support INDEX_op_extract2_{i32, i64})
8/9 Checking commit ff97eff06477 (target/arm: Use extract2 for EXTR)
9/9 Checking commit fd5c8534d847 (target/arm: Simplify BFXIL expansion)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190307144126.31847-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64}
2019-03-07 14:41 [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64} Richard Henderson
` (13 preceding siblings ...)
2019-03-09 0:16 ` no-reply
@ 2019-03-09 0:49 ` no-reply
2019-04-09 18:53 ` David Hildenbrand
15 siblings, 0 replies; 33+ messages in thread
From: no-reply @ 2019-03-09 0:49 UTC (permalink / raw)
To: richard.henderson; +Cc: fam, qemu-devel, david
Patchew URL: https://patchew.org/QEMU/20190307144126.31847-1-richard.henderson@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190307144126.31847-1-richard.henderson@linaro.org
Subject: [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64}
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190307144126.31847-1-richard.henderson@linaro.org -> patchew/20190307144126.31847-1-richard.henderson@linaro.org
Switched to a new branch 'test'
a7913aa23f target/arm: Simplify BFXIL expansion
39046cd16f target/arm: Use extract2 for EXTR
896fc67f40 tcg/aarch64: Support INDEX_op_extract2_{i32, i64}
a4d81fe0bf tcg/arm: Support INDEX_op_extract2_i32
e4d782a991 tcg/i386: Support INDEX_op_extract2_{i32, i64}
c614b0e300 tcg: Use extract2 in tcg_gen_deposit_{i32, i64}
c3d7ab05b4 tcg: Use extract2 in tcg_gen_shifti_i64
6ab392e136 tcg: Add INDEX_op_extract2_{i32,i64}
ed214d13db tcg: Implement tcg_gen_extract2_{i32, i64}
=== OUTPUT BEGIN ===
1/9 Checking commit ed214d13dbba (tcg: Implement tcg_gen_extract2_{i32, i64})
2/9 Checking commit 6ab392e1361b (tcg: Add INDEX_op_extract2_{i32,i64})
ERROR: spaces required around that ':' (ctx:VxE)
#109: FILE: tcg/optimize.c:1205:
+ CASE_OP_32_64(extract2):
^
total: 1 errors, 0 warnings, 199 lines checked
Patch 2/9 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/9 Checking commit c3d7ab05b49c (tcg: Use extract2 in tcg_gen_shifti_i64)
4/9 Checking commit c614b0e30007 (tcg: Use extract2 in tcg_gen_deposit_{i32, i64})
5/9 Checking commit e4d782a99180 (tcg/i386: Support INDEX_op_extract2_{i32, i64})
ERROR: spaces required around that ':' (ctx:VxE)
#48: FILE: tcg/i386/tcg-target.inc.c:2591:
+ OP_32_64(extract2):
^
total: 1 errors, 0 warnings, 51 lines checked
Patch 5/9 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/9 Checking commit a4d81fe0bf4b (tcg/arm: Support INDEX_op_extract2_i32)
7/9 Checking commit 896fc67f40fa (tcg/aarch64: Support INDEX_op_extract2_{i32, i64})
8/9 Checking commit 39046cd16fe9 (target/arm: Use extract2 for EXTR)
9/9 Checking commit a7913aa23f53 (target/arm: Simplify BFXIL expansion)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190307144126.31847-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64}
2019-03-07 14:41 [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64} Richard Henderson
` (14 preceding siblings ...)
2019-03-09 0:49 ` no-reply
@ 2019-04-09 18:53 ` David Hildenbrand
2019-04-09 19:02 ` Richard Henderson
15 siblings, 1 reply; 33+ messages in thread
From: David Hildenbrand @ 2019-04-09 18:53 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 07.03.19 15:41, Richard Henderson wrote:
> The primary motivator here is usage within s390x,
> but (as with any good primitive) the opcode has
> applications outside that.
I am planning to send the next big part of vector instruction support
(Vector Integer Instructions) soon, that would make use of these patches.
--
Thanks,
David / dhildenb
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64}
2019-04-09 18:53 ` David Hildenbrand
@ 2019-04-09 19:02 ` Richard Henderson
2019-04-09 19:05 ` David Hildenbrand
0 siblings, 1 reply; 33+ messages in thread
From: Richard Henderson @ 2019-04-09 19:02 UTC (permalink / raw)
To: David Hildenbrand, qemu-devel
On 4/9/19 8:53 AM, David Hildenbrand wrote:
> On 07.03.19 15:41, Richard Henderson wrote:
>> The primary motivator here is usage within s390x,
>> but (as with any good primitive) the opcode has
>> applications outside that.
>
> I am planning to send the next big part of vector instruction support
> (Vector Integer Instructions) soon, that would make use of these patches.
I'll be sure to get them into the first pull after 4.1 opens.
r~
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64}
2019-04-09 19:02 ` Richard Henderson
@ 2019-04-09 19:05 ` David Hildenbrand
0 siblings, 0 replies; 33+ messages in thread
From: David Hildenbrand @ 2019-04-09 19:05 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 09.04.19 21:02, Richard Henderson wrote:
> On 4/9/19 8:53 AM, David Hildenbrand wrote:
>> On 07.03.19 15:41, Richard Henderson wrote:
>>> The primary motivator here is usage within s390x,
>>> but (as with any good primitive) the opcode has
>>> applications outside that.
>>
>> I am planning to send the next big part of vector instruction support
>> (Vector Integer Instructions) soon, that would make use of these patches.
>
> I'll be sure to get them into the first pull after 4.1 opens.
>
Nice, I'll be posting the next series, referencing this series (might
take some days as the amount of instructions is getting out of hand).
Thanks!
--
Thanks,
David / dhildenb
^ permalink raw reply [flat|nested] 33+ messages in thread