* [PATCH net] net: dsa: mv88e6xxx: Set correct interface mode for CPU/DSA ports
@ 2019-03-08 0:21 Andrew Lunn
2019-03-09 7:02 ` David Miller
0 siblings, 1 reply; 7+ messages in thread
From: Andrew Lunn @ 2019-03-08 0:21 UTC (permalink / raw)
To: David Miller; +Cc: netdev, Vivien Didelot, Heiner Kallweit, Andrew Lunn
By default, the switch driver is expected to configure CPU and DSA
ports to their maximum speed. For the 6341 and 6390 families, the
ports interface mode has to be configured as well. The 6390X range
support 10G ports using XAUI, while the 6341 and 6390 supports
2500BaseX, as their maximum speed.
Fixes: 787799a9d555 ("net: dsa: mv88e6xxx: Default ports 9/10 6390X CMODE to 1000BaseX")
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
---
drivers/net/dsa/mv88e6xxx/chip.c | 11 +++++++++++
drivers/net/dsa/mv88e6xxx/chip.h | 3 +++
drivers/net/dsa/mv88e6xxx/port.c | 24 ++++++++++++++++++++++++
drivers/net/dsa/mv88e6xxx/port.h | 4 ++++
4 files changed, 42 insertions(+)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index 96728d1e9824..f4e2db44ad91 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -569,6 +569,9 @@ int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link,
goto restore_link;
}
+ if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode)
+ mode = chip->info->ops->port_max_speed_mode(port);
+
if (chip->info->ops->port_set_pause) {
err = chip->info->ops->port_set_pause(chip, port, pause);
if (err)
@@ -3067,6 +3070,7 @@ static const struct mv88e6xxx_ops mv88e6141_ops = {
.port_set_duplex = mv88e6xxx_port_set_duplex,
.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
.port_set_speed = mv88e6341_port_set_speed,
+ .port_max_speed_mode = mv88e6341_port_max_speed_mode,
.port_tag_remap = mv88e6095_port_tag_remap,
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
@@ -3385,6 +3389,7 @@ static const struct mv88e6xxx_ops mv88e6190_ops = {
.port_set_duplex = mv88e6xxx_port_set_duplex,
.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
.port_set_speed = mv88e6390_port_set_speed,
+ .port_max_speed_mode = mv88e6390_port_max_speed_mode,
.port_tag_remap = mv88e6390_port_tag_remap,
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
@@ -3429,6 +3434,7 @@ static const struct mv88e6xxx_ops mv88e6190x_ops = {
.port_set_duplex = mv88e6xxx_port_set_duplex,
.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
.port_set_speed = mv88e6390x_port_set_speed,
+ .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
.port_tag_remap = mv88e6390_port_tag_remap,
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
@@ -3473,6 +3479,7 @@ static const struct mv88e6xxx_ops mv88e6191_ops = {
.port_set_duplex = mv88e6xxx_port_set_duplex,
.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
.port_set_speed = mv88e6390_port_set_speed,
+ .port_max_speed_mode = mv88e6390_port_max_speed_mode,
.port_tag_remap = mv88e6390_port_tag_remap,
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
@@ -3566,6 +3573,7 @@ static const struct mv88e6xxx_ops mv88e6290_ops = {
.port_set_duplex = mv88e6xxx_port_set_duplex,
.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
.port_set_speed = mv88e6390_port_set_speed,
+ .port_max_speed_mode = mv88e6390_port_max_speed_mode,
.port_tag_remap = mv88e6390_port_tag_remap,
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
@@ -3697,6 +3705,7 @@ static const struct mv88e6xxx_ops mv88e6341_ops = {
.port_set_duplex = mv88e6xxx_port_set_duplex,
.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
.port_set_speed = mv88e6341_port_set_speed,
+ .port_max_speed_mode = mv88e6341_port_max_speed_mode,
.port_tag_remap = mv88e6095_port_tag_remap,
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
@@ -3872,6 +3881,7 @@ static const struct mv88e6xxx_ops mv88e6390_ops = {
.port_set_duplex = mv88e6xxx_port_set_duplex,
.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
.port_set_speed = mv88e6390_port_set_speed,
+ .port_max_speed_mode = mv88e6390_port_max_speed_mode,
.port_tag_remap = mv88e6390_port_tag_remap,
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
@@ -3920,6 +3930,7 @@ static const struct mv88e6xxx_ops mv88e6390x_ops = {
.port_set_duplex = mv88e6xxx_port_set_duplex,
.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
.port_set_speed = mv88e6390x_port_set_speed,
+ .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
.port_tag_remap = mv88e6390_port_tag_remap,
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/chip.h
index adcf60779895..19c07dff0440 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.h
+++ b/drivers/net/dsa/mv88e6xxx/chip.h
@@ -377,6 +377,9 @@ struct mv88e6xxx_ops {
*/
int (*port_set_speed)(struct mv88e6xxx_chip *chip, int port, int speed);
+ /* What interface mode should be used for maximum speed? */
+ phy_interface_t (*port_max_speed_mode)(int port);
+
int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c
index 0796c6feec55..dce84a2a65c7 100644
--- a/drivers/net/dsa/mv88e6xxx/port.c
+++ b/drivers/net/dsa/mv88e6xxx/port.c
@@ -312,6 +312,14 @@ int mv88e6341_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
return mv88e6xxx_port_set_speed(chip, port, speed, !port, true);
}
+phy_interface_t mv88e6341_port_max_speed_mode(int port)
+{
+ if (port == 5)
+ return PHY_INTERFACE_MODE_2500BASEX;
+
+ return PHY_INTERFACE_MODE_NA;
+}
+
/* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */
int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
{
@@ -345,6 +353,14 @@ int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
return mv88e6xxx_port_set_speed(chip, port, speed, true, true);
}
+phy_interface_t mv88e6390_port_max_speed_mode(int port)
+{
+ if (port == 9 || port == 10)
+ return PHY_INTERFACE_MODE_2500BASEX;
+
+ return PHY_INTERFACE_MODE_NA;
+}
+
/* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */
int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
{
@@ -360,6 +376,14 @@ int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
return mv88e6xxx_port_set_speed(chip, port, speed, true, true);
}
+phy_interface_t mv88e6390x_port_max_speed_mode(int port)
+{
+ if (port == 9 || port == 10)
+ return PHY_INTERFACE_MODE_XAUI;
+
+ return PHY_INTERFACE_MODE_NA;
+}
+
int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
phy_interface_t mode)
{
diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h
index 4aadf321edb7..c7bed263a0f4 100644
--- a/drivers/net/dsa/mv88e6xxx/port.h
+++ b/drivers/net/dsa/mv88e6xxx/port.h
@@ -285,6 +285,10 @@ int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
+phy_interface_t mv88e6341_port_max_speed_mode(int port);
+phy_interface_t mv88e6390_port_max_speed_mode(int port);
+phy_interface_t mv88e6390x_port_max_speed_mode(int port);
+
int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state);
int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map);
--
2.20.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH net] net: dsa: mv88e6xxx: Set correct interface mode for CPU/DSA ports
2019-03-08 0:21 [PATCH net] net: dsa: mv88e6xxx: Set correct interface mode for CPU/DSA ports Andrew Lunn
@ 2019-03-09 7:02 ` David Miller
0 siblings, 0 replies; 7+ messages in thread
From: David Miller @ 2019-03-09 7:02 UTC (permalink / raw)
To: andrew; +Cc: netdev, vivien.didelot, hkallweit1
From: Andrew Lunn <andrew@lunn.ch>
Date: Fri, 8 Mar 2019 01:21:27 +0100
> By default, the switch driver is expected to configure CPU and DSA
> ports to their maximum speed. For the 6341 and 6390 families, the
> ports interface mode has to be configured as well. The 6390X range
> support 10G ports using XAUI, while the 6341 and 6390 supports
> 2500BaseX, as their maximum speed.
>
> Fixes: 787799a9d555 ("net: dsa: mv88e6xxx: Default ports 9/10 6390X CMODE to 1000BaseX")
> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Applied and queued up for -stable, thanks Andrew.
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH net] net: dsa: mv88e6xxx: Set correct interface mode for CPU/DSA ports
2019-05-28 13:17 ` Andrew Lunn
@ 2019-05-29 1:12 ` Greg Ungerer
0 siblings, 0 replies; 7+ messages in thread
From: Greg Ungerer @ 2019-05-29 1:12 UTC (permalink / raw)
To: Andrew Lunn; +Cc: netdev
Hi Andrew,
On 28/5/19 11:17 pm, Andrew Lunn wrote:
>> My hardware has the CPU port on 9, and it is SGMII. The existing working
>> devicetree setup I used is:
>>
>> port@9 {
>> reg = <9>;
>> label = "cpu";
>> ethernet = <ð0>;
>> fixed-link {
>> speed = <1000>;
>> full-duplex;
>> };
>> };
>
> Hi Greg
>
> You might need to set the phy-mode to SGMII. I'm surprised you are
> using SGMII, not 1000Base-X. Do you have a PHY connected?
No, no PHY connected. Direct Armada 380 to 6390 switch with SGMII.
Adding
phy-mode = "sgmii";
to that port fixes it.
Thanks!
Greg
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH net] net: dsa: mv88e6xxx: Set correct interface mode for CPU/DSA ports
2019-05-27 1:26 ` Greg Ungerer
@ 2019-05-28 13:17 ` Andrew Lunn
2019-05-29 1:12 ` Greg Ungerer
0 siblings, 1 reply; 7+ messages in thread
From: Andrew Lunn @ 2019-05-28 13:17 UTC (permalink / raw)
To: Greg Ungerer; +Cc: netdev
> My hardware has the CPU port on 9, and it is SGMII. The existing working
> devicetree setup I used is:
>
> port@9 {
> reg = <9>;
> label = "cpu";
> ethernet = <ð0>;
> fixed-link {
> speed = <1000>;
> full-duplex;
> };
> };
Hi Greg
You might need to set the phy-mode to SGMII. I'm surprised you are
using SGMII, not 1000Base-X. Do you have a PHY connected?
Andrew
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH net] net: dsa: mv88e6xxx: Set correct interface mode for CPU/DSA ports
2019-05-24 13:44 ` Andrew Lunn
@ 2019-05-27 1:26 ` Greg Ungerer
2019-05-28 13:17 ` Andrew Lunn
0 siblings, 1 reply; 7+ messages in thread
From: Greg Ungerer @ 2019-05-27 1:26 UTC (permalink / raw)
To: Andrew Lunn; +Cc: netdev
Hi Andrew,
Thanks for the quick response.
On 24/5/19 11:44 pm, Andrew Lunn wrote:
> On Fri, May 24, 2019 at 11:25:03AM +1000, Greg Ungerer wrote:
>> Hi Andrew,
>>
>> I have a problem with a Marvell 6390 switch that I have bisected
>> back to commit 7cbbee050c95, "[PATCH] net: dsa: mv88e6xxx: Set correct
>> interface mode for CPU/DSA ports".
>>
>> I have a Marvell 380 SoC based platform with a Marvell 6390 10 port
>> switch, everything works with kernel 5.0 and older. As of 5.1 the
>> switch ports no longer work - no packets are ever received and
>> none get sent out.
>>
>> The ports are probed and all discovered ok, they just don't work.
>>
>> mv88e6085 f1072004.mdio-mii:10: switch 0x3900 detected: Marvell 88E6390, revision 1
>> libphy: mv88e6xxx SMI: probed
>> mv88e6085 f1072004.mdio-mii:10 lan1 (uninitialized): PHY [mv88e6xxx-1:01] driver [Marvell 88E6390]
>> mv88e6085 f1072004.mdio-mii:10 lan2 (uninitialized): PHY [mv88e6xxx-1:02] driver [Marvell 88E6390]
>> mv88e6085 f1072004.mdio-mii:10 lan3 (uninitialized): PHY [mv88e6xxx-1:03] driver [Marvell 88E6390]
>> mv88e6085 f1072004.mdio-mii:10 lan4 (uninitialized): PHY [mv88e6xxx-1:04] driver [Marvell 88E6390]
>> mv88e6085 f1072004.mdio-mii:10 lan5 (uninitialized): PHY [mv88e6xxx-1:05] driver [Marvell 88E6390]
>> mv88e6085 f1072004.mdio-mii:10 lan6 (uninitialized): PHY [mv88e6xxx-1:06] driver [Marvell 88E6390]
>> mv88e6085 f1072004.mdio-mii:10 lan7 (uninitialized): PHY [mv88e6xxx-1:07] driver [Marvell 88E6390]
>> mv88e6085 f1072004.mdio-mii:10 lan8 (uninitialized): PHY [mv88e6xxx-1:08] driver [Marvell 88E6390]
>> DSA: tree 0 setup
>>
>> Things like ethtool on the ports seem to work ok, reports link correctly.
>> Configuring ports as part of a bridge or individually gets the same result.
>
> Hi Greg
>
> DSA by default should configure the CPU port and DSA ports to there
> maximum speed. For port 10, that is 10Gbps. Your 380 cannot do that
> speed. So you need to tell the switch driver to slow down. Add a fixed
> link node to port ten, with speed 1000. You might also need to set the
> phy-mode to rgmii.
My hardware has the CPU port on 9, and it is SGMII. The existing working
devicetree setup I used is:
port@9 {
reg = <9>;
label = "cpu";
ethernet = <ð0>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
> Can the 380 do 2500BaseX? There is work in progress to support this
> speed, so maybe next cycle you can change to that.
That would be nice.
Regards
Greg
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH net] net: dsa: mv88e6xxx: Set correct interface mode for CPU/DSA ports
2019-05-24 1:25 Greg Ungerer
@ 2019-05-24 13:44 ` Andrew Lunn
2019-05-27 1:26 ` Greg Ungerer
0 siblings, 1 reply; 7+ messages in thread
From: Andrew Lunn @ 2019-05-24 13:44 UTC (permalink / raw)
To: Greg Ungerer; +Cc: netdev
On Fri, May 24, 2019 at 11:25:03AM +1000, Greg Ungerer wrote:
> Hi Andrew,
>
> I have a problem with a Marvell 6390 switch that I have bisected
> back to commit 7cbbee050c95, "[PATCH] net: dsa: mv88e6xxx: Set correct
> interface mode for CPU/DSA ports".
>
> I have a Marvell 380 SoC based platform with a Marvell 6390 10 port
> switch, everything works with kernel 5.0 and older. As of 5.1 the
> switch ports no longer work - no packets are ever received and
> none get sent out.
>
> The ports are probed and all discovered ok, they just don't work.
>
> mv88e6085 f1072004.mdio-mii:10: switch 0x3900 detected: Marvell 88E6390, revision 1
> libphy: mv88e6xxx SMI: probed
> mv88e6085 f1072004.mdio-mii:10 lan1 (uninitialized): PHY [mv88e6xxx-1:01] driver [Marvell 88E6390]
> mv88e6085 f1072004.mdio-mii:10 lan2 (uninitialized): PHY [mv88e6xxx-1:02] driver [Marvell 88E6390]
> mv88e6085 f1072004.mdio-mii:10 lan3 (uninitialized): PHY [mv88e6xxx-1:03] driver [Marvell 88E6390]
> mv88e6085 f1072004.mdio-mii:10 lan4 (uninitialized): PHY [mv88e6xxx-1:04] driver [Marvell 88E6390]
> mv88e6085 f1072004.mdio-mii:10 lan5 (uninitialized): PHY [mv88e6xxx-1:05] driver [Marvell 88E6390]
> mv88e6085 f1072004.mdio-mii:10 lan6 (uninitialized): PHY [mv88e6xxx-1:06] driver [Marvell 88E6390]
> mv88e6085 f1072004.mdio-mii:10 lan7 (uninitialized): PHY [mv88e6xxx-1:07] driver [Marvell 88E6390]
> mv88e6085 f1072004.mdio-mii:10 lan8 (uninitialized): PHY [mv88e6xxx-1:08] driver [Marvell 88E6390]
> DSA: tree 0 setup
>
> Things like ethtool on the ports seem to work ok, reports link correctly.
> Configuring ports as part of a bridge or individually gets the same result.
Hi Greg
DSA by default should configure the CPU port and DSA ports to there
maximum speed. For port 10, that is 10Gbps. Your 380 cannot do that
speed. So you need to tell the switch driver to slow down. Add a fixed
link node to port ten, with speed 1000. You might also need to set the
phy-mode to rgmii.
Can the 380 do 2500BaseX? There is work in progress to support this
speed, so maybe next cycle you can change to that.
Andrew
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH net] net: dsa: mv88e6xxx: Set correct interface mode for CPU/DSA ports
@ 2019-05-24 1:25 Greg Ungerer
2019-05-24 13:44 ` Andrew Lunn
0 siblings, 1 reply; 7+ messages in thread
From: Greg Ungerer @ 2019-05-24 1:25 UTC (permalink / raw)
To: Andrew Lunn; +Cc: netdev
Hi Andrew,
I have a problem with a Marvell 6390 switch that I have bisected
back to commit 7cbbee050c95, "[PATCH] net: dsa: mv88e6xxx: Set correct
interface mode for CPU/DSA ports".
I have a Marvell 380 SoC based platform with a Marvell 6390 10 port
switch, everything works with kernel 5.0 and older. As of 5.1 the
switch ports no longer work - no packets are ever received and
none get sent out.
The ports are probed and all discovered ok, they just don't work.
mv88e6085 f1072004.mdio-mii:10: switch 0x3900 detected: Marvell 88E6390, revision 1
libphy: mv88e6xxx SMI: probed
mv88e6085 f1072004.mdio-mii:10 lan1 (uninitialized): PHY [mv88e6xxx-1:01] driver [Marvell 88E6390]
mv88e6085 f1072004.mdio-mii:10 lan2 (uninitialized): PHY [mv88e6xxx-1:02] driver [Marvell 88E6390]
mv88e6085 f1072004.mdio-mii:10 lan3 (uninitialized): PHY [mv88e6xxx-1:03] driver [Marvell 88E6390]
mv88e6085 f1072004.mdio-mii:10 lan4 (uninitialized): PHY [mv88e6xxx-1:04] driver [Marvell 88E6390]
mv88e6085 f1072004.mdio-mii:10 lan5 (uninitialized): PHY [mv88e6xxx-1:05] driver [Marvell 88E6390]
mv88e6085 f1072004.mdio-mii:10 lan6 (uninitialized): PHY [mv88e6xxx-1:06] driver [Marvell 88E6390]
mv88e6085 f1072004.mdio-mii:10 lan7 (uninitialized): PHY [mv88e6xxx-1:07] driver [Marvell 88E6390]
mv88e6085 f1072004.mdio-mii:10 lan8 (uninitialized): PHY [mv88e6xxx-1:08] driver [Marvell 88E6390]
DSA: tree 0 setup
Things like ethtool on the ports seem to work ok, reports link correctly.
Configuring ports as part of a bridge or individually gets the same result.
Reverting just this single commit gets the ports working again
with a linux-5.1 kernel.
Any ideas?
Regards
Greg
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2019-05-29 1:12 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-03-08 0:21 [PATCH net] net: dsa: mv88e6xxx: Set correct interface mode for CPU/DSA ports Andrew Lunn
2019-03-09 7:02 ` David Miller
2019-05-24 1:25 Greg Ungerer
2019-05-24 13:44 ` Andrew Lunn
2019-05-27 1:26 ` Greg Ungerer
2019-05-28 13:17 ` Andrew Lunn
2019-05-29 1:12 ` Greg Ungerer
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