* [PATCH 2/5] drm/i915: Record platform specific ppGTT size in intel_device_info
2019-03-14 22:38 [PATCH 1/5] drm/i915: Mark up vGPU support for full-ppgtt Chris Wilson
@ 2019-03-14 22:38 ` Chris Wilson
2019-03-14 23:56 ` Rodrigo Vivi
2019-03-14 22:38 ` [PATCH 3/5] drm/i915: Drop address size from ppgtt_type Chris Wilson
` (6 subsequent siblings)
7 siblings, 1 reply; 19+ messages in thread
From: Chris Wilson @ 2019-03-14 22:38 UTC (permalink / raw)
To: intel-gfx
As the maximum addressable bits is determined by platform, record that
information in our static chipset tables. This has the advantage of
being clearly recorded in our capability dumps for dmesg, debugfs and
error states.
Based on a patch by Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Bob Paauwe <bob.j.paauwe@intel.com>
Cc: Matthew Auld <matthew.william.auld@gmail.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++------
drivers/gpu/drm/i915/i915_pci.c | 18 ++++++++++++------
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.h | 6 ++++--
drivers/gpu/drm/i915/selftests/huge_pages.c | 3 ++-
6 files changed, 22 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index dccb6006aabf..4864a35ddaca 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2452,7 +2452,7 @@ static inline unsigned int i915_sg_segment_size(void)
#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
-#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt)
+#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
#define HAS_PPGTT(dev_priv) \
(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
#define HAS_FULL_PPGTT(dev_priv) \
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index dac08d9c3fab..845d0ed5755b 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1538,10 +1538,7 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
ppgtt->vm.i915 = i915;
ppgtt->vm.dma = &i915->drm.pdev->dev;
-
- ppgtt->vm.total = HAS_FULL_48BIT_PPGTT(i915) ?
- 1ULL << 48 :
- 1ULL << 32;
+ ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
/* From bdw, there is support for read-only pages in the PPGTT. */
ppgtt->vm.has_read_only = true;
@@ -1991,8 +1988,7 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915)
ppgtt->base.vm.i915 = i915;
ppgtt->base.vm.dma = &i915->drm.pdev->dev;
-
- ppgtt->base.vm.total = I915_PDES * GEN6_PTES * I915_GTT_PAGE_SIZE;
+ ppgtt->base.vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
i915_address_space_init(&ppgtt->base.vm, VM_CLASS_PPGTT);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 3cf697e8f1fa..a13ac0f3e528 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -349,7 +349,8 @@ static const struct intel_device_info intel_ironlake_m_info = {
.has_llc = 1, \
.has_rc6 = 1, \
.has_rc6p = 1, \
- .ppgtt = INTEL_PPGTT_ALIASING, \
+ .ppgtt_type = INTEL_PPGTT_ALIASING, \
+ .ppgtt_size = 31, \
I9XX_PIPE_OFFSETS, \
I9XX_CURSOR_OFFSETS, \
GEN_DEFAULT_PAGE_SIZES
@@ -394,7 +395,8 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
.has_llc = 1, \
.has_rc6 = 1, \
.has_rc6p = 1, \
- .ppgtt = INTEL_PPGTT_FULL, \
+ .ppgtt_type = INTEL_PPGTT_FULL, \
+ .ppgtt_size = 31, \
IVB_PIPE_OFFSETS, \
IVB_CURSOR_OFFSETS, \
GEN_DEFAULT_PAGE_SIZES
@@ -447,7 +449,8 @@ static const struct intel_device_info intel_valleyview_info = {
.has_rc6 = 1,
.display.has_gmch = 1,
.display.has_hotplug = 1,
- .ppgtt = INTEL_PPGTT_FULL,
+ .ppgtt_type = INTEL_PPGTT_FULL,
+ .ppgtt_size = 31,
.has_snoop = true,
.has_coherent_ggtt = false,
.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
@@ -495,7 +498,8 @@ static const struct intel_device_info intel_haswell_gt3_info = {
.page_sizes = I915_GTT_PAGE_SIZE_4K | \
I915_GTT_PAGE_SIZE_2M, \
.has_logical_ring_contexts = 1, \
- .ppgtt = INTEL_PPGTT_FULL_4LVL, \
+ .ppgtt_type = INTEL_PPGTT_FULL_4LVL, \
+ .ppgtt_size = 48, \
.has_64bit_reloc = 1, \
.has_reset_engine = 1
@@ -540,7 +544,8 @@ static const struct intel_device_info intel_cherryview_info = {
.has_rc6 = 1,
.has_logical_ring_contexts = 1,
.display.has_gmch = 1,
- .ppgtt = INTEL_PPGTT_FULL,
+ .ppgtt_type = INTEL_PPGTT_FULL,
+ .ppgtt_size = 32,
.has_reset_engine = 1,
.has_snoop = true,
.has_coherent_ggtt = false,
@@ -616,7 +621,8 @@ static const struct intel_device_info intel_skylake_gt4_info = {
.has_logical_ring_contexts = 1, \
.has_logical_ring_preemption = 1, \
.has_guc = 1, \
- .ppgtt = INTEL_PPGTT_FULL_4LVL, \
+ .ppgtt_type = INTEL_PPGTT_FULL_4LVL, \
+ .ppgtt_size = 48, \
.has_reset_engine = 1, \
.has_snoop = true, \
.has_coherent_ggtt = false, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index aac19b1c419c..eddf83807957 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -844,7 +844,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
if (IS_GEN(dev_priv, 6) && intel_vtd_active()) {
DRM_INFO("Disabling ppGTT for VT-d support\n");
- info->ppgtt = INTEL_PPGTT_NONE;
+ info->ppgtt_type = INTEL_PPGTT_NONE;
}
/* Initialize command stream timestamp frequency */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 047d10bdd455..b57b34c96b3d 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -76,7 +76,7 @@ enum intel_platform {
INTEL_MAX_PLATFORMS
};
-enum intel_ppgtt {
+enum intel_ppgtt_type {
INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
@@ -162,7 +162,9 @@ struct intel_device_info {
enum intel_platform platform;
u32 platform_mask;
- enum intel_ppgtt ppgtt;
+ enum intel_ppgtt_type ppgtt_type;
+ unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
+
unsigned int page_sizes; /* page sizes supported by the HW */
u32 display_mmio_offset;
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 1e66cff985f8..e8b3f417a122 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1709,7 +1709,8 @@ int i915_gem_huge_page_mock_selftests(void)
return -ENOMEM;
/* Pretend to be a device which supports the 48b PPGTT */
- mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL_4LVL;
+ mkwrite_device_info(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL_4LVL;
+ mkwrite_device_info(dev_priv)->ppgtt_size = 48;
mutex_lock(&dev_priv->drm.struct_mutex);
ppgtt = i915_ppgtt_create(dev_priv, ERR_PTR(-ENODEV));
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH 2/5] drm/i915: Record platform specific ppGTT size in intel_device_info
2019-03-14 22:38 ` [PATCH 2/5] drm/i915: Record platform specific ppGTT size in intel_device_info Chris Wilson
@ 2019-03-14 23:56 ` Rodrigo Vivi
0 siblings, 0 replies; 19+ messages in thread
From: Rodrigo Vivi @ 2019-03-14 23:56 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Thu, Mar 14, 2019 at 10:38:36PM +0000, Chris Wilson wrote:
> As the maximum addressable bits is determined by platform, record that
> information in our static chipset tables. This has the advantage of
> being clearly recorded in our capability dumps for dmesg, debugfs and
> error states.
>
> Based on a patch by Bob Paauwe <bob.j.paauwe@intel.com>
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Bob Paauwe <bob.j.paauwe@intel.com>
> Cc: Matthew Auld <matthew.william.auld@gmail.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++------
> drivers/gpu/drm/i915/i915_pci.c | 18 ++++++++++++------
> drivers/gpu/drm/i915/intel_device_info.c | 2 +-
> drivers/gpu/drm/i915/intel_device_info.h | 6 ++++--
> drivers/gpu/drm/i915/selftests/huge_pages.c | 3 ++-
> 6 files changed, 22 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index dccb6006aabf..4864a35ddaca 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2452,7 +2452,7 @@ static inline unsigned int i915_sg_segment_size(void)
>
> #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
>
> -#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt)
> +#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
> #define HAS_PPGTT(dev_priv) \
> (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
> #define HAS_FULL_PPGTT(dev_priv) \
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index dac08d9c3fab..845d0ed5755b 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1538,10 +1538,7 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
>
> ppgtt->vm.i915 = i915;
> ppgtt->vm.dma = &i915->drm.pdev->dev;
> -
> - ppgtt->vm.total = HAS_FULL_48BIT_PPGTT(i915) ?
> - 1ULL << 48 :
> - 1ULL << 32;
> + ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
>
> /* From bdw, there is support for read-only pages in the PPGTT. */
> ppgtt->vm.has_read_only = true;
> @@ -1991,8 +1988,7 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915)
>
> ppgtt->base.vm.i915 = i915;
> ppgtt->base.vm.dma = &i915->drm.pdev->dev;
> -
> - ppgtt->base.vm.total = I915_PDES * GEN6_PTES * I915_GTT_PAGE_SIZE;
> + ppgtt->base.vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
! I would swear this was 32 so I had to check it with:
512 * ((unsigned int) getpagesize()/sizeof(int)) * BIT_ULL(12);
vs
BIT_ULL(31)
2147483648 vs 2147483648
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> i915_address_space_init(&ppgtt->base.vm, VM_CLASS_PPGTT);
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 3cf697e8f1fa..a13ac0f3e528 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -349,7 +349,8 @@ static const struct intel_device_info intel_ironlake_m_info = {
> .has_llc = 1, \
> .has_rc6 = 1, \
> .has_rc6p = 1, \
> - .ppgtt = INTEL_PPGTT_ALIASING, \
> + .ppgtt_type = INTEL_PPGTT_ALIASING, \
> + .ppgtt_size = 31, \
> I9XX_PIPE_OFFSETS, \
> I9XX_CURSOR_OFFSETS, \
> GEN_DEFAULT_PAGE_SIZES
> @@ -394,7 +395,8 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
> .has_llc = 1, \
> .has_rc6 = 1, \
> .has_rc6p = 1, \
> - .ppgtt = INTEL_PPGTT_FULL, \
> + .ppgtt_type = INTEL_PPGTT_FULL, \
> + .ppgtt_size = 31, \
> IVB_PIPE_OFFSETS, \
> IVB_CURSOR_OFFSETS, \
> GEN_DEFAULT_PAGE_SIZES
> @@ -447,7 +449,8 @@ static const struct intel_device_info intel_valleyview_info = {
> .has_rc6 = 1,
> .display.has_gmch = 1,
> .display.has_hotplug = 1,
> - .ppgtt = INTEL_PPGTT_FULL,
> + .ppgtt_type = INTEL_PPGTT_FULL,
> + .ppgtt_size = 31,
> .has_snoop = true,
> .has_coherent_ggtt = false,
> .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
> @@ -495,7 +498,8 @@ static const struct intel_device_info intel_haswell_gt3_info = {
> .page_sizes = I915_GTT_PAGE_SIZE_4K | \
> I915_GTT_PAGE_SIZE_2M, \
> .has_logical_ring_contexts = 1, \
> - .ppgtt = INTEL_PPGTT_FULL_4LVL, \
> + .ppgtt_type = INTEL_PPGTT_FULL_4LVL, \
> + .ppgtt_size = 48, \
> .has_64bit_reloc = 1, \
> .has_reset_engine = 1
>
> @@ -540,7 +544,8 @@ static const struct intel_device_info intel_cherryview_info = {
> .has_rc6 = 1,
> .has_logical_ring_contexts = 1,
> .display.has_gmch = 1,
> - .ppgtt = INTEL_PPGTT_FULL,
> + .ppgtt_type = INTEL_PPGTT_FULL,
> + .ppgtt_size = 32,
> .has_reset_engine = 1,
> .has_snoop = true,
> .has_coherent_ggtt = false,
> @@ -616,7 +621,8 @@ static const struct intel_device_info intel_skylake_gt4_info = {
> .has_logical_ring_contexts = 1, \
> .has_logical_ring_preemption = 1, \
> .has_guc = 1, \
> - .ppgtt = INTEL_PPGTT_FULL_4LVL, \
> + .ppgtt_type = INTEL_PPGTT_FULL_4LVL, \
> + .ppgtt_size = 48, \
> .has_reset_engine = 1, \
> .has_snoop = true, \
> .has_coherent_ggtt = false, \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index aac19b1c419c..eddf83807957 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -844,7 +844,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>
> if (IS_GEN(dev_priv, 6) && intel_vtd_active()) {
> DRM_INFO("Disabling ppGTT for VT-d support\n");
> - info->ppgtt = INTEL_PPGTT_NONE;
> + info->ppgtt_type = INTEL_PPGTT_NONE;
> }
>
> /* Initialize command stream timestamp frequency */
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 047d10bdd455..b57b34c96b3d 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -76,7 +76,7 @@ enum intel_platform {
> INTEL_MAX_PLATFORMS
> };
>
> -enum intel_ppgtt {
> +enum intel_ppgtt_type {
> INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
> INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
> INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
> @@ -162,7 +162,9 @@ struct intel_device_info {
> enum intel_platform platform;
> u32 platform_mask;
>
> - enum intel_ppgtt ppgtt;
> + enum intel_ppgtt_type ppgtt_type;
> + unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
> +
> unsigned int page_sizes; /* page sizes supported by the HW */
>
> u32 display_mmio_offset;
> diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
> index 1e66cff985f8..e8b3f417a122 100644
> --- a/drivers/gpu/drm/i915/selftests/huge_pages.c
> +++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
> @@ -1709,7 +1709,8 @@ int i915_gem_huge_page_mock_selftests(void)
> return -ENOMEM;
>
> /* Pretend to be a device which supports the 48b PPGTT */
> - mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL_4LVL;
> + mkwrite_device_info(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL_4LVL;
> + mkwrite_device_info(dev_priv)->ppgtt_size = 48;
>
> mutex_lock(&dev_priv->drm.struct_mutex);
> ppgtt = i915_ppgtt_create(dev_priv, ERR_PTR(-ENODEV));
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 3/5] drm/i915: Drop address size from ppgtt_type
2019-03-14 22:38 [PATCH 1/5] drm/i915: Mark up vGPU support for full-ppgtt Chris Wilson
2019-03-14 22:38 ` [PATCH 2/5] drm/i915: Record platform specific ppGTT size in intel_device_info Chris Wilson
@ 2019-03-14 22:38 ` Chris Wilson
2019-03-15 0:03 ` Rodrigo Vivi
2019-03-14 22:38 ` [PATCH 4/5] drm/i915/gtt: Rename i915_vm_is_48b to i915_vm_is_4lvl Chris Wilson
` (5 subsequent siblings)
7 siblings, 1 reply; 19+ messages in thread
From: Chris Wilson @ 2019-03-14 22:38 UTC (permalink / raw)
To: intel-gfx
With the introduction of the separate addressable bits into the device
info, we can remove the conflation of the ppgtt size from the ppgtt
type.
Based on a patch by Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Bob Paauwe <bob.j.paauwe@intel.com>
Cc: Matthew Auld <matthew.william.auld@gmail.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/i915_pci.c | 4 ++--
drivers/gpu/drm/i915/intel_device_info.h | 1 -
drivers/gpu/drm/i915/selftests/huge_pages.c | 2 +-
5 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index ad695cdc0487..a3b00ecc58c9 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -348,7 +348,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
value = HAS_WT(dev_priv);
break;
case I915_PARAM_HAS_ALIASING_PPGTT:
- value = min_t(int, INTEL_PPGTT(dev_priv), I915_GEM_PPGTT_FULL);
+ value = INTEL_PPGTT(dev_priv);
break;
case I915_PARAM_HAS_SEMAPHORES:
value = !!(dev_priv->caps.scheduler & I915_SCHEDULER_CAP_SEMAPHORES);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4864a35ddaca..c65c2e6649df 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2457,8 +2457,6 @@ static inline unsigned int i915_sg_segment_size(void)
(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
#define HAS_FULL_PPGTT(dev_priv) \
(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
-#define HAS_FULL_48BIT_PPGTT(dev_priv) \
- (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
GEM_BUG_ON((sizes) == 0); \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index a13ac0f3e528..ef7410c492fd 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -498,7 +498,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
.page_sizes = I915_GTT_PAGE_SIZE_4K | \
I915_GTT_PAGE_SIZE_2M, \
.has_logical_ring_contexts = 1, \
- .ppgtt_type = INTEL_PPGTT_FULL_4LVL, \
+ .ppgtt_type = INTEL_PPGTT_FULL, \
.ppgtt_size = 48, \
.has_64bit_reloc = 1, \
.has_reset_engine = 1
@@ -621,7 +621,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
.has_logical_ring_contexts = 1, \
.has_logical_ring_preemption = 1, \
.has_guc = 1, \
- .ppgtt_type = INTEL_PPGTT_FULL_4LVL, \
+ .ppgtt_type = INTEL_PPGTT_FULL, \
.ppgtt_size = 48, \
.has_reset_engine = 1, \
.has_snoop = true, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index b57b34c96b3d..6234570a9b17 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -80,7 +80,6 @@ enum intel_ppgtt_type {
INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
- INTEL_PPGTT_FULL_4LVL,
};
#define DEV_INFO_FOR_EACH_FLAG(func) \
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index e8b3f417a122..3ad7f041ae84 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1709,7 +1709,7 @@ int i915_gem_huge_page_mock_selftests(void)
return -ENOMEM;
/* Pretend to be a device which supports the 48b PPGTT */
- mkwrite_device_info(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL_4LVL;
+ mkwrite_device_info(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL;
mkwrite_device_info(dev_priv)->ppgtt_size = 48;
mutex_lock(&dev_priv->drm.struct_mutex);
--
2.20.1
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^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH 3/5] drm/i915: Drop address size from ppgtt_type
2019-03-14 22:38 ` [PATCH 3/5] drm/i915: Drop address size from ppgtt_type Chris Wilson
@ 2019-03-15 0:03 ` Rodrigo Vivi
2019-03-15 8:32 ` Chris Wilson
0 siblings, 1 reply; 19+ messages in thread
From: Rodrigo Vivi @ 2019-03-15 0:03 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Thu, Mar 14, 2019 at 10:38:37PM +0000, Chris Wilson wrote:
> With the introduction of the separate addressable bits into the device
> info, we can remove the conflation of the ppgtt size from the ppgtt
> type.
>
> Based on a patch by Bob Paauwe <bob.j.paauwe@intel.com>
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Bob Paauwe <bob.j.paauwe@intel.com>
> Cc: Matthew Auld <matthew.william.auld@gmail.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 2 --
> drivers/gpu/drm/i915/i915_pci.c | 4 ++--
> drivers/gpu/drm/i915/intel_device_info.h | 1 -
> drivers/gpu/drm/i915/selftests/huge_pages.c | 2 +-
> 5 files changed, 4 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index ad695cdc0487..a3b00ecc58c9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -348,7 +348,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
> value = HAS_WT(dev_priv);
> break;
> case I915_PARAM_HAS_ALIASING_PPGTT:
> - value = min_t(int, INTEL_PPGTT(dev_priv), I915_GEM_PPGTT_FULL);
> + value = INTEL_PPGTT(dev_priv);
I don't know the users of this param so I'm not 100% confident that this
doesn't break something.
But overall this seems the right way to go and the rest of
the patch looks correct...
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> break;
> case I915_PARAM_HAS_SEMAPHORES:
> value = !!(dev_priv->caps.scheduler & I915_SCHEDULER_CAP_SEMAPHORES);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4864a35ddaca..c65c2e6649df 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2457,8 +2457,6 @@ static inline unsigned int i915_sg_segment_size(void)
> (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
> #define HAS_FULL_PPGTT(dev_priv) \
> (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
> -#define HAS_FULL_48BIT_PPGTT(dev_priv) \
> - (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
>
> #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
> GEM_BUG_ON((sizes) == 0); \
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index a13ac0f3e528..ef7410c492fd 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -498,7 +498,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
> .page_sizes = I915_GTT_PAGE_SIZE_4K | \
> I915_GTT_PAGE_SIZE_2M, \
> .has_logical_ring_contexts = 1, \
> - .ppgtt_type = INTEL_PPGTT_FULL_4LVL, \
> + .ppgtt_type = INTEL_PPGTT_FULL, \
> .ppgtt_size = 48, \
> .has_64bit_reloc = 1, \
> .has_reset_engine = 1
> @@ -621,7 +621,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
> .has_logical_ring_contexts = 1, \
> .has_logical_ring_preemption = 1, \
> .has_guc = 1, \
> - .ppgtt_type = INTEL_PPGTT_FULL_4LVL, \
> + .ppgtt_type = INTEL_PPGTT_FULL, \
> .ppgtt_size = 48, \
> .has_reset_engine = 1, \
> .has_snoop = true, \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index b57b34c96b3d..6234570a9b17 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -80,7 +80,6 @@ enum intel_ppgtt_type {
> INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
> INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
> INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
> - INTEL_PPGTT_FULL_4LVL,
> };
>
> #define DEV_INFO_FOR_EACH_FLAG(func) \
> diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
> index e8b3f417a122..3ad7f041ae84 100644
> --- a/drivers/gpu/drm/i915/selftests/huge_pages.c
> +++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
> @@ -1709,7 +1709,7 @@ int i915_gem_huge_page_mock_selftests(void)
> return -ENOMEM;
>
> /* Pretend to be a device which supports the 48b PPGTT */
> - mkwrite_device_info(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL_4LVL;
> + mkwrite_device_info(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL;
> mkwrite_device_info(dev_priv)->ppgtt_size = 48;
>
> mutex_lock(&dev_priv->drm.struct_mutex);
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 3/5] drm/i915: Drop address size from ppgtt_type
2019-03-15 0:03 ` Rodrigo Vivi
@ 2019-03-15 8:32 ` Chris Wilson
0 siblings, 0 replies; 19+ messages in thread
From: Chris Wilson @ 2019-03-15 8:32 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
Quoting Rodrigo Vivi (2019-03-15 00:03:43)
> On Thu, Mar 14, 2019 at 10:38:37PM +0000, Chris Wilson wrote:
> > With the introduction of the separate addressable bits into the device
> > info, we can remove the conflation of the ppgtt size from the ppgtt
> > type.
> >
> > Based on a patch by Bob Paauwe <bob.j.paauwe@intel.com>
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Bob Paauwe <bob.j.paauwe@intel.com>
> > Cc: Matthew Auld <matthew.william.auld@gmail.com>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.c | 2 +-
> > drivers/gpu/drm/i915/i915_drv.h | 2 --
> > drivers/gpu/drm/i915/i915_pci.c | 4 ++--
> > drivers/gpu/drm/i915/intel_device_info.h | 1 -
> > drivers/gpu/drm/i915/selftests/huge_pages.c | 2 +-
> > 5 files changed, 4 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > index ad695cdc0487..a3b00ecc58c9 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -348,7 +348,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
> > value = HAS_WT(dev_priv);
> > break;
> > case I915_PARAM_HAS_ALIASING_PPGTT:
> > - value = min_t(int, INTEL_PPGTT(dev_priv), I915_GEM_PPGTT_FULL);
> > + value = INTEL_PPGTT(dev_priv);
>
> I don't know the users of this param so I'm not 100% confident that this
> doesn't break something.
The point was that we made the change earlier to define intel_ppgtt_type
from the uABI values, of which INTEL_PPGTT_FULL_4LVL was the odd one out
for not being exported as it still implied _48b_ (back when it was just
a reflection of the modparam). Upon introducing 48b, we added
I915_CONTEXT_PARAM_GTT_SIZE precisely for the purpose of reporting the
actual GTT size (with the hope that we could one day support dynamic
resizing per-context) rather than infer it based on an global enum.
-Chris
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^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 4/5] drm/i915/gtt: Rename i915_vm_is_48b to i915_vm_is_4lvl
2019-03-14 22:38 [PATCH 1/5] drm/i915: Mark up vGPU support for full-ppgtt Chris Wilson
2019-03-14 22:38 ` [PATCH 2/5] drm/i915: Record platform specific ppGTT size in intel_device_info Chris Wilson
2019-03-14 22:38 ` [PATCH 3/5] drm/i915: Drop address size from ppgtt_type Chris Wilson
@ 2019-03-14 22:38 ` Chris Wilson
2019-03-14 22:52 ` Rodrigo Vivi
2019-03-14 22:38 ` [PATCH 5/5] drm/i915/gtt: Refactor common ppgtt initialisation Chris Wilson
` (4 subsequent siblings)
7 siblings, 1 reply; 19+ messages in thread
From: Chris Wilson @ 2019-03-14 22:38 UTC (permalink / raw)
To: intel-gfx
Large ppGTT are differentiated by the requirement to go to four levels
to address more than 32b. Given the introduction of more 4 level ppGTT
with different sizes of addressable bits, rename i915_vm_is_48b() to
better reflect the commonality of using 4 levels.
Based on a patch by Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Bob Paauwe <bob.j.paauwe@intel.com>
Cc: Matthew Auld <matthew.william.auld@gmail.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/gvt/scheduler.c | 6 ++---
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 27 +++++++++------------
drivers/gpu/drm/i915/i915_gem_gtt.h | 4 +--
drivers/gpu/drm/i915/intel_lrc.c | 4 +--
drivers/gpu/drm/i915/selftests/huge_pages.c | 4 +--
6 files changed, 21 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index 709bcaaed765..7550e09939ae 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -1101,9 +1101,9 @@ i915_context_ppgtt_root_restore(struct intel_vgpu_submission *s)
struct i915_hw_ppgtt *i915_ppgtt = s->shadow_ctx->ppgtt;
int i;
- if (i915_vm_is_48bit(&i915_ppgtt->vm))
+ if (i915_vm_is_4lvl(&i915_ppgtt->vm)) {
px_dma(&i915_ppgtt->pml4) = s->i915_context_pml4;
- else {
+ } else {
for (i = 0; i < GEN8_3LVL_PDPES; i++)
px_dma(i915_ppgtt->pdp.page_directory[i]) =
s->i915_context_pdps[i];
@@ -1154,7 +1154,7 @@ i915_context_ppgtt_root_save(struct intel_vgpu_submission *s)
struct i915_hw_ppgtt *i915_ppgtt = s->shadow_ctx->ppgtt;
int i;
- if (i915_vm_is_48bit(&i915_ppgtt->vm))
+ if (i915_vm_is_4lvl(&i915_ppgtt->vm))
s->i915_context_pml4 = px_dma(&i915_ppgtt->pml4);
else {
for (i = 0; i < GEN8_3LVL_PDPES; i++)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index b6370225dcb5..21208a865380 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -321,7 +321,7 @@ static u32 default_desc_template(const struct drm_i915_private *i915,
desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
address_mode = INTEL_LEGACY_32B_CONTEXT;
- if (ppgtt && i915_vm_is_48bit(&ppgtt->vm))
+ if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm))
address_mode = INTEL_LEGACY_64B_CONTEXT;
desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 845d0ed5755b..83362c8ac110 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -584,7 +584,7 @@ setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
* for all.
*/
size = I915_GTT_PAGE_SIZE_4K;
- if (i915_vm_is_48bit(vm) &&
+ if (i915_vm_is_4lvl(vm) &&
HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K)) {
size = I915_GTT_PAGE_SIZE_64K;
gfp |= __GFP_NOWARN;
@@ -727,18 +727,13 @@ static void __pdp_fini(struct i915_page_directory_pointer *pdp)
pdp->page_directory = NULL;
}
-static inline bool use_4lvl(const struct i915_address_space *vm)
-{
- return i915_vm_is_48bit(vm);
-}
-
static struct i915_page_directory_pointer *
alloc_pdp(struct i915_address_space *vm)
{
struct i915_page_directory_pointer *pdp;
int ret = -ENOMEM;
- GEM_BUG_ON(!use_4lvl(vm));
+ GEM_BUG_ON(!i915_vm_is_4lvl(vm));
pdp = kzalloc(sizeof(*pdp), GFP_KERNEL);
if (!pdp)
@@ -767,7 +762,7 @@ static void free_pdp(struct i915_address_space *vm,
{
__pdp_fini(pdp);
- if (!use_4lvl(vm))
+ if (!i915_vm_is_4lvl(vm))
return;
cleanup_px(vm, pdp);
@@ -871,7 +866,7 @@ static void gen8_ppgtt_set_pdpe(struct i915_address_space *vm,
gen8_ppgtt_pdpe_t *vaddr;
pdp->page_directory[pdpe] = pd;
- if (!use_4lvl(vm))
+ if (!i915_vm_is_4lvl(vm))
return;
vaddr = kmap_atomic_px(pdp);
@@ -936,7 +931,7 @@ static void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm,
struct i915_page_directory_pointer *pdp;
unsigned int pml4e;
- GEM_BUG_ON(!use_4lvl(vm));
+ GEM_BUG_ON(!i915_vm_is_4lvl(vm));
gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
GEM_BUG_ON(pdp == vm->scratch_pdp);
@@ -1247,7 +1242,7 @@ static int gen8_init_scratch(struct i915_address_space *vm)
goto free_pt;
}
- if (use_4lvl(vm)) {
+ if (i915_vm_is_4lvl(vm)) {
vm->scratch_pdp = alloc_pdp(vm);
if (IS_ERR(vm->scratch_pdp)) {
ret = PTR_ERR(vm->scratch_pdp);
@@ -1257,7 +1252,7 @@ static int gen8_init_scratch(struct i915_address_space *vm)
gen8_initialize_pt(vm, vm->scratch_pt);
gen8_initialize_pd(vm, vm->scratch_pd);
- if (use_4lvl(vm))
+ if (i915_vm_is_4lvl(vm))
gen8_initialize_pdp(vm, vm->scratch_pdp);
return 0;
@@ -1279,7 +1274,7 @@ static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create)
enum vgt_g2v_type msg;
int i;
- if (use_4lvl(vm)) {
+ if (i915_vm_is_4lvl(vm)) {
const u64 daddr = px_dma(&ppgtt->pml4);
I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr));
@@ -1309,7 +1304,7 @@ static void gen8_free_scratch(struct i915_address_space *vm)
if (!vm->scratch_page.daddr)
return;
- if (use_4lvl(vm))
+ if (i915_vm_is_4lvl(vm))
free_pdp(vm, vm->scratch_pdp);
free_pd(vm, vm->scratch_pd);
free_pt(vm, vm->scratch_pt);
@@ -1355,7 +1350,7 @@ static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
if (intel_vgpu_active(dev_priv))
gen8_ppgtt_notify_vgt(ppgtt, false);
- if (use_4lvl(vm))
+ if (i915_vm_is_4lvl(vm))
gen8_ppgtt_cleanup_4lvl(ppgtt);
else
gen8_ppgtt_cleanup_3lvl(&ppgtt->vm, &ppgtt->pdp);
@@ -1555,7 +1550,7 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
if (err)
goto err_free;
- if (use_4lvl(&ppgtt->vm)) {
+ if (i915_vm_is_4lvl(&ppgtt->vm)) {
err = setup_px(&ppgtt->vm, &ppgtt->pml4);
if (err)
goto err_scratch;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index a47e11e6fc1b..35f21a2ae36c 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -348,7 +348,7 @@ struct i915_address_space {
#define i915_is_ggtt(vm) ((vm)->is_ggtt)
static inline bool
-i915_vm_is_48bit(const struct i915_address_space *vm)
+i915_vm_is_4lvl(const struct i915_address_space *vm)
{
return (vm->total - 1) >> 32;
}
@@ -488,7 +488,7 @@ static inline u32 gen6_pde_index(u32 addr)
static inline unsigned int
i915_pdpes_per_pdp(const struct i915_address_space *vm)
{
- if (i915_vm_is_48bit(vm))
+ if (i915_vm_is_4lvl(vm))
return GEN8_PML4ES_PER_PML4;
return GEN8_3LVL_PDPES;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index dc3de09c7586..11b81fd15fab 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1499,7 +1499,7 @@ static int execlists_request_alloc(struct i915_request *request)
*/
/* Unconditionally invalidate GPU caches and TLBs. */
- if (i915_vm_is_48bit(&request->gem_context->ppgtt->vm))
+ if (i915_vm_is_4lvl(&request->gem_context->ppgtt->vm))
ret = request->engine->emit_flush(request, EMIT_INVALIDATE);
else
ret = emit_pdps(request);
@@ -2719,7 +2719,7 @@ static void execlists_init_reg_state(u32 *regs,
CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
- if (i915_vm_is_48bit(&ppgtt->vm)) {
+ if (i915_vm_is_4lvl(&ppgtt->vm)) {
/* 64b PPGTT (48bit canonical)
* PDP0_DESCRIPTOR contains the base address to PML4 and
* other PDP Descriptors are ignored.
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 3ad7f041ae84..2e1db30af477 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1449,7 +1449,7 @@ static int igt_ppgtt_pin_update(void *arg)
* huge-gtt-pages.
*/
- if (!ppgtt || !i915_vm_is_48bit(&ppgtt->vm)) {
+ if (!ppgtt || !i915_vm_is_4lvl(&ppgtt->vm)) {
pr_info("48b PPGTT not supported, skipping\n");
return 0;
}
@@ -1719,7 +1719,7 @@ int i915_gem_huge_page_mock_selftests(void)
goto out_unlock;
}
- if (!i915_vm_is_48bit(&ppgtt->vm)) {
+ if (!i915_vm_is_4lvl(&ppgtt->vm)) {
pr_err("failed to create 48b PPGTT\n");
err = -EINVAL;
goto out_close;
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH 4/5] drm/i915/gtt: Rename i915_vm_is_48b to i915_vm_is_4lvl
2019-03-14 22:38 ` [PATCH 4/5] drm/i915/gtt: Rename i915_vm_is_48b to i915_vm_is_4lvl Chris Wilson
@ 2019-03-14 22:52 ` Rodrigo Vivi
0 siblings, 0 replies; 19+ messages in thread
From: Rodrigo Vivi @ 2019-03-14 22:52 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Thu, Mar 14, 2019 at 10:38:38PM +0000, Chris Wilson wrote:
> Large ppGTT are differentiated by the requirement to go to four levels
> to address more than 32b. Given the introduction of more 4 level ppGTT
> with different sizes of addressable bits, rename i915_vm_is_48b() to
> better reflect the commonality of using 4 levels.
>
> Based on a patch by Bob Paauwe <bob.j.paauwe@intel.com>
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Bob Paauwe <bob.j.paauwe@intel.com>
> Cc: Matthew Auld <matthew.william.auld@gmail.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/gvt/scheduler.c | 6 ++---
> drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
> drivers/gpu/drm/i915/i915_gem_gtt.c | 27 +++++++++------------
> drivers/gpu/drm/i915/i915_gem_gtt.h | 4 +--
> drivers/gpu/drm/i915/intel_lrc.c | 4 +--
> drivers/gpu/drm/i915/selftests/huge_pages.c | 4 +--
> 6 files changed, 21 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
> index 709bcaaed765..7550e09939ae 100644
> --- a/drivers/gpu/drm/i915/gvt/scheduler.c
> +++ b/drivers/gpu/drm/i915/gvt/scheduler.c
> @@ -1101,9 +1101,9 @@ i915_context_ppgtt_root_restore(struct intel_vgpu_submission *s)
> struct i915_hw_ppgtt *i915_ppgtt = s->shadow_ctx->ppgtt;
> int i;
>
> - if (i915_vm_is_48bit(&i915_ppgtt->vm))
> + if (i915_vm_is_4lvl(&i915_ppgtt->vm)) {
> px_dma(&i915_ppgtt->pml4) = s->i915_context_pml4;
> - else {
> + } else {
> for (i = 0; i < GEN8_3LVL_PDPES; i++)
> px_dma(i915_ppgtt->pdp.page_directory[i]) =
> s->i915_context_pdps[i];
> @@ -1154,7 +1154,7 @@ i915_context_ppgtt_root_save(struct intel_vgpu_submission *s)
> struct i915_hw_ppgtt *i915_ppgtt = s->shadow_ctx->ppgtt;
> int i;
>
> - if (i915_vm_is_48bit(&i915_ppgtt->vm))
> + if (i915_vm_is_4lvl(&i915_ppgtt->vm))
> s->i915_context_pml4 = px_dma(&i915_ppgtt->pml4);
> else {
> for (i = 0; i < GEN8_3LVL_PDPES; i++)
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index b6370225dcb5..21208a865380 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -321,7 +321,7 @@ static u32 default_desc_template(const struct drm_i915_private *i915,
> desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
>
> address_mode = INTEL_LEGACY_32B_CONTEXT;
> - if (ppgtt && i915_vm_is_48bit(&ppgtt->vm))
> + if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm))
> address_mode = INTEL_LEGACY_64B_CONTEXT;
> desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 845d0ed5755b..83362c8ac110 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -584,7 +584,7 @@ setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
> * for all.
> */
> size = I915_GTT_PAGE_SIZE_4K;
> - if (i915_vm_is_48bit(vm) &&
> + if (i915_vm_is_4lvl(vm) &&
> HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K)) {
> size = I915_GTT_PAGE_SIZE_64K;
> gfp |= __GFP_NOWARN;
> @@ -727,18 +727,13 @@ static void __pdp_fini(struct i915_page_directory_pointer *pdp)
> pdp->page_directory = NULL;
> }
>
> -static inline bool use_4lvl(const struct i915_address_space *vm)
> -{
> - return i915_vm_is_48bit(vm);
> -}
> -
> static struct i915_page_directory_pointer *
> alloc_pdp(struct i915_address_space *vm)
> {
> struct i915_page_directory_pointer *pdp;
> int ret = -ENOMEM;
>
> - GEM_BUG_ON(!use_4lvl(vm));
> + GEM_BUG_ON(!i915_vm_is_4lvl(vm));
>
> pdp = kzalloc(sizeof(*pdp), GFP_KERNEL);
> if (!pdp)
> @@ -767,7 +762,7 @@ static void free_pdp(struct i915_address_space *vm,
> {
> __pdp_fini(pdp);
>
> - if (!use_4lvl(vm))
> + if (!i915_vm_is_4lvl(vm))
> return;
>
> cleanup_px(vm, pdp);
> @@ -871,7 +866,7 @@ static void gen8_ppgtt_set_pdpe(struct i915_address_space *vm,
> gen8_ppgtt_pdpe_t *vaddr;
>
> pdp->page_directory[pdpe] = pd;
> - if (!use_4lvl(vm))
> + if (!i915_vm_is_4lvl(vm))
> return;
>
> vaddr = kmap_atomic_px(pdp);
> @@ -936,7 +931,7 @@ static void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm,
> struct i915_page_directory_pointer *pdp;
> unsigned int pml4e;
>
> - GEM_BUG_ON(!use_4lvl(vm));
> + GEM_BUG_ON(!i915_vm_is_4lvl(vm));
>
> gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
> GEM_BUG_ON(pdp == vm->scratch_pdp);
> @@ -1247,7 +1242,7 @@ static int gen8_init_scratch(struct i915_address_space *vm)
> goto free_pt;
> }
>
> - if (use_4lvl(vm)) {
> + if (i915_vm_is_4lvl(vm)) {
> vm->scratch_pdp = alloc_pdp(vm);
> if (IS_ERR(vm->scratch_pdp)) {
> ret = PTR_ERR(vm->scratch_pdp);
> @@ -1257,7 +1252,7 @@ static int gen8_init_scratch(struct i915_address_space *vm)
>
> gen8_initialize_pt(vm, vm->scratch_pt);
> gen8_initialize_pd(vm, vm->scratch_pd);
> - if (use_4lvl(vm))
> + if (i915_vm_is_4lvl(vm))
> gen8_initialize_pdp(vm, vm->scratch_pdp);
>
> return 0;
> @@ -1279,7 +1274,7 @@ static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create)
> enum vgt_g2v_type msg;
> int i;
>
> - if (use_4lvl(vm)) {
> + if (i915_vm_is_4lvl(vm)) {
> const u64 daddr = px_dma(&ppgtt->pml4);
>
> I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr));
> @@ -1309,7 +1304,7 @@ static void gen8_free_scratch(struct i915_address_space *vm)
> if (!vm->scratch_page.daddr)
> return;
>
> - if (use_4lvl(vm))
> + if (i915_vm_is_4lvl(vm))
> free_pdp(vm, vm->scratch_pdp);
> free_pd(vm, vm->scratch_pd);
> free_pt(vm, vm->scratch_pt);
> @@ -1355,7 +1350,7 @@ static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
> if (intel_vgpu_active(dev_priv))
> gen8_ppgtt_notify_vgt(ppgtt, false);
>
> - if (use_4lvl(vm))
> + if (i915_vm_is_4lvl(vm))
> gen8_ppgtt_cleanup_4lvl(ppgtt);
> else
> gen8_ppgtt_cleanup_3lvl(&ppgtt->vm, &ppgtt->pdp);
> @@ -1555,7 +1550,7 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
> if (err)
> goto err_free;
>
> - if (use_4lvl(&ppgtt->vm)) {
> + if (i915_vm_is_4lvl(&ppgtt->vm)) {
> err = setup_px(&ppgtt->vm, &ppgtt->pml4);
> if (err)
> goto err_scratch;
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
> index a47e11e6fc1b..35f21a2ae36c 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> @@ -348,7 +348,7 @@ struct i915_address_space {
> #define i915_is_ggtt(vm) ((vm)->is_ggtt)
>
> static inline bool
> -i915_vm_is_48bit(const struct i915_address_space *vm)
> +i915_vm_is_4lvl(const struct i915_address_space *vm)
> {
> return (vm->total - 1) >> 32;
> }
> @@ -488,7 +488,7 @@ static inline u32 gen6_pde_index(u32 addr)
> static inline unsigned int
> i915_pdpes_per_pdp(const struct i915_address_space *vm)
> {
> - if (i915_vm_is_48bit(vm))
> + if (i915_vm_is_4lvl(vm))
> return GEN8_PML4ES_PER_PML4;
>
> return GEN8_3LVL_PDPES;
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index dc3de09c7586..11b81fd15fab 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1499,7 +1499,7 @@ static int execlists_request_alloc(struct i915_request *request)
> */
>
> /* Unconditionally invalidate GPU caches and TLBs. */
> - if (i915_vm_is_48bit(&request->gem_context->ppgtt->vm))
> + if (i915_vm_is_4lvl(&request->gem_context->ppgtt->vm))
> ret = request->engine->emit_flush(request, EMIT_INVALIDATE);
> else
> ret = emit_pdps(request);
> @@ -2719,7 +2719,7 @@ static void execlists_init_reg_state(u32 *regs,
> CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
> CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
>
> - if (i915_vm_is_48bit(&ppgtt->vm)) {
> + if (i915_vm_is_4lvl(&ppgtt->vm)) {
> /* 64b PPGTT (48bit canonical)
> * PDP0_DESCRIPTOR contains the base address to PML4 and
> * other PDP Descriptors are ignored.
> diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
> index 3ad7f041ae84..2e1db30af477 100644
> --- a/drivers/gpu/drm/i915/selftests/huge_pages.c
> +++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
> @@ -1449,7 +1449,7 @@ static int igt_ppgtt_pin_update(void *arg)
> * huge-gtt-pages.
> */
>
> - if (!ppgtt || !i915_vm_is_48bit(&ppgtt->vm)) {
> + if (!ppgtt || !i915_vm_is_4lvl(&ppgtt->vm)) {
> pr_info("48b PPGTT not supported, skipping\n");
> return 0;
> }
> @@ -1719,7 +1719,7 @@ int i915_gem_huge_page_mock_selftests(void)
> goto out_unlock;
> }
>
> - if (!i915_vm_is_48bit(&ppgtt->vm)) {
> + if (!i915_vm_is_4lvl(&ppgtt->vm)) {
> pr_err("failed to create 48b PPGTT\n");
> err = -EINVAL;
> goto out_close;
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 5/5] drm/i915/gtt: Refactor common ppgtt initialisation
2019-03-14 22:38 [PATCH 1/5] drm/i915: Mark up vGPU support for full-ppgtt Chris Wilson
` (2 preceding siblings ...)
2019-03-14 22:38 ` [PATCH 4/5] drm/i915/gtt: Rename i915_vm_is_48b to i915_vm_is_4lvl Chris Wilson
@ 2019-03-14 22:38 ` Chris Wilson
2019-03-14 22:53 ` Rodrigo Vivi
2019-03-14 22:55 ` [PATCH 1/5] drm/i915: Mark up vGPU support for full-ppgtt Rodrigo Vivi
` (3 subsequent siblings)
7 siblings, 1 reply; 19+ messages in thread
From: Chris Wilson @ 2019-03-14 22:38 UTC (permalink / raw)
To: intel-gfx
The basic setup of the i915_hw_ppgtt is the same between gen6 and gen8,
so refactor that into a common routine.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Bob Paauwe <bob.j.paauwe@intel.com>
Cc: Matthew Auld <matthew.william.auld@gmail.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 43 +++++++++++++----------------
1 file changed, 19 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 83362c8ac110..b8055c8d4e71 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1513,6 +1513,23 @@ static int gen8_preallocate_top_level_pdp(struct i915_hw_ppgtt *ppgtt)
return -ENOMEM;
}
+static void ppgtt_init(struct drm_i915_private *i915,
+ struct i915_hw_ppgtt *ppgtt)
+{
+ kref_init(&ppgtt->ref);
+
+ ppgtt->vm.i915 = i915;
+ ppgtt->vm.dma = &i915->drm.pdev->dev;
+ ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
+
+ i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT);
+
+ ppgtt->vm.vma_ops.bind_vma = ppgtt_bind_vma;
+ ppgtt->vm.vma_ops.unbind_vma = ppgtt_unbind_vma;
+ ppgtt->vm.vma_ops.set_pages = ppgtt_set_pages;
+ ppgtt->vm.vma_ops.clear_pages = clear_pages;
+}
+
/*
* GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
* with a net effect resembling a 2-level page table in normal x86 terms. Each
@@ -1529,17 +1546,11 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
if (!ppgtt)
return ERR_PTR(-ENOMEM);
- kref_init(&ppgtt->ref);
-
- ppgtt->vm.i915 = i915;
- ppgtt->vm.dma = &i915->drm.pdev->dev;
- ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
+ ppgtt_init(i915, ppgtt);
/* From bdw, there is support for read-only pages in the PPGTT. */
ppgtt->vm.has_read_only = true;
- i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT);
-
/* There are only few exceptions for gen >=6. chv and bxt.
* And we are not sure about the latter so play safe for now.
*/
@@ -1583,11 +1594,6 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
ppgtt->vm.cleanup = gen8_ppgtt_cleanup;
- ppgtt->vm.vma_ops.bind_vma = ppgtt_bind_vma;
- ppgtt->vm.vma_ops.unbind_vma = ppgtt_unbind_vma;
- ppgtt->vm.vma_ops.set_pages = ppgtt_set_pages;
- ppgtt->vm.vma_ops.clear_pages = clear_pages;
-
return ppgtt;
err_scratch:
@@ -1979,24 +1985,13 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915)
if (!ppgtt)
return ERR_PTR(-ENOMEM);
- kref_init(&ppgtt->base.ref);
-
- ppgtt->base.vm.i915 = i915;
- ppgtt->base.vm.dma = &i915->drm.pdev->dev;
- ppgtt->base.vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
-
- i915_address_space_init(&ppgtt->base.vm, VM_CLASS_PPGTT);
+ ppgtt_init(i915, &ppgtt->base);
ppgtt->base.vm.allocate_va_range = gen6_alloc_va_range;
ppgtt->base.vm.clear_range = gen6_ppgtt_clear_range;
ppgtt->base.vm.insert_entries = gen6_ppgtt_insert_entries;
ppgtt->base.vm.cleanup = gen6_ppgtt_cleanup;
- ppgtt->base.vm.vma_ops.bind_vma = ppgtt_bind_vma;
- ppgtt->base.vm.vma_ops.unbind_vma = ppgtt_unbind_vma;
- ppgtt->base.vm.vma_ops.set_pages = ppgtt_set_pages;
- ppgtt->base.vm.vma_ops.clear_pages = clear_pages;
-
ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode;
err = gen6_ppgtt_init_scratch(ppgtt);
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH 5/5] drm/i915/gtt: Refactor common ppgtt initialisation
2019-03-14 22:38 ` [PATCH 5/5] drm/i915/gtt: Refactor common ppgtt initialisation Chris Wilson
@ 2019-03-14 22:53 ` Rodrigo Vivi
2019-03-15 9:09 ` Chris Wilson
0 siblings, 1 reply; 19+ messages in thread
From: Rodrigo Vivi @ 2019-03-14 22:53 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Thu, Mar 14, 2019 at 10:38:39PM +0000, Chris Wilson wrote:
> The basic setup of the i915_hw_ppgtt is the same between gen6 and gen8,
> so refactor that into a common routine.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Bob Paauwe <bob.j.paauwe@intel.com>
> Cc: Matthew Auld <matthew.william.auld@gmail.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 43 +++++++++++++----------------
> 1 file changed, 19 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 83362c8ac110..b8055c8d4e71 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1513,6 +1513,23 @@ static int gen8_preallocate_top_level_pdp(struct i915_hw_ppgtt *ppgtt)
> return -ENOMEM;
> }
>
> +static void ppgtt_init(struct drm_i915_private *i915,
> + struct i915_hw_ppgtt *ppgtt)
> +{
> + kref_init(&ppgtt->ref);
> +
> + ppgtt->vm.i915 = i915;
> + ppgtt->vm.dma = &i915->drm.pdev->dev;
> + ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
> +
> + i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT);
> +
> + ppgtt->vm.vma_ops.bind_vma = ppgtt_bind_vma;
> + ppgtt->vm.vma_ops.unbind_vma = ppgtt_unbind_vma;
> + ppgtt->vm.vma_ops.set_pages = ppgtt_set_pages;
> + ppgtt->vm.vma_ops.clear_pages = clear_pages;
> +}
> +
> /*
> * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
> * with a net effect resembling a 2-level page table in normal x86 terms. Each
> @@ -1529,17 +1546,11 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
> if (!ppgtt)
> return ERR_PTR(-ENOMEM);
>
> - kref_init(&ppgtt->ref);
> -
> - ppgtt->vm.i915 = i915;
> - ppgtt->vm.dma = &i915->drm.pdev->dev;
> - ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
> + ppgtt_init(i915, ppgtt);
>
> /* From bdw, there is support for read-only pages in the PPGTT. */
> ppgtt->vm.has_read_only = true;
>
> - i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT);
> -
> /* There are only few exceptions for gen >=6. chv and bxt.
> * And we are not sure about the latter so play safe for now.
> */
> @@ -1583,11 +1594,6 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
>
> ppgtt->vm.cleanup = gen8_ppgtt_cleanup;
>
> - ppgtt->vm.vma_ops.bind_vma = ppgtt_bind_vma;
> - ppgtt->vm.vma_ops.unbind_vma = ppgtt_unbind_vma;
> - ppgtt->vm.vma_ops.set_pages = ppgtt_set_pages;
> - ppgtt->vm.vma_ops.clear_pages = clear_pages;
> -
> return ppgtt;
>
> err_scratch:
> @@ -1979,24 +1985,13 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915)
> if (!ppgtt)
> return ERR_PTR(-ENOMEM);
>
> - kref_init(&ppgtt->base.ref);
> -
> - ppgtt->base.vm.i915 = i915;
> - ppgtt->base.vm.dma = &i915->drm.pdev->dev;
> - ppgtt->base.vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
> -
> - i915_address_space_init(&ppgtt->base.vm, VM_CLASS_PPGTT);
> + ppgtt_init(i915, &ppgtt->base);
>
> ppgtt->base.vm.allocate_va_range = gen6_alloc_va_range;
> ppgtt->base.vm.clear_range = gen6_ppgtt_clear_range;
> ppgtt->base.vm.insert_entries = gen6_ppgtt_insert_entries;
> ppgtt->base.vm.cleanup = gen6_ppgtt_cleanup;
>
> - ppgtt->base.vm.vma_ops.bind_vma = ppgtt_bind_vma;
> - ppgtt->base.vm.vma_ops.unbind_vma = ppgtt_unbind_vma;
> - ppgtt->base.vm.vma_ops.set_pages = ppgtt_set_pages;
> - ppgtt->base.vm.vma_ops.clear_pages = clear_pages;
> -
> ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode;
>
> err = gen6_ppgtt_init_scratch(ppgtt);
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 5/5] drm/i915/gtt: Refactor common ppgtt initialisation
2019-03-14 22:53 ` Rodrigo Vivi
@ 2019-03-15 9:09 ` Chris Wilson
2019-03-15 16:55 ` Bob Paauwe
0 siblings, 1 reply; 19+ messages in thread
From: Chris Wilson @ 2019-03-15 9:09 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
Quoting Rodrigo Vivi (2019-03-14 22:53:44)
> On Thu, Mar 14, 2019 at 10:38:39PM +0000, Chris Wilson wrote:
> > The basic setup of the i915_hw_ppgtt is the same between gen6 and gen8,
> > so refactor that into a common routine.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Bob Paauwe <bob.j.paauwe@intel.com>
> > Cc: Matthew Auld <matthew.william.auld@gmail.com>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
I've pushed this series so that 36 bits should be a nice and simple drop
in.
Thank you Bob for preparing these, sorry for not being clear enough on
the direction I felt the patches should take.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 5/5] drm/i915/gtt: Refactor common ppgtt initialisation
2019-03-15 9:09 ` Chris Wilson
@ 2019-03-15 16:55 ` Bob Paauwe
2019-03-15 17:01 ` Rodrigo Vivi
0 siblings, 1 reply; 19+ messages in thread
From: Bob Paauwe @ 2019-03-15 16:55 UTC (permalink / raw)
To: intel-gfx
On Fri, 15 Mar 2019 09:09:11 +0000
Chris Wilson <chris@chris-wilson.co.uk> wrote:
> Quoting Rodrigo Vivi (2019-03-14 22:53:44)
> > On Thu, Mar 14, 2019 at 10:38:39PM +0000, Chris Wilson wrote:
> > > The basic setup of the i915_hw_ppgtt is the same between gen6 and gen8,
> > > so refactor that into a common routine.
> > >
> > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > Cc: Bob Paauwe <bob.j.paauwe@intel.com>
> > > Cc: Matthew Auld <matthew.william.auld@gmail.com>
> > > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> >
> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> I've pushed this series so that 36 bits should be a nice and simple drop
> in.
>
> Thank you Bob for preparing these, sorry for not being clear enough on
> the direction I felt the patches should take.
> -Chris
Thanks Chris,
It was helpful to see how you organized and re-wrote the series. This
was not code I was familiar with when I started so you're guidance
helped a lot.
Now I get to fix the EHL patches to take advantage of this.
Bob
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
--
Bob Paauwe
Bob.J.Paauwe@intel.com
IOTG / PED Software Organization
Intel Corp. Folsom, CA
(916) 356-6193
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 5/5] drm/i915/gtt: Refactor common ppgtt initialisation
2019-03-15 16:55 ` Bob Paauwe
@ 2019-03-15 17:01 ` Rodrigo Vivi
2019-03-15 17:26 ` Bob Paauwe
0 siblings, 1 reply; 19+ messages in thread
From: Rodrigo Vivi @ 2019-03-15 17:01 UTC (permalink / raw)
To: Bob Paauwe; +Cc: intel-gfx
On Fri, Mar 15, 2019 at 09:55:47AM -0700, Bob Paauwe wrote:
> On Fri, 15 Mar 2019 09:09:11 +0000
> Chris Wilson <chris@chris-wilson.co.uk> wrote:
>
> > Quoting Rodrigo Vivi (2019-03-14 22:53:44)
> > > On Thu, Mar 14, 2019 at 10:38:39PM +0000, Chris Wilson wrote:
> > > > The basic setup of the i915_hw_ppgtt is the same between gen6 and gen8,
> > > > so refactor that into a common routine.
> > > >
> > > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > > Cc: Bob Paauwe <bob.j.paauwe@intel.com>
> > > > Cc: Matthew Auld <matthew.william.auld@gmail.com>
> > > > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > >
> > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >
> > I've pushed this series so that 36 bits should be a nice and simple drop
> > in.
> >
> > Thank you Bob for preparing these, sorry for not being clear enough on
> > the direction I felt the patches should take.
> > -Chris
>
> Thanks Chris,
Thanks a lot Chris.
>
> It was helpful to see how you organized and re-wrote the series. This
> was not code I was familiar with when I started so you're guidance
> helped a lot.
>
> Now I get to fix the EHL patches to take advantage of this.
cool, so I will split the series into rv-b ones and probably
push soon just leaving the ppgt_size one for you to rebase
on top...
thoughts?
>
> Bob
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
> --
> --
> Bob Paauwe
> Bob.J.Paauwe@intel.com
> IOTG / PED Software Organization
> Intel Corp. Folsom, CA
> (916) 356-6193
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 5/5] drm/i915/gtt: Refactor common ppgtt initialisation
2019-03-15 17:01 ` Rodrigo Vivi
@ 2019-03-15 17:26 ` Bob Paauwe
2019-03-15 17:59 ` Rodrigo Vivi
0 siblings, 1 reply; 19+ messages in thread
From: Bob Paauwe @ 2019-03-15 17:26 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Fri, 15 Mar 2019 10:01:51 -0700
Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> On Fri, Mar 15, 2019 at 09:55:47AM -0700, Bob Paauwe wrote:
> > On Fri, 15 Mar 2019 09:09:11 +0000
> > Chris Wilson <chris@chris-wilson.co.uk> wrote:
> >
> > > Quoting Rodrigo Vivi (2019-03-14 22:53:44)
> > > > On Thu, Mar 14, 2019 at 10:38:39PM +0000, Chris Wilson wrote:
> > > > > The basic setup of the i915_hw_ppgtt is the same between gen6 and gen8,
> > > > > so refactor that into a common routine.
> > > > >
> > > > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > > > Cc: Bob Paauwe <bob.j.paauwe@intel.com>
> > > > > Cc: Matthew Auld <matthew.william.auld@gmail.com>
> > > > > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > > >
> > > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > >
> > > I've pushed this series so that 36 bits should be a nice and simple drop
> > > in.
> > >
> > > Thank you Bob for preparing these, sorry for not being clear enough on
> > > the direction I felt the patches should take.
> > > -Chris
> >
> > Thanks Chris,
>
> Thanks a lot Chris.
>
> >
> > It was helpful to see how you organized and re-wrote the series. This
> > was not code I was familiar with when I started so you're guidance
> > helped a lot.
> >
> > Now I get to fix the EHL patches to take advantage of this.
>
> cool, so I will split the series into rv-b ones and probably
> push soon just leaving the ppgt_size one for you to rebase
> on top...
>
> thoughts?
Would it make more sense to drop Patch 8, drm/i915/ehl: ehl has only
36bit extended ppgtt support and update patch 1 with the size added to the
device_info?
Otherwise, patch 8 becomes just adding the size into the device_info.
Either way works for me.
>
> >
> > Bob
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> >
> > --
> > --
> > Bob Paauwe
> > Bob.J.Paauwe@intel.com
> > IOTG / PED Software Organization
> > Intel Corp. Folsom, CA
> > (916) 356-6193
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
--
Bob Paauwe
Bob.J.Paauwe@intel.com
IOTG / PED Software Organization
Intel Corp. Folsom, CA
(916) 356-6193
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 5/5] drm/i915/gtt: Refactor common ppgtt initialisation
2019-03-15 17:26 ` Bob Paauwe
@ 2019-03-15 17:59 ` Rodrigo Vivi
0 siblings, 0 replies; 19+ messages in thread
From: Rodrigo Vivi @ 2019-03-15 17:59 UTC (permalink / raw)
To: Bob Paauwe; +Cc: intel-gfx
On Fri, Mar 15, 2019 at 10:26:04AM -0700, Bob Paauwe wrote:
> On Fri, 15 Mar 2019 10:01:51 -0700
> Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
>
> > On Fri, Mar 15, 2019 at 09:55:47AM -0700, Bob Paauwe wrote:
> > > On Fri, 15 Mar 2019 09:09:11 +0000
> > > Chris Wilson <chris@chris-wilson.co.uk> wrote:
> > >
> > > > Quoting Rodrigo Vivi (2019-03-14 22:53:44)
> > > > > On Thu, Mar 14, 2019 at 10:38:39PM +0000, Chris Wilson wrote:
> > > > > > The basic setup of the i915_hw_ppgtt is the same between gen6 and gen8,
> > > > > > so refactor that into a common routine.
> > > > > >
> > > > > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > > > > Cc: Bob Paauwe <bob.j.paauwe@intel.com>
> > > > > > Cc: Matthew Auld <matthew.william.auld@gmail.com>
> > > > > > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > > > >
> > > > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > >
> > > > I've pushed this series so that 36 bits should be a nice and simple drop
> > > > in.
> > > >
> > > > Thank you Bob for preparing these, sorry for not being clear enough on
> > > > the direction I felt the patches should take.
> > > > -Chris
> > >
> > > Thanks Chris,
> >
> > Thanks a lot Chris.
> >
> > >
> > > It was helpful to see how you organized and re-wrote the series. This
> > > was not code I was familiar with when I started so you're guidance
> > > helped a lot.
> > >
> > > Now I get to fix the EHL patches to take advantage of this.
> >
> > cool, so I will split the series into rv-b ones and probably
> > push soon just leaving the ppgt_size one for you to rebase
> > on top...
> >
> > thoughts?
>
> Would it make more sense to drop Patch 8, drm/i915/ehl: ehl has only
> 36bit extended ppgtt support and update patch 1 with the size added to the
> device_info?
>
> Otherwise, patch 8 becomes just adding the size into the device_info.
of course!
Unfortunately I read the email after I sent the rv-b patches for CI...
But I will change it there and send a v2 on top.
>
> Either way works for me.
>
> >
> > >
> > > Bob
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > >
> > >
> > > --
> > > --
> > > Bob Paauwe
> > > Bob.J.Paauwe@intel.com
> > > IOTG / PED Software Organization
> > > Intel Corp. Folsom, CA
> > > (916) 356-6193
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
> --
> --
> Bob Paauwe
> Bob.J.Paauwe@intel.com
> IOTG / PED Software Organization
> Intel Corp. Folsom, CA
> (916) 356-6193
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/5] drm/i915: Mark up vGPU support for full-ppgtt
2019-03-14 22:38 [PATCH 1/5] drm/i915: Mark up vGPU support for full-ppgtt Chris Wilson
` (3 preceding siblings ...)
2019-03-14 22:38 ` [PATCH 5/5] drm/i915/gtt: Refactor common ppgtt initialisation Chris Wilson
@ 2019-03-14 22:55 ` Rodrigo Vivi
2019-03-14 23:18 ` ✗ Fi.CI.SPARSE: warning for series starting with [1/5] " Patchwork
` (2 subsequent siblings)
7 siblings, 0 replies; 19+ messages in thread
From: Rodrigo Vivi @ 2019-03-14 22:55 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Thu, Mar 14, 2019 at 10:38:35PM +0000, Chris Wilson wrote:
> For compatibility reasons, we only care if the vGPU host provides
> support for full-ppgtt. This is independent of the addressable memory
> size, so remove the conflation of 48b from the capability name.
>
> Based on a patch by Bob Paauwe <bob.j.paauwe@intel.com>
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Bob Paauwe <bob.j.paauwe@intel.com>
> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> Cc: Zhi Wang <zhi.a.wang@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/gvt/vgpu.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> drivers/gpu/drm/i915/i915_pvinfo.h | 2 +-
> drivers/gpu/drm/i915/i915_vgpu.c | 4 ++--
> drivers/gpu/drm/i915/i915_vgpu.h | 2 +-
> 5 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
> index 720e2b10adaa..314e40121e47 100644
> --- a/drivers/gpu/drm/i915/gvt/vgpu.c
> +++ b/drivers/gpu/drm/i915/gvt/vgpu.c
> @@ -44,7 +44,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
> vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
> vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
>
> - vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
> + vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_PPGTT;
> vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
> vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 0d743907e7bc..ad695cdc0487 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1494,7 +1494,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
>
> if (HAS_PPGTT(dev_priv)) {
> if (intel_vgpu_active(dev_priv) &&
> - !intel_vgpu_has_full_48bit_ppgtt(dev_priv)) {
> + !intel_vgpu_has_full_ppgtt(dev_priv)) {
> i915_report_error(dev_priv,
> "incompatible vGPU found, support for isolated ppGTT required\n");
> return -ENXIO;
> diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
> index eeaa3d506d95..969e514916ab 100644
> --- a/drivers/gpu/drm/i915/i915_pvinfo.h
> +++ b/drivers/gpu/drm/i915/i915_pvinfo.h
> @@ -52,7 +52,7 @@ enum vgt_g2v_type {
> /*
> * VGT capabilities type
> */
> -#define VGT_CAPS_FULL_48BIT_PPGTT BIT(2)
> +#define VGT_CAPS_FULL_PPGTT BIT(2)
> #define VGT_CAPS_HWSP_EMULATION BIT(3)
> #define VGT_CAPS_HUGE_GTT BIT(4)
>
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
> index 869cf4a3b6de..3b2d83f704e3 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.c
> +++ b/drivers/gpu/drm/i915/i915_vgpu.c
> @@ -81,9 +81,9 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
> DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
> }
>
> -bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv)
> +bool intel_vgpu_has_full_ppgtt(struct drm_i915_private *dev_priv)
> {
> - return dev_priv->vgpu.caps & VGT_CAPS_FULL_48BIT_PPGTT;
> + return dev_priv->vgpu.caps & VGT_CAPS_FULL_PPGTT;
> }
>
> struct _balloon_info_ {
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
> index 551acc390046..ebe1b7bced98 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.h
> +++ b/drivers/gpu/drm/i915/i915_vgpu.h
> @@ -28,7 +28,7 @@
>
> void i915_check_vgpu(struct drm_i915_private *dev_priv);
>
> -bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv);
> +bool intel_vgpu_has_full_ppgtt(struct drm_i915_private *dev_priv);
>
> static inline bool
> intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread* ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915: Mark up vGPU support for full-ppgtt
2019-03-14 22:38 [PATCH 1/5] drm/i915: Mark up vGPU support for full-ppgtt Chris Wilson
` (4 preceding siblings ...)
2019-03-14 22:55 ` [PATCH 1/5] drm/i915: Mark up vGPU support for full-ppgtt Rodrigo Vivi
@ 2019-03-14 23:18 ` Patchwork
2019-03-14 23:36 ` ✓ Fi.CI.BAT: success " Patchwork
2019-03-15 2:15 ` [PATCH 1/5] " Zhenyu Wang
7 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2019-03-14 23:18 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/5] drm/i915: Mark up vGPU support for full-ppgtt
URL : https://patchwork.freedesktop.org/series/58024/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Mark up vGPU support for full-ppgtt
Okay!
Commit: drm/i915: Record platform specific ppGTT size in intel_device_info
Okay!
Commit: drm/i915: Drop address size from ppgtt_type
-O:drivers/gpu/drm/i915/i915_drv.c:351:25: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3560:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3558:16: warning: expression using sizeof(void)
Commit: drm/i915/gtt: Rename i915_vm_is_48b to i915_vm_is_4lvl
-O:drivers/gpu/drm/i915/i915_gem_gtt.c:941:9: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/i915_gem_gtt.c:941:9: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_gem_gtt.c:936:9: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_gem_gtt.c:936:9: warning: expression using sizeof(void)
Commit: drm/i915/gtt: Refactor common ppgtt initialisation
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread* ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915: Mark up vGPU support for full-ppgtt
2019-03-14 22:38 [PATCH 1/5] drm/i915: Mark up vGPU support for full-ppgtt Chris Wilson
` (5 preceding siblings ...)
2019-03-14 23:18 ` ✗ Fi.CI.SPARSE: warning for series starting with [1/5] " Patchwork
@ 2019-03-14 23:36 ` Patchwork
2019-03-15 2:15 ` [PATCH 1/5] " Zhenyu Wang
7 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2019-03-14 23:36 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/5] drm/i915: Mark up vGPU support for full-ppgtt
URL : https://patchwork.freedesktop.org/series/58024/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5750 -> Patchwork_12468
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/58024/revisions/1/mbox/
Known issues
------------
Here are the changes found in Patchwork_12468 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-gfx:
- fi-skl-6700k2: NOTRUN -> SKIP [fdo#109271] +41
* igt@amdgpu/amd_basic@cs-multi-fence:
- fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +27
* igt@amdgpu/amd_basic@cs-sdma:
- fi-cfl-8109u: NOTRUN -> SKIP [fdo#109271] +37
* igt@amdgpu/amd_basic@userptr:
- fi-kbl-8809g: PASS -> DMESG-WARN [fdo#108965]
* igt@gem_ctx_param@basic:
- fi-gdg-551: NOTRUN -> SKIP [fdo#109271] +106
* igt@gem_exec_basic@gtt-bsd1:
- fi-bxt-j4205: NOTRUN -> SKIP [fdo#109271] +47
* igt@gem_exec_basic@gtt-bsd2:
- fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] +57
* igt@gem_exec_basic@readonly-bsd:
- fi-pnv-d510: NOTRUN -> SKIP [fdo#109271] +76
* igt@gem_workarounds@basic-read:
- fi-snb-2600: NOTRUN -> SKIP [fdo#109271] +57
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720]
* igt@kms_busy@basic-flip-c:
- fi-gdg-551: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
- fi-pnv-d510: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
- fi-snb-2600: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
- fi-byt-n2820: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
- fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_chamelium@dp-edid-read:
- fi-byt-n2820: NOTRUN -> SKIP [fdo#109271] +56
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: NOTRUN -> FAIL [fdo#103167]
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- fi-byt-clapper: NOTRUN -> FAIL [fdo#103191] / [fdo#107362]
* igt@kms_pipe_crc_basic@read-crc-pipe-b:
- fi-byt-clapper: NOTRUN -> FAIL [fdo#107362]
* igt@runner@aborted:
- fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720]
- fi-bxt-dsi: NOTRUN -> FAIL [fdo#109516]
#### Possible fixes ####
* igt@gem_flink_basic@bad-flink:
- fi-icl-u2: DMESG-WARN [fdo#109638] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109516]: https://bugs.freedesktop.org/show_bug.cgi?id=109516
[fdo#109638]: https://bugs.freedesktop.org/show_bug.cgi?id=109638
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
[fdo#110028]: https://bugs.freedesktop.org/show_bug.cgi?id=110028
Participating hosts (35 -> 36)
------------------------------
Additional (10): fi-bxt-dsi fi-bxt-j4205 fi-gdg-551 fi-cfl-8109u fi-pnv-d510 fi-icl-y fi-byt-n2820 fi-byt-clapper fi-skl-6700k2 fi-snb-2600
Missing (9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-hsw-peppy fi-byt-squawks fi-bwr-2160 fi-bsw-kefka fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_5750 -> Patchwork_12468
CI_DRM_5750: 2b6425f8c26cb2578d408f7c21e7ac92f83c0b4a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4886: de53202ae4b5747b86ccda22986dbeb47f65d732 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12468: c12426eb8231d3424cc51ee9f064fd5ce60538bc @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c12426eb8231 drm/i915/gtt: Refactor common ppgtt initialisation
d7c9908ec6fb drm/i915/gtt: Rename i915_vm_is_48b to i915_vm_is_4lvl
76a8f860dec0 drm/i915: Drop address size from ppgtt_type
98ccff46e2b1 drm/i915: Record platform specific ppGTT size in intel_device_info
6552b225a13b drm/i915: Mark up vGPU support for full-ppgtt
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12468/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 1/5] drm/i915: Mark up vGPU support for full-ppgtt
2019-03-14 22:38 [PATCH 1/5] drm/i915: Mark up vGPU support for full-ppgtt Chris Wilson
` (6 preceding siblings ...)
2019-03-14 23:36 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-03-15 2:15 ` Zhenyu Wang
7 siblings, 0 replies; 19+ messages in thread
From: Zhenyu Wang @ 2019-03-15 2:15 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
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On 2019.03.14 22:38:35 +0000, Chris Wilson wrote:
> For compatibility reasons, we only care if the vGPU host provides
> support for full-ppgtt. This is independent of the addressable memory
> size, so remove the conflation of 48b from the capability name.
>
> Based on a patch by Bob Paauwe <bob.j.paauwe@intel.com>
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Bob Paauwe <bob.j.paauwe@intel.com>
> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> Cc: Zhi Wang <zhi.a.wang@intel.com>
> ---
> drivers/gpu/drm/i915/gvt/vgpu.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> drivers/gpu/drm/i915/i915_pvinfo.h | 2 +-
> drivers/gpu/drm/i915/i915_vgpu.c | 4 ++--
> drivers/gpu/drm/i915/i915_vgpu.h | 2 +-
> 5 files changed, 6 insertions(+), 6 deletions(-)
>
Looks good to me.
Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
> diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
> index 720e2b10adaa..314e40121e47 100644
> --- a/drivers/gpu/drm/i915/gvt/vgpu.c
> +++ b/drivers/gpu/drm/i915/gvt/vgpu.c
> @@ -44,7 +44,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
> vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
> vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
>
> - vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
> + vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_PPGTT;
> vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
> vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 0d743907e7bc..ad695cdc0487 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1494,7 +1494,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
>
> if (HAS_PPGTT(dev_priv)) {
> if (intel_vgpu_active(dev_priv) &&
> - !intel_vgpu_has_full_48bit_ppgtt(dev_priv)) {
> + !intel_vgpu_has_full_ppgtt(dev_priv)) {
> i915_report_error(dev_priv,
> "incompatible vGPU found, support for isolated ppGTT required\n");
> return -ENXIO;
> diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
> index eeaa3d506d95..969e514916ab 100644
> --- a/drivers/gpu/drm/i915/i915_pvinfo.h
> +++ b/drivers/gpu/drm/i915/i915_pvinfo.h
> @@ -52,7 +52,7 @@ enum vgt_g2v_type {
> /*
> * VGT capabilities type
> */
> -#define VGT_CAPS_FULL_48BIT_PPGTT BIT(2)
> +#define VGT_CAPS_FULL_PPGTT BIT(2)
> #define VGT_CAPS_HWSP_EMULATION BIT(3)
> #define VGT_CAPS_HUGE_GTT BIT(4)
>
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
> index 869cf4a3b6de..3b2d83f704e3 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.c
> +++ b/drivers/gpu/drm/i915/i915_vgpu.c
> @@ -81,9 +81,9 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
> DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
> }
>
> -bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv)
> +bool intel_vgpu_has_full_ppgtt(struct drm_i915_private *dev_priv)
> {
> - return dev_priv->vgpu.caps & VGT_CAPS_FULL_48BIT_PPGTT;
> + return dev_priv->vgpu.caps & VGT_CAPS_FULL_PPGTT;
> }
>
> struct _balloon_info_ {
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
> index 551acc390046..ebe1b7bced98 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.h
> +++ b/drivers/gpu/drm/i915/i915_vgpu.h
> @@ -28,7 +28,7 @@
>
> void i915_check_vgpu(struct drm_i915_private *dev_priv);
>
> -bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv);
> +bool intel_vgpu_has_full_ppgtt(struct drm_i915_private *dev_priv);
>
> static inline bool
> intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)
> --
> 2.20.1
>
--
Open Source Technology Center, Intel ltd.
$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827
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_______________________________________________
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^ permalink raw reply [flat|nested] 19+ messages in thread