* [U-Boot] [PATCH v12 0/9] Add support for loading FPGA bitstream
@ 2019-03-19 8:50 tien.fong.chee at intel.com
2019-03-19 8:50 ` [U-Boot] [PATCH v12 1/9] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10 tien.fong.chee at intel.com
` (9 more replies)
0 siblings, 10 replies; 27+ messages in thread
From: tien.fong.chee at intel.com @ 2019-03-19 8:50 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
This version mainly resolved comments from Dinh in [v11].
This series is working on top of u-boot.git http://git.denx.de/u-boot.git
These patches are required before applying this series of patches
1. [U-Boot,v4] misc: fs_loader: Add support for initializing block device
https://patchwork.ozlabs.org/project/uboot/list/?series=89282 (done review)
2. [U-Boot] fpga: Replace char * with const char * for filename
https://patchwork.ozlabs.org/patch/1042665/ (done review)
3. [U-Boot] misc: fs_loader: Replace label with DT phandle
https://patchwork.ozlabs.org/patch/1051782/ (under review)
[v11]: https://www.mail-archive.com/u-boot at lists.denx.de/msg318174.html
[v10]: https://www.mail-archive.com/u-boot at lists.denx.de/msg318167.html
[v9]: https://www.mail-archive.com/u-boot at lists.denx.de/msg316086.html
[v8]: https://www.mail-archive.com/u-boot at lists.denx.de/msg316086.html
[v7]: https://www.mail-archive.com/u-boot at lists.denx.de/msg314511.html
Tien Fong Chee (9):
ARM: socfpga: Description on FPGA bitstream type and file name for
Arria 10
ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK
ARM: socfpga: Cleaning up and ensuring consistent format messages in
driver
ARM: socfpga: Moving the watchdog reset to the for-loop status polling
ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK
spl : socfpga: Implement fpga bitstream loading with socfpga loadfs
ARM: socfpga: Synchronize the configuration for A10 SoCDK
ARM: socfpga: Increase Malloc pool size to support FAT filesystem in
SPL
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +
.../include/mach/fpga_manager_arria10.h | 40 +-
arch/arm/mach-socfpga/spl_a10.c | 31 +-
board/altera/arria10-socdk/fit_spl_fpga.its | 38 ++
configs/socfpga_arria10_defconfig | 22 +-
.../fpga/altera-socfpga-a10-fpga-mgr.txt | 26 +-
drivers/fpga/socfpga_arria10.c | 514 ++++++++++++++++++++-
include/configs/socfpga_common.h | 4 +-
include/image.h | 4 +
9 files changed, 664 insertions(+), 32 deletions(-)
create mode 100644 board/altera/arria10-socdk/fit_spl_fpga.its
--
2.13.0
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v12 1/9] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10
2019-03-19 8:50 [U-Boot] [PATCH v12 0/9] Add support for loading FPGA bitstream tien.fong.chee at intel.com
@ 2019-03-19 8:50 ` tien.fong.chee at intel.com
2019-03-19 8:50 ` [U-Boot] [PATCH v12 2/9] ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK tien.fong.chee at intel.com
` (8 subsequent siblings)
9 siblings, 0 replies; 27+ messages in thread
From: tien.fong.chee at intel.com @ 2019-03-19 8:50 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
This patch adds description on properties about file name used for both
peripheral bitstream and core bitstream.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
changes for v12
- No changes.
changes for v11
- No changes.
changes for v10
- No changes.
changes for v9
- No changes.
changes for v8
- Removed explanation about support for altr,bitstream-core
changes for v7
- Provided example of setting FPGA FIT image for both early IO release
and full release FPGA configuration.
---
.../fpga/altera-socfpga-a10-fpga-mgr.txt | 26 +++++++++++++++++++++-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
index 2fd8e7a847..da210bfc86 100644
--- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
+++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
@@ -7,8 +7,31 @@ Required properties:
- The second index is for writing FPGA configuration data.
- resets : Phandle and reset specifier for the device's reset.
- clocks : Clocks used by the device.
+- altr,bitstream : Fit image file name for both FPGA peripheral bitstream,
+ FPGA core bitstream and full bitstream.
-Example:
+ Full bitstream, consist of peripheral bitstream and core
+ bitstream.
+
+ FPGA peripheral bitstream is used to initialize FPGA IOs,
+ PLL, IO48 and DDR. This bitstream is required to get DDR up
+ running.
+
+ FPGA core bitstream contains FPGA design which is used to
+ program FPGA CRAM and ERAM.
+
+Example: Bundles both peripheral bitstream and core bitstream into FIT image
+ called fit_spl_fpga.itb. This FIT image can be created through running
+ this command: tools/mkimage
+ -E -p 400
+ -f board/altera/arria10-socdk/fit_spl_fpga.its
+ fit_spl_fpga.itb
+
+ For details of describing structure and contents of the FIT image,
+ please refer board/altera/arria10-socdk/fit_spl_fpga.its
+
+- Examples for booting with full release or booting with early IO release, then
+ follow by entering early user mode:
fpga_mgr: fpga-mgr at ffd03000 {
compatible = "altr,socfpga-a10-fpga-mgr";
@@ -16,4 +39,5 @@ Example:
0xffcfe400 0x20>;
clocks = <&l4_mp_clk>;
resets = <&rst FPGAMGR_RESET>;
+ altr,bitstream = "fit_spl_fpga.itb";
};
--
2.13.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v12 2/9] ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK
2019-03-19 8:50 [U-Boot] [PATCH v12 0/9] Add support for loading FPGA bitstream tien.fong.chee at intel.com
2019-03-19 8:50 ` [U-Boot] [PATCH v12 1/9] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10 tien.fong.chee at intel.com
@ 2019-03-19 8:50 ` tien.fong.chee at intel.com
2019-03-19 8:50 ` [U-Boot] [PATCH v12 3/9] ARM: socfpga: Cleaning up and ensuring consistent format messages in driver tien.fong.chee at intel.com
` (7 subsequent siblings)
9 siblings, 0 replies; 27+ messages in thread
From: tien.fong.chee at intel.com @ 2019-03-19 8:50 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Add default fitImage file bundling FPGA bitstreams for Arria10.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
changes for v12
- No changes.
changes for v11
- Replaced core image node "-2" with "-1",
the numeric associates the core and periph images in case where there
are multiple.
changes for v10
- Replaced both image nodes "@1" and "@2" with "-1" and "-2" respectively.
changes for v9
- Reordered the images and fpga configurations.
- Removed the load property at core image.
changes for v8
- Changed the FPGA node name to fpga-core and fpga-periph for both core and
periph bitstreams respectively.
changes for v7
- No changes.
---
board/altera/arria10-socdk/fit_spl_fpga.its | 38 +++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
create mode 100644 board/altera/arria10-socdk/fit_spl_fpga.its
diff --git a/board/altera/arria10-socdk/fit_spl_fpga.its b/board/altera/arria10-socdk/fit_spl_fpga.its
new file mode 100644
index 0000000000..adae997213
--- /dev/null
+++ b/board/altera/arria10-socdk/fit_spl_fpga.its
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0
+ /*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+/dts-v1/;
+
+/ {
+ description = "FIT image with FPGA bistream";
+ #address-cells = <1>;
+
+ images {
+ fpga-periph-1 {
+ description = "FPGA peripheral bitstream";
+ data = /incbin/("../../../ghrd_10as066n2.periph.rbf");
+ type = "fpga";
+ arch = "arm";
+ compression = "none";
+ };
+
+ fpga-core-1 {
+ description = "FPGA core bitstream";
+ data = /incbin/("../../../ghrd_10as066n2.core.rbf");
+ type = "fpga";
+ arch = "arm";
+ compression = "none";
+ };
+ };
+
+ configurations {
+ default = "config-1";
+ config-1 {
+ description = "Boot with FPGA early IO release config";
+ fpga = "fpga-periph-1", "fpga-core-1";
+ };
+ };
+};
--
2.13.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v12 3/9] ARM: socfpga: Cleaning up and ensuring consistent format messages in driver
2019-03-19 8:50 [U-Boot] [PATCH v12 0/9] Add support for loading FPGA bitstream tien.fong.chee at intel.com
2019-03-19 8:50 ` [U-Boot] [PATCH v12 1/9] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10 tien.fong.chee at intel.com
2019-03-19 8:50 ` [U-Boot] [PATCH v12 2/9] ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK tien.fong.chee at intel.com
@ 2019-03-19 8:50 ` tien.fong.chee at intel.com
2019-03-19 8:50 ` [U-Boot] [PATCH v12 4/9] ARM: socfpga: Moving the watchdog reset to the for-loop status polling tien.fong.chee at intel.com
` (6 subsequent siblings)
9 siblings, 0 replies; 27+ messages in thread
From: tien.fong.chee at intel.com @ 2019-03-19 8:50 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Ensure all the debug messages are always prefix with "FPGA: " and comment
beginning with uppercase letter.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
changes for v12
- Improved the commit messages.
changes for v11
- No changes.
changes for v10
- This patch was split out from [PATCH v10 5/9]
ARM: socfpga: Add FPGA drivers for Arria 10 FPGA.
---
drivers/fpga/socfpga_arria10.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 114dd910ab..b0abe1955c 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -94,7 +94,7 @@ int fpgamgr_wait_early_user_mode(void)
i++;
}
- debug("Additional %i sync word needed\n", i);
+ debug("FPGA: Additional %i sync word needed\n", i);
/* restoring original CDRATIO */
fpgamgr_set_cd_ratio(cd_ratio);
@@ -172,9 +172,10 @@ static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,
compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
compress = !compress;
- debug("header word %d = %08x\n", 69, rbf_data[69]);
- debug("header word %d = %08x\n", 229, rbf_data[229]);
- debug("read from rbf header: encrypt=%d compress=%d\n", encrypt, compress);
+ debug("FPGA: Header word %d = %08x.\n", 69, rbf_data[69]);
+ debug("FPGA: Header word %d = %08x.\n", 229, rbf_data[229]);
+ debug("FPGA: Read from rbf header: encrypt=%d compress=%d.\n", encrypt,
+ compress);
/*
* from the register map description of cdratio in imgcfg_ctrl_02:
@@ -455,10 +456,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
{
int status;
- /* disable all signals from hps peripheral controller to fpga */
+ /* Disable all signals from hps peripheral controller to fpga */
writel(0, &system_manager_base->fpgaintf_en_global);
- /* disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
+ /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
socfpga_bridges_reset();
/* Initialize the FPGA Manager */
--
2.13.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v12 4/9] ARM: socfpga: Moving the watchdog reset to the for-loop status polling
2019-03-19 8:50 [U-Boot] [PATCH v12 0/9] Add support for loading FPGA bitstream tien.fong.chee at intel.com
` (2 preceding siblings ...)
2019-03-19 8:50 ` [U-Boot] [PATCH v12 3/9] ARM: socfpga: Cleaning up and ensuring consistent format messages in driver tien.fong.chee at intel.com
@ 2019-03-19 8:50 ` tien.fong.chee at intel.com
2019-04-27 19:34 ` Simon Goldschmidt
2019-03-19 8:50 ` [U-Boot] [PATCH v12 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading tien.fong.chee at intel.com
` (5 subsequent siblings)
9 siblings, 1 reply; 27+ messages in thread
From: tien.fong.chee at intel.com @ 2019-03-19 8:50 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Ensure the watchdog is reset timely on each status polling.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
changes for v12
- Improved the commit messages.
changes for v11
- No changes.
changes for v10
- This patch was split out from [PATCH v10 5/9]
ARM: socfpga: Add FPGA drivers for Arria 10 FPGA.
---
drivers/fpga/socfpga_arria10.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index b0abe1955c..9499d1a014 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -360,6 +360,7 @@ static int fpgamgr_program_poll_cd(void)
printf("nstatus == 0 while waiting for condone\n");
return -EPERM;
}
+ WATCHDOG_RESET();
}
if (i == FPGA_TIMEOUT_CNT)
@@ -433,7 +434,6 @@ int fpgamgr_program_finish(void)
printf("FPGA: Poll CD failed with error code %d\n", status);
return -EPERM;
}
- WATCHDOG_RESET();
/* Ensure the FPGA entering user mode */
status = fpgamgr_program_poll_usermode();
--
2.13.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v12 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
2019-03-19 8:50 [U-Boot] [PATCH v12 0/9] Add support for loading FPGA bitstream tien.fong.chee at intel.com
` (3 preceding siblings ...)
2019-03-19 8:50 ` [U-Boot] [PATCH v12 4/9] ARM: socfpga: Moving the watchdog reset to the for-loop status polling tien.fong.chee at intel.com
@ 2019-03-19 8:50 ` tien.fong.chee at intel.com
2019-04-27 19:57 ` Simon Goldschmidt
2019-03-19 8:50 ` [U-Boot] [PATCH v12 6/9] ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK tien.fong.chee at intel.com
` (4 subsequent siblings)
9 siblings, 1 reply; 27+ messages in thread
From: tien.fong.chee at intel.com @ 2019-03-19 8:50 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Add FPGA driver to support program FPGA with FPGA bitstream loading from
filesystem. The driver are designed based on generic firmware loader
framework. The driver can handle FPGA program operation from loading FPGA
bitstream in flash to memory and then to program FPGA.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
changes for v12
- No changes.
changes for v11
- No changes.
changes for v10
-Cleaned up the codes.
-Return -EPERM when programing core on non early IO release mode.
-Using live function to get rid of gd->
-Removed @0 for fs-loader node
changes for v9
- Support data offset
- Added default DDR load address
- Squashed the image.h
- Changed to phandle
- Ensure the DDR is fully up running by checking the gd->ram
changes for v8
- Added codes to discern bitstream type based on fpga node name.
changes for v7
- Restructure the FPGA driver to support both peripheral bitstream and core
bitstream bundled into FIT image.
- Support loadable property for core bitstream. User can set loadable
in DDR for better performance. This loading would be done in one large
chunk instead of chunk by chunk loading with small memory buffer.
---
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +
.../include/mach/fpga_manager_arria10.h | 39 +-
drivers/fpga/socfpga_arria10.c | 497 ++++++++++++++++++++-
include/image.h | 4 +
4 files changed, 542 insertions(+), 15 deletions(-)
diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
index 998d811210..cc761967c7 100644
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
@@ -18,6 +18,23 @@
/dts-v1/;
#include "socfpga_arria10_socdk.dtsi"
+/ {
+ chosen {
+ firmware-loader = <&fs_loader0>;
+ };
+
+ fs_loader0: fs-loader {
+ u-boot,dm-pre-reloc;
+ compatible = "u-boot,fs-loader";
+ phandlepart = <&mmc 1>;
+ };
+};
+
+&fpga_mgr {
+ u-boot,dm-pre-reloc;
+ altr,bitstream = "fit_spl_fpga.itb";
+};
+
&mmc {
u-boot,dm-pre-reloc;
status = "okay";
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
index 09d13f6fd3..c5f67714aa 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
@@ -1,9 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
* All rights reserved.
*/
+#include <asm/cache.h>
+#include <altera.h>
+#include <image.h>
+
#ifndef _FPGA_MANAGER_ARRIA10_H_
#define _FPGA_MANAGER_ARRIA10_H_
@@ -51,6 +55,10 @@
#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24)
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16
+#define FPGA_SOCFPGA_A10_RBF_UNENCRYPTED 0xa65c
+#define FPGA_SOCFPGA_A10_RBF_ENCRYPTED 0xa65d
+#define FPGA_SOCFPGA_A10_RBF_PERIPH 0x0001
+#define FPGA_SOCFPGA_A10_RBF_CORE 0x8001
#ifndef __ASSEMBLY__
struct socfpga_fpga_manager {
@@ -88,12 +96,39 @@ struct socfpga_fpga_manager {
u32 imgcfg_fifo_status;
};
+enum rbf_type {
+ unknown,
+ periph_section,
+ core_section
+};
+
+enum rbf_security {
+ invalid,
+ unencrypted,
+ encrypted
+};
+
+struct rbf_info {
+ enum rbf_type section;
+ enum rbf_security security;
+};
+
+struct fpga_loadfs_info {
+ fpga_fs_info *fpga_fsinfo;
+ u32 remaining;
+ u32 offset;
+ struct rbf_info rbfinfo;
+};
+
/* Functions */
int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
int fpgamgr_program_finish(void);
int is_fpgamgr_user_mode(void);
int fpgamgr_wait_early_user_mode(void);
-
+const char *get_fpga_filename(void);
+int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
+ u32 offset);
+void fpgamgr_program(const void *buf, size_t bsize, u32 offset);
#endif /* __ASSEMBLY__ */
#endif /* _FPGA_MANAGER_ARRIA10_H_ */
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 9499d1a014..9df2c430d7 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -1,8 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
*/
-
#include <asm/io.h>
#include <asm/arch/fpga_manager.h>
#include <asm/arch/reset_manager.h>
@@ -10,8 +9,11 @@
#include <asm/arch/sdram.h>
#include <asm/arch/misc.h>
#include <altera.h>
+#include <asm/arch/pinmux.h>
#include <common.h>
+#include <dm/ofnode.h>
#include <errno.h>
+#include <fs_loader.h>
#include <wait_bit.h>
#include <watchdog.h>
@@ -21,6 +23,9 @@
#define COMPRESSION_OFFSET 229
#define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
#define FPGA_TIMEOUT_CNT 0x1000000
+#define DEFAULT_DDR_LOAD_ADDRESS 0x400
+
+DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_fpga_manager *fpga_manager_base =
(void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
@@ -448,13 +453,461 @@ int fpgamgr_program_finish(void)
return 0;
}
-/*
- * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
- * Return 0 for sucess, non-zero for error.
- */
+ofnode get_fpga_mgr_ofnode(ofnode from)
+{
+ return ofnode_by_compatible(from, "altr,socfpga-a10-fpga-mgr");
+}
+
+const char *get_fpga_filename(void)
+{
+ const char *fpga_filename = NULL;
+
+ ofnode fpgamgr_node = get_fpga_mgr_ofnode(ofnode_null());
+
+ if (ofnode_valid(fpgamgr_node))
+ fpga_filename = ofnode_read_string(fpgamgr_node,
+ "altr,bitstream");
+
+ return fpga_filename;
+}
+
+static void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer)
+{
+ /*
+ * Magic ID starting at:
+ * -> 1st dword[15:0] in periph.rbf
+ * -> 2nd dword[15:0] in core.rbf
+ * Note: dword == 32 bits
+ */
+ u32 word_reading_max = 2;
+ u32 i;
+
+ for (i = 0; i < word_reading_max; i++) {
+ if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
+ rbf->security = unencrypted;
+ } else if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
+ rbf->security = encrypted;
+ } else if (*(buffer + i + 1) ==
+ FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
+ rbf->security = unencrypted;
+ } else if (*(buffer + i + 1) ==
+ FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
+ rbf->security = encrypted;
+ } else {
+ rbf->security = invalid;
+ continue;
+ }
+
+ /* PERIPH RBF(buffer + i + 1), CORE RBF(buffer + i + 2) */
+ if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
+ rbf->section = periph_section;
+ break;
+ } else if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_CORE) {
+ rbf->section = core_section;
+ break;
+ } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
+ rbf->section = periph_section;
+ break;
+ } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_CORE) {
+ rbf->section = core_section;
+ break;
+ }
+
+ rbf->section = unknown;
+ break;
+
+ WATCHDOG_RESET();
+ }
+}
+
+#ifdef CONFIG_FS_LOADER
+static int first_loading_rbf_to_buffer(struct udevice *dev,
+ struct fpga_loadfs_info *fpga_loadfs,
+ u32 *buffer, size_t *buffer_bsize)
+{
+ u32 *buffer_p = (u32 *)*buffer;
+ u32 *loadable = buffer_p;
+ size_t buffer_size = *buffer_bsize;
+ size_t fit_size;
+ int ret, i, count, confs_noffset, images_noffset, rbf_offset, rbf_size;
+ const char *fpga_node_name = NULL;
+ const char *uname = NULL;
+
+ /* Load image header into buffer */
+ ret = request_firmware_into_buf(dev,
+ fpga_loadfs->fpga_fsinfo->filename,
+ buffer_p, sizeof(struct image_header),
+ 0);
+ if (ret < 0) {
+ debug("FPGA: Failed to read image header from flash.\n");
+ return -ENOENT;
+ }
+
+ if (image_get_magic((struct image_header *)buffer_p) != FDT_MAGIC) {
+ debug("FPGA: No FDT magic was found.\n");
+ return -EBADF;
+ }
+
+ fit_size = fdt_totalsize(buffer_p);
+
+ if (fit_size > buffer_size) {
+ debug("FPGA: FIT image is larger than available buffer.\n");
+ debug("Please use FIT external data or increasing buffer.\n");
+ return -ENOMEM;
+ }
+
+ /* Load entire FIT into buffer */
+ ret = request_firmware_into_buf(dev,
+ fpga_loadfs->fpga_fsinfo->filename,
+ buffer_p, fit_size, 0);
+ if (ret < 0)
+ return ret;
+
+ ret = fit_check_format(buffer_p);
+ if (!ret) {
+ debug("FPGA: No valid FIT image was found.\n");
+ return -EBADF;
+ }
+
+ confs_noffset = fdt_path_offset(buffer_p, FIT_CONFS_PATH);
+ images_noffset = fdt_path_offset(buffer_p, FIT_IMAGES_PATH);
+ if (confs_noffset < 0 || images_noffset < 0) {
+ debug("FPGA: No Configurations or images nodes were found.\n");
+ return -ENOENT;
+ }
+
+ /* Get default configuration unit name from default property */
+ confs_noffset = fit_conf_get_node(buffer_p, NULL);
+ if (confs_noffset < 0) {
+ debug("FPGA: No default configuration was found in config.\n");
+ return -ENOENT;
+ }
+
+ count = fit_conf_get_prop_node_count(buffer_p, confs_noffset,
+ FIT_FPGA_PROP);
+ if (count < 0) {
+ debug("FPGA: Invalid configuration format for FPGA node.\n");
+ return count;
+ }
+ debug("FPGA: FPGA node count: %d\n", count);
+
+ for (i = 0; i < count; i++) {
+ images_noffset = fit_conf_get_prop_node_index(buffer_p,
+ confs_noffset,
+ FIT_FPGA_PROP, i);
+ uname = fit_get_name(buffer_p, images_noffset, NULL);
+ if (uname) {
+ debug("FPGA: %s\n", uname);
+
+ if (strstr(uname, "fpga-periph") &&
+ (!is_fpgamgr_early_user_mode() ||
+ is_fpgamgr_user_mode())) {
+ fpga_node_name = uname;
+ printf("FPGA: Start to program ");
+ printf("peripheral/full bitstream ...\n");
+ break;
+ } else if (strstr(uname, "fpga-core") &&
+ (is_fpgamgr_early_user_mode() &&
+ !is_fpgamgr_user_mode())) {
+ fpga_node_name = uname;
+ printf("FPGA: Start to program core ");
+ printf("bitstream ...\n");
+ break;
+ }
+ }
+ WATCHDOG_RESET();
+ }
+
+ if (!fpga_node_name) {
+ debug("FPGA: No suitable bitstream was found, count: %d.\n", i);
+ return 1;
+ }
+
+ images_noffset = fit_image_get_node(buffer_p, fpga_node_name);
+ if (images_noffset < 0) {
+ debug("FPGA: No node '%s' was found in FIT.\n",
+ fpga_node_name);
+ return -ENOENT;
+ }
+
+ if (!fit_image_get_data_position(buffer_p, images_noffset,
+ &rbf_offset)) {
+ debug("FPGA: Data position was found.\n");
+ } else if (!fit_image_get_data_offset(buffer_p, images_noffset,
+ &rbf_offset)) {
+ /*
+ * For FIT with external data, figure out where
+ * the external images start. This is the base
+ * for the data-offset properties in each image.
+ */
+ rbf_offset += ((fdt_totalsize(buffer_p) + 3) & ~3);
+ debug("FPGA: Data offset was found.\n");
+ } else {
+ debug("FPGA: No data position/offset was found.\n");
+ return -ENOENT;
+ }
+
+ ret = fit_image_get_data_size(buffer_p, images_noffset, &rbf_size);
+ if (ret < 0) {
+ debug("FPGA: No data size was found (err=%d).\n", ret);
+ return -ENOENT;
+ }
+
+ if (gd->ram_size < rbf_size) {
+ debug("FPGA: Using default OCRAM buffer and size.\n");
+ } else {
+ ret = fit_image_get_load(buffer_p, images_noffset,
+ (ulong *)loadable);
+ if (ret < 0) {
+ buffer_p = (u32 *)DEFAULT_DDR_LOAD_ADDRESS;
+ debug("FPGA: No loadable was found.\n");
+ debug("FPGA: Using default DDR load address: 0x%x .\n",
+ DEFAULT_DDR_LOAD_ADDRESS);
+ } else {
+ buffer_p = (u32 *)*loadable;
+ debug("FPGA: Found loadable address = 0x%x.\n",
+ *loadable);
+ }
+
+ buffer_size = rbf_size;
+ }
+
+ debug("FPGA: External data: offset = 0x%x, size = 0x%x.\n",
+ rbf_offset, rbf_size);
+
+ fpga_loadfs->remaining = rbf_size;
+
+ /*
+ * Determine buffer size vs bitstream size, and calculating number of
+ * chunk by chunk transfer is required due to smaller buffer size
+ * compare to bitstream
+ */
+ if (rbf_size <= buffer_size) {
+ /* Loading whole bitstream into buffer */
+ buffer_size = rbf_size;
+ fpga_loadfs->remaining = 0;
+ } else {
+ fpga_loadfs->remaining -= buffer_size;
+ }
+
+ fpga_loadfs->offset = rbf_offset;
+ /* Loading bitstream into buffer */
+ ret = request_firmware_into_buf(dev,
+ fpga_loadfs->fpga_fsinfo->filename,
+ buffer_p, buffer_size,
+ fpga_loadfs->offset);
+ if (ret < 0) {
+ debug("FPGA: Failed to read bitstream from flash.\n");
+ return -ENOENT;
+ }
+
+ /* Getting info about bitstream types */
+ get_rbf_image_info(&fpga_loadfs->rbfinfo, (u16 *)buffer_p);
+
+ /* Update next reading bitstream offset */
+ fpga_loadfs->offset += buffer_size;
+
+ /* Update the final addr for bitstream */
+ *buffer = (u32)buffer_p;
+
+ /* Update the size of bitstream to be programmed into FPGA */
+ *buffer_bsize = buffer_size;
+
+ return 0;
+}
+
+static int subsequent_loading_rbf_to_buffer(struct udevice *dev,
+ struct fpga_loadfs_info *fpga_loadfs,
+ u32 *buffer, size_t *buffer_bsize)
+{
+ int ret = 0;
+ u32 *buffer_p = (u32 *)*buffer;
+
+ /* Read the bitstream chunk by chunk. */
+ if (fpga_loadfs->remaining > *buffer_bsize) {
+ fpga_loadfs->remaining -= *buffer_bsize;
+ } else {
+ *buffer_bsize = fpga_loadfs->remaining;
+ fpga_loadfs->remaining = 0;
+ }
+
+ ret = request_firmware_into_buf(dev,
+ fpga_loadfs->fpga_fsinfo->filename,
+ buffer_p, *buffer_bsize,
+ fpga_loadfs->offset);
+ if (ret < 0) {
+ debug("FPGA: Failed to read bitstream from flash.\n");
+ return -ENOENT;
+ }
+
+ /* Update next reading bitstream offset */
+ fpga_loadfs->offset += *buffer_bsize;
+
+ return 0;
+}
+
+int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
+ u32 offset)
+{
+ struct fpga_loadfs_info fpga_loadfs;
+ struct udevice *dev;
+ int status, ret, size;
+ u32 buffer = (uintptr_t)buf;
+ size_t buffer_sizebytes = bsize;
+ size_t buffer_sizebytes_ori = bsize;
+ size_t total_sizeof_image = 0;
+ ofnode node;
+ const fdt32_t *phandle_p;
+ u32 phandle;
+
+ node = get_fpga_mgr_ofnode(ofnode_null());
+
+ if (ofnode_valid(node)) {
+ phandle_p = ofnode_get_property(node, "firmware-loader", &size);
+ if (!phandle_p) {
+ node = ofnode_path("/chosen");
+ if (!ofnode_valid(node)) {
+ debug("FPGA: /chosen node was not found.\n");
+ return -ENOENT;
+ }
+
+ phandle_p = ofnode_get_property(node, "firmware-loader",
+ &size);
+ if (!phandle_p) {
+ debug("FPGA: firmware-loader property was not");
+ debug(" found.\n");
+ return -ENOENT;
+ }
+ }
+ } else {
+ debug("FPGA: FPGA manager node was not found.\n");
+ return -ENOENT;
+ }
+
+ phandle = fdt32_to_cpu(*phandle_p);
+ ret = uclass_get_device_by_phandle_id(UCLASS_FS_FIRMWARE_LOADER,
+ phandle, &dev);
+ if (ret)
+ return ret;
+
+ memset(&fpga_loadfs, 0, sizeof(fpga_loadfs));
+
+ fpga_loadfs.fpga_fsinfo = fpga_fsinfo;
+ fpga_loadfs.offset = offset;
+
+ printf("FPGA: Checking FPGA configuration setting ...\n");
+
+ /*
+ * Note: Both buffer and buffer_sizebytes values can be altered by
+ * function below.
+ */
+ ret = first_loading_rbf_to_buffer(dev, &fpga_loadfs, &buffer,
+ &buffer_sizebytes);
+ if (ret == 1) {
+ printf("FPGA: Skipping configuration ...\n");
+ return 0;
+ } else if (ret) {
+ return ret;
+ }
+
+ if (fpga_loadfs.rbfinfo.section == core_section &&
+ !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
+ debug("FPGA : Must be in Early Release mode to program ");
+ debug("core bitstream.\n");
+ return -EPERM;
+ }
+
+ /* Disable all signals from HPS peripheral controller to FPGA */
+ writel(0, &system_manager_base->fpgaintf_en_global);
+
+ /* Disable all axi bridges (hps2fpga, lwhps2fpga & fpga2hps) */
+ socfpga_bridges_reset();
+
+ if (fpga_loadfs.rbfinfo.section == periph_section) {
+ /* Initialize the FPGA Manager */
+ status = fpgamgr_program_init((u32 *)buffer, buffer_sizebytes);
+ if (status) {
+ debug("FPGA: Init with peripheral bitstream failed.\n");
+ return -EPERM;
+ }
+ }
+
+ /* Transfer bitstream to FPGA Manager */
+ fpgamgr_program_write((void *)buffer, buffer_sizebytes);
+
+ total_sizeof_image += buffer_sizebytes;
+
+ while (fpga_loadfs.remaining) {
+ ret = subsequent_loading_rbf_to_buffer(dev,
+ &fpga_loadfs,
+ &buffer,
+ &buffer_sizebytes_ori);
+
+ if (ret)
+ return ret;
+
+ /* Transfer data to FPGA Manager */
+ fpgamgr_program_write((void *)buffer,
+ buffer_sizebytes_ori);
+
+ total_sizeof_image += buffer_sizebytes_ori;
+
+ WATCHDOG_RESET();
+ }
+
+ if (fpga_loadfs.rbfinfo.section == periph_section) {
+ if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT) {
+ config_pins(gd->fdt_blob, "shared");
+ puts("FPGA: Early Release Succeeded.\n");
+ } else {
+ debug("FPGA: Failed to see Early Release.\n");
+ return -EIO;
+ }
+
+ /* For monolithic bitstream */
+ if (is_fpgamgr_user_mode()) {
+ /* Ensure the FPGA entering config done */
+ status = fpgamgr_program_finish();
+ if (status)
+ return status;
+
+ config_pins(gd->fdt_blob, "fpga");
+ puts("FPGA: Enter user mode.\n");
+ }
+ } else if (fpga_loadfs.rbfinfo.section == core_section) {
+ /* Ensure the FPGA entering config done */
+ status = fpgamgr_program_finish();
+ if (status)
+ return status;
+
+ config_pins(gd->fdt_blob, "fpga");
+ puts("FPGA: Enter user mode.\n");
+ } else {
+ debug("FPGA: Config Error: Unsupported bitstream type.\n");
+ return -ENOEXEC;
+ }
+
+ return (int)total_sizeof_image;
+}
+
+void fpgamgr_program(const void *buf, size_t bsize, u32 offset)
+{
+ fpga_fs_info fpga_fsinfo;
+
+ fpga_fsinfo.filename = get_fpga_filename();
+
+ if (fpga_fsinfo.filename)
+ socfpga_loadfs(&fpga_fsinfo, buf, bsize, offset);
+}
+#endif
+
+/* This function is used to load the core bitstream from the OCRAM. */
int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
{
- int status;
+ unsigned long status;
+ struct rbf_info rbfinfo;
+
+ memset(&rbfinfo, 0, sizeof(rbfinfo));
/* Disable all signals from hps peripheral controller to fpga */
writel(0, &system_manager_base->fpgaintf_en_global);
@@ -462,13 +915,31 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
/* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
socfpga_bridges_reset();
- /* Initialize the FPGA Manager */
- status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
- if (status)
- return status;
+ /* Getting info about bitstream types */
+ get_rbf_image_info(&rbfinfo, (u16 *)rbf_data);
+
+ if (rbfinfo.section == periph_section) {
+ /* Initialize the FPGA Manager */
+ status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
+ if (status)
+ return status;
+ }
- /* Write the RBF data to FPGA Manager */
+ if (rbfinfo.section == core_section &&
+ !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
+ debug("FPGA : Must be in early release mode to program ");
+ debug("core bitstream.\n");
+ return -EPERM;
+ }
+
+ /* Write the bitstream to FPGA Manager */
fpgamgr_program_write(rbf_data, rbf_size);
- return fpgamgr_program_finish();
+ status = fpgamgr_program_finish();
+ if (status) {
+ config_pins(gd->fdt_blob, "fpga");
+ puts("FPGA: Enter user mode.\n");
+ }
+
+ return status;
}
diff --git a/include/image.h b/include/image.h
index 765ffecee0..cc976f70ce 100644
--- a/include/image.h
+++ b/include/image.h
@@ -1046,6 +1046,10 @@ int fit_check_format(const void *fit);
int fit_conf_find_compat(const void *fit, const void *fdt);
int fit_conf_get_node(const void *fit, const char *conf_uname);
+int fit_conf_get_prop_node_count(const void *fit, int noffset,
+ const char *prop_name);
+int fit_conf_get_prop_node_index(const void *fit, int noffset,
+ const char *prop_name, int index);
/**
* fit_conf_get_prop_node() - Get node refered to by a configuration
--
2.13.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v12 6/9] ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK
2019-03-19 8:50 [U-Boot] [PATCH v12 0/9] Add support for loading FPGA bitstream tien.fong.chee at intel.com
` (4 preceding siblings ...)
2019-03-19 8:50 ` [U-Boot] [PATCH v12 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading tien.fong.chee at intel.com
@ 2019-03-19 8:50 ` tien.fong.chee at intel.com
2019-03-19 8:50 ` [U-Boot] [PATCH v12 7/9] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs tien.fong.chee at intel.com
` (3 subsequent siblings)
9 siblings, 0 replies; 27+ messages in thread
From: tien.fong.chee at intel.com @ 2019-03-19 8:50 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Update the default configuration file to enable the necessary functionality
to get the SoCFPGA loadfs driver support. This would enable the
implementation of programming bitstream into FPGA from MMC.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
changes for v12
- No changes.
changes for v11
- No changes.
changes for v10
- No changes.
changes for v9
- No changes.
changes for v8
- Added FIT related configs
changes for v7
- Removed limit set for CONFIG_FS_FAT_MAX_CLUSTSIZE
---
configs/socfpga_arria10_defconfig | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
index f321a0ac3b..192cf7e05f 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -28,9 +28,18 @@ CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
# CONFIG_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_DM_MMC=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_FS_LOADER=y
CONFIG_FPGA_SOCFPGA=y
+CONFIG_SPL_FIT=y
+CONFIG_FIT=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_MMC=y
--
2.13.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v12 7/9] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs
2019-03-19 8:50 [U-Boot] [PATCH v12 0/9] Add support for loading FPGA bitstream tien.fong.chee at intel.com
` (5 preceding siblings ...)
2019-03-19 8:50 ` [U-Boot] [PATCH v12 6/9] ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK tien.fong.chee at intel.com
@ 2019-03-19 8:50 ` tien.fong.chee at intel.com
2019-03-19 8:50 ` [U-Boot] [PATCH v12 8/9] ARM: socfpga: Synchronize the configuration for A10 SoCDK tien.fong.chee at intel.com
` (2 subsequent siblings)
9 siblings, 0 replies; 27+ messages in thread
From: tien.fong.chee at intel.com @ 2019-03-19 8:50 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Add support for loading FPGA bitstream to get DDR up running before
U-Boot is loaded into DDR. Boot device initialization, generic firmware
loader and SPL FAT support are required for this whole mechanism to work.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
changes for v12
- No changes.
changes for v11
- No changes.
changes for v10
- Removed the static so the function can be referred by other c file.
changes for v9
- Used ALLOC_CACHE_ALIGN_BUFFER
- De-duplicated the same chunks of codes
changes for v8
- No changes.
changes for v7
- Removed casting for get_fpga_filename
- Removed hard coding DDR address for loading core bistream, using loadable
property from FIT.
- Added checking for config_pins, return if error.
---
.../include/mach/fpga_manager_arria10.h | 1 +
arch/arm/mach-socfpga/spl_a10.c | 31 +++++++++++++++++++++-
drivers/fpga/socfpga_arria10.c | 2 +-
3 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
index c5f67714aa..62249b3695 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
@@ -126,6 +126,7 @@ int fpgamgr_program_finish(void);
int is_fpgamgr_user_mode(void);
int fpgamgr_wait_early_user_mode(void);
const char *get_fpga_filename(void);
+int is_fpgamgr_early_user_mode(void);
int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
u32 offset);
void fpgamgr_program(const void *buf, size_t bsize, u32 offset);
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index c8e73d47c0..b466307f98 100644
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
*/
#include <common.h>
@@ -23,6 +23,11 @@
#include <fdtdec.h>
#include <watchdog.h>
#include <asm/arch/pinmux.h>
+#include <asm/arch/fpga_manager.h>
+#include <mmc.h>
+#include <memalign.h>
+
+#define FPGA_BUFSIZ 16 * 1024
DECLARE_GLOBAL_DATA_PTR;
@@ -68,11 +73,35 @@ u32 spl_boot_mode(const u32 boot_device)
void spl_board_init(void)
{
+ ALLOC_CACHE_ALIGN_BUFFER(char, buf, FPGA_BUFSIZ);
+
/* enable console uart printing */
preloader_console_init();
WATCHDOG_RESET();
arch_early_init_r();
+
+ /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
+ if (is_fpgamgr_user_mode()) {
+ int ret = config_pins(gd->fdt_blob, "shared");
+
+ if (ret)
+ return;
+
+ ret = config_pins(gd->fdt_blob, "fpga");
+ if (ret)
+ return;
+ } else if (!is_fpgamgr_early_user_mode()) {
+ /* Program IOSSM(early IO release) or full FPGA */
+ fpgamgr_program(buf, FPGA_BUFSIZ, 0);
+ }
+
+ /* If the IOSSM/full FPGA is already loaded, start DDR */
+ if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode())
+ ddr_calibration_sequence();
+
+ if (!is_fpgamgr_user_mode())
+ fpgamgr_program(buf, FPGA_BUFSIZ, 0);
}
void board_init_f(ulong dummy)
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 9df2c430d7..285280e507 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -69,7 +69,7 @@ static int wait_for_user_mode(void)
1, FPGA_TIMEOUT_MSEC, false);
}
-static int is_fpgamgr_early_user_mode(void)
+int is_fpgamgr_early_user_mode(void)
{
return (readl(&fpga_manager_base->imgcfg_stat) &
ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
--
2.13.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v12 8/9] ARM: socfpga: Synchronize the configuration for A10 SoCDK
2019-03-19 8:50 [U-Boot] [PATCH v12 0/9] Add support for loading FPGA bitstream tien.fong.chee at intel.com
` (6 preceding siblings ...)
2019-03-19 8:50 ` [U-Boot] [PATCH v12 7/9] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs tien.fong.chee at intel.com
@ 2019-03-19 8:50 ` tien.fong.chee at intel.com
2019-03-19 8:50 ` [U-Boot] [PATCH v12 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL tien.fong.chee at intel.com
2019-04-15 3:52 ` [U-Boot] [PATCH v12 0/9] Add support for loading FPGA bitstream Chee, Tien Fong
9 siblings, 0 replies; 27+ messages in thread
From: tien.fong.chee at intel.com @ 2019-03-19 8:50 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Update the default configuration file to enable the necessary functionality
the get the kit working.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
changes for v12
- No changes.
changes for v11
- No changes.
changes for v10
- No changes.
changes for v9
- No changes.
changes for v8
- Moved the FIT related configs to the patch of configuration for FPGA
SoCFPGA A10 SoCDK.
changes for v7
- Keep minimal configs.
---
configs/socfpga_arria10_defconfig | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
index 192cf7e05f..759fc771e6 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -10,11 +10,14 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
+CONFIG_VERSION_VARIABLE=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_FPGA_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
# CONFIG_CMD_FLASH is not set
@@ -23,9 +26,7 @@ CONFIG_CMD_MMC=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
-# CONFIG_SPL_DOS_PARTITION is not set
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_ENV_SUPPORT=y
@@ -33,7 +34,6 @@ CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_DM_MMC=y
CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_FS_LOADER=y
@@ -44,11 +44,14 @@ CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_MMC=y
CONFIG_MTD_DEVICE=y
+CONFIG_MMC_DW=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
+CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_DESIGNWARE_APB_TIMER=y
-CONFIG_USE_TINY_PRINTF=y
--
2.13.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v12 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL
2019-03-19 8:50 [U-Boot] [PATCH v12 0/9] Add support for loading FPGA bitstream tien.fong.chee at intel.com
` (7 preceding siblings ...)
2019-03-19 8:50 ` [U-Boot] [PATCH v12 8/9] ARM: socfpga: Synchronize the configuration for A10 SoCDK tien.fong.chee at intel.com
@ 2019-03-19 8:50 ` tien.fong.chee at intel.com
2019-04-27 19:50 ` Simon Goldschmidt
2019-04-15 3:52 ` [U-Boot] [PATCH v12 0/9] Add support for loading FPGA bitstream Chee, Tien Fong
9 siblings, 1 reply; 27+ messages in thread
From: tien.fong.chee at intel.com @ 2019-03-19 8:50 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Increasing Malloc pool size up to 0x15000 is required to support FAT in SPL
. The result of calculation is come from after applying some few patches
which are required for optimizing vfat and maximizing resusable of the
memory pool, and then followed by the size required come from default max
cluster(0x10000) + others(0x2000) + additional memory for headroom(0x3000).
Previous records of describing these few patches can be checked from here
[v7]: https://www.mail-archive.com/u-boot at lists.denx.de/msg314511.html .
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
changes for v12
- Improved the commit messages.
changes for v11
- No changes.
changes for v10
- No changes.
changes for v9
- No changes.
changes for v8
- Moved the FIT related configs to the patch of configuration for FPGA
SoCFPGA A10 SoCDK.
changes for v7
- Keep minimal configs.
---
include/configs/socfpga_common.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 181af9b646..22533036ed 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
*/
#ifndef __CONFIG_SOCFPGA_COMMON_H__
#define __CONFIG_SOCFPGA_COMMON_H__
@@ -254,7 +254,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
/* SPL memory allocation configuration, this is for FAT implementation */
#ifndef CONFIG_SYS_SPL_MALLOC_START
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00015000
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_SIZE - \
CONFIG_SYS_SPL_MALLOC_SIZE + \
CONFIG_SYS_INIT_RAM_ADDR)
--
2.13.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v12 0/9] Add support for loading FPGA bitstream
2019-03-19 8:50 [U-Boot] [PATCH v12 0/9] Add support for loading FPGA bitstream tien.fong.chee at intel.com
` (8 preceding siblings ...)
2019-03-19 8:50 ` [U-Boot] [PATCH v12 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL tien.fong.chee at intel.com
@ 2019-04-15 3:52 ` Chee, Tien Fong
9 siblings, 0 replies; 27+ messages in thread
From: Chee, Tien Fong @ 2019-04-15 3:52 UTC (permalink / raw)
To: u-boot
On Tue, 2019-03-19 at 16:50 +0800, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
>
> This version mainly resolved comments from Dinh in [v11].
>
> This series is working on top of u-boot.git http://git.denx.de/u-boot
> .git
>
> These patches are required before applying this series of patches
> 1. [U-Boot,v4] misc: fs_loader: Add support for initializing block
> device
> https://patchwork.ozlabs.org/project/uboot/list/?series=89282 (done
> review)
>
> 2. [U-Boot] fpga: Replace char * with const char * for filename
> https://patchwork.ozlabs.org/patch/1042665/ (done review)
>
> 3. [U-Boot] misc: fs_loader: Replace label with DT phandle
> https://patchwork.ozlabs.org/patch/1051782/ (under review)
>
> [v11]: https://www.mail-archive.com/u-boot at lists.denx.de/msg318174.ht
> ml
> [v10]: https://www.mail-archive.com/u-boot at lists.denx.de/msg318167.ht
> ml
> [v9]: https://www.mail-archive.com/u-boot at lists.denx.de/msg316086.htm
> l
> [v8]: https://www.mail-archive.com/u-boot at lists.denx.de/msg316086.htm
> l
> [v7]: https://www.mail-archive.com/u-boot at lists.denx.de/msg314511.htm
> l
>
> Tien Fong Chee (9):
> ARM: socfpga: Description on FPGA bitstream type and file name for
> Arria 10
> ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK
> ARM: socfpga: Cleaning up and ensuring consistent format messages
> in
> driver
> ARM: socfpga: Moving the watchdog reset to the for-loop status
> polling
> ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
> ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK
> spl : socfpga: Implement fpga bitstream loading with socfpga loadfs
> ARM: socfpga: Synchronize the configuration for A10 SoCDK
> ARM: socfpga: Increase Malloc pool size to support FAT filesystem
> in
> SPL
>
> arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +
> .../include/mach/fpga_manager_arria10.h | 40 +-
> arch/arm/mach-socfpga/spl_a10.c | 31 +-
> board/altera/arria10-socdk/fit_spl_fpga.its | 38 ++
> configs/socfpga_arria10_defconfig | 22 +-
> .../fpga/altera-socfpga-a10-fpga-mgr.txt | 26 +-
> drivers/fpga/socfpga_arria10.c | 514
> ++++++++++++++++++++-
> include/configs/socfpga_common.h | 4 +-
> include/image.h | 4 +
> 9 files changed, 664 insertions(+), 32 deletions(-)
> create mode 100644 board/altera/arria10-socdk/fit_spl_fpga.its
>
Any comment about this series of patches?
Thanks.
Regards,
TF.
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v12 4/9] ARM: socfpga: Moving the watchdog reset to the for-loop status polling
2019-03-19 8:50 ` [U-Boot] [PATCH v12 4/9] ARM: socfpga: Moving the watchdog reset to the for-loop status polling tien.fong.chee at intel.com
@ 2019-04-27 19:34 ` Simon Goldschmidt
2019-04-30 11:57 ` Chee, Tien Fong
2019-05-06 3:36 ` Chee, Tien Fong
0 siblings, 2 replies; 27+ messages in thread
From: Simon Goldschmidt @ 2019-04-27 19:34 UTC (permalink / raw)
To: u-boot
On 19.03.19 09:50, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
>
> Ensure the watchdog is reset timely on each status polling.
I would have expected a longer commit message here explaining why this
is done, and from where, where to, and why the watchdog reset has been
moved.
Anyway, I don't want to hold back this series again for this, but please
next time: write longer commit messages. Better write too much than risk
someone in the future doesn't get what or why you did things.
Thanks,
Simon
>
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>
> ---
>
> changes for v12
> - Improved the commit messages.
>
> changes for v11
> - No changes.
>
> changes for v10
> - This patch was split out from [PATCH v10 5/9]
> ARM: socfpga: Add FPGA drivers for Arria 10 FPGA.
> ---
> drivers/fpga/socfpga_arria10.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
> index b0abe1955c..9499d1a014 100644
> --- a/drivers/fpga/socfpga_arria10.c
> +++ b/drivers/fpga/socfpga_arria10.c
> @@ -360,6 +360,7 @@ static int fpgamgr_program_poll_cd(void)
> printf("nstatus == 0 while waiting for condone\n");
> return -EPERM;
> }
> + WATCHDOG_RESET();
> }
>
> if (i == FPGA_TIMEOUT_CNT)
> @@ -433,7 +434,6 @@ int fpgamgr_program_finish(void)
> printf("FPGA: Poll CD failed with error code %d\n", status);
> return -EPERM;
> }
> - WATCHDOG_RESET();
>
> /* Ensure the FPGA entering user mode */
> status = fpgamgr_program_poll_usermode();
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v12 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL
2019-03-19 8:50 ` [U-Boot] [PATCH v12 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL tien.fong.chee at intel.com
@ 2019-04-27 19:50 ` Simon Goldschmidt
2019-04-30 12:13 ` Chee, Tien Fong
0 siblings, 1 reply; 27+ messages in thread
From: Simon Goldschmidt @ 2019-04-27 19:50 UTC (permalink / raw)
To: u-boot
On 19.03.19 09:50, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
>
> Increasing Malloc pool size up to 0x15000 is required to support FAT in SPL
> . The result of calculation is come from after applying some few patches
"Some few patches"? What should that mean? Either you refer to the
current state or you can refer to the patchwork items.
> which are required for optimizing vfat and maximizing resusable of the
> memory pool, and then followed by the size required come from default max
> cluster(0x10000) + others(0x2000) + additional memory for headroom(0x3000).
> Previous records of describing these few patches can be checked from here
> [v7]: https://www.mail-archive.com/u-boot at lists.denx.de/msg314511.html .
Why do you refer to mail-archive.com instead of patchwork?
Regards,
Simon
>
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>
> ---
>
> changes for v12
> - Improved the commit messages.
>
> changes for v11
> - No changes.
>
> changes for v10
> - No changes.
>
> changes for v9
> - No changes.
>
> changes for v8
> - Moved the FIT related configs to the patch of configuration for FPGA
> SoCFPGA A10 SoCDK.
>
> changes for v7
> - Keep minimal configs.
> ---
> include/configs/socfpga_common.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
> index 181af9b646..22533036ed 100644
> --- a/include/configs/socfpga_common.h
> +++ b/include/configs/socfpga_common.h
> @@ -1,6 +1,6 @@
> /* SPDX-License-Identifier: GPL-2.0+ */
> /*
> - * Copyright (C) 2012 Altera Corporation <www.altera.com>
> + * Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
> */
> #ifndef __CONFIG_SOCFPGA_COMMON_H__
> #define __CONFIG_SOCFPGA_COMMON_H__
> @@ -254,7 +254,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
> #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> /* SPL memory allocation configuration, this is for FAT implementation */
> #ifndef CONFIG_SYS_SPL_MALLOC_START
> -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
> +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00015000
> #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_SIZE - \
> CONFIG_SYS_SPL_MALLOC_SIZE + \
> CONFIG_SYS_INIT_RAM_ADDR)
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v12 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
2019-03-19 8:50 ` [U-Boot] [PATCH v12 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading tien.fong.chee at intel.com
@ 2019-04-27 19:57 ` Simon Goldschmidt
2019-04-30 12:09 ` Chee, Tien Fong
0 siblings, 1 reply; 27+ messages in thread
From: Simon Goldschmidt @ 2019-04-27 19:57 UTC (permalink / raw)
To: u-boot
On 19.03.19 09:50, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
>
> Add FPGA driver to support program FPGA with FPGA bitstream loading from
> filesystem. The driver are designed based on generic firmware loader
> framework. The driver can handle FPGA program operation from loading FPGA
> bitstream in flash to memory and then to program FPGA.
>
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>
> ---
>
> changes for v12
> - No changes.
>
> changes for v11
> - No changes.
>
> changes for v10
> -Cleaned up the codes.
> -Return -EPERM when programing core on non early IO release mode. > -Using live function to get rid of gd->
You got rid of gd-> in v10? How come I see numerous references to it below?
Regards,
Simon
> -Removed @0 for fs-loader node
>
> changes for v9
> - Support data offset
> - Added default DDR load address
> - Squashed the image.h
> - Changed to phandle
> - Ensure the DDR is fully up running by checking the gd->ram
>
> changes for v8
> - Added codes to discern bitstream type based on fpga node name.
>
> changes for v7
> - Restructure the FPGA driver to support both peripheral bitstream and core
> bitstream bundled into FIT image.
> - Support loadable property for core bitstream. User can set loadable
> in DDR for better performance. This loading would be done in one large
> chunk instead of chunk by chunk loading with small memory buffer.
> ---
> arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +
> .../include/mach/fpga_manager_arria10.h | 39 +-
> drivers/fpga/socfpga_arria10.c | 497 ++++++++++++++++++++-
> include/image.h | 4 +
> 4 files changed, 542 insertions(+), 15 deletions(-)
>
> diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> index 998d811210..cc761967c7 100644
> --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> @@ -18,6 +18,23 @@
> /dts-v1/;
> #include "socfpga_arria10_socdk.dtsi"
>
> +/ {
> + chosen {
> + firmware-loader = <&fs_loader0>;
> + };
> +
> + fs_loader0: fs-loader {
> + u-boot,dm-pre-reloc;
> + compatible = "u-boot,fs-loader";
> + phandlepart = <&mmc 1>;
> + };
> +};
> +
> +&fpga_mgr {
> + u-boot,dm-pre-reloc;
> + altr,bitstream = "fit_spl_fpga.itb";
> +};
> +
> &mmc {
> u-boot,dm-pre-reloc;
> status = "okay";
> diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> index 09d13f6fd3..c5f67714aa 100644
> --- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> @@ -1,9 +1,13 @@
> /* SPDX-License-Identifier: GPL-2.0 */
> /*
> - * Copyright (C) 2017 Intel Corporation <www.intel.com>
> + * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
> * All rights reserved.
> */
>
> +#include <asm/cache.h>
> +#include <altera.h>
> +#include <image.h>
> +
> #ifndef _FPGA_MANAGER_ARRIA10_H_
> #define _FPGA_MANAGER_ARRIA10_H_
>
> @@ -51,6 +55,10 @@
> #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24)
> #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16
>
> +#define FPGA_SOCFPGA_A10_RBF_UNENCRYPTED 0xa65c
> +#define FPGA_SOCFPGA_A10_RBF_ENCRYPTED 0xa65d
> +#define FPGA_SOCFPGA_A10_RBF_PERIPH 0x0001
> +#define FPGA_SOCFPGA_A10_RBF_CORE 0x8001
> #ifndef __ASSEMBLY__
>
> struct socfpga_fpga_manager {
> @@ -88,12 +96,39 @@ struct socfpga_fpga_manager {
> u32 imgcfg_fifo_status;
> };
>
> +enum rbf_type {
> + unknown,
> + periph_section,
> + core_section
> +};
> +
> +enum rbf_security {
> + invalid,
> + unencrypted,
> + encrypted
> +};
> +
> +struct rbf_info {
> + enum rbf_type section;
> + enum rbf_security security;
> +};
> +
> +struct fpga_loadfs_info {
> + fpga_fs_info *fpga_fsinfo;
> + u32 remaining;
> + u32 offset;
> + struct rbf_info rbfinfo;
> +};
> +
> /* Functions */
> int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
> int fpgamgr_program_finish(void);
> int is_fpgamgr_user_mode(void);
> int fpgamgr_wait_early_user_mode(void);
> -
> +const char *get_fpga_filename(void);
> +int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
> + u32 offset);
> +void fpgamgr_program(const void *buf, size_t bsize, u32 offset);
> #endif /* __ASSEMBLY__ */
>
> #endif /* _FPGA_MANAGER_ARRIA10_H_ */
> diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
> index 9499d1a014..9df2c430d7 100644
> --- a/drivers/fpga/socfpga_arria10.c
> +++ b/drivers/fpga/socfpga_arria10.c
> @@ -1,8 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
> - * Copyright (C) 2017 Intel Corporation <www.intel.com>
> + * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
> */
> -
> #include <asm/io.h>
> #include <asm/arch/fpga_manager.h>
> #include <asm/arch/reset_manager.h>
> @@ -10,8 +9,11 @@
> #include <asm/arch/sdram.h>
> #include <asm/arch/misc.h>
> #include <altera.h>
> +#include <asm/arch/pinmux.h>
> #include <common.h>
> +#include <dm/ofnode.h>
> #include <errno.h>
> +#include <fs_loader.h>
> #include <wait_bit.h>
> #include <watchdog.h>
>
> @@ -21,6 +23,9 @@
> #define COMPRESSION_OFFSET 229
> #define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
> #define FPGA_TIMEOUT_CNT 0x1000000
> +#define DEFAULT_DDR_LOAD_ADDRESS 0x400
> +
> +DECLARE_GLOBAL_DATA_PTR;
>
> static const struct socfpga_fpga_manager *fpga_manager_base =
> (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
> @@ -448,13 +453,461 @@ int fpgamgr_program_finish(void)
> return 0;
> }
>
> -/*
> - * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
> - * Return 0 for sucess, non-zero for error.
> - */
> +ofnode get_fpga_mgr_ofnode(ofnode from)
> +{
> + return ofnode_by_compatible(from, "altr,socfpga-a10-fpga-mgr");
> +}
> +
> +const char *get_fpga_filename(void)
> +{
> + const char *fpga_filename = NULL;
> +
> + ofnode fpgamgr_node = get_fpga_mgr_ofnode(ofnode_null());
> +
> + if (ofnode_valid(fpgamgr_node))
> + fpga_filename = ofnode_read_string(fpgamgr_node,
> + "altr,bitstream");
> +
> + return fpga_filename;
> +}
> +
> +static void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer)
> +{
> + /*
> + * Magic ID starting at:
> + * -> 1st dword[15:0] in periph.rbf
> + * -> 2nd dword[15:0] in core.rbf
> + * Note: dword == 32 bits
> + */
> + u32 word_reading_max = 2;
> + u32 i;
> +
> + for (i = 0; i < word_reading_max; i++) {
> + if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
> + rbf->security = unencrypted;
> + } else if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
> + rbf->security = encrypted;
> + } else if (*(buffer + i + 1) ==
> + FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
> + rbf->security = unencrypted;
> + } else if (*(buffer + i + 1) ==
> + FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
> + rbf->security = encrypted;
> + } else {
> + rbf->security = invalid;
> + continue;
> + }
> +
> + /* PERIPH RBF(buffer + i + 1), CORE RBF(buffer + i + 2) */
> + if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
> + rbf->section = periph_section;
> + break;
> + } else if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_CORE) {
> + rbf->section = core_section;
> + break;
> + } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
> + rbf->section = periph_section;
> + break;
> + } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_CORE) {
> + rbf->section = core_section;
> + break;
> + }
> +
> + rbf->section = unknown;
> + break;
> +
> + WATCHDOG_RESET();
> + }
> +}
> +
> +#ifdef CONFIG_FS_LOADER
> +static int first_loading_rbf_to_buffer(struct udevice *dev,
> + struct fpga_loadfs_info *fpga_loadfs,
> + u32 *buffer, size_t *buffer_bsize)
> +{
> + u32 *buffer_p = (u32 *)*buffer;
> + u32 *loadable = buffer_p;
> + size_t buffer_size = *buffer_bsize;
> + size_t fit_size;
> + int ret, i, count, confs_noffset, images_noffset, rbf_offset, rbf_size;
> + const char *fpga_node_name = NULL;
> + const char *uname = NULL;
> +
> + /* Load image header into buffer */
> + ret = request_firmware_into_buf(dev,
> + fpga_loadfs->fpga_fsinfo->filename,
> + buffer_p, sizeof(struct image_header),
> + 0);
> + if (ret < 0) {
> + debug("FPGA: Failed to read image header from flash.\n");
> + return -ENOENT;
> + }
> +
> + if (image_get_magic((struct image_header *)buffer_p) != FDT_MAGIC) {
> + debug("FPGA: No FDT magic was found.\n");
> + return -EBADF;
> + }
> +
> + fit_size = fdt_totalsize(buffer_p);
> +
> + if (fit_size > buffer_size) {
> + debug("FPGA: FIT image is larger than available buffer.\n");
> + debug("Please use FIT external data or increasing buffer.\n");
> + return -ENOMEM;
> + }
> +
> + /* Load entire FIT into buffer */
> + ret = request_firmware_into_buf(dev,
> + fpga_loadfs->fpga_fsinfo->filename,
> + buffer_p, fit_size, 0);
> + if (ret < 0)
> + return ret;
> +
> + ret = fit_check_format(buffer_p);
> + if (!ret) {
> + debug("FPGA: No valid FIT image was found.\n");
> + return -EBADF;
> + }
> +
> + confs_noffset = fdt_path_offset(buffer_p, FIT_CONFS_PATH);
> + images_noffset = fdt_path_offset(buffer_p, FIT_IMAGES_PATH);
> + if (confs_noffset < 0 || images_noffset < 0) {
> + debug("FPGA: No Configurations or images nodes were found.\n");
> + return -ENOENT;
> + }
> +
> + /* Get default configuration unit name from default property */
> + confs_noffset = fit_conf_get_node(buffer_p, NULL);
> + if (confs_noffset < 0) {
> + debug("FPGA: No default configuration was found in config.\n");
> + return -ENOENT;
> + }
> +
> + count = fit_conf_get_prop_node_count(buffer_p, confs_noffset,
> + FIT_FPGA_PROP);
> + if (count < 0) {
> + debug("FPGA: Invalid configuration format for FPGA node.\n");
> + return count;
> + }
> + debug("FPGA: FPGA node count: %d\n", count);
> +
> + for (i = 0; i < count; i++) {
> + images_noffset = fit_conf_get_prop_node_index(buffer_p,
> + confs_noffset,
> + FIT_FPGA_PROP, i);
> + uname = fit_get_name(buffer_p, images_noffset, NULL);
> + if (uname) {
> + debug("FPGA: %s\n", uname);
> +
> + if (strstr(uname, "fpga-periph") &&
> + (!is_fpgamgr_early_user_mode() ||
> + is_fpgamgr_user_mode())) {
> + fpga_node_name = uname;
> + printf("FPGA: Start to program ");
> + printf("peripheral/full bitstream ...\n");
> + break;
> + } else if (strstr(uname, "fpga-core") &&
> + (is_fpgamgr_early_user_mode() &&
> + !is_fpgamgr_user_mode())) {
> + fpga_node_name = uname;
> + printf("FPGA: Start to program core ");
> + printf("bitstream ...\n");
> + break;
> + }
> + }
> + WATCHDOG_RESET();
> + }
> +
> + if (!fpga_node_name) {
> + debug("FPGA: No suitable bitstream was found, count: %d.\n", i);
> + return 1;
> + }
> +
> + images_noffset = fit_image_get_node(buffer_p, fpga_node_name);
> + if (images_noffset < 0) {
> + debug("FPGA: No node '%s' was found in FIT.\n",
> + fpga_node_name);
> + return -ENOENT;
> + }
> +
> + if (!fit_image_get_data_position(buffer_p, images_noffset,
> + &rbf_offset)) {
> + debug("FPGA: Data position was found.\n");
> + } else if (!fit_image_get_data_offset(buffer_p, images_noffset,
> + &rbf_offset)) {
> + /*
> + * For FIT with external data, figure out where
> + * the external images start. This is the base
> + * for the data-offset properties in each image.
> + */
> + rbf_offset += ((fdt_totalsize(buffer_p) + 3) & ~3);
> + debug("FPGA: Data offset was found.\n");
> + } else {
> + debug("FPGA: No data position/offset was found.\n");
> + return -ENOENT;
> + }
> +
> + ret = fit_image_get_data_size(buffer_p, images_noffset, &rbf_size);
> + if (ret < 0) {
> + debug("FPGA: No data size was found (err=%d).\n", ret);
> + return -ENOENT;
> + }
> +
> + if (gd->ram_size < rbf_size) {
> + debug("FPGA: Using default OCRAM buffer and size.\n");
> + } else {
> + ret = fit_image_get_load(buffer_p, images_noffset,
> + (ulong *)loadable);
> + if (ret < 0) {
> + buffer_p = (u32 *)DEFAULT_DDR_LOAD_ADDRESS;
> + debug("FPGA: No loadable was found.\n");
> + debug("FPGA: Using default DDR load address: 0x%x .\n",
> + DEFAULT_DDR_LOAD_ADDRESS);
> + } else {
> + buffer_p = (u32 *)*loadable;
> + debug("FPGA: Found loadable address = 0x%x.\n",
> + *loadable);
> + }
> +
> + buffer_size = rbf_size;
> + }
> +
> + debug("FPGA: External data: offset = 0x%x, size = 0x%x.\n",
> + rbf_offset, rbf_size);
> +
> + fpga_loadfs->remaining = rbf_size;
> +
> + /*
> + * Determine buffer size vs bitstream size, and calculating number of
> + * chunk by chunk transfer is required due to smaller buffer size
> + * compare to bitstream
> + */
> + if (rbf_size <= buffer_size) {
> + /* Loading whole bitstream into buffer */
> + buffer_size = rbf_size;
> + fpga_loadfs->remaining = 0;
> + } else {
> + fpga_loadfs->remaining -= buffer_size;
> + }
> +
> + fpga_loadfs->offset = rbf_offset;
> + /* Loading bitstream into buffer */
> + ret = request_firmware_into_buf(dev,
> + fpga_loadfs->fpga_fsinfo->filename,
> + buffer_p, buffer_size,
> + fpga_loadfs->offset);
> + if (ret < 0) {
> + debug("FPGA: Failed to read bitstream from flash.\n");
> + return -ENOENT;
> + }
> +
> + /* Getting info about bitstream types */
> + get_rbf_image_info(&fpga_loadfs->rbfinfo, (u16 *)buffer_p);
> +
> + /* Update next reading bitstream offset */
> + fpga_loadfs->offset += buffer_size;
> +
> + /* Update the final addr for bitstream */
> + *buffer = (u32)buffer_p;
> +
> + /* Update the size of bitstream to be programmed into FPGA */
> + *buffer_bsize = buffer_size;
> +
> + return 0;
> +}
> +
> +static int subsequent_loading_rbf_to_buffer(struct udevice *dev,
> + struct fpga_loadfs_info *fpga_loadfs,
> + u32 *buffer, size_t *buffer_bsize)
> +{
> + int ret = 0;
> + u32 *buffer_p = (u32 *)*buffer;
> +
> + /* Read the bitstream chunk by chunk. */
> + if (fpga_loadfs->remaining > *buffer_bsize) {
> + fpga_loadfs->remaining -= *buffer_bsize;
> + } else {
> + *buffer_bsize = fpga_loadfs->remaining;
> + fpga_loadfs->remaining = 0;
> + }
> +
> + ret = request_firmware_into_buf(dev,
> + fpga_loadfs->fpga_fsinfo->filename,
> + buffer_p, *buffer_bsize,
> + fpga_loadfs->offset);
> + if (ret < 0) {
> + debug("FPGA: Failed to read bitstream from flash.\n");
> + return -ENOENT;
> + }
> +
> + /* Update next reading bitstream offset */
> + fpga_loadfs->offset += *buffer_bsize;
> +
> + return 0;
> +}
> +
> +int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
> + u32 offset)
> +{
> + struct fpga_loadfs_info fpga_loadfs;
> + struct udevice *dev;
> + int status, ret, size;
> + u32 buffer = (uintptr_t)buf;
> + size_t buffer_sizebytes = bsize;
> + size_t buffer_sizebytes_ori = bsize;
> + size_t total_sizeof_image = 0;
> + ofnode node;
> + const fdt32_t *phandle_p;
> + u32 phandle;
> +
> + node = get_fpga_mgr_ofnode(ofnode_null());
> +
> + if (ofnode_valid(node)) {
> + phandle_p = ofnode_get_property(node, "firmware-loader", &size);
> + if (!phandle_p) {
> + node = ofnode_path("/chosen");
> + if (!ofnode_valid(node)) {
> + debug("FPGA: /chosen node was not found.\n");
> + return -ENOENT;
> + }
> +
> + phandle_p = ofnode_get_property(node, "firmware-loader",
> + &size);
> + if (!phandle_p) {
> + debug("FPGA: firmware-loader property was not");
> + debug(" found.\n");
> + return -ENOENT;
> + }
> + }
> + } else {
> + debug("FPGA: FPGA manager node was not found.\n");
> + return -ENOENT;
> + }
> +
> + phandle = fdt32_to_cpu(*phandle_p);
> + ret = uclass_get_device_by_phandle_id(UCLASS_FS_FIRMWARE_LOADER,
> + phandle, &dev);
> + if (ret)
> + return ret;
> +
> + memset(&fpga_loadfs, 0, sizeof(fpga_loadfs));
> +
> + fpga_loadfs.fpga_fsinfo = fpga_fsinfo;
> + fpga_loadfs.offset = offset;
> +
> + printf("FPGA: Checking FPGA configuration setting ...\n");
> +
> + /*
> + * Note: Both buffer and buffer_sizebytes values can be altered by
> + * function below.
> + */
> + ret = first_loading_rbf_to_buffer(dev, &fpga_loadfs, &buffer,
> + &buffer_sizebytes);
> + if (ret == 1) {
> + printf("FPGA: Skipping configuration ...\n");
> + return 0;
> + } else if (ret) {
> + return ret;
> + }
> +
> + if (fpga_loadfs.rbfinfo.section == core_section &&
> + !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
> + debug("FPGA : Must be in Early Release mode to program ");
> + debug("core bitstream.\n");
> + return -EPERM;
> + }
> +
> + /* Disable all signals from HPS peripheral controller to FPGA */
> + writel(0, &system_manager_base->fpgaintf_en_global);
> +
> + /* Disable all axi bridges (hps2fpga, lwhps2fpga & fpga2hps) */
> + socfpga_bridges_reset();
> +
> + if (fpga_loadfs.rbfinfo.section == periph_section) {
> + /* Initialize the FPGA Manager */
> + status = fpgamgr_program_init((u32 *)buffer, buffer_sizebytes);
> + if (status) {
> + debug("FPGA: Init with peripheral bitstream failed.\n");
> + return -EPERM;
> + }
> + }
> +
> + /* Transfer bitstream to FPGA Manager */
> + fpgamgr_program_write((void *)buffer, buffer_sizebytes);
> +
> + total_sizeof_image += buffer_sizebytes;
> +
> + while (fpga_loadfs.remaining) {
> + ret = subsequent_loading_rbf_to_buffer(dev,
> + &fpga_loadfs,
> + &buffer,
> + &buffer_sizebytes_ori);
> +
> + if (ret)
> + return ret;
> +
> + /* Transfer data to FPGA Manager */
> + fpgamgr_program_write((void *)buffer,
> + buffer_sizebytes_ori);
> +
> + total_sizeof_image += buffer_sizebytes_ori;
> +
> + WATCHDOG_RESET();
> + }
> +
> + if (fpga_loadfs.rbfinfo.section == periph_section) {
> + if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT) {
> + config_pins(gd->fdt_blob, "shared");
> + puts("FPGA: Early Release Succeeded.\n");
> + } else {
> + debug("FPGA: Failed to see Early Release.\n");
> + return -EIO;
> + }
> +
> + /* For monolithic bitstream */
> + if (is_fpgamgr_user_mode()) {
> + /* Ensure the FPGA entering config done */
> + status = fpgamgr_program_finish();
> + if (status)
> + return status;
> +
> + config_pins(gd->fdt_blob, "fpga");
> + puts("FPGA: Enter user mode.\n");
> + }
> + } else if (fpga_loadfs.rbfinfo.section == core_section) {
> + /* Ensure the FPGA entering config done */
> + status = fpgamgr_program_finish();
> + if (status)
> + return status;
> +
> + config_pins(gd->fdt_blob, "fpga");
> + puts("FPGA: Enter user mode.\n");
> + } else {
> + debug("FPGA: Config Error: Unsupported bitstream type.\n");
> + return -ENOEXEC;
> + }
> +
> + return (int)total_sizeof_image;
> +}
> +
> +void fpgamgr_program(const void *buf, size_t bsize, u32 offset)
> +{
> + fpga_fs_info fpga_fsinfo;
> +
> + fpga_fsinfo.filename = get_fpga_filename();
> +
> + if (fpga_fsinfo.filename)
> + socfpga_loadfs(&fpga_fsinfo, buf, bsize, offset);
> +}
> +#endif
> +
> +/* This function is used to load the core bitstream from the OCRAM. */
> int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
> {
> - int status;
> + unsigned long status;
> + struct rbf_info rbfinfo;
> +
> + memset(&rbfinfo, 0, sizeof(rbfinfo));
>
> /* Disable all signals from hps peripheral controller to fpga */
> writel(0, &system_manager_base->fpgaintf_en_global);
> @@ -462,13 +915,31 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
> /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
> socfpga_bridges_reset();
>
> - /* Initialize the FPGA Manager */
> - status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
> - if (status)
> - return status;
> + /* Getting info about bitstream types */
> + get_rbf_image_info(&rbfinfo, (u16 *)rbf_data);
> +
> + if (rbfinfo.section == periph_section) {
> + /* Initialize the FPGA Manager */
> + status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
> + if (status)
> + return status;
> + }
>
> - /* Write the RBF data to FPGA Manager */
> + if (rbfinfo.section == core_section &&
> + !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
> + debug("FPGA : Must be in early release mode to program ");
> + debug("core bitstream.\n");
> + return -EPERM;
> + }
> +
> + /* Write the bitstream to FPGA Manager */
> fpgamgr_program_write(rbf_data, rbf_size);
>
> - return fpgamgr_program_finish();
> + status = fpgamgr_program_finish();
> + if (status) {
> + config_pins(gd->fdt_blob, "fpga");
> + puts("FPGA: Enter user mode.\n");
> + }
> +
> + return status;
> }
> diff --git a/include/image.h b/include/image.h
> index 765ffecee0..cc976f70ce 100644
> --- a/include/image.h
> +++ b/include/image.h
> @@ -1046,6 +1046,10 @@ int fit_check_format(const void *fit);
>
> int fit_conf_find_compat(const void *fit, const void *fdt);
> int fit_conf_get_node(const void *fit, const char *conf_uname);
> +int fit_conf_get_prop_node_count(const void *fit, int noffset,
> + const char *prop_name);
> +int fit_conf_get_prop_node_index(const void *fit, int noffset,
> + const char *prop_name, int index);
>
> /**
> * fit_conf_get_prop_node() - Get node refered to by a configuration
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v12 4/9] ARM: socfpga: Moving the watchdog reset to the for-loop status polling
2019-04-27 19:34 ` Simon Goldschmidt
@ 2019-04-30 11:57 ` Chee, Tien Fong
2019-05-06 3:36 ` Chee, Tien Fong
1 sibling, 0 replies; 27+ messages in thread
From: Chee, Tien Fong @ 2019-04-30 11:57 UTC (permalink / raw)
To: u-boot
On Sat, 2019-04-27 at 21:34 +0200, Simon Goldschmidt wrote:
>
> On 19.03.19 09:50, tien.fong.chee at intel.com wrote:
> >
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > Ensure the watchdog is reset timely on each status polling.
> I would have expected a longer commit message here explaining why
> this
> is done, and from where, where to, and why the watchdog reset has
> been
> moved.
>
> Anyway, I don't want to hold back this series again for this, but
> please
> next time: write longer commit messages. Better write too much than
> risk
> someone in the future doesn't get what or why you did things.
>
Noted.
Thanks.
>
> >
> >
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > ---
> >
> > changes for v12
> > - Improved the commit messages.
> >
> > changes for v11
> > - No changes.
> >
> > changes for v10
> > - This patch was split out from [PATCH v10 5/9]
> > ARM: socfpga: Add FPGA drivers for Arria 10 FPGA.
> > ---
> > drivers/fpga/socfpga_arria10.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/fpga/socfpga_arria10.c
> > b/drivers/fpga/socfpga_arria10.c
> > index b0abe1955c..9499d1a014 100644
> > --- a/drivers/fpga/socfpga_arria10.c
> > +++ b/drivers/fpga/socfpga_arria10.c
> > @@ -360,6 +360,7 @@ static int fpgamgr_program_poll_cd(void)
> > printf("nstatus == 0 while waiting for
> > condone\n");
> > return -EPERM;
> > }
> > + WATCHDOG_RESET();
> > }
> >
> > if (i == FPGA_TIMEOUT_CNT)
> > @@ -433,7 +434,6 @@ int fpgamgr_program_finish(void)
> > printf("FPGA: Poll CD failed with error code
> > %d\n", status);
> > return -EPERM;
> > }
> > - WATCHDOG_RESET();
> >
> > /* Ensure the FPGA entering user mode */
> > status = fpgamgr_program_poll_usermode();
> >
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v12 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
2019-04-27 19:57 ` Simon Goldschmidt
@ 2019-04-30 12:09 ` Chee, Tien Fong
2019-04-30 12:24 ` Simon Goldschmidt
0 siblings, 1 reply; 27+ messages in thread
From: Chee, Tien Fong @ 2019-04-30 12:09 UTC (permalink / raw)
To: u-boot
On Sat, 2019-04-27 at 21:57 +0200, Simon Goldschmidt wrote:
>
> On 19.03.19 09:50, tien.fong.chee at intel.com wrote:
> >
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > Add FPGA driver to support program FPGA with FPGA bitstream loading
> > from
> > filesystem. The driver are designed based on generic firmware
> > loader
> > framework. The driver can handle FPGA program operation from
> > loading FPGA
> > bitstream in flash to memory and then to program FPGA.
> >
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > ---
> >
> > changes for v12
> > - No changes.
> >
> > changes for v11
> > - No changes.
> >
> > changes for v10
> > -Cleaned up the codes.
> > -Return -EPERM when programing core on non early IO release mode. >
> > -Using live function to get rid of gd->
> You got rid of gd-> in v10? How come I see numerous references to it
> below?
get rid of using gd->fdt_blob for finding the node_offset.
Details in https://patchwork.ozlabs.org/patch/1044415/
-/*
- * FPGA Manager to program the FPGA. This is the interface used by
FPGA driver.
- * Return 0 for sucess, non-zero for error.
- */
+ofnode get_fpga_mgr_ofnode(void)
+{
+ int node_offset;
+
+ fdtdec_find_aliases_for_id(gd->fdt_blob, "fpga_mgr",
nit: using of live functions would be better to get rid of gd->.
+ COMPAT_ALTERA_SOCFPGA_FPGA0,
+ &node_offset, 1);
Thanks.
>
> >
> > -Removed @0 for fs-loader node
> >
> > changes for v9
> > - Support data offset
> > - Added default DDR load address
> > - Squashed the image.h
> > - Changed to phandle
> > - Ensure the DDR is fully up running by checking the gd->ram
> >
> > changes for v8
> > - Added codes to discern bitstream type based on fpga node name.
> >
> > changes for v7
> > - Restructure the FPGA driver to support both peripheral bitstream
> > and core
> > bitstream bundled into FIT image.
> > - Support loadable property for core bitstream. User can set
> > loadable
> > in DDR for better performance. This loading would be done in one
> > large
> > chunk instead of chunk by chunk loading with small memory
> > buffer.
> > ---
> > arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +
> > .../include/mach/fpga_manager_arria10.h | 39 +-
> > drivers/fpga/socfpga_arria10.c | 497
> > ++++++++++++++++++++-
> > include/image.h | 4 +
> > 4 files changed, 542 insertions(+), 15 deletions(-)
> >
> > diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > index 998d811210..cc761967c7 100644
> > --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > @@ -18,6 +18,23 @@
> > /dts-v1/;
> > #include "socfpga_arria10_socdk.dtsi"
> >
> > +/ {
> > + chosen {
> > + firmware-loader = <&fs_loader0>;
> > + };
> > +
> > + fs_loader0: fs-loader {
> > + u-boot,dm-pre-reloc;
> > + compatible = "u-boot,fs-loader";
> > + phandlepart = <&mmc 1>;
> > + };
> > +};
> > +
> > +&fpga_mgr {
> > + u-boot,dm-pre-reloc;
> > + altr,bitstream = "fit_spl_fpga.itb";
> > +};
> > +
> > &mmc {
> > u-boot,dm-pre-reloc;
> > status = "okay";
> > diff --git a/arch/arm/mach-
> > socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-
> > socfpga/include/mach/fpga_manager_arria10.h
> > index 09d13f6fd3..c5f67714aa 100644
> > --- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> > +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> > @@ -1,9 +1,13 @@
> > /* SPDX-License-Identifier: GPL-2.0 */
> > /*
> > - * Copyright (C) 2017 Intel Corporation <www.intel.com>
> > + * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
> > * All rights reserved.
> > */
> >
> > +#include <asm/cache.h>
> > +#include <altera.h>
> > +#include <image.h>
> > +
> > #ifndef _FPGA_MANAGER_ARRIA10_H_
> > #define _FPGA_MANAGER_ARRIA10_H_
> >
> > @@ -51,6 +55,10 @@
> > #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK
> > BIT(24)
> > #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB
> > 16
> >
> > +#define FPGA_SOCFPGA_A10_RBF_UNENCRYPTED 0xa65c
> > +#define FPGA_SOCFPGA_A10_RBF_ENCRYPTED 0xa65d
> > +#define FPGA_SOCFPGA_A10_RBF_PERIPH 0x0001
> > +#define FPGA_SOCFPGA_A10_RBF_CORE 0x8001
> > #ifndef __ASSEMBLY__
> >
> > struct socfpga_fpga_manager {
> > @@ -88,12 +96,39 @@ struct socfpga_fpga_manager {
> > u32 imgcfg_fifo_status;
> > };
> >
> > +enum rbf_type {
> > + unknown,
> > + periph_section,
> > + core_section
> > +};
> > +
> > +enum rbf_security {
> > + invalid,
> > + unencrypted,
> > + encrypted
> > +};
> > +
> > +struct rbf_info {
> > + enum rbf_type section;
> > + enum rbf_security security;
> > +};
> > +
> > +struct fpga_loadfs_info {
> > + fpga_fs_info *fpga_fsinfo;
> > + u32 remaining;
> > + u32 offset;
> > + struct rbf_info rbfinfo;
> > +};
> > +
> > /* Functions */
> > int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
> > int fpgamgr_program_finish(void);
> > int is_fpgamgr_user_mode(void);
> > int fpgamgr_wait_early_user_mode(void);
> > -
> > +const char *get_fpga_filename(void);
> > +int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf,
> > size_t bsize,
> > + u32 offset);
> > +void fpgamgr_program(const void *buf, size_t bsize, u32 offset);
> > #endif /* __ASSEMBLY__ */
> >
> > #endif /* _FPGA_MANAGER_ARRIA10_H_ */
> > diff --git a/drivers/fpga/socfpga_arria10.c
> > b/drivers/fpga/socfpga_arria10.c
> > index 9499d1a014..9df2c430d7 100644
> > --- a/drivers/fpga/socfpga_arria10.c
> > +++ b/drivers/fpga/socfpga_arria10.c
> > @@ -1,8 +1,7 @@
> > // SPDX-License-Identifier: GPL-2.0
> > /*
> > - * Copyright (C) 2017 Intel Corporation <www.intel.com>
> > + * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
> > */
> > -
> > #include <asm/io.h>
> > #include <asm/arch/fpga_manager.h>
> > #include <asm/arch/reset_manager.h>
> > @@ -10,8 +9,11 @@
> > #include <asm/arch/sdram.h>
> > #include <asm/arch/misc.h>
> > #include <altera.h>
> > +#include <asm/arch/pinmux.h>
> > #include <common.h>
> > +#include <dm/ofnode.h>
> > #include <errno.h>
> > +#include <fs_loader.h>
> > #include <wait_bit.h>
> > #include <watchdog.h>
> >
> > @@ -21,6 +23,9 @@
> > #define COMPRESSION_OFFSET 229
> > #define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
> > #define FPGA_TIMEOUT_CNT 0x1000000
> > +#define DEFAULT_DDR_LOAD_ADDRESS 0x400
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> >
> > static const struct socfpga_fpga_manager *fpga_manager_base =
> > (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
> > @@ -448,13 +453,461 @@ int fpgamgr_program_finish(void)
> > return 0;
> > }
> >
> > -/*
> > - * FPGA Manager to program the FPGA. This is the interface used by
> > FPGA driver.
> > - * Return 0 for sucess, non-zero for error.
> > - */
> > +ofnode get_fpga_mgr_ofnode(ofnode from)
> > +{
> > + return ofnode_by_compatible(from, "altr,socfpga-a10-fpga-
> > mgr");
> > +}
> > +
> > +const char *get_fpga_filename(void)
> > +{
> > + const char *fpga_filename = NULL;
> > +
> > + ofnode fpgamgr_node = get_fpga_mgr_ofnode(ofnode_null());
> > +
> > + if (ofnode_valid(fpgamgr_node))
> > + fpga_filename = ofnode_read_string(fpgamgr_node,
> > + "altr,bitstream");
> > +
> > + return fpga_filename;
> > +}
> > +
> > +static void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer)
> > +{
> > + /*
> > + * Magic ID starting at:
> > + * -> 1st dword[15:0] in periph.rbf
> > + * -> 2nd dword[15:0] in core.rbf
> > + * Note: dword == 32 bits
> > + */
> > + u32 word_reading_max = 2;
> > + u32 i;
> > +
> > + for (i = 0; i < word_reading_max; i++) {
> > + if (*(buffer + i) ==
> > FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
> > + rbf->security = unencrypted;
> > + } else if (*(buffer + i) ==
> > FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
> > + rbf->security = encrypted;
> > + } else if (*(buffer + i + 1) ==
> > + FPGA_SOCFPGA_A10_RBF_UNENCRYPTED)
> > {
> > + rbf->security = unencrypted;
> > + } else if (*(buffer + i + 1) ==
> > + FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
> > + rbf->security = encrypted;
> > + } else {
> > + rbf->security = invalid;
> > + continue;
> > + }
> > +
> > + /* PERIPH RBF(buffer + i + 1), CORE RBF(buffer + i
> > + 2) */
> > + if (*(buffer + i + 1) ==
> > FPGA_SOCFPGA_A10_RBF_PERIPH) {
> > + rbf->section = periph_section;
> > + break;
> > + } else if (*(buffer + i + 1) ==
> > FPGA_SOCFPGA_A10_RBF_CORE) {
> > + rbf->section = core_section;
> > + break;
> > + } else if (*(buffer + i + 2) ==
> > FPGA_SOCFPGA_A10_RBF_PERIPH) {
> > + rbf->section = periph_section;
> > + break;
> > + } else if (*(buffer + i + 2) ==
> > FPGA_SOCFPGA_A10_RBF_CORE) {
> > + rbf->section = core_section;
> > + break;
> > + }
> > +
> > + rbf->section = unknown;
> > + break;
> > +
> > + WATCHDOG_RESET();
> > + }
> > +}
> > +
> > +#ifdef CONFIG_FS_LOADER
> > +static int first_loading_rbf_to_buffer(struct udevice *dev,
> > + struct fpga_loadfs_info
> > *fpga_loadfs,
> > + u32 *buffer, size_t *buffer_bsize)
> > +{
> > + u32 *buffer_p = (u32 *)*buffer;
> > + u32 *loadable = buffer_p;
> > + size_t buffer_size = *buffer_bsize;
> > + size_t fit_size;
> > + int ret, i, count, confs_noffset, images_noffset,
> > rbf_offset, rbf_size;
> > + const char *fpga_node_name = NULL;
> > + const char *uname = NULL;
> > +
> > + /* Load image header into buffer */
> > + ret = request_firmware_into_buf(dev,
> > + fpga_loadfs->fpga_fsinfo-
> > >filename,
> > + buffer_p, sizeof(struct
> > image_header),
> > + 0);
> > + if (ret < 0) {
> > + debug("FPGA: Failed to read image header from
> > flash.\n");
> > + return -ENOENT;
> > + }
> > +
> > + if (image_get_magic((struct image_header *)buffer_p) !=
> > FDT_MAGIC) {
> > + debug("FPGA: No FDT magic was found.\n");
> > + return -EBADF;
> > + }
> > +
> > + fit_size = fdt_totalsize(buffer_p);
> > +
> > + if (fit_size > buffer_size) {
> > + debug("FPGA: FIT image is larger than available
> > buffer.\n");
> > + debug("Please use FIT external data or increasing
> > buffer.\n");
> > + return -ENOMEM;
> > + }
> > +
> > + /* Load entire FIT into buffer */
> > + ret = request_firmware_into_buf(dev,
> > + fpga_loadfs->fpga_fsinfo-
> > >filename,
> > + buffer_p, fit_size, 0);
> > + if (ret < 0)
> > + return ret;
> > +
> > + ret = fit_check_format(buffer_p);
> > + if (!ret) {
> > + debug("FPGA: No valid FIT image was found.\n");
> > + return -EBADF;
> > + }
> > +
> > + confs_noffset = fdt_path_offset(buffer_p, FIT_CONFS_PATH);
> > + images_noffset = fdt_path_offset(buffer_p,
> > FIT_IMAGES_PATH);
> > + if (confs_noffset < 0 || images_noffset < 0) {
> > + debug("FPGA: No Configurations or images nodes
> > were found.\n");
> > + return -ENOENT;
> > + }
> > +
> > + /* Get default configuration unit name from default
> > property */
> > + confs_noffset = fit_conf_get_node(buffer_p, NULL);
> > + if (confs_noffset < 0) {
> > + debug("FPGA: No default configuration was found in
> > config.\n");
> > + return -ENOENT;
> > + }
> > +
> > + count = fit_conf_get_prop_node_count(buffer_p,
> > confs_noffset,
> > + FIT_FPGA_PROP);
> > + if (count < 0) {
> > + debug("FPGA: Invalid configuration format for FPGA
> > node.\n");
> > + return count;
> > + }
> > + debug("FPGA: FPGA node count: %d\n", count);
> > +
> > + for (i = 0; i < count; i++) {
> > + images_noffset =
> > fit_conf_get_prop_node_index(buffer_p,
> > + confs
> > _noffset,
> > + FIT_F
> > PGA_PROP, i);
> > + uname = fit_get_name(buffer_p, images_noffset,
> > NULL);
> > + if (uname) {
> > + debug("FPGA: %s\n", uname);
> > +
> > + if (strstr(uname, "fpga-periph") &&
> > + (!is_fpgamgr_early_user_mode() ||
> > + is_fpgamgr_user_mode())) {
> > + fpga_node_name = uname;
> > + printf("FPGA: Start to program ");
> > + printf("peripheral/full bitstream
> > ...\n");
> > + break;
> > + } else if (strstr(uname, "fpga-core") &&
> > + (is_fpgamgr_early_user_mod
> > e() &&
> > + !is_fpgamgr_user_mode()))
> > {
> > + fpga_node_name = uname;
> > + printf("FPGA: Start to program
> > core ");
> > + printf("bitstream ...\n");
> > + break;
> > + }
> > + }
> > + WATCHDOG_RESET();
> > + }
> > +
> > + if (!fpga_node_name) {
> > + debug("FPGA: No suitable bitstream was found,
> > count: %d.\n", i);
> > + return 1;
> > + }
> > +
> > + images_noffset = fit_image_get_node(buffer_p,
> > fpga_node_name);
> > + if (images_noffset < 0) {
> > + debug("FPGA: No node '%s' was found in FIT.\n",
> > + fpga_node_name);
> > + return -ENOENT;
> > + }
> > +
> > + if (!fit_image_get_data_position(buffer_p, images_noffset,
> > + &rbf_offset)) {
> > + debug("FPGA: Data position was found.\n");
> > + } else if (!fit_image_get_data_offset(buffer_p,
> > images_noffset,
> > + &rbf_offset)) {
> > + /*
> > + * For FIT with external data, figure out where
> > + * the external images start. This is the base
> > + * for the data-offset properties in each image.
> > + */
> > + rbf_offset += ((fdt_totalsize(buffer_p) + 3) &
> > ~3);
> > + debug("FPGA: Data offset was found.\n");
> > + } else {
> > + debug("FPGA: No data position/offset was
> > found.\n");
> > + return -ENOENT;
> > + }
> > +
> > + ret = fit_image_get_data_size(buffer_p, images_noffset,
> > &rbf_size);
> > + if (ret < 0) {
> > + debug("FPGA: No data size was found (err=%d).\n",
> > ret);
> > + return -ENOENT;
> > + }
> > +
> > + if (gd->ram_size < rbf_size) {
> > + debug("FPGA: Using default OCRAM buffer and
> > size.\n");
> > + } else {
> > + ret = fit_image_get_load(buffer_p, images_noffset,
> > + (ulong *)loadable);
> > + if (ret < 0) {
> > + buffer_p = (u32
> > *)DEFAULT_DDR_LOAD_ADDRESS;
> > + debug("FPGA: No loadable was found.\n");
> > + debug("FPGA: Using default DDR load
> > address: 0x%x .\n",
> > + DEFAULT_DDR_LOAD_ADDRESS);
> > + } else {
> > + buffer_p = (u32 *)*loadable;
> > + debug("FPGA: Found loadable address =
> > 0x%x.\n",
> > + *loadable);
> > + }
> > +
> > + buffer_size = rbf_size;
> > + }
> > +
> > + debug("FPGA: External data: offset = 0x%x, size =
> > 0x%x.\n",
> > + rbf_offset, rbf_size);
> > +
> > + fpga_loadfs->remaining = rbf_size;
> > +
> > + /*
> > + * Determine buffer size vs bitstream size, and
> > calculating number of
> > + * chunk by chunk transfer is required due to smaller
> > buffer size
> > + * compare to bitstream
> > + */
> > + if (rbf_size <= buffer_size) {
> > + /* Loading whole bitstream into buffer */
> > + buffer_size = rbf_size;
> > + fpga_loadfs->remaining = 0;
> > + } else {
> > + fpga_loadfs->remaining -= buffer_size;
> > + }
> > +
> > + fpga_loadfs->offset = rbf_offset;
> > + /* Loading bitstream into buffer */
> > + ret = request_firmware_into_buf(dev,
> > + fpga_loadfs->fpga_fsinfo-
> > >filename,
> > + buffer_p, buffer_size,
> > + fpga_loadfs->offset);
> > + if (ret < 0) {
> > + debug("FPGA: Failed to read bitstream from
> > flash.\n");
> > + return -ENOENT;
> > + }
> > +
> > + /* Getting info about bitstream types */
> > + get_rbf_image_info(&fpga_loadfs->rbfinfo, (u16
> > *)buffer_p);
> > +
> > + /* Update next reading bitstream offset */
> > + fpga_loadfs->offset += buffer_size;
> > +
> > + /* Update the final addr for bitstream */
> > + *buffer = (u32)buffer_p;
> > +
> > + /* Update the size of bitstream to be programmed into FPGA
> > */
> > + *buffer_bsize = buffer_size;
> > +
> > + return 0;
> > +}
> > +
> > +static int subsequent_loading_rbf_to_buffer(struct udevice *dev,
> > + struct fpga_loadfs_info
> > *fpga_loadfs,
> > + u32 *buffer, size_t
> > *buffer_bsize)
> > +{
> > + int ret = 0;
> > + u32 *buffer_p = (u32 *)*buffer;
> > +
> > + /* Read the bitstream chunk by chunk. */
> > + if (fpga_loadfs->remaining > *buffer_bsize) {
> > + fpga_loadfs->remaining -= *buffer_bsize;
> > + } else {
> > + *buffer_bsize = fpga_loadfs->remaining;
> > + fpga_loadfs->remaining = 0;
> > + }
> > +
> > + ret = request_firmware_into_buf(dev,
> > + fpga_loadfs->fpga_fsinfo-
> > >filename,
> > + buffer_p, *buffer_bsize,
> > + fpga_loadfs->offset);
> > + if (ret < 0) {
> > + debug("FPGA: Failed to read bitstream from
> > flash.\n");
> > + return -ENOENT;
> > + }
> > +
> > + /* Update next reading bitstream offset */
> > + fpga_loadfs->offset += *buffer_bsize;
> > +
> > + return 0;
> > +}
> > +
> > +int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf,
> > size_t bsize,
> > + u32 offset)
> > +{
> > + struct fpga_loadfs_info fpga_loadfs;
> > + struct udevice *dev;
> > + int status, ret, size;
> > + u32 buffer = (uintptr_t)buf;
> > + size_t buffer_sizebytes = bsize;
> > + size_t buffer_sizebytes_ori = bsize;
> > + size_t total_sizeof_image = 0;
> > + ofnode node;
> > + const fdt32_t *phandle_p;
> > + u32 phandle;
> > +
> > + node = get_fpga_mgr_ofnode(ofnode_null());
> > +
> > + if (ofnode_valid(node)) {
> > + phandle_p = ofnode_get_property(node, "firmware-
> > loader", &size);
> > + if (!phandle_p) {
> > + node = ofnode_path("/chosen");
> > + if (!ofnode_valid(node)) {
> > + debug("FPGA: /chosen node was not
> > found.\n");
> > + return -ENOENT;
> > + }
> > +
> > + phandle_p = ofnode_get_property(node,
> > "firmware-loader",
> > + &size);
> > + if (!phandle_p) {
> > + debug("FPGA: firmware-loader
> > property was not");
> > + debug(" found.\n");
> > + return -ENOENT;
> > + }
> > + }
> > + } else {
> > + debug("FPGA: FPGA manager node was not found.\n");
> > + return -ENOENT;
> > + }
> > +
> > + phandle = fdt32_to_cpu(*phandle_p);
> > + ret =
> > uclass_get_device_by_phandle_id(UCLASS_FS_FIRMWARE_LOADER,
> > + phandle, &dev);
> > + if (ret)
> > + return ret;
> > +
> > + memset(&fpga_loadfs, 0, sizeof(fpga_loadfs));
> > +
> > + fpga_loadfs.fpga_fsinfo = fpga_fsinfo;
> > + fpga_loadfs.offset = offset;
> > +
> > + printf("FPGA: Checking FPGA configuration setting ...\n");
> > +
> > + /*
> > + * Note: Both buffer and buffer_sizebytes values can be
> > altered by
> > + * function below.
> > + */
> > + ret = first_loading_rbf_to_buffer(dev, &fpga_loadfs,
> > &buffer,
> > + &buffer_sizebytes);
> > + if (ret == 1) {
> > + printf("FPGA: Skipping configuration ...\n");
> > + return 0;
> > + } else if (ret) {
> > + return ret;
> > + }
> > +
> > + if (fpga_loadfs.rbfinfo.section == core_section &&
> > + !(is_fpgamgr_early_user_mode() &&
> > !is_fpgamgr_user_mode())) {
> > + debug("FPGA : Must be in Early Release mode to
> > program ");
> > + debug("core bitstream.\n");
> > + return -EPERM;
> > + }
> > +
> > + /* Disable all signals from HPS peripheral controller to
> > FPGA */
> > + writel(0, &system_manager_base->fpgaintf_en_global);
> > +
> > + /* Disable all axi bridges (hps2fpga, lwhps2fpga &
> > fpga2hps) */
> > + socfpga_bridges_reset();
> > +
> > + if (fpga_loadfs.rbfinfo.section == periph_section) {
> > + /* Initialize the FPGA Manager */
> > + status = fpgamgr_program_init((u32 *)buffer,
> > buffer_sizebytes);
> > + if (status) {
> > + debug("FPGA: Init with peripheral
> > bitstream failed.\n");
> > + return -EPERM;
> > + }
> > + }
> > +
> > + /* Transfer bitstream to FPGA Manager */
> > + fpgamgr_program_write((void *)buffer, buffer_sizebytes);
> > +
> > + total_sizeof_image += buffer_sizebytes;
> > +
> > + while (fpga_loadfs.remaining) {
> > + ret = subsequent_loading_rbf_to_buffer(dev,
> > + &fpga_load
> > fs,
> > + &buffer,
> > + &buffer_si
> > zebytes_ori);
> > +
> > + if (ret)
> > + return ret;
> > +
> > + /* Transfer data to FPGA Manager */
> > + fpgamgr_program_write((void *)buffer,
> > + buffer_sizebytes_ori);
> > +
> > + total_sizeof_image += buffer_sizebytes_ori;
> > +
> > + WATCHDOG_RESET();
> > + }
> > +
> > + if (fpga_loadfs.rbfinfo.section == periph_section) {
> > + if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT)
> > {
> > + config_pins(gd->fdt_blob, "shared");
> > + puts("FPGA: Early Release Succeeded.\n");
> > + } else {
> > + debug("FPGA: Failed to see Early
> > Release.\n");
> > + return -EIO;
> > + }
> > +
> > + /* For monolithic bitstream */
> > + if (is_fpgamgr_user_mode()) {
> > + /* Ensure the FPGA entering config done */
> > + status = fpgamgr_program_finish();
> > + if (status)
> > + return status;
> > +
> > + config_pins(gd->fdt_blob, "fpga");
> > + puts("FPGA: Enter user mode.\n");
> > + }
> > + } else if (fpga_loadfs.rbfinfo.section == core_section) {
> > + /* Ensure the FPGA entering config done */
> > + status = fpgamgr_program_finish();
> > + if (status)
> > + return status;
> > +
> > + config_pins(gd->fdt_blob, "fpga");
> > + puts("FPGA: Enter user mode.\n");
> > + } else {
> > + debug("FPGA: Config Error: Unsupported bitstream
> > type.\n");
> > + return -ENOEXEC;
> > + }
> > +
> > + return (int)total_sizeof_image;
> > +}
> > +
> > +void fpgamgr_program(const void *buf, size_t bsize, u32 offset)
> > +{
> > + fpga_fs_info fpga_fsinfo;
> > +
> > + fpga_fsinfo.filename = get_fpga_filename();
> > +
> > + if (fpga_fsinfo.filename)
> > + socfpga_loadfs(&fpga_fsinfo, buf, bsize, offset);
> > +}
> > +#endif
> > +
> > +/* This function is used to load the core bitstream from the
> > OCRAM. */
> > int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t
> > rbf_size)
> > {
> > - int status;
> > + unsigned long status;
> > + struct rbf_info rbfinfo;
> > +
> > + memset(&rbfinfo, 0, sizeof(rbfinfo));
> >
> > /* Disable all signals from hps peripheral controller to
> > fpga */
> > writel(0, &system_manager_base->fpgaintf_en_global);
> > @@ -462,13 +915,31 @@ int socfpga_load(Altera_desc *desc, const
> > void *rbf_data, size_t rbf_size)
> > /* Disable all axi bridge (hps2fpga, lwhps2fpga &
> > fpga2hps) */
> > socfpga_bridges_reset();
> >
> > - /* Initialize the FPGA Manager */
> > - status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
> > - if (status)
> > - return status;
> > + /* Getting info about bitstream types */
> > + get_rbf_image_info(&rbfinfo, (u16 *)rbf_data);
> > +
> > + if (rbfinfo.section == periph_section) {
> > + /* Initialize the FPGA Manager */
> > + status = fpgamgr_program_init((u32 *)rbf_data,
> > rbf_size);
> > + if (status)
> > + return status;
> > + }
> >
> > - /* Write the RBF data to FPGA Manager */
> > + if (rbfinfo.section == core_section &&
> > + !(is_fpgamgr_early_user_mode() &&
> > !is_fpgamgr_user_mode())) {
> > + debug("FPGA : Must be in early release mode to
> > program ");
> > + debug("core bitstream.\n");
> > + return -EPERM;
> > + }
> > +
> > + /* Write the bitstream to FPGA Manager */
> > fpgamgr_program_write(rbf_data, rbf_size);
> >
> > - return fpgamgr_program_finish();
> > + status = fpgamgr_program_finish();
> > + if (status) {
> > + config_pins(gd->fdt_blob, "fpga");
> > + puts("FPGA: Enter user mode.\n");
> > + }
> > +
> > + return status;
> > }
> > diff --git a/include/image.h b/include/image.h
> > index 765ffecee0..cc976f70ce 100644
> > --- a/include/image.h
> > +++ b/include/image.h
> > @@ -1046,6 +1046,10 @@ int fit_check_format(const void *fit);
> >
> > int fit_conf_find_compat(const void *fit, const void *fdt);
> > int fit_conf_get_node(const void *fit, const char *conf_uname);
> > +int fit_conf_get_prop_node_count(const void *fit, int noffset,
> > + const char *prop_name);
> > +int fit_conf_get_prop_node_index(const void *fit, int noffset,
> > + const char *prop_name, int index);
> >
> > /**
> > * fit_conf_get_prop_node() - Get node refered to by a
> > configuration
> >
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v12 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL
2019-04-27 19:50 ` Simon Goldschmidt
@ 2019-04-30 12:13 ` Chee, Tien Fong
2019-04-30 12:26 ` Simon Goldschmidt
0 siblings, 1 reply; 27+ messages in thread
From: Chee, Tien Fong @ 2019-04-30 12:13 UTC (permalink / raw)
To: u-boot
On Sat, 2019-04-27 at 21:50 +0200, Simon Goldschmidt wrote:
>
> On 19.03.19 09:50, tien.fong.chee at intel.com wrote:
> >
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > Increasing Malloc pool size up to 0x15000 is required to support
> > FAT in SPL
> > . The result of calculation is come from after applying some few
> > patches
> "Some few patches"? What should that mean? Either you refer to the
> current state or you can refer to the patchwork items.
>
> >
> > which are required for optimizing vfat and maximizing resusable of
> > the
> > memory pool, and then followed by the size required come from
> > default max
> > cluster(0x10000) + others(0x2000) + additional memory for
> > headroom(0x3000).
> > Previous records of describing these few patches can be checked
> > from here
> > [v7]: https://www.mail-archive.com/u-boot at lists.denx.de/msg314511.h
> > tml .
> Why do you refer to mail-archive.com instead of patchwork?
Contains the cover letter in case reviewer need to know more
information.
Thanks.
>
> >
> >
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > ---
> >
> > changes for v12
> > - Improved the commit messages.
> >
> > changes for v11
> > - No changes.
> >
> > changes for v10
> > - No changes.
> >
> > changes for v9
> > - No changes.
> >
> > changes for v8
> > - Moved the FIT related configs to the patch of configuration for
> > FPGA
> > SoCFPGA A10 SoCDK.
> >
> > changes for v7
> > - Keep minimal configs.
> > ---
> > include/configs/socfpga_common.h | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/include/configs/socfpga_common.h
> > b/include/configs/socfpga_common.h
> > index 181af9b646..22533036ed 100644
> > --- a/include/configs/socfpga_common.h
> > +++ b/include/configs/socfpga_common.h
> > @@ -1,6 +1,6 @@
> > /* SPDX-License-Identifier: GPL-2.0+ */
> > /*
> > - * Copyright (C) 2012 Altera Corporation <www.altera.com>
> > + * Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
> > */
> > #ifndef __CONFIG_SOCFPGA_COMMON_H__
> > #define __CONFIG_SOCFPGA_COMMON_H__
> > @@ -254,7 +254,7 @@ unsigned int
> > cm_get_qspi_controller_clk_hz(void);
> > #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > /* SPL memory allocation configuration, this is for FAT
> > implementation */
> > #ifndef CONFIG_SYS_SPL_MALLOC_START
> > -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
> > +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00015000
> > #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_S
> > IZE - \
> > CONFIG_SYS_SPL_MALLOC_SI
> > ZE + \
> > CONFIG_SYS_INIT_RAM_ADDR
> > )
> >
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v12 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
2019-04-30 12:09 ` Chee, Tien Fong
@ 2019-04-30 12:24 ` Simon Goldschmidt
2019-05-02 7:49 ` Chee, Tien Fong
0 siblings, 1 reply; 27+ messages in thread
From: Simon Goldschmidt @ 2019-04-30 12:24 UTC (permalink / raw)
To: u-boot
On Tue, Apr 30, 2019 at 2:09 PM Chee, Tien Fong
<tien.fong.chee@intel.com> wrote:
>
> On Sat, 2019-04-27 at 21:57 +0200, Simon Goldschmidt wrote:
> >
> > On 19.03.19 09:50, tien.fong.chee at intel.com wrote:
> > >
> > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > >
> > > Add FPGA driver to support program FPGA with FPGA bitstream loading
> > > from
> > > filesystem. The driver are designed based on generic firmware
> > > loader
> > > framework. The driver can handle FPGA program operation from
> > > loading FPGA
> > > bitstream in flash to memory and then to program FPGA.
> > >
> > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > >
> > > ---
> > >
> > > changes for v12
> > > - No changes.
> > >
> > > changes for v11
> > > - No changes.
> > >
> > > changes for v10
> > > -Cleaned up the codes.
> > > -Return -EPERM when programing core on non early IO release mode. >
> > > -Using live function to get rid of gd->
> > You got rid of gd-> in v10? How come I see numerous references to it
> > below?
>
> get rid of using gd->fdt_blob for finding the node_offset.
> Details in https://patchwork.ozlabs.org/patch/1044415/
Ah, ok. But still, here you're introducing yet more references to gd->fdt_blob.
That wouldn't work with a live tree, either, or would it?
Regards,
Simon
>
> -/*
> - * FPGA Manager to program the FPGA. This is the interface used by
> FPGA driver.
> - * Return 0 for sucess, non-zero for error.
> - */
> +ofnode get_fpga_mgr_ofnode(void)
> +{
> + int node_offset;
> +
> + fdtdec_find_aliases_for_id(gd->fdt_blob, "fpga_mgr",
>
> nit: using of live functions would be better to get rid of gd->.
>
> + COMPAT_ALTERA_SOCFPGA_FPGA0,
> + &node_offset, 1);
>
> Thanks.
> >
> > >
> > > -Removed @0 for fs-loader node
> > >
> > > changes for v9
> > > - Support data offset
> > > - Added default DDR load address
> > > - Squashed the image.h
> > > - Changed to phandle
> > > - Ensure the DDR is fully up running by checking the gd->ram
> > >
> > > changes for v8
> > > - Added codes to discern bitstream type based on fpga node name.
> > >
> > > changes for v7
> > > - Restructure the FPGA driver to support both peripheral bitstream
> > > and core
> > > bitstream bundled into FIT image.
> > > - Support loadable property for core bitstream. User can set
> > > loadable
> > > in DDR for better performance. This loading would be done in one
> > > large
> > > chunk instead of chunk by chunk loading with small memory
> > > buffer.
> > > ---
> > > arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +
> > > .../include/mach/fpga_manager_arria10.h | 39 +-
> > > drivers/fpga/socfpga_arria10.c | 497
> > > ++++++++++++++++++++-
> > > include/image.h | 4 +
> > > 4 files changed, 542 insertions(+), 15 deletions(-)
> > >
> > > diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > index 998d811210..cc761967c7 100644
> > > --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > @@ -18,6 +18,23 @@
> > > /dts-v1/;
> > > #include "socfpga_arria10_socdk.dtsi"
> > >
> > > +/ {
> > > + chosen {
> > > + firmware-loader = <&fs_loader0>;
> > > + };
> > > +
> > > + fs_loader0: fs-loader {
> > > + u-boot,dm-pre-reloc;
> > > + compatible = "u-boot,fs-loader";
> > > + phandlepart = <&mmc 1>;
> > > + };
> > > +};
> > > +
> > > +&fpga_mgr {
> > > + u-boot,dm-pre-reloc;
> > > + altr,bitstream = "fit_spl_fpga.itb";
> > > +};
> > > +
> > > &mmc {
> > > u-boot,dm-pre-reloc;
> > > status = "okay";
> > > diff --git a/arch/arm/mach-
> > > socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-
> > > socfpga/include/mach/fpga_manager_arria10.h
> > > index 09d13f6fd3..c5f67714aa 100644
> > > --- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> > > +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> > > @@ -1,9 +1,13 @@
> > > /* SPDX-License-Identifier: GPL-2.0 */
> > > /*
> > > - * Copyright (C) 2017 Intel Corporation <www.intel.com>
> > > + * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
> > > * All rights reserved.
> > > */
> > >
> > > +#include <asm/cache.h>
> > > +#include <altera.h>
> > > +#include <image.h>
> > > +
> > > #ifndef _FPGA_MANAGER_ARRIA10_H_
> > > #define _FPGA_MANAGER_ARRIA10_H_
> > >
> > > @@ -51,6 +55,10 @@
> > > #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK
> > > BIT(24)
> > > #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB
> > > 16
> > >
> > > +#define FPGA_SOCFPGA_A10_RBF_UNENCRYPTED 0xa65c
> > > +#define FPGA_SOCFPGA_A10_RBF_ENCRYPTED 0xa65d
> > > +#define FPGA_SOCFPGA_A10_RBF_PERIPH 0x0001
> > > +#define FPGA_SOCFPGA_A10_RBF_CORE 0x8001
> > > #ifndef __ASSEMBLY__
> > >
> > > struct socfpga_fpga_manager {
> > > @@ -88,12 +96,39 @@ struct socfpga_fpga_manager {
> > > u32 imgcfg_fifo_status;
> > > };
> > >
> > > +enum rbf_type {
> > > + unknown,
> > > + periph_section,
> > > + core_section
> > > +};
> > > +
> > > +enum rbf_security {
> > > + invalid,
> > > + unencrypted,
> > > + encrypted
> > > +};
> > > +
> > > +struct rbf_info {
> > > + enum rbf_type section;
> > > + enum rbf_security security;
> > > +};
> > > +
> > > +struct fpga_loadfs_info {
> > > + fpga_fs_info *fpga_fsinfo;
> > > + u32 remaining;
> > > + u32 offset;
> > > + struct rbf_info rbfinfo;
> > > +};
> > > +
> > > /* Functions */
> > > int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
> > > int fpgamgr_program_finish(void);
> > > int is_fpgamgr_user_mode(void);
> > > int fpgamgr_wait_early_user_mode(void);
> > > -
> > > +const char *get_fpga_filename(void);
> > > +int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf,
> > > size_t bsize,
> > > + u32 offset);
> > > +void fpgamgr_program(const void *buf, size_t bsize, u32 offset);
> > > #endif /* __ASSEMBLY__ */
> > >
> > > #endif /* _FPGA_MANAGER_ARRIA10_H_ */
> > > diff --git a/drivers/fpga/socfpga_arria10.c
> > > b/drivers/fpga/socfpga_arria10.c
> > > index 9499d1a014..9df2c430d7 100644
> > > --- a/drivers/fpga/socfpga_arria10.c
> > > +++ b/drivers/fpga/socfpga_arria10.c
> > > @@ -1,8 +1,7 @@
> > > // SPDX-License-Identifier: GPL-2.0
> > > /*
> > > - * Copyright (C) 2017 Intel Corporation <www.intel.com>
> > > + * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
> > > */
> > > -
> > > #include <asm/io.h>
> > > #include <asm/arch/fpga_manager.h>
> > > #include <asm/arch/reset_manager.h>
> > > @@ -10,8 +9,11 @@
> > > #include <asm/arch/sdram.h>
> > > #include <asm/arch/misc.h>
> > > #include <altera.h>
> > > +#include <asm/arch/pinmux.h>
> > > #include <common.h>
> > > +#include <dm/ofnode.h>
> > > #include <errno.h>
> > > +#include <fs_loader.h>
> > > #include <wait_bit.h>
> > > #include <watchdog.h>
> > >
> > > @@ -21,6 +23,9 @@
> > > #define COMPRESSION_OFFSET 229
> > > #define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
> > > #define FPGA_TIMEOUT_CNT 0x1000000
> > > +#define DEFAULT_DDR_LOAD_ADDRESS 0x400
> > > +
> > > +DECLARE_GLOBAL_DATA_PTR;
> > >
> > > static const struct socfpga_fpga_manager *fpga_manager_base =
> > > (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
> > > @@ -448,13 +453,461 @@ int fpgamgr_program_finish(void)
> > > return 0;
> > > }
> > >
> > > -/*
> > > - * FPGA Manager to program the FPGA. This is the interface used by
> > > FPGA driver.
> > > - * Return 0 for sucess, non-zero for error.
> > > - */
> > > +ofnode get_fpga_mgr_ofnode(ofnode from)
> > > +{
> > > + return ofnode_by_compatible(from, "altr,socfpga-a10-fpga-
> > > mgr");
> > > +}
> > > +
> > > +const char *get_fpga_filename(void)
> > > +{
> > > + const char *fpga_filename = NULL;
> > > +
> > > + ofnode fpgamgr_node = get_fpga_mgr_ofnode(ofnode_null());
> > > +
> > > + if (ofnode_valid(fpgamgr_node))
> > > + fpga_filename = ofnode_read_string(fpgamgr_node,
> > > + "altr,bitstream");
> > > +
> > > + return fpga_filename;
> > > +}
> > > +
> > > +static void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer)
> > > +{
> > > + /*
> > > + * Magic ID starting at:
> > > + * -> 1st dword[15:0] in periph.rbf
> > > + * -> 2nd dword[15:0] in core.rbf
> > > + * Note: dword == 32 bits
> > > + */
> > > + u32 word_reading_max = 2;
> > > + u32 i;
> > > +
> > > + for (i = 0; i < word_reading_max; i++) {
> > > + if (*(buffer + i) ==
> > > FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
> > > + rbf->security = unencrypted;
> > > + } else if (*(buffer + i) ==
> > > FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
> > > + rbf->security = encrypted;
> > > + } else if (*(buffer + i + 1) ==
> > > + FPGA_SOCFPGA_A10_RBF_UNENCRYPTED)
> > > {
> > > + rbf->security = unencrypted;
> > > + } else if (*(buffer + i + 1) ==
> > > + FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
> > > + rbf->security = encrypted;
> > > + } else {
> > > + rbf->security = invalid;
> > > + continue;
> > > + }
> > > +
> > > + /* PERIPH RBF(buffer + i + 1), CORE RBF(buffer + i
> > > + 2) */
> > > + if (*(buffer + i + 1) ==
> > > FPGA_SOCFPGA_A10_RBF_PERIPH) {
> > > + rbf->section = periph_section;
> > > + break;
> > > + } else if (*(buffer + i + 1) ==
> > > FPGA_SOCFPGA_A10_RBF_CORE) {
> > > + rbf->section = core_section;
> > > + break;
> > > + } else if (*(buffer + i + 2) ==
> > > FPGA_SOCFPGA_A10_RBF_PERIPH) {
> > > + rbf->section = periph_section;
> > > + break;
> > > + } else if (*(buffer + i + 2) ==
> > > FPGA_SOCFPGA_A10_RBF_CORE) {
> > > + rbf->section = core_section;
> > > + break;
> > > + }
> > > +
> > > + rbf->section = unknown;
> > > + break;
> > > +
> > > + WATCHDOG_RESET();
> > > + }
> > > +}
> > > +
> > > +#ifdef CONFIG_FS_LOADER
> > > +static int first_loading_rbf_to_buffer(struct udevice *dev,
> > > + struct fpga_loadfs_info
> > > *fpga_loadfs,
> > > + u32 *buffer, size_t *buffer_bsize)
> > > +{
> > > + u32 *buffer_p = (u32 *)*buffer;
> > > + u32 *loadable = buffer_p;
> > > + size_t buffer_size = *buffer_bsize;
> > > + size_t fit_size;
> > > + int ret, i, count, confs_noffset, images_noffset,
> > > rbf_offset, rbf_size;
> > > + const char *fpga_node_name = NULL;
> > > + const char *uname = NULL;
> > > +
> > > + /* Load image header into buffer */
> > > + ret = request_firmware_into_buf(dev,
> > > + fpga_loadfs->fpga_fsinfo-
> > > >filename,
> > > + buffer_p, sizeof(struct
> > > image_header),
> > > + 0);
> > > + if (ret < 0) {
> > > + debug("FPGA: Failed to read image header from
> > > flash.\n");
> > > + return -ENOENT;
> > > + }
> > > +
> > > + if (image_get_magic((struct image_header *)buffer_p) !=
> > > FDT_MAGIC) {
> > > + debug("FPGA: No FDT magic was found.\n");
> > > + return -EBADF;
> > > + }
> > > +
> > > + fit_size = fdt_totalsize(buffer_p);
> > > +
> > > + if (fit_size > buffer_size) {
> > > + debug("FPGA: FIT image is larger than available
> > > buffer.\n");
> > > + debug("Please use FIT external data or increasing
> > > buffer.\n");
> > > + return -ENOMEM;
> > > + }
> > > +
> > > + /* Load entire FIT into buffer */
> > > + ret = request_firmware_into_buf(dev,
> > > + fpga_loadfs->fpga_fsinfo-
> > > >filename,
> > > + buffer_p, fit_size, 0);
> > > + if (ret < 0)
> > > + return ret;
> > > +
> > > + ret = fit_check_format(buffer_p);
> > > + if (!ret) {
> > > + debug("FPGA: No valid FIT image was found.\n");
> > > + return -EBADF;
> > > + }
> > > +
> > > + confs_noffset = fdt_path_offset(buffer_p, FIT_CONFS_PATH);
> > > + images_noffset = fdt_path_offset(buffer_p,
> > > FIT_IMAGES_PATH);
> > > + if (confs_noffset < 0 || images_noffset < 0) {
> > > + debug("FPGA: No Configurations or images nodes
> > > were found.\n");
> > > + return -ENOENT;
> > > + }
> > > +
> > > + /* Get default configuration unit name from default
> > > property */
> > > + confs_noffset = fit_conf_get_node(buffer_p, NULL);
> > > + if (confs_noffset < 0) {
> > > + debug("FPGA: No default configuration was found in
> > > config.\n");
> > > + return -ENOENT;
> > > + }
> > > +
> > > + count = fit_conf_get_prop_node_count(buffer_p,
> > > confs_noffset,
> > > + FIT_FPGA_PROP);
> > > + if (count < 0) {
> > > + debug("FPGA: Invalid configuration format for FPGA
> > > node.\n");
> > > + return count;
> > > + }
> > > + debug("FPGA: FPGA node count: %d\n", count);
> > > +
> > > + for (i = 0; i < count; i++) {
> > > + images_noffset =
> > > fit_conf_get_prop_node_index(buffer_p,
> > > + confs
> > > _noffset,
> > > + FIT_F
> > > PGA_PROP, i);
> > > + uname = fit_get_name(buffer_p, images_noffset,
> > > NULL);
> > > + if (uname) {
> > > + debug("FPGA: %s\n", uname);
> > > +
> > > + if (strstr(uname, "fpga-periph") &&
> > > + (!is_fpgamgr_early_user_mode() ||
> > > + is_fpgamgr_user_mode())) {
> > > + fpga_node_name = uname;
> > > + printf("FPGA: Start to program ");
> > > + printf("peripheral/full bitstream
> > > ...\n");
> > > + break;
> > > + } else if (strstr(uname, "fpga-core") &&
> > > + (is_fpgamgr_early_user_mod
> > > e() &&
> > > + !is_fpgamgr_user_mode()))
> > > {
> > > + fpga_node_name = uname;
> > > + printf("FPGA: Start to program
> > > core ");
> > > + printf("bitstream ...\n");
> > > + break;
> > > + }
> > > + }
> > > + WATCHDOG_RESET();
> > > + }
> > > +
> > > + if (!fpga_node_name) {
> > > + debug("FPGA: No suitable bitstream was found,
> > > count: %d.\n", i);
> > > + return 1;
> > > + }
> > > +
> > > + images_noffset = fit_image_get_node(buffer_p,
> > > fpga_node_name);
> > > + if (images_noffset < 0) {
> > > + debug("FPGA: No node '%s' was found in FIT.\n",
> > > + fpga_node_name);
> > > + return -ENOENT;
> > > + }
> > > +
> > > + if (!fit_image_get_data_position(buffer_p, images_noffset,
> > > + &rbf_offset)) {
> > > + debug("FPGA: Data position was found.\n");
> > > + } else if (!fit_image_get_data_offset(buffer_p,
> > > images_noffset,
> > > + &rbf_offset)) {
> > > + /*
> > > + * For FIT with external data, figure out where
> > > + * the external images start. This is the base
> > > + * for the data-offset properties in each image.
> > > + */
> > > + rbf_offset += ((fdt_totalsize(buffer_p) + 3) &
> > > ~3);
> > > + debug("FPGA: Data offset was found.\n");
> > > + } else {
> > > + debug("FPGA: No data position/offset was
> > > found.\n");
> > > + return -ENOENT;
> > > + }
> > > +
> > > + ret = fit_image_get_data_size(buffer_p, images_noffset,
> > > &rbf_size);
> > > + if (ret < 0) {
> > > + debug("FPGA: No data size was found (err=%d).\n",
> > > ret);
> > > + return -ENOENT;
> > > + }
> > > +
> > > + if (gd->ram_size < rbf_size) {
> > > + debug("FPGA: Using default OCRAM buffer and
> > > size.\n");
> > > + } else {
> > > + ret = fit_image_get_load(buffer_p, images_noffset,
> > > + (ulong *)loadable);
> > > + if (ret < 0) {
> > > + buffer_p = (u32
> > > *)DEFAULT_DDR_LOAD_ADDRESS;
> > > + debug("FPGA: No loadable was found.\n");
> > > + debug("FPGA: Using default DDR load
> > > address: 0x%x .\n",
> > > + DEFAULT_DDR_LOAD_ADDRESS);
> > > + } else {
> > > + buffer_p = (u32 *)*loadable;
> > > + debug("FPGA: Found loadable address =
> > > 0x%x.\n",
> > > + *loadable);
> > > + }
> > > +
> > > + buffer_size = rbf_size;
> > > + }
> > > +
> > > + debug("FPGA: External data: offset = 0x%x, size =
> > > 0x%x.\n",
> > > + rbf_offset, rbf_size);
> > > +
> > > + fpga_loadfs->remaining = rbf_size;
> > > +
> > > + /*
> > > + * Determine buffer size vs bitstream size, and
> > > calculating number of
> > > + * chunk by chunk transfer is required due to smaller
> > > buffer size
> > > + * compare to bitstream
> > > + */
> > > + if (rbf_size <= buffer_size) {
> > > + /* Loading whole bitstream into buffer */
> > > + buffer_size = rbf_size;
> > > + fpga_loadfs->remaining = 0;
> > > + } else {
> > > + fpga_loadfs->remaining -= buffer_size;
> > > + }
> > > +
> > > + fpga_loadfs->offset = rbf_offset;
> > > + /* Loading bitstream into buffer */
> > > + ret = request_firmware_into_buf(dev,
> > > + fpga_loadfs->fpga_fsinfo-
> > > >filename,
> > > + buffer_p, buffer_size,
> > > + fpga_loadfs->offset);
> > > + if (ret < 0) {
> > > + debug("FPGA: Failed to read bitstream from
> > > flash.\n");
> > > + return -ENOENT;
> > > + }
> > > +
> > > + /* Getting info about bitstream types */
> > > + get_rbf_image_info(&fpga_loadfs->rbfinfo, (u16
> > > *)buffer_p);
> > > +
> > > + /* Update next reading bitstream offset */
> > > + fpga_loadfs->offset += buffer_size;
> > > +
> > > + /* Update the final addr for bitstream */
> > > + *buffer = (u32)buffer_p;
> > > +
> > > + /* Update the size of bitstream to be programmed into FPGA
> > > */
> > > + *buffer_bsize = buffer_size;
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int subsequent_loading_rbf_to_buffer(struct udevice *dev,
> > > + struct fpga_loadfs_info
> > > *fpga_loadfs,
> > > + u32 *buffer, size_t
> > > *buffer_bsize)
> > > +{
> > > + int ret = 0;
> > > + u32 *buffer_p = (u32 *)*buffer;
> > > +
> > > + /* Read the bitstream chunk by chunk. */
> > > + if (fpga_loadfs->remaining > *buffer_bsize) {
> > > + fpga_loadfs->remaining -= *buffer_bsize;
> > > + } else {
> > > + *buffer_bsize = fpga_loadfs->remaining;
> > > + fpga_loadfs->remaining = 0;
> > > + }
> > > +
> > > + ret = request_firmware_into_buf(dev,
> > > + fpga_loadfs->fpga_fsinfo-
> > > >filename,
> > > + buffer_p, *buffer_bsize,
> > > + fpga_loadfs->offset);
> > > + if (ret < 0) {
> > > + debug("FPGA: Failed to read bitstream from
> > > flash.\n");
> > > + return -ENOENT;
> > > + }
> > > +
> > > + /* Update next reading bitstream offset */
> > > + fpga_loadfs->offset += *buffer_bsize;
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf,
> > > size_t bsize,
> > > + u32 offset)
> > > +{
> > > + struct fpga_loadfs_info fpga_loadfs;
> > > + struct udevice *dev;
> > > + int status, ret, size;
> > > + u32 buffer = (uintptr_t)buf;
> > > + size_t buffer_sizebytes = bsize;
> > > + size_t buffer_sizebytes_ori = bsize;
> > > + size_t total_sizeof_image = 0;
> > > + ofnode node;
> > > + const fdt32_t *phandle_p;
> > > + u32 phandle;
> > > +
> > > + node = get_fpga_mgr_ofnode(ofnode_null());
> > > +
> > > + if (ofnode_valid(node)) {
> > > + phandle_p = ofnode_get_property(node, "firmware-
> > > loader", &size);
> > > + if (!phandle_p) {
> > > + node = ofnode_path("/chosen");
> > > + if (!ofnode_valid(node)) {
> > > + debug("FPGA: /chosen node was not
> > > found.\n");
> > > + return -ENOENT;
> > > + }
> > > +
> > > + phandle_p = ofnode_get_property(node,
> > > "firmware-loader",
> > > + &size);
> > > + if (!phandle_p) {
> > > + debug("FPGA: firmware-loader
> > > property was not");
> > > + debug(" found.\n");
> > > + return -ENOENT;
> > > + }
> > > + }
> > > + } else {
> > > + debug("FPGA: FPGA manager node was not found.\n");
> > > + return -ENOENT;
> > > + }
> > > +
> > > + phandle = fdt32_to_cpu(*phandle_p);
> > > + ret =
> > > uclass_get_device_by_phandle_id(UCLASS_FS_FIRMWARE_LOADER,
> > > + phandle, &dev);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + memset(&fpga_loadfs, 0, sizeof(fpga_loadfs));
> > > +
> > > + fpga_loadfs.fpga_fsinfo = fpga_fsinfo;
> > > + fpga_loadfs.offset = offset;
> > > +
> > > + printf("FPGA: Checking FPGA configuration setting ...\n");
> > > +
> > > + /*
> > > + * Note: Both buffer and buffer_sizebytes values can be
> > > altered by
> > > + * function below.
> > > + */
> > > + ret = first_loading_rbf_to_buffer(dev, &fpga_loadfs,
> > > &buffer,
> > > + &buffer_sizebytes);
> > > + if (ret == 1) {
> > > + printf("FPGA: Skipping configuration ...\n");
> > > + return 0;
> > > + } else if (ret) {
> > > + return ret;
> > > + }
> > > +
> > > + if (fpga_loadfs.rbfinfo.section == core_section &&
> > > + !(is_fpgamgr_early_user_mode() &&
> > > !is_fpgamgr_user_mode())) {
> > > + debug("FPGA : Must be in Early Release mode to
> > > program ");
> > > + debug("core bitstream.\n");
> > > + return -EPERM;
> > > + }
> > > +
> > > + /* Disable all signals from HPS peripheral controller to
> > > FPGA */
> > > + writel(0, &system_manager_base->fpgaintf_en_global);
> > > +
> > > + /* Disable all axi bridges (hps2fpga, lwhps2fpga &
> > > fpga2hps) */
> > > + socfpga_bridges_reset();
> > > +
> > > + if (fpga_loadfs.rbfinfo.section == periph_section) {
> > > + /* Initialize the FPGA Manager */
> > > + status = fpgamgr_program_init((u32 *)buffer,
> > > buffer_sizebytes);
> > > + if (status) {
> > > + debug("FPGA: Init with peripheral
> > > bitstream failed.\n");
> > > + return -EPERM;
> > > + }
> > > + }
> > > +
> > > + /* Transfer bitstream to FPGA Manager */
> > > + fpgamgr_program_write((void *)buffer, buffer_sizebytes);
> > > +
> > > + total_sizeof_image += buffer_sizebytes;
> > > +
> > > + while (fpga_loadfs.remaining) {
> > > + ret = subsequent_loading_rbf_to_buffer(dev,
> > > + &fpga_load
> > > fs,
> > > + &buffer,
> > > + &buffer_si
> > > zebytes_ori);
> > > +
> > > + if (ret)
> > > + return ret;
> > > +
> > > + /* Transfer data to FPGA Manager */
> > > + fpgamgr_program_write((void *)buffer,
> > > + buffer_sizebytes_ori);
> > > +
> > > + total_sizeof_image += buffer_sizebytes_ori;
> > > +
> > > + WATCHDOG_RESET();
> > > + }
> > > +
> > > + if (fpga_loadfs.rbfinfo.section == periph_section) {
> > > + if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT)
> > > {
> > > + config_pins(gd->fdt_blob, "shared");
> > > + puts("FPGA: Early Release Succeeded.\n");
> > > + } else {
> > > + debug("FPGA: Failed to see Early
> > > Release.\n");
> > > + return -EIO;
> > > + }
> > > +
> > > + /* For monolithic bitstream */
> > > + if (is_fpgamgr_user_mode()) {
> > > + /* Ensure the FPGA entering config done */
> > > + status = fpgamgr_program_finish();
> > > + if (status)
> > > + return status;
> > > +
> > > + config_pins(gd->fdt_blob, "fpga");
> > > + puts("FPGA: Enter user mode.\n");
> > > + }
> > > + } else if (fpga_loadfs.rbfinfo.section == core_section) {
> > > + /* Ensure the FPGA entering config done */
> > > + status = fpgamgr_program_finish();
> > > + if (status)
> > > + return status;
> > > +
> > > + config_pins(gd->fdt_blob, "fpga");
> > > + puts("FPGA: Enter user mode.\n");
> > > + } else {
> > > + debug("FPGA: Config Error: Unsupported bitstream
> > > type.\n");
> > > + return -ENOEXEC;
> > > + }
> > > +
> > > + return (int)total_sizeof_image;
> > > +}
> > > +
> > > +void fpgamgr_program(const void *buf, size_t bsize, u32 offset)
> > > +{
> > > + fpga_fs_info fpga_fsinfo;
> > > +
> > > + fpga_fsinfo.filename = get_fpga_filename();
> > > +
> > > + if (fpga_fsinfo.filename)
> > > + socfpga_loadfs(&fpga_fsinfo, buf, bsize, offset);
> > > +}
> > > +#endif
> > > +
> > > +/* This function is used to load the core bitstream from the
> > > OCRAM. */
> > > int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t
> > > rbf_size)
> > > {
> > > - int status;
> > > + unsigned long status;
> > > + struct rbf_info rbfinfo;
> > > +
> > > + memset(&rbfinfo, 0, sizeof(rbfinfo));
> > >
> > > /* Disable all signals from hps peripheral controller to
> > > fpga */
> > > writel(0, &system_manager_base->fpgaintf_en_global);
> > > @@ -462,13 +915,31 @@ int socfpga_load(Altera_desc *desc, const
> > > void *rbf_data, size_t rbf_size)
> > > /* Disable all axi bridge (hps2fpga, lwhps2fpga &
> > > fpga2hps) */
> > > socfpga_bridges_reset();
> > >
> > > - /* Initialize the FPGA Manager */
> > > - status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
> > > - if (status)
> > > - return status;
> > > + /* Getting info about bitstream types */
> > > + get_rbf_image_info(&rbfinfo, (u16 *)rbf_data);
> > > +
> > > + if (rbfinfo.section == periph_section) {
> > > + /* Initialize the FPGA Manager */
> > > + status = fpgamgr_program_init((u32 *)rbf_data,
> > > rbf_size);
> > > + if (status)
> > > + return status;
> > > + }
> > >
> > > - /* Write the RBF data to FPGA Manager */
> > > + if (rbfinfo.section == core_section &&
> > > + !(is_fpgamgr_early_user_mode() &&
> > > !is_fpgamgr_user_mode())) {
> > > + debug("FPGA : Must be in early release mode to
> > > program ");
> > > + debug("core bitstream.\n");
> > > + return -EPERM;
> > > + }
> > > +
> > > + /* Write the bitstream to FPGA Manager */
> > > fpgamgr_program_write(rbf_data, rbf_size);
> > >
> > > - return fpgamgr_program_finish();
> > > + status = fpgamgr_program_finish();
> > > + if (status) {
> > > + config_pins(gd->fdt_blob, "fpga");
> > > + puts("FPGA: Enter user mode.\n");
> > > + }
> > > +
> > > + return status;
> > > }
> > > diff --git a/include/image.h b/include/image.h
> > > index 765ffecee0..cc976f70ce 100644
> > > --- a/include/image.h
> > > +++ b/include/image.h
> > > @@ -1046,6 +1046,10 @@ int fit_check_format(const void *fit);
> > >
> > > int fit_conf_find_compat(const void *fit, const void *fdt);
> > > int fit_conf_get_node(const void *fit, const char *conf_uname);
> > > +int fit_conf_get_prop_node_count(const void *fit, int noffset,
> > > + const char *prop_name);
> > > +int fit_conf_get_prop_node_index(const void *fit, int noffset,
> > > + const char *prop_name, int index);
> > >
> > > /**
> > > * fit_conf_get_prop_node() - Get node refered to by a
> > > configuration
> > >
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v12 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL
2019-04-30 12:13 ` Chee, Tien Fong
@ 2019-04-30 12:26 ` Simon Goldschmidt
2019-05-02 7:56 ` Chee, Tien Fong
0 siblings, 1 reply; 27+ messages in thread
From: Simon Goldschmidt @ 2019-04-30 12:26 UTC (permalink / raw)
To: u-boot
On Tue, Apr 30, 2019 at 2:19 PM Chee, Tien Fong
<tien.fong.chee@intel.com> wrote:
>
> On Sat, 2019-04-27 at 21:50 +0200, Simon Goldschmidt wrote:
> >
> > On 19.03.19 09:50, tien.fong.chee at intel.com wrote:
> > >
> > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > >
> > > Increasing Malloc pool size up to 0x15000 is required to support
> > > FAT in SPL
> > > . The result of calculation is come from after applying some few
> > > patches
> > "Some few patches"? What should that mean? Either you refer to the
> > current state or you can refer to the patchwork items.
> >
> > >
> > > which are required for optimizing vfat and maximizing resusable of
> > > the
> > > memory pool, and then followed by the size required come from
> > > default max
> > > cluster(0x10000) + others(0x2000) + additional memory for
> > > headroom(0x3000).
> > > Previous records of describing these few patches can be checked
> > > from here
> > > [v7]: https://www.mail-archive.com/u-boot at lists.denx.de/msg314511.h
> > > tml .
> > Why do you refer to mail-archive.com instead of patchwork?
> Contains the cover letter in case reviewer need to know more
> information.
I think you understood that wrong. Why do you reference a 3rd party
host (mail-archive.com) instead of the official list archive or patchwork?
And please note patchwork keeps the cover letter as well.
Also note, this is the commit message which will got into the git lot.
Referencing v7 and older history seems misplaced here. Better move
it below the '---'.
Regards,
Simon
>
> Thanks.
> >
> > >
> > >
> > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > >
> > > ---
> > >
> > > changes for v12
> > > - Improved the commit messages.
> > >
> > > changes for v11
> > > - No changes.
> > >
> > > changes for v10
> > > - No changes.
> > >
> > > changes for v9
> > > - No changes.
> > >
> > > changes for v8
> > > - Moved the FIT related configs to the patch of configuration for
> > > FPGA
> > > SoCFPGA A10 SoCDK.
> > >
> > > changes for v7
> > > - Keep minimal configs.
> > > ---
> > > include/configs/socfpga_common.h | 4 ++--
> > > 1 file changed, 2 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/include/configs/socfpga_common.h
> > > b/include/configs/socfpga_common.h
> > > index 181af9b646..22533036ed 100644
> > > --- a/include/configs/socfpga_common.h
> > > +++ b/include/configs/socfpga_common.h
> > > @@ -1,6 +1,6 @@
> > > /* SPDX-License-Identifier: GPL-2.0+ */
> > > /*
> > > - * Copyright (C) 2012 Altera Corporation <www.altera.com>
> > > + * Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
> > > */
> > > #ifndef __CONFIG_SOCFPGA_COMMON_H__
> > > #define __CONFIG_SOCFPGA_COMMON_H__
> > > @@ -254,7 +254,7 @@ unsigned int
> > > cm_get_qspi_controller_clk_hz(void);
> > > #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > /* SPL memory allocation configuration, this is for FAT
> > > implementation */
> > > #ifndef CONFIG_SYS_SPL_MALLOC_START
> > > -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
> > > +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00015000
> > > #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_S
> > > IZE - \
> > > CONFIG_SYS_SPL_MALLOC_SI
> > > ZE + \
> > > CONFIG_SYS_INIT_RAM_ADDR
> > > )
> > >
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v12 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
2019-04-30 12:24 ` Simon Goldschmidt
@ 2019-05-02 7:49 ` Chee, Tien Fong
2019-05-03 11:26 ` Simon Goldschmidt
0 siblings, 1 reply; 27+ messages in thread
From: Chee, Tien Fong @ 2019-05-02 7:49 UTC (permalink / raw)
To: u-boot
On Tue, 2019-04-30 at 14:24 +0200, Simon Goldschmidt wrote:
> On Tue, Apr 30, 2019 at 2:09 PM Chee, Tien Fong
> <tien.fong.chee@intel.com> wrote:
> >
> >
> > On Sat, 2019-04-27 at 21:57 +0200, Simon Goldschmidt wrote:
> > >
> > >
> > > On 19.03.19 09:50, tien.fong.chee at intel.com wrote:
> > > >
> > > >
> > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > >
> > > > Add FPGA driver to support program FPGA with FPGA bitstream
> > > > loading
> > > > from
> > > > filesystem. The driver are designed based on generic firmware
> > > > loader
> > > > framework. The driver can handle FPGA program operation from
> > > > loading FPGA
> > > > bitstream in flash to memory and then to program FPGA.
> > > >
> > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > >
> > > > ---
> > > >
> > > > changes for v12
> > > > - No changes.
> > > >
> > > > changes for v11
> > > > - No changes.
> > > >
> > > > changes for v10
> > > > -Cleaned up the codes.
> > > > -Return -EPERM when programing core on non early IO release
> > > > mode. >
> > > > -Using live function to get rid of gd->
> > > You got rid of gd-> in v10? How come I see numerous references to
> > > it
> > > below?
> > get rid of using gd->fdt_blob for finding the node_offset.
> > Details in https://patchwork.ozlabs.org/patch/1044415/
> Ah, ok. But still, here you're introducing yet more references to gd-
> >fdt_blob.
> That wouldn't work with a live tree, either, or would it?
Yeah, few direct call to config_pin function are still using gd-
fdt_blob as argument. But, i'm not sure i should fix this function in
this series patch set, or separately patch after this series patch set?
What do you think?
Thanks,
TF
>
> >
> >
> > -/*
> > - * FPGA Manager to program the FPGA. This is the interface used by
> > FPGA driver.
> > - * Return 0 for sucess, non-zero for error.
> > - */
> > +ofnode get_fpga_mgr_ofnode(void)
> > +{
> > + int node_offset;
> > +
> > + fdtdec_find_aliases_for_id(gd->fdt_blob, "fpga_mgr",
> >
> > nit: using of live functions would be better to get rid of gd->.
> >
> > + COMPAT_ALTERA_SOCFPGA_FPGA0,
> > + &node_offset, 1);
> >
> > Thanks.
> > >
> > >
> > > >
> > > >
> > > > -Removed @0 for fs-loader node
> > > >
> > > > changes for v9
> > > > - Support data offset
> > > > - Added default DDR load address
> > > > - Squashed the image.h
> > > > - Changed to phandle
> > > > - Ensure the DDR is fully up running by checking the gd->ram
> > > >
> > > > changes for v8
> > > > - Added codes to discern bitstream type based on fpga node
> > > > name.
> > > >
> > > > changes for v7
> > > > - Restructure the FPGA driver to support both peripheral
> > > > bitstream
> > > > and core
> > > > bitstream bundled into FIT image.
> > > > - Support loadable property for core bitstream. User can set
> > > > loadable
> > > > in DDR for better performance. This loading would be done in
> > > > one
> > > > large
> > > > chunk instead of chunk by chunk loading with small memory
> > > > buffer.
> > > > ---
> > > > arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +
> > > > .../include/mach/fpga_manager_arria10.h | 39 +-
> > > > drivers/fpga/socfpga_arria10.c | 497
> > > > ++++++++++++++++++++-
> > > > include/image.h | 4 +
> > > > 4 files changed, 542 insertions(+), 15 deletions(-)
> > > >
> > > > diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > index 998d811210..cc761967c7 100644
> > > > --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > @@ -18,6 +18,23 @@
> > > > /dts-v1/;
> > > > #include "socfpga_arria10_socdk.dtsi"
> > > >
> > > > +/ {
> > > > + chosen {
> > > > + firmware-loader = <&fs_loader0>;
> > > > + };
> > > > +
> > > > + fs_loader0: fs-loader {
> > > > + u-boot,dm-pre-reloc;
> > > > + compatible = "u-boot,fs-loader";
> > > > + phandlepart = <&mmc 1>;
> > > > + };
> > > > +};
> > > > +
> > > > +&fpga_mgr {
> > > > + u-boot,dm-pre-reloc;
> > > > + altr,bitstream = "fit_spl_fpga.itb";
> > > > +};
> > > > +
> > > > &mmc {
> > > > u-boot,dm-pre-reloc;
> > > > status = "okay";
> > > > diff --git a/arch/arm/mach-
> > > > socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-
> > > > socfpga/include/mach/fpga_manager_arria10.h
> > > > index 09d13f6fd3..c5f67714aa 100644
> > > > --- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> > > > +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> > > > @@ -1,9 +1,13 @@
> > > > /* SPDX-License-Identifier: GPL-2.0 */
> > > > /*
> > > > - * Copyright (C) 2017 Intel Corporation <www.intel.com>
> > > > + * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
> > > > * All rights reserved.
> > > > */
> > > >
> > > > +#include <asm/cache.h>
> > > > +#include <altera.h>
> > > > +#include <image.h>
> > > > +
> > > > #ifndef _FPGA_MANAGER_ARRIA10_H_
> > > > #define _FPGA_MANAGER_ARRIA10_H_
> > > >
> > > > @@ -51,6 +55,10 @@
> > > > #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK
> > > > BIT(24)
> > > > #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB
> > > > 16
> > > >
> > > > +#define FPGA_SOCFPGA_A10_RBF_UNENCRYPTED 0xa65c
> > > > +#define FPGA_SOCFPGA_A10_RBF_ENCRYPTED 0xa65d
> > > > +#define FPGA_SOCFPGA_A10_RBF_PERIPH 0x0001
> > > > +#define FPGA_SOCFPGA_A10_RBF_CORE 0x8001
> > > > #ifndef __ASSEMBLY__
> > > >
> > > > struct socfpga_fpga_manager {
> > > > @@ -88,12 +96,39 @@ struct socfpga_fpga_manager {
> > > > u32 imgcfg_fifo_status;
> > > > };
> > > >
> > > > +enum rbf_type {
> > > > + unknown,
> > > > + periph_section,
> > > > + core_section
> > > > +};
> > > > +
> > > > +enum rbf_security {
> > > > + invalid,
> > > > + unencrypted,
> > > > + encrypted
> > > > +};
> > > > +
> > > > +struct rbf_info {
> > > > + enum rbf_type section;
> > > > + enum rbf_security security;
> > > > +};
> > > > +
> > > > +struct fpga_loadfs_info {
> > > > + fpga_fs_info *fpga_fsinfo;
> > > > + u32 remaining;
> > > > + u32 offset;
> > > > + struct rbf_info rbfinfo;
> > > > +};
> > > > +
> > > > /* Functions */
> > > > int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
> > > > int fpgamgr_program_finish(void);
> > > > int is_fpgamgr_user_mode(void);
> > > > int fpgamgr_wait_early_user_mode(void);
> > > > -
> > > > +const char *get_fpga_filename(void);
> > > > +int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf,
> > > > size_t bsize,
> > > > + u32 offset);
> > > > +void fpgamgr_program(const void *buf, size_t bsize, u32
> > > > offset);
> > > > #endif /* __ASSEMBLY__ */
> > > >
> > > > #endif /* _FPGA_MANAGER_ARRIA10_H_ */
> > > > diff --git a/drivers/fpga/socfpga_arria10.c
> > > > b/drivers/fpga/socfpga_arria10.c
> > > > index 9499d1a014..9df2c430d7 100644
> > > > --- a/drivers/fpga/socfpga_arria10.c
> > > > +++ b/drivers/fpga/socfpga_arria10.c
> > > > @@ -1,8 +1,7 @@
> > > > // SPDX-License-Identifier: GPL-2.0
> > > > /*
> > > > - * Copyright (C) 2017 Intel Corporation <www.intel.com>
> > > > + * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
> > > > */
> > > > -
> > > > #include <asm/io.h>
> > > > #include <asm/arch/fpga_manager.h>
> > > > #include <asm/arch/reset_manager.h>
> > > > @@ -10,8 +9,11 @@
> > > > #include <asm/arch/sdram.h>
> > > > #include <asm/arch/misc.h>
> > > > #include <altera.h>
> > > > +#include <asm/arch/pinmux.h>
> > > > #include <common.h>
> > > > +#include <dm/ofnode.h>
> > > > #include <errno.h>
> > > > +#include <fs_loader.h>
> > > > #include <wait_bit.h>
> > > > #include <watchdog.h>
> > > >
> > > > @@ -21,6 +23,9 @@
> > > > #define COMPRESSION_OFFSET 229
> > > > #define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
> > > > #define FPGA_TIMEOUT_CNT 0x1000000
> > > > +#define DEFAULT_DDR_LOAD_ADDRESS 0x400
> > > > +
> > > > +DECLARE_GLOBAL_DATA_PTR;
> > > >
> > > > static const struct socfpga_fpga_manager *fpga_manager_base =
> > > > (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
> > > > @@ -448,13 +453,461 @@ int fpgamgr_program_finish(void)
> > > > return 0;
> > > > }
> > > >
> > > > -/*
> > > > - * FPGA Manager to program the FPGA. This is the interface
> > > > used by
> > > > FPGA driver.
> > > > - * Return 0 for sucess, non-zero for error.
> > > > - */
> > > > +ofnode get_fpga_mgr_ofnode(ofnode from)
> > > > +{
> > > > + return ofnode_by_compatible(from, "altr,socfpga-a10-fpga-
> > > > mgr");
> > > > +}
> > > > +
> > > > +const char *get_fpga_filename(void)
> > > > +{
> > > > + const char *fpga_filename = NULL;
> > > > +
> > > > + ofnode fpgamgr_node = get_fpga_mgr_ofnode(ofnode_null());
> > > > +
> > > > + if (ofnode_valid(fpgamgr_node))
> > > > + fpga_filename = ofnode_read_string(fpgamgr_node,
> > > > + "altr,bitstream");
> > > > +
> > > > + return fpga_filename;
> > > > +}
> > > > +
> > > > +static void get_rbf_image_info(struct rbf_info *rbf, u16
> > > > *buffer)
> > > > +{
> > > > + /*
> > > > + * Magic ID starting at:
> > > > + * -> 1st dword[15:0] in periph.rbf
> > > > + * -> 2nd dword[15:0] in core.rbf
> > > > + * Note: dword == 32 bits
> > > > + */
> > > > + u32 word_reading_max = 2;
> > > > + u32 i;
> > > > +
> > > > + for (i = 0; i < word_reading_max; i++) {
> > > > + if (*(buffer + i) ==
> > > > FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
> > > > + rbf->security = unencrypted;
> > > > + } else if (*(buffer + i) ==
> > > > FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
> > > > + rbf->security = encrypted;
> > > > + } else if (*(buffer + i + 1) ==
> > > > + FPGA_SOCFPGA_A10_RBF_UNENCRYPTED)
> > > > {
> > > > + rbf->security = unencrypted;
> > > > + } else if (*(buffer + i + 1) ==
> > > > + FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
> > > > + rbf->security = encrypted;
> > > > + } else {
> > > > + rbf->security = invalid;
> > > > + continue;
> > > > + }
> > > > +
> > > > + /* PERIPH RBF(buffer + i + 1), CORE RBF(buffer + i
> > > > + 2) */
> > > > + if (*(buffer + i + 1) ==
> > > > FPGA_SOCFPGA_A10_RBF_PERIPH) {
> > > > + rbf->section = periph_section;
> > > > + break;
> > > > + } else if (*(buffer + i + 1) ==
> > > > FPGA_SOCFPGA_A10_RBF_CORE) {
> > > > + rbf->section = core_section;
> > > > + break;
> > > > + } else if (*(buffer + i + 2) ==
> > > > FPGA_SOCFPGA_A10_RBF_PERIPH) {
> > > > + rbf->section = periph_section;
> > > > + break;
> > > > + } else if (*(buffer + i + 2) ==
> > > > FPGA_SOCFPGA_A10_RBF_CORE) {
> > > > + rbf->section = core_section;
> > > > + break;
> > > > + }
> > > > +
> > > > + rbf->section = unknown;
> > > > + break;
> > > > +
> > > > + WATCHDOG_RESET();
> > > > + }
> > > > +}
> > > > +
> > > > +#ifdef CONFIG_FS_LOADER
> > > > +static int first_loading_rbf_to_buffer(struct udevice *dev,
> > > > + struct fpga_loadfs_info
> > > > *fpga_loadfs,
> > > > + u32 *buffer, size_t *buffer_bsize)
> > > > +{
> > > > + u32 *buffer_p = (u32 *)*buffer;
> > > > + u32 *loadable = buffer_p;
> > > > + size_t buffer_size = *buffer_bsize;
> > > > + size_t fit_size;
> > > > + int ret, i, count, confs_noffset, images_noffset,
> > > > rbf_offset, rbf_size;
> > > > + const char *fpga_node_name = NULL;
> > > > + const char *uname = NULL;
> > > > +
> > > > + /* Load image header into buffer */
> > > > + ret = request_firmware_into_buf(dev,
> > > > + fpga_loadfs->fpga_fsinfo-
> > > > >
> > > > > filename,
> > > > + buffer_p, sizeof(struct
> > > > image_header),
> > > > + 0);
> > > > + if (ret < 0) {
> > > > + debug("FPGA: Failed to read image header from
> > > > flash.\n");
> > > > + return -ENOENT;
> > > > + }
> > > > +
> > > > + if (image_get_magic((struct image_header *)buffer_p) !=
> > > > FDT_MAGIC) {
> > > > + debug("FPGA: No FDT magic was found.\n");
> > > > + return -EBADF;
> > > > + }
> > > > +
> > > > + fit_size = fdt_totalsize(buffer_p);
> > > > +
> > > > + if (fit_size > buffer_size) {
> > > > + debug("FPGA: FIT image is larger than available
> > > > buffer.\n");
> > > > + debug("Please use FIT external data or increasing
> > > > buffer.\n");
> > > > + return -ENOMEM;
> > > > + }
> > > > +
> > > > + /* Load entire FIT into buffer */
> > > > + ret = request_firmware_into_buf(dev,
> > > > + fpga_loadfs->fpga_fsinfo-
> > > > >
> > > > > filename,
> > > > + buffer_p, fit_size, 0);
> > > > + if (ret < 0)
> > > > + return ret;
> > > > +
> > > > + ret = fit_check_format(buffer_p);
> > > > + if (!ret) {
> > > > + debug("FPGA: No valid FIT image was found.\n");
> > > > + return -EBADF;
> > > > + }
> > > > +
> > > > + confs_noffset = fdt_path_offset(buffer_p, FIT_CONFS_PATH);
> > > > + images_noffset = fdt_path_offset(buffer_p,
> > > > FIT_IMAGES_PATH);
> > > > + if (confs_noffset < 0 || images_noffset < 0) {
> > > > + debug("FPGA: No Configurations or images nodes
> > > > were found.\n");
> > > > + return -ENOENT;
> > > > + }
> > > > +
> > > > + /* Get default configuration unit name from default
> > > > property */
> > > > + confs_noffset = fit_conf_get_node(buffer_p, NULL);
> > > > + if (confs_noffset < 0) {
> > > > + debug("FPGA: No default configuration was found in
> > > > config.\n");
> > > > + return -ENOENT;
> > > > + }
> > > > +
> > > > + count = fit_conf_get_prop_node_count(buffer_p,
> > > > confs_noffset,
> > > > + FIT_FPGA_PROP);
> > > > + if (count < 0) {
> > > > + debug("FPGA: Invalid configuration format for FPGA
> > > > node.\n");
> > > > + return count;
> > > > + }
> > > > + debug("FPGA: FPGA node count: %d\n", count);
> > > > +
> > > > + for (i = 0; i < count; i++) {
> > > > + images_noffset =
> > > > fit_conf_get_prop_node_index(buffer_p,
> > > > + confs
> > > > _noffset,
> > > > + FIT_F
> > > > PGA_PROP, i);
> > > > + uname = fit_get_name(buffer_p, images_noffset,
> > > > NULL);
> > > > + if (uname) {
> > > > + debug("FPGA: %s\n", uname);
> > > > +
> > > > + if (strstr(uname, "fpga-periph") &&
> > > > + (!is_fpgamgr_early_user_mode() ||
> > > > + is_fpgamgr_user_mode())) {
> > > > + fpga_node_name = uname;
> > > > + printf("FPGA: Start to program ");
> > > > + printf("peripheral/full bitstream
> > > > ...\n");
> > > > + break;
> > > > + } else if (strstr(uname, "fpga-core") &&
> > > > + (is_fpgamgr_early_user_mod
> > > > e() &&
> > > > + !is_fpgamgr_user_mode()))
> > > > {
> > > > + fpga_node_name = uname;
> > > > + printf("FPGA: Start to program
> > > > core ");
> > > > + printf("bitstream ...\n");
> > > > + break;
> > > > + }
> > > > + }
> > > > + WATCHDOG_RESET();
> > > > + }
> > > > +
> > > > + if (!fpga_node_name) {
> > > > + debug("FPGA: No suitable bitstream was found,
> > > > count: %d.\n", i);
> > > > + return 1;
> > > > + }
> > > > +
> > > > + images_noffset = fit_image_get_node(buffer_p,
> > > > fpga_node_name);
> > > > + if (images_noffset < 0) {
> > > > + debug("FPGA: No node '%s' was found in FIT.\n",
> > > > + fpga_node_name);
> > > > + return -ENOENT;
> > > > + }
> > > > +
> > > > + if (!fit_image_get_data_position(buffer_p, images_noffset,
> > > > + &rbf_offset)) {
> > > > + debug("FPGA: Data position was found.\n");
> > > > + } else if (!fit_image_get_data_offset(buffer_p,
> > > > images_noffset,
> > > > + &rbf_offset)) {
> > > > + /*
> > > > + * For FIT with external data, figure out where
> > > > + * the external images start. This is the base
> > > > + * for the data-offset properties in each image.
> > > > + */
> > > > + rbf_offset += ((fdt_totalsize(buffer_p) + 3) &
> > > > ~3);
> > > > + debug("FPGA: Data offset was found.\n");
> > > > + } else {
> > > > + debug("FPGA: No data position/offset was
> > > > found.\n");
> > > > + return -ENOENT;
> > > > + }
> > > > +
> > > > + ret = fit_image_get_data_size(buffer_p, images_noffset,
> > > > &rbf_size);
> > > > + if (ret < 0) {
> > > > + debug("FPGA: No data size was found (err=%d).\n",
> > > > ret);
> > > > + return -ENOENT;
> > > > + }
> > > > +
> > > > + if (gd->ram_size < rbf_size) {
> > > > + debug("FPGA: Using default OCRAM buffer and
> > > > size.\n");
> > > > + } else {
> > > > + ret = fit_image_get_load(buffer_p, images_noffset,
> > > > + (ulong *)loadable);
> > > > + if (ret < 0) {
> > > > + buffer_p = (u32
> > > > *)DEFAULT_DDR_LOAD_ADDRESS;
> > > > + debug("FPGA: No loadable was found.\n");
> > > > + debug("FPGA: Using default DDR load
> > > > address: 0x%x .\n",
> > > > + DEFAULT_DDR_LOAD_ADDRESS);
> > > > + } else {
> > > > + buffer_p = (u32 *)*loadable;
> > > > + debug("FPGA: Found loadable address =
> > > > 0x%x.\n",
> > > > + *loadable);
> > > > + }
> > > > +
> > > > + buffer_size = rbf_size;
> > > > + }
> > > > +
> > > > + debug("FPGA: External data: offset = 0x%x, size =
> > > > 0x%x.\n",
> > > > + rbf_offset, rbf_size);
> > > > +
> > > > + fpga_loadfs->remaining = rbf_size;
> > > > +
> > > > + /*
> > > > + * Determine buffer size vs bitstream size, and
> > > > calculating number of
> > > > + * chunk by chunk transfer is required due to smaller
> > > > buffer size
> > > > + * compare to bitstream
> > > > + */
> > > > + if (rbf_size <= buffer_size) {
> > > > + /* Loading whole bitstream into buffer */
> > > > + buffer_size = rbf_size;
> > > > + fpga_loadfs->remaining = 0;
> > > > + } else {
> > > > + fpga_loadfs->remaining -= buffer_size;
> > > > + }
> > > > +
> > > > + fpga_loadfs->offset = rbf_offset;
> > > > + /* Loading bitstream into buffer */
> > > > + ret = request_firmware_into_buf(dev,
> > > > + fpga_loadfs->fpga_fsinfo-
> > > > >
> > > > > filename,
> > > > + buffer_p, buffer_size,
> > > > + fpga_loadfs->offset);
> > > > + if (ret < 0) {
> > > > + debug("FPGA: Failed to read bitstream from
> > > > flash.\n");
> > > > + return -ENOENT;
> > > > + }
> > > > +
> > > > + /* Getting info about bitstream types */
> > > > + get_rbf_image_info(&fpga_loadfs->rbfinfo, (u16
> > > > *)buffer_p);
> > > > +
> > > > + /* Update next reading bitstream offset */
> > > > + fpga_loadfs->offset += buffer_size;
> > > > +
> > > > + /* Update the final addr for bitstream */
> > > > + *buffer = (u32)buffer_p;
> > > > +
> > > > + /* Update the size of bitstream to be programmed into FPGA
> > > > */
> > > > + *buffer_bsize = buffer_size;
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static int subsequent_loading_rbf_to_buffer(struct udevice
> > > > *dev,
> > > > + struct fpga_loadfs_info
> > > > *fpga_loadfs,
> > > > + u32 *buffer, size_t
> > > > *buffer_bsize)
> > > > +{
> > > > + int ret = 0;
> > > > + u32 *buffer_p = (u32 *)*buffer;
> > > > +
> > > > + /* Read the bitstream chunk by chunk. */
> > > > + if (fpga_loadfs->remaining > *buffer_bsize) {
> > > > + fpga_loadfs->remaining -= *buffer_bsize;
> > > > + } else {
> > > > + *buffer_bsize = fpga_loadfs->remaining;
> > > > + fpga_loadfs->remaining = 0;
> > > > + }
> > > > +
> > > > + ret = request_firmware_into_buf(dev,
> > > > + fpga_loadfs->fpga_fsinfo-
> > > > >
> > > > > filename,
> > > > + buffer_p, *buffer_bsize,
> > > > + fpga_loadfs->offset);
> > > > + if (ret < 0) {
> > > > + debug("FPGA: Failed to read bitstream from
> > > > flash.\n");
> > > > + return -ENOENT;
> > > > + }
> > > > +
> > > > + /* Update next reading bitstream offset */
> > > > + fpga_loadfs->offset += *buffer_bsize;
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf,
> > > > size_t bsize,
> > > > + u32 offset)
> > > > +{
> > > > + struct fpga_loadfs_info fpga_loadfs;
> > > > + struct udevice *dev;
> > > > + int status, ret, size;
> > > > + u32 buffer = (uintptr_t)buf;
> > > > + size_t buffer_sizebytes = bsize;
> > > > + size_t buffer_sizebytes_ori = bsize;
> > > > + size_t total_sizeof_image = 0;
> > > > + ofnode node;
> > > > + const fdt32_t *phandle_p;
> > > > + u32 phandle;
> > > > +
> > > > + node = get_fpga_mgr_ofnode(ofnode_null());
> > > > +
> > > > + if (ofnode_valid(node)) {
> > > > + phandle_p = ofnode_get_property(node, "firmware-
> > > > loader", &size);
> > > > + if (!phandle_p) {
> > > > + node = ofnode_path("/chosen");
> > > > + if (!ofnode_valid(node)) {
> > > > + debug("FPGA: /chosen node was not
> > > > found.\n");
> > > > + return -ENOENT;
> > > > + }
> > > > +
> > > > + phandle_p = ofnode_get_property(node,
> > > > "firmware-loader",
> > > > + &size);
> > > > + if (!phandle_p) {
> > > > + debug("FPGA: firmware-loader
> > > > property was not");
> > > > + debug(" found.\n");
> > > > + return -ENOENT;
> > > > + }
> > > > + }
> > > > + } else {
> > > > + debug("FPGA: FPGA manager node was not found.\n");
> > > > + return -ENOENT;
> > > > + }
> > > > +
> > > > + phandle = fdt32_to_cpu(*phandle_p);
> > > > + ret =
> > > > uclass_get_device_by_phandle_id(UCLASS_FS_FIRMWARE_LOADER,
> > > > + phandle, &dev);
> > > > + if (ret)
> > > > + return ret;
> > > > +
> > > > + memset(&fpga_loadfs, 0, sizeof(fpga_loadfs));
> > > > +
> > > > + fpga_loadfs.fpga_fsinfo = fpga_fsinfo;
> > > > + fpga_loadfs.offset = offset;
> > > > +
> > > > + printf("FPGA: Checking FPGA configuration setting ...\n");
> > > > +
> > > > + /*
> > > > + * Note: Both buffer and buffer_sizebytes values can be
> > > > altered by
> > > > + * function below.
> > > > + */
> > > > + ret = first_loading_rbf_to_buffer(dev, &fpga_loadfs,
> > > > &buffer,
> > > > + &buffer_sizebytes);
> > > > + if (ret == 1) {
> > > > + printf("FPGA: Skipping configuration ...\n");
> > > > + return 0;
> > > > + } else if (ret) {
> > > > + return ret;
> > > > + }
> > > > +
> > > > + if (fpga_loadfs.rbfinfo.section == core_section &&
> > > > + !(is_fpgamgr_early_user_mode() &&
> > > > !is_fpgamgr_user_mode())) {
> > > > + debug("FPGA : Must be in Early Release mode to
> > > > program ");
> > > > + debug("core bitstream.\n");
> > > > + return -EPERM;
> > > > + }
> > > > +
> > > > + /* Disable all signals from HPS peripheral controller to
> > > > FPGA */
> > > > + writel(0, &system_manager_base->fpgaintf_en_global);
> > > > +
> > > > + /* Disable all axi bridges (hps2fpga, lwhps2fpga &
> > > > fpga2hps) */
> > > > + socfpga_bridges_reset();
> > > > +
> > > > + if (fpga_loadfs.rbfinfo.section == periph_section) {
> > > > + /* Initialize the FPGA Manager */
> > > > + status = fpgamgr_program_init((u32 *)buffer,
> > > > buffer_sizebytes);
> > > > + if (status) {
> > > > + debug("FPGA: Init with peripheral
> > > > bitstream failed.\n");
> > > > + return -EPERM;
> > > > + }
> > > > + }
> > > > +
> > > > + /* Transfer bitstream to FPGA Manager */
> > > > + fpgamgr_program_write((void *)buffer, buffer_sizebytes);
> > > > +
> > > > + total_sizeof_image += buffer_sizebytes;
> > > > +
> > > > + while (fpga_loadfs.remaining) {
> > > > + ret = subsequent_loading_rbf_to_buffer(dev,
> > > > + &fpga_load
> > > > fs,
> > > > + &buffer,
> > > > + &buffer_si
> > > > zebytes_ori);
> > > > +
> > > > + if (ret)
> > > > + return ret;
> > > > +
> > > > + /* Transfer data to FPGA Manager */
> > > > + fpgamgr_program_write((void *)buffer,
> > > > + buffer_sizebytes_ori);
> > > > +
> > > > + total_sizeof_image += buffer_sizebytes_ori;
> > > > +
> > > > + WATCHDOG_RESET();
> > > > + }
> > > > +
> > > > + if (fpga_loadfs.rbfinfo.section == periph_section) {
> > > > + if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT)
> > > > {
> > > > + config_pins(gd->fdt_blob, "shared");
> > > > + puts("FPGA: Early Release Succeeded.\n");
> > > > + } else {
> > > > + debug("FPGA: Failed to see Early
> > > > Release.\n");
> > > > + return -EIO;
> > > > + }
> > > > +
> > > > + /* For monolithic bitstream */
> > > > + if (is_fpgamgr_user_mode()) {
> > > > + /* Ensure the FPGA entering config done */
> > > > + status = fpgamgr_program_finish();
> > > > + if (status)
> > > > + return status;
> > > > +
> > > > + config_pins(gd->fdt_blob, "fpga");
> > > > + puts("FPGA: Enter user mode.\n");
> > > > + }
> > > > + } else if (fpga_loadfs.rbfinfo.section == core_section) {
> > > > + /* Ensure the FPGA entering config done */
> > > > + status = fpgamgr_program_finish();
> > > > + if (status)
> > > > + return status;
> > > > +
> > > > + config_pins(gd->fdt_blob, "fpga");
> > > > + puts("FPGA: Enter user mode.\n");
> > > > + } else {
> > > > + debug("FPGA: Config Error: Unsupported bitstream
> > > > type.\n");
> > > > + return -ENOEXEC;
> > > > + }
> > > > +
> > > > + return (int)total_sizeof_image;
> > > > +}
> > > > +
> > > > +void fpgamgr_program(const void *buf, size_t bsize, u32
> > > > offset)
> > > > +{
> > > > + fpga_fs_info fpga_fsinfo;
> > > > +
> > > > + fpga_fsinfo.filename = get_fpga_filename();
> > > > +
> > > > + if (fpga_fsinfo.filename)
> > > > + socfpga_loadfs(&fpga_fsinfo, buf, bsize, offset);
> > > > +}
> > > > +#endif
> > > > +
> > > > +/* This function is used to load the core bitstream from the
> > > > OCRAM. */
> > > > int socfpga_load(Altera_desc *desc, const void *rbf_data,
> > > > size_t
> > > > rbf_size)
> > > > {
> > > > - int status;
> > > > + unsigned long status;
> > > > + struct rbf_info rbfinfo;
> > > > +
> > > > + memset(&rbfinfo, 0, sizeof(rbfinfo));
> > > >
> > > > /* Disable all signals from hps peripheral controller to
> > > > fpga */
> > > > writel(0, &system_manager_base->fpgaintf_en_global);
> > > > @@ -462,13 +915,31 @@ int socfpga_load(Altera_desc *desc, const
> > > > void *rbf_data, size_t rbf_size)
> > > > /* Disable all axi bridge (hps2fpga, lwhps2fpga &
> > > > fpga2hps) */
> > > > socfpga_bridges_reset();
> > > >
> > > > - /* Initialize the FPGA Manager */
> > > > - status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
> > > > - if (status)
> > > > - return status;
> > > > + /* Getting info about bitstream types */
> > > > + get_rbf_image_info(&rbfinfo, (u16 *)rbf_data);
> > > > +
> > > > + if (rbfinfo.section == periph_section) {
> > > > + /* Initialize the FPGA Manager */
> > > > + status = fpgamgr_program_init((u32 *)rbf_data,
> > > > rbf_size);
> > > > + if (status)
> > > > + return status;
> > > > + }
> > > >
> > > > - /* Write the RBF data to FPGA Manager */
> > > > + if (rbfinfo.section == core_section &&
> > > > + !(is_fpgamgr_early_user_mode() &&
> > > > !is_fpgamgr_user_mode())) {
> > > > + debug("FPGA : Must be in early release mode to
> > > > program ");
> > > > + debug("core bitstream.\n");
> > > > + return -EPERM;
> > > > + }
> > > > +
> > > > + /* Write the bitstream to FPGA Manager */
> > > > fpgamgr_program_write(rbf_data, rbf_size);
> > > >
> > > > - return fpgamgr_program_finish();
> > > > + status = fpgamgr_program_finish();
> > > > + if (status) {
> > > > + config_pins(gd->fdt_blob, "fpga");
> > > > + puts("FPGA: Enter user mode.\n");
> > > > + }
> > > > +
> > > > + return status;
> > > > }
> > > > diff --git a/include/image.h b/include/image.h
> > > > index 765ffecee0..cc976f70ce 100644
> > > > --- a/include/image.h
> > > > +++ b/include/image.h
> > > > @@ -1046,6 +1046,10 @@ int fit_check_format(const void *fit);
> > > >
> > > > int fit_conf_find_compat(const void *fit, const void *fdt);
> > > > int fit_conf_get_node(const void *fit, const char
> > > > *conf_uname);
> > > > +int fit_conf_get_prop_node_count(const void *fit, int noffset,
> > > > + const char *prop_name);
> > > > +int fit_conf_get_prop_node_index(const void *fit, int noffset,
> > > > + const char *prop_name, int index);
> > > >
> > > > /**
> > > > * fit_conf_get_prop_node() - Get node refered to by a
> > > > configuration
> > > >
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v12 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL
2019-04-30 12:26 ` Simon Goldschmidt
@ 2019-05-02 7:56 ` Chee, Tien Fong
2019-05-03 11:54 ` Simon Goldschmidt
0 siblings, 1 reply; 27+ messages in thread
From: Chee, Tien Fong @ 2019-05-02 7:56 UTC (permalink / raw)
To: u-boot
On Tue, 2019-04-30 at 14:26 +0200, Simon Goldschmidt wrote:
> On Tue, Apr 30, 2019 at 2:19 PM Chee, Tien Fong
> <tien.fong.chee@intel.com> wrote:
> >
> >
> > On Sat, 2019-04-27 at 21:50 +0200, Simon Goldschmidt wrote:
> > >
> > >
> > > On 19.03.19 09:50, tien.fong.chee at intel.com wrote:
> > > >
> > > >
> > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > >
> > > > Increasing Malloc pool size up to 0x15000 is required to
> > > > support
> > > > FAT in SPL
> > > > . The result of calculation is come from after applying some
> > > > few
> > > > patches
> > > "Some few patches"? What should that mean? Either you refer to
> > > the
> > > current state or you can refer to the patchwork items.
> > >
> > > >
> > > >
> > > > which are required for optimizing vfat and maximizing resusable
> > > > of
> > > > the
> > > > memory pool, and then followed by the size required come from
> > > > default max
> > > > cluster(0x10000) + others(0x2000) + additional memory for
> > > > headroom(0x3000).
> > > > Previous records of describing these few patches can be checked
> > > > from here
> > > > [v7]: https://www.mail-archive.com/u-boot at lists.denx.de/msg3145
> > > > 11.h
> > > > tml .
> > > Why do you refer to mail-archive.com instead of patchwork?
> > Contains the cover letter in case reviewer need to know more
> > information.
> I think you understood that wrong. Why do you reference a 3rd party
> host (mail-archive.com) instead of the official list archive or
> patchwork?
>
> And please note patchwork keeps the cover letter as well.
Okay, i can't find any cover letter from this link https://patchwork.oz
labs.org/project/uboot/list/?series=&submitter=70549&state=*&q=&archive
=both&delegate= . Do you know how to find it?
>
> Also note, this is the commit message which will got into the git
> lot.
> Referencing v7 and older history seems misplaced here. Better move
> it below the '---'.
Okay, noted. So, what should i do with this patch now? Should i send
next version with new commit message?
Thanks.
TF
>
> >
> >
> > Thanks.
> > >
> > >
> > > >
> > > >
> > > >
> > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > >
> > > > ---
> > > >
> > > > changes for v12
> > > > - Improved the commit messages.
> > > >
> > > > changes for v11
> > > > - No changes.
> > > >
> > > > changes for v10
> > > > - No changes.
> > > >
> > > > changes for v9
> > > > - No changes.
> > > >
> > > > changes for v8
> > > > - Moved the FIT related configs to the patch of configuration
> > > > for
> > > > FPGA
> > > > SoCFPGA A10 SoCDK.
> > > >
> > > > changes for v7
> > > > - Keep minimal configs.
> > > > ---
> > > > include/configs/socfpga_common.h | 4 ++--
> > > > 1 file changed, 2 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/include/configs/socfpga_common.h
> > > > b/include/configs/socfpga_common.h
> > > > index 181af9b646..22533036ed 100644
> > > > --- a/include/configs/socfpga_common.h
> > > > +++ b/include/configs/socfpga_common.h
> > > > @@ -1,6 +1,6 @@
> > > > /* SPDX-License-Identifier: GPL-2.0+ */
> > > > /*
> > > > - * Copyright (C) 2012 Altera Corporation <www.altera.com>
> > > > + * Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
> > > > */
> > > > #ifndef __CONFIG_SOCFPGA_COMMON_H__
> > > > #define __CONFIG_SOCFPGA_COMMON_H__
> > > > @@ -254,7 +254,7 @@ unsigned int
> > > > cm_get_qspi_controller_clk_hz(void);
> > > > #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > > /* SPL memory allocation configuration, this is for FAT
> > > > implementation */
> > > > #ifndef CONFIG_SYS_SPL_MALLOC_START
> > > > -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
> > > > +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00015000
> > > > #define
> > > > CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_S
> > > > IZE - \
> > > > CONFIG_SYS_SPL_MALLOC_SI
> > > > ZE + \
> > > > CONFIG_SYS_INIT_RAM_ADDR
> > > > )
> > > >
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v12 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
2019-05-02 7:49 ` Chee, Tien Fong
@ 2019-05-03 11:26 ` Simon Goldschmidt
2019-05-06 3:36 ` Chee, Tien Fong
0 siblings, 1 reply; 27+ messages in thread
From: Simon Goldschmidt @ 2019-05-03 11:26 UTC (permalink / raw)
To: u-boot
On Thu, May 2, 2019 at 9:49 AM Chee, Tien Fong <tien.fong.chee@intel.com> wrote:
>
> On Tue, 2019-04-30 at 14:24 +0200, Simon Goldschmidt wrote:
> > On Tue, Apr 30, 2019 at 2:09 PM Chee, Tien Fong
> > <tien.fong.chee@intel.com> wrote:
> > >
> > >
> > > On Sat, 2019-04-27 at 21:57 +0200, Simon Goldschmidt wrote:
> > > >
> > > >
> > > > On 19.03.19 09:50, tien.fong.chee at intel.com wrote:
> > > > >
> > > > >
> > > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > >
> > > > > Add FPGA driver to support program FPGA with FPGA bitstream
> > > > > loading
> > > > > from
> > > > > filesystem. The driver are designed based on generic firmware
> > > > > loader
> > > > > framework. The driver can handle FPGA program operation from
> > > > > loading FPGA
> > > > > bitstream in flash to memory and then to program FPGA.
> > > > >
> > > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > >
> > > > > ---
> > > > >
> > > > > changes for v12
> > > > > - No changes.
> > > > >
> > > > > changes for v11
> > > > > - No changes.
> > > > >
> > > > > changes for v10
> > > > > -Cleaned up the codes.
> > > > > -Return -EPERM when programing core on non early IO release
> > > > > mode. >
> > > > > -Using live function to get rid of gd->
> > > > You got rid of gd-> in v10? How come I see numerous references to
> > > > it
> > > > below?
> > > get rid of using gd->fdt_blob for finding the node_offset.
> > > Details in https://patchwork.ozlabs.org/patch/1044415/
> > Ah, ok. But still, here you're introducing yet more references to gd-
> > >fdt_blob.
> > That wouldn't work with a live tree, either, or would it?
>
> Yeah, few direct call to config_pin function are still using gd-
> fdt_blob as argument. But, i'm not sure i should fix this function in
> this series patch set, or separately patch after this series patch set?
>
> What do you think?
While I do have a strong opinion that this should be cleaned up,
it would be kind of off-topic in this patch. I was just confused by the
version log.
Regards,
Simon
>
> Thanks,
> TF
> >
> > >
> > >
> > > -/*
> > > - * FPGA Manager to program the FPGA. This is the interface used by
> > > FPGA driver.
> > > - * Return 0 for sucess, non-zero for error.
> > > - */
> > > +ofnode get_fpga_mgr_ofnode(void)
> > > +{
> > > + int node_offset;
> > > +
> > > + fdtdec_find_aliases_for_id(gd->fdt_blob, "fpga_mgr",
> > >
> > > nit: using of live functions would be better to get rid of gd->.
> > >
> > > + COMPAT_ALTERA_SOCFPGA_FPGA0,
> > > + &node_offset, 1);
> > >
> > > Thanks.
> > > >
> > > >
> > > > >
> > > > >
> > > > > -Removed @0 for fs-loader node
> > > > >
> > > > > changes for v9
> > > > > - Support data offset
> > > > > - Added default DDR load address
> > > > > - Squashed the image.h
> > > > > - Changed to phandle
> > > > > - Ensure the DDR is fully up running by checking the gd->ram
> > > > >
> > > > > changes for v8
> > > > > - Added codes to discern bitstream type based on fpga node
> > > > > name.
> > > > >
> > > > > changes for v7
> > > > > - Restructure the FPGA driver to support both peripheral
> > > > > bitstream
> > > > > and core
> > > > > bitstream bundled into FIT image.
> > > > > - Support loadable property for core bitstream. User can set
> > > > > loadable
> > > > > in DDR for better performance. This loading would be done in
> > > > > one
> > > > > large
> > > > > chunk instead of chunk by chunk loading with small memory
> > > > > buffer.
> > > > > ---
> > > > > arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +
> > > > > .../include/mach/fpga_manager_arria10.h | 39 +-
> > > > > drivers/fpga/socfpga_arria10.c | 497
> > > > > ++++++++++++++++++++-
> > > > > include/image.h | 4 +
> > > > > 4 files changed, 542 insertions(+), 15 deletions(-)
> > > > >
> > > > > diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > > b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > > index 998d811210..cc761967c7 100644
> > > > > --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > > +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > > @@ -18,6 +18,23 @@
> > > > > /dts-v1/;
> > > > > #include "socfpga_arria10_socdk.dtsi"
> > > > >
> > > > > +/ {
> > > > > + chosen {
> > > > > + firmware-loader = <&fs_loader0>;
> > > > > + };
> > > > > +
> > > > > + fs_loader0: fs-loader {
> > > > > + u-boot,dm-pre-reloc;
> > > > > + compatible = "u-boot,fs-loader";
> > > > > + phandlepart = <&mmc 1>;
> > > > > + };
> > > > > +};
> > > > > +
> > > > > +&fpga_mgr {
> > > > > + u-boot,dm-pre-reloc;
> > > > > + altr,bitstream = "fit_spl_fpga.itb";
> > > > > +};
> > > > > +
> > > > > &mmc {
> > > > > u-boot,dm-pre-reloc;
> > > > > status = "okay";
> > > > > diff --git a/arch/arm/mach-
> > > > > socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-
> > > > > socfpga/include/mach/fpga_manager_arria10.h
> > > > > index 09d13f6fd3..c5f67714aa 100644
> > > > > --- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> > > > > +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> > > > > @@ -1,9 +1,13 @@
> > > > > /* SPDX-License-Identifier: GPL-2.0 */
> > > > > /*
> > > > > - * Copyright (C) 2017 Intel Corporation <www.intel.com>
> > > > > + * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
> > > > > * All rights reserved.
> > > > > */
> > > > >
> > > > > +#include <asm/cache.h>
> > > > > +#include <altera.h>
> > > > > +#include <image.h>
> > > > > +
> > > > > #ifndef _FPGA_MANAGER_ARRIA10_H_
> > > > > #define _FPGA_MANAGER_ARRIA10_H_
> > > > >
> > > > > @@ -51,6 +55,10 @@
> > > > > #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK
> > > > > BIT(24)
> > > > > #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB
> > > > > 16
> > > > >
> > > > > +#define FPGA_SOCFPGA_A10_RBF_UNENCRYPTED 0xa65c
> > > > > +#define FPGA_SOCFPGA_A10_RBF_ENCRYPTED 0xa65d
> > > > > +#define FPGA_SOCFPGA_A10_RBF_PERIPH 0x0001
> > > > > +#define FPGA_SOCFPGA_A10_RBF_CORE 0x8001
> > > > > #ifndef __ASSEMBLY__
> > > > >
> > > > > struct socfpga_fpga_manager {
> > > > > @@ -88,12 +96,39 @@ struct socfpga_fpga_manager {
> > > > > u32 imgcfg_fifo_status;
> > > > > };
> > > > >
> > > > > +enum rbf_type {
> > > > > + unknown,
> > > > > + periph_section,
> > > > > + core_section
> > > > > +};
> > > > > +
> > > > > +enum rbf_security {
> > > > > + invalid,
> > > > > + unencrypted,
> > > > > + encrypted
> > > > > +};
> > > > > +
> > > > > +struct rbf_info {
> > > > > + enum rbf_type section;
> > > > > + enum rbf_security security;
> > > > > +};
> > > > > +
> > > > > +struct fpga_loadfs_info {
> > > > > + fpga_fs_info *fpga_fsinfo;
> > > > > + u32 remaining;
> > > > > + u32 offset;
> > > > > + struct rbf_info rbfinfo;
> > > > > +};
> > > > > +
> > > > > /* Functions */
> > > > > int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
> > > > > int fpgamgr_program_finish(void);
> > > > > int is_fpgamgr_user_mode(void);
> > > > > int fpgamgr_wait_early_user_mode(void);
> > > > > -
> > > > > +const char *get_fpga_filename(void);
> > > > > +int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf,
> > > > > size_t bsize,
> > > > > + u32 offset);
> > > > > +void fpgamgr_program(const void *buf, size_t bsize, u32
> > > > > offset);
> > > > > #endif /* __ASSEMBLY__ */
> > > > >
> > > > > #endif /* _FPGA_MANAGER_ARRIA10_H_ */
> > > > > diff --git a/drivers/fpga/socfpga_arria10.c
> > > > > b/drivers/fpga/socfpga_arria10.c
> > > > > index 9499d1a014..9df2c430d7 100644
> > > > > --- a/drivers/fpga/socfpga_arria10.c
> > > > > +++ b/drivers/fpga/socfpga_arria10.c
> > > > > @@ -1,8 +1,7 @@
> > > > > // SPDX-License-Identifier: GPL-2.0
> > > > > /*
> > > > > - * Copyright (C) 2017 Intel Corporation <www.intel.com>
> > > > > + * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
> > > > > */
> > > > > -
> > > > > #include <asm/io.h>
> > > > > #include <asm/arch/fpga_manager.h>
> > > > > #include <asm/arch/reset_manager.h>
> > > > > @@ -10,8 +9,11 @@
> > > > > #include <asm/arch/sdram.h>
> > > > > #include <asm/arch/misc.h>
> > > > > #include <altera.h>
> > > > > +#include <asm/arch/pinmux.h>
> > > > > #include <common.h>
> > > > > +#include <dm/ofnode.h>
> > > > > #include <errno.h>
> > > > > +#include <fs_loader.h>
> > > > > #include <wait_bit.h>
> > > > > #include <watchdog.h>
> > > > >
> > > > > @@ -21,6 +23,9 @@
> > > > > #define COMPRESSION_OFFSET 229
> > > > > #define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
> > > > > #define FPGA_TIMEOUT_CNT 0x1000000
> > > > > +#define DEFAULT_DDR_LOAD_ADDRESS 0x400
> > > > > +
> > > > > +DECLARE_GLOBAL_DATA_PTR;
> > > > >
> > > > > static const struct socfpga_fpga_manager *fpga_manager_base =
> > > > > (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
> > > > > @@ -448,13 +453,461 @@ int fpgamgr_program_finish(void)
> > > > > return 0;
> > > > > }
> > > > >
> > > > > -/*
> > > > > - * FPGA Manager to program the FPGA. This is the interface
> > > > > used by
> > > > > FPGA driver.
> > > > > - * Return 0 for sucess, non-zero for error.
> > > > > - */
> > > > > +ofnode get_fpga_mgr_ofnode(ofnode from)
> > > > > +{
> > > > > + return ofnode_by_compatible(from, "altr,socfpga-a10-fpga-
> > > > > mgr");
> > > > > +}
> > > > > +
> > > > > +const char *get_fpga_filename(void)
> > > > > +{
> > > > > + const char *fpga_filename = NULL;
> > > > > +
> > > > > + ofnode fpgamgr_node = get_fpga_mgr_ofnode(ofnode_null());
> > > > > +
> > > > > + if (ofnode_valid(fpgamgr_node))
> > > > > + fpga_filename = ofnode_read_string(fpgamgr_node,
> > > > > + "altr,bitstream");
> > > > > +
> > > > > + return fpga_filename;
> > > > > +}
> > > > > +
> > > > > +static void get_rbf_image_info(struct rbf_info *rbf, u16
> > > > > *buffer)
> > > > > +{
> > > > > + /*
> > > > > + * Magic ID starting at:
> > > > > + * -> 1st dword[15:0] in periph.rbf
> > > > > + * -> 2nd dword[15:0] in core.rbf
> > > > > + * Note: dword == 32 bits
> > > > > + */
> > > > > + u32 word_reading_max = 2;
> > > > > + u32 i;
> > > > > +
> > > > > + for (i = 0; i < word_reading_max; i++) {
> > > > > + if (*(buffer + i) ==
> > > > > FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
> > > > > + rbf->security = unencrypted;
> > > > > + } else if (*(buffer + i) ==
> > > > > FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
> > > > > + rbf->security = encrypted;
> > > > > + } else if (*(buffer + i + 1) ==
> > > > > + FPGA_SOCFPGA_A10_RBF_UNENCRYPTED)
> > > > > {
> > > > > + rbf->security = unencrypted;
> > > > > + } else if (*(buffer + i + 1) ==
> > > > > + FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
> > > > > + rbf->security = encrypted;
> > > > > + } else {
> > > > > + rbf->security = invalid;
> > > > > + continue;
> > > > > + }
> > > > > +
> > > > > + /* PERIPH RBF(buffer + i + 1), CORE RBF(buffer + i
> > > > > + 2) */
> > > > > + if (*(buffer + i + 1) ==
> > > > > FPGA_SOCFPGA_A10_RBF_PERIPH) {
> > > > > + rbf->section = periph_section;
> > > > > + break;
> > > > > + } else if (*(buffer + i + 1) ==
> > > > > FPGA_SOCFPGA_A10_RBF_CORE) {
> > > > > + rbf->section = core_section;
> > > > > + break;
> > > > > + } else if (*(buffer + i + 2) ==
> > > > > FPGA_SOCFPGA_A10_RBF_PERIPH) {
> > > > > + rbf->section = periph_section;
> > > > > + break;
> > > > > + } else if (*(buffer + i + 2) ==
> > > > > FPGA_SOCFPGA_A10_RBF_CORE) {
> > > > > + rbf->section = core_section;
> > > > > + break;
> > > > > + }
> > > > > +
> > > > > + rbf->section = unknown;
> > > > > + break;
> > > > > +
> > > > > + WATCHDOG_RESET();
> > > > > + }
> > > > > +}
> > > > > +
> > > > > +#ifdef CONFIG_FS_LOADER
> > > > > +static int first_loading_rbf_to_buffer(struct udevice *dev,
> > > > > + struct fpga_loadfs_info
> > > > > *fpga_loadfs,
> > > > > + u32 *buffer, size_t *buffer_bsize)
> > > > > +{
> > > > > + u32 *buffer_p = (u32 *)*buffer;
> > > > > + u32 *loadable = buffer_p;
> > > > > + size_t buffer_size = *buffer_bsize;
> > > > > + size_t fit_size;
> > > > > + int ret, i, count, confs_noffset, images_noffset,
> > > > > rbf_offset, rbf_size;
> > > > > + const char *fpga_node_name = NULL;
> > > > > + const char *uname = NULL;
> > > > > +
> > > > > + /* Load image header into buffer */
> > > > > + ret = request_firmware_into_buf(dev,
> > > > > + fpga_loadfs->fpga_fsinfo-
> > > > > >
> > > > > > filename,
> > > > > + buffer_p, sizeof(struct
> > > > > image_header),
> > > > > + 0);
> > > > > + if (ret < 0) {
> > > > > + debug("FPGA: Failed to read image header from
> > > > > flash.\n");
> > > > > + return -ENOENT;
> > > > > + }
> > > > > +
> > > > > + if (image_get_magic((struct image_header *)buffer_p) !=
> > > > > FDT_MAGIC) {
> > > > > + debug("FPGA: No FDT magic was found.\n");
> > > > > + return -EBADF;
> > > > > + }
> > > > > +
> > > > > + fit_size = fdt_totalsize(buffer_p);
> > > > > +
> > > > > + if (fit_size > buffer_size) {
> > > > > + debug("FPGA: FIT image is larger than available
> > > > > buffer.\n");
> > > > > + debug("Please use FIT external data or increasing
> > > > > buffer.\n");
> > > > > + return -ENOMEM;
> > > > > + }
> > > > > +
> > > > > + /* Load entire FIT into buffer */
> > > > > + ret = request_firmware_into_buf(dev,
> > > > > + fpga_loadfs->fpga_fsinfo-
> > > > > >
> > > > > > filename,
> > > > > + buffer_p, fit_size, 0);
> > > > > + if (ret < 0)
> > > > > + return ret;
> > > > > +
> > > > > + ret = fit_check_format(buffer_p);
> > > > > + if (!ret) {
> > > > > + debug("FPGA: No valid FIT image was found.\n");
> > > > > + return -EBADF;
> > > > > + }
> > > > > +
> > > > > + confs_noffset = fdt_path_offset(buffer_p, FIT_CONFS_PATH);
> > > > > + images_noffset = fdt_path_offset(buffer_p,
> > > > > FIT_IMAGES_PATH);
> > > > > + if (confs_noffset < 0 || images_noffset < 0) {
> > > > > + debug("FPGA: No Configurations or images nodes
> > > > > were found.\n");
> > > > > + return -ENOENT;
> > > > > + }
> > > > > +
> > > > > + /* Get default configuration unit name from default
> > > > > property */
> > > > > + confs_noffset = fit_conf_get_node(buffer_p, NULL);
> > > > > + if (confs_noffset < 0) {
> > > > > + debug("FPGA: No default configuration was found in
> > > > > config.\n");
> > > > > + return -ENOENT;
> > > > > + }
> > > > > +
> > > > > + count = fit_conf_get_prop_node_count(buffer_p,
> > > > > confs_noffset,
> > > > > + FIT_FPGA_PROP);
> > > > > + if (count < 0) {
> > > > > + debug("FPGA: Invalid configuration format for FPGA
> > > > > node.\n");
> > > > > + return count;
> > > > > + }
> > > > > + debug("FPGA: FPGA node count: %d\n", count);
> > > > > +
> > > > > + for (i = 0; i < count; i++) {
> > > > > + images_noffset =
> > > > > fit_conf_get_prop_node_index(buffer_p,
> > > > > + confs
> > > > > _noffset,
> > > > > + FIT_F
> > > > > PGA_PROP, i);
> > > > > + uname = fit_get_name(buffer_p, images_noffset,
> > > > > NULL);
> > > > > + if (uname) {
> > > > > + debug("FPGA: %s\n", uname);
> > > > > +
> > > > > + if (strstr(uname, "fpga-periph") &&
> > > > > + (!is_fpgamgr_early_user_mode() ||
> > > > > + is_fpgamgr_user_mode())) {
> > > > > + fpga_node_name = uname;
> > > > > + printf("FPGA: Start to program ");
> > > > > + printf("peripheral/full bitstream
> > > > > ...\n");
> > > > > + break;
> > > > > + } else if (strstr(uname, "fpga-core") &&
> > > > > + (is_fpgamgr_early_user_mod
> > > > > e() &&
> > > > > + !is_fpgamgr_user_mode()))
> > > > > {
> > > > > + fpga_node_name = uname;
> > > > > + printf("FPGA: Start to program
> > > > > core ");
> > > > > + printf("bitstream ...\n");
> > > > > + break;
> > > > > + }
> > > > > + }
> > > > > + WATCHDOG_RESET();
> > > > > + }
> > > > > +
> > > > > + if (!fpga_node_name) {
> > > > > + debug("FPGA: No suitable bitstream was found,
> > > > > count: %d.\n", i);
> > > > > + return 1;
> > > > > + }
> > > > > +
> > > > > + images_noffset = fit_image_get_node(buffer_p,
> > > > > fpga_node_name);
> > > > > + if (images_noffset < 0) {
> > > > > + debug("FPGA: No node '%s' was found in FIT.\n",
> > > > > + fpga_node_name);
> > > > > + return -ENOENT;
> > > > > + }
> > > > > +
> > > > > + if (!fit_image_get_data_position(buffer_p, images_noffset,
> > > > > + &rbf_offset)) {
> > > > > + debug("FPGA: Data position was found.\n");
> > > > > + } else if (!fit_image_get_data_offset(buffer_p,
> > > > > images_noffset,
> > > > > + &rbf_offset)) {
> > > > > + /*
> > > > > + * For FIT with external data, figure out where
> > > > > + * the external images start. This is the base
> > > > > + * for the data-offset properties in each image.
> > > > > + */
> > > > > + rbf_offset += ((fdt_totalsize(buffer_p) + 3) &
> > > > > ~3);
> > > > > + debug("FPGA: Data offset was found.\n");
> > > > > + } else {
> > > > > + debug("FPGA: No data position/offset was
> > > > > found.\n");
> > > > > + return -ENOENT;
> > > > > + }
> > > > > +
> > > > > + ret = fit_image_get_data_size(buffer_p, images_noffset,
> > > > > &rbf_size);
> > > > > + if (ret < 0) {
> > > > > + debug("FPGA: No data size was found (err=%d).\n",
> > > > > ret);
> > > > > + return -ENOENT;
> > > > > + }
> > > > > +
> > > > > + if (gd->ram_size < rbf_size) {
> > > > > + debug("FPGA: Using default OCRAM buffer and
> > > > > size.\n");
> > > > > + } else {
> > > > > + ret = fit_image_get_load(buffer_p, images_noffset,
> > > > > + (ulong *)loadable);
> > > > > + if (ret < 0) {
> > > > > + buffer_p = (u32
> > > > > *)DEFAULT_DDR_LOAD_ADDRESS;
> > > > > + debug("FPGA: No loadable was found.\n");
> > > > > + debug("FPGA: Using default DDR load
> > > > > address: 0x%x .\n",
> > > > > + DEFAULT_DDR_LOAD_ADDRESS);
> > > > > + } else {
> > > > > + buffer_p = (u32 *)*loadable;
> > > > > + debug("FPGA: Found loadable address =
> > > > > 0x%x.\n",
> > > > > + *loadable);
> > > > > + }
> > > > > +
> > > > > + buffer_size = rbf_size;
> > > > > + }
> > > > > +
> > > > > + debug("FPGA: External data: offset = 0x%x, size =
> > > > > 0x%x.\n",
> > > > > + rbf_offset, rbf_size);
> > > > > +
> > > > > + fpga_loadfs->remaining = rbf_size;
> > > > > +
> > > > > + /*
> > > > > + * Determine buffer size vs bitstream size, and
> > > > > calculating number of
> > > > > + * chunk by chunk transfer is required due to smaller
> > > > > buffer size
> > > > > + * compare to bitstream
> > > > > + */
> > > > > + if (rbf_size <= buffer_size) {
> > > > > + /* Loading whole bitstream into buffer */
> > > > > + buffer_size = rbf_size;
> > > > > + fpga_loadfs->remaining = 0;
> > > > > + } else {
> > > > > + fpga_loadfs->remaining -= buffer_size;
> > > > > + }
> > > > > +
> > > > > + fpga_loadfs->offset = rbf_offset;
> > > > > + /* Loading bitstream into buffer */
> > > > > + ret = request_firmware_into_buf(dev,
> > > > > + fpga_loadfs->fpga_fsinfo-
> > > > > >
> > > > > > filename,
> > > > > + buffer_p, buffer_size,
> > > > > + fpga_loadfs->offset);
> > > > > + if (ret < 0) {
> > > > > + debug("FPGA: Failed to read bitstream from
> > > > > flash.\n");
> > > > > + return -ENOENT;
> > > > > + }
> > > > > +
> > > > > + /* Getting info about bitstream types */
> > > > > + get_rbf_image_info(&fpga_loadfs->rbfinfo, (u16
> > > > > *)buffer_p);
> > > > > +
> > > > > + /* Update next reading bitstream offset */
> > > > > + fpga_loadfs->offset += buffer_size;
> > > > > +
> > > > > + /* Update the final addr for bitstream */
> > > > > + *buffer = (u32)buffer_p;
> > > > > +
> > > > > + /* Update the size of bitstream to be programmed into FPGA
> > > > > */
> > > > > + *buffer_bsize = buffer_size;
> > > > > +
> > > > > + return 0;
> > > > > +}
> > > > > +
> > > > > +static int subsequent_loading_rbf_to_buffer(struct udevice
> > > > > *dev,
> > > > > + struct fpga_loadfs_info
> > > > > *fpga_loadfs,
> > > > > + u32 *buffer, size_t
> > > > > *buffer_bsize)
> > > > > +{
> > > > > + int ret = 0;
> > > > > + u32 *buffer_p = (u32 *)*buffer;
> > > > > +
> > > > > + /* Read the bitstream chunk by chunk. */
> > > > > + if (fpga_loadfs->remaining > *buffer_bsize) {
> > > > > + fpga_loadfs->remaining -= *buffer_bsize;
> > > > > + } else {
> > > > > + *buffer_bsize = fpga_loadfs->remaining;
> > > > > + fpga_loadfs->remaining = 0;
> > > > > + }
> > > > > +
> > > > > + ret = request_firmware_into_buf(dev,
> > > > > + fpga_loadfs->fpga_fsinfo-
> > > > > >
> > > > > > filename,
> > > > > + buffer_p, *buffer_bsize,
> > > > > + fpga_loadfs->offset);
> > > > > + if (ret < 0) {
> > > > > + debug("FPGA: Failed to read bitstream from
> > > > > flash.\n");
> > > > > + return -ENOENT;
> > > > > + }
> > > > > +
> > > > > + /* Update next reading bitstream offset */
> > > > > + fpga_loadfs->offset += *buffer_bsize;
> > > > > +
> > > > > + return 0;
> > > > > +}
> > > > > +
> > > > > +int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf,
> > > > > size_t bsize,
> > > > > + u32 offset)
> > > > > +{
> > > > > + struct fpga_loadfs_info fpga_loadfs;
> > > > > + struct udevice *dev;
> > > > > + int status, ret, size;
> > > > > + u32 buffer = (uintptr_t)buf;
> > > > > + size_t buffer_sizebytes = bsize;
> > > > > + size_t buffer_sizebytes_ori = bsize;
> > > > > + size_t total_sizeof_image = 0;
> > > > > + ofnode node;
> > > > > + const fdt32_t *phandle_p;
> > > > > + u32 phandle;
> > > > > +
> > > > > + node = get_fpga_mgr_ofnode(ofnode_null());
> > > > > +
> > > > > + if (ofnode_valid(node)) {
> > > > > + phandle_p = ofnode_get_property(node, "firmware-
> > > > > loader", &size);
> > > > > + if (!phandle_p) {
> > > > > + node = ofnode_path("/chosen");
> > > > > + if (!ofnode_valid(node)) {
> > > > > + debug("FPGA: /chosen node was not
> > > > > found.\n");
> > > > > + return -ENOENT;
> > > > > + }
> > > > > +
> > > > > + phandle_p = ofnode_get_property(node,
> > > > > "firmware-loader",
> > > > > + &size);
> > > > > + if (!phandle_p) {
> > > > > + debug("FPGA: firmware-loader
> > > > > property was not");
> > > > > + debug(" found.\n");
> > > > > + return -ENOENT;
> > > > > + }
> > > > > + }
> > > > > + } else {
> > > > > + debug("FPGA: FPGA manager node was not found.\n");
> > > > > + return -ENOENT;
> > > > > + }
> > > > > +
> > > > > + phandle = fdt32_to_cpu(*phandle_p);
> > > > > + ret =
> > > > > uclass_get_device_by_phandle_id(UCLASS_FS_FIRMWARE_LOADER,
> > > > > + phandle, &dev);
> > > > > + if (ret)
> > > > > + return ret;
> > > > > +
> > > > > + memset(&fpga_loadfs, 0, sizeof(fpga_loadfs));
> > > > > +
> > > > > + fpga_loadfs.fpga_fsinfo = fpga_fsinfo;
> > > > > + fpga_loadfs.offset = offset;
> > > > > +
> > > > > + printf("FPGA: Checking FPGA configuration setting ...\n");
> > > > > +
> > > > > + /*
> > > > > + * Note: Both buffer and buffer_sizebytes values can be
> > > > > altered by
> > > > > + * function below.
> > > > > + */
> > > > > + ret = first_loading_rbf_to_buffer(dev, &fpga_loadfs,
> > > > > &buffer,
> > > > > + &buffer_sizebytes);
> > > > > + if (ret == 1) {
> > > > > + printf("FPGA: Skipping configuration ...\n");
> > > > > + return 0;
> > > > > + } else if (ret) {
> > > > > + return ret;
> > > > > + }
> > > > > +
> > > > > + if (fpga_loadfs.rbfinfo.section == core_section &&
> > > > > + !(is_fpgamgr_early_user_mode() &&
> > > > > !is_fpgamgr_user_mode())) {
> > > > > + debug("FPGA : Must be in Early Release mode to
> > > > > program ");
> > > > > + debug("core bitstream.\n");
> > > > > + return -EPERM;
> > > > > + }
> > > > > +
> > > > > + /* Disable all signals from HPS peripheral controller to
> > > > > FPGA */
> > > > > + writel(0, &system_manager_base->fpgaintf_en_global);
> > > > > +
> > > > > + /* Disable all axi bridges (hps2fpga, lwhps2fpga &
> > > > > fpga2hps) */
> > > > > + socfpga_bridges_reset();
> > > > > +
> > > > > + if (fpga_loadfs.rbfinfo.section == periph_section) {
> > > > > + /* Initialize the FPGA Manager */
> > > > > + status = fpgamgr_program_init((u32 *)buffer,
> > > > > buffer_sizebytes);
> > > > > + if (status) {
> > > > > + debug("FPGA: Init with peripheral
> > > > > bitstream failed.\n");
> > > > > + return -EPERM;
> > > > > + }
> > > > > + }
> > > > > +
> > > > > + /* Transfer bitstream to FPGA Manager */
> > > > > + fpgamgr_program_write((void *)buffer, buffer_sizebytes);
> > > > > +
> > > > > + total_sizeof_image += buffer_sizebytes;
> > > > > +
> > > > > + while (fpga_loadfs.remaining) {
> > > > > + ret = subsequent_loading_rbf_to_buffer(dev,
> > > > > + &fpga_load
> > > > > fs,
> > > > > + &buffer,
> > > > > + &buffer_si
> > > > > zebytes_ori);
> > > > > +
> > > > > + if (ret)
> > > > > + return ret;
> > > > > +
> > > > > + /* Transfer data to FPGA Manager */
> > > > > + fpgamgr_program_write((void *)buffer,
> > > > > + buffer_sizebytes_ori);
> > > > > +
> > > > > + total_sizeof_image += buffer_sizebytes_ori;
> > > > > +
> > > > > + WATCHDOG_RESET();
> > > > > + }
> > > > > +
> > > > > + if (fpga_loadfs.rbfinfo.section == periph_section) {
> > > > > + if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT)
> > > > > {
> > > > > + config_pins(gd->fdt_blob, "shared");
> > > > > + puts("FPGA: Early Release Succeeded.\n");
> > > > > + } else {
> > > > > + debug("FPGA: Failed to see Early
> > > > > Release.\n");
> > > > > + return -EIO;
> > > > > + }
> > > > > +
> > > > > + /* For monolithic bitstream */
> > > > > + if (is_fpgamgr_user_mode()) {
> > > > > + /* Ensure the FPGA entering config done */
> > > > > + status = fpgamgr_program_finish();
> > > > > + if (status)
> > > > > + return status;
> > > > > +
> > > > > + config_pins(gd->fdt_blob, "fpga");
> > > > > + puts("FPGA: Enter user mode.\n");
> > > > > + }
> > > > > + } else if (fpga_loadfs.rbfinfo.section == core_section) {
> > > > > + /* Ensure the FPGA entering config done */
> > > > > + status = fpgamgr_program_finish();
> > > > > + if (status)
> > > > > + return status;
> > > > > +
> > > > > + config_pins(gd->fdt_blob, "fpga");
> > > > > + puts("FPGA: Enter user mode.\n");
> > > > > + } else {
> > > > > + debug("FPGA: Config Error: Unsupported bitstream
> > > > > type.\n");
> > > > > + return -ENOEXEC;
> > > > > + }
> > > > > +
> > > > > + return (int)total_sizeof_image;
> > > > > +}
> > > > > +
> > > > > +void fpgamgr_program(const void *buf, size_t bsize, u32
> > > > > offset)
> > > > > +{
> > > > > + fpga_fs_info fpga_fsinfo;
> > > > > +
> > > > > + fpga_fsinfo.filename = get_fpga_filename();
> > > > > +
> > > > > + if (fpga_fsinfo.filename)
> > > > > + socfpga_loadfs(&fpga_fsinfo, buf, bsize, offset);
> > > > > +}
> > > > > +#endif
> > > > > +
> > > > > +/* This function is used to load the core bitstream from the
> > > > > OCRAM. */
> > > > > int socfpga_load(Altera_desc *desc, const void *rbf_data,
> > > > > size_t
> > > > > rbf_size)
> > > > > {
> > > > > - int status;
> > > > > + unsigned long status;
> > > > > + struct rbf_info rbfinfo;
> > > > > +
> > > > > + memset(&rbfinfo, 0, sizeof(rbfinfo));
> > > > >
> > > > > /* Disable all signals from hps peripheral controller to
> > > > > fpga */
> > > > > writel(0, &system_manager_base->fpgaintf_en_global);
> > > > > @@ -462,13 +915,31 @@ int socfpga_load(Altera_desc *desc, const
> > > > > void *rbf_data, size_t rbf_size)
> > > > > /* Disable all axi bridge (hps2fpga, lwhps2fpga &
> > > > > fpga2hps) */
> > > > > socfpga_bridges_reset();
> > > > >
> > > > > - /* Initialize the FPGA Manager */
> > > > > - status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
> > > > > - if (status)
> > > > > - return status;
> > > > > + /* Getting info about bitstream types */
> > > > > + get_rbf_image_info(&rbfinfo, (u16 *)rbf_data);
> > > > > +
> > > > > + if (rbfinfo.section == periph_section) {
> > > > > + /* Initialize the FPGA Manager */
> > > > > + status = fpgamgr_program_init((u32 *)rbf_data,
> > > > > rbf_size);
> > > > > + if (status)
> > > > > + return status;
> > > > > + }
> > > > >
> > > > > - /* Write the RBF data to FPGA Manager */
> > > > > + if (rbfinfo.section == core_section &&
> > > > > + !(is_fpgamgr_early_user_mode() &&
> > > > > !is_fpgamgr_user_mode())) {
> > > > > + debug("FPGA : Must be in early release mode to
> > > > > program ");
> > > > > + debug("core bitstream.\n");
> > > > > + return -EPERM;
> > > > > + }
> > > > > +
> > > > > + /* Write the bitstream to FPGA Manager */
> > > > > fpgamgr_program_write(rbf_data, rbf_size);
> > > > >
> > > > > - return fpgamgr_program_finish();
> > > > > + status = fpgamgr_program_finish();
> > > > > + if (status) {
> > > > > + config_pins(gd->fdt_blob, "fpga");
> > > > > + puts("FPGA: Enter user mode.\n");
> > > > > + }
> > > > > +
> > > > > + return status;
> > > > > }
> > > > > diff --git a/include/image.h b/include/image.h
> > > > > index 765ffecee0..cc976f70ce 100644
> > > > > --- a/include/image.h
> > > > > +++ b/include/image.h
> > > > > @@ -1046,6 +1046,10 @@ int fit_check_format(const void *fit);
> > > > >
> > > > > int fit_conf_find_compat(const void *fit, const void *fdt);
> > > > > int fit_conf_get_node(const void *fit, const char
> > > > > *conf_uname);
> > > > > +int fit_conf_get_prop_node_count(const void *fit, int noffset,
> > > > > + const char *prop_name);
> > > > > +int fit_conf_get_prop_node_index(const void *fit, int noffset,
> > > > > + const char *prop_name, int index);
> > > > >
> > > > > /**
> > > > > * fit_conf_get_prop_node() - Get node refered to by a
> > > > > configuration
> > > > >
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v12 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL
2019-05-02 7:56 ` Chee, Tien Fong
@ 2019-05-03 11:54 ` Simon Goldschmidt
2019-05-06 3:34 ` Chee, Tien Fong
0 siblings, 1 reply; 27+ messages in thread
From: Simon Goldschmidt @ 2019-05-03 11:54 UTC (permalink / raw)
To: u-boot
On Thu, May 2, 2019 at 9:56 AM Chee, Tien Fong <tien.fong.chee@intel.com> wrote:
>
> On Tue, 2019-04-30 at 14:26 +0200, Simon Goldschmidt wrote:
> > On Tue, Apr 30, 2019 at 2:19 PM Chee, Tien Fong
> > <tien.fong.chee@intel.com> wrote:
> > >
> > >
> > > On Sat, 2019-04-27 at 21:50 +0200, Simon Goldschmidt wrote:
> > > >
> > > >
> > > > On 19.03.19 09:50, tien.fong.chee at intel.com wrote:
> > > > >
> > > > >
> > > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > >
> > > > > Increasing Malloc pool size up to 0x15000 is required to
> > > > > support
> > > > > FAT in SPL
> > > > > . The result of calculation is come from after applying some
> > > > > few
> > > > > patches
> > > > "Some few patches"? What should that mean? Either you refer to
> > > > the
> > > > current state or you can refer to the patchwork items.
> > > >
> > > > >
> > > > >
> > > > > which are required for optimizing vfat and maximizing resusable
> > > > > of
> > > > > the
> > > > > memory pool, and then followed by the size required come from
> > > > > default max
> > > > > cluster(0x10000) + others(0x2000) + additional memory for
> > > > > headroom(0x3000).
> > > > > Previous records of describing these few patches can be checked
> > > > > from here
> > > > > [v7]: https://www.mail-archive.com/u-boot at lists.denx.de/msg3145
> > > > > 11.h
> > > > > tml .
> > > > Why do you refer to mail-archive.com instead of patchwork?
> > > Contains the cover letter in case reviewer need to know more
> > > information.
> > I think you understood that wrong. Why do you reference a 3rd party
> > host (mail-archive.com) instead of the official list archive or
> > patchwork?
> >
> > And please note patchwork keeps the cover letter as well.
>
> Okay, i can't find any cover letter from this link https://patchwork.oz
> labs.org/project/uboot/list/?series=&submitter=70549&state=*&q=&archive
> =both&delegate= . Do you know how to find it?
- Go to one of the patches of v7, e.g.:
https://patchwork.ozlabs.org/patch/1034279/
- click "Related"
- click the 0/7 link and you'll get the cover letter:
https://patchwork.ozlabs.org/cover/1034282/
>
> >
> > Also note, this is the commit message which will got into the git
> > lot.
> > Referencing v7 and older history seems misplaced here. Better move
> > it below the '---'.
>
> Okay, noted. So, what should i do with this patch now? Should i send
> next version with new commit message?
Well, I don't really care about which host you reference, but yes,
please send a version that doesn't contain such a reference in
the commit log.
Other than that, the series is, well, good enough for me to be
accepted, I guess.
Regards,
Simon
>
> Thanks.
> TF
>
> >
> > >
> > >
> > > Thanks.
> > > >
> > > >
> > > > >
> > > > >
> > > > >
> > > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > >
> > > > > ---
> > > > >
> > > > > changes for v12
> > > > > - Improved the commit messages.
> > > > >
> > > > > changes for v11
> > > > > - No changes.
> > > > >
> > > > > changes for v10
> > > > > - No changes.
> > > > >
> > > > > changes for v9
> > > > > - No changes.
> > > > >
> > > > > changes for v8
> > > > > - Moved the FIT related configs to the patch of configuration
> > > > > for
> > > > > FPGA
> > > > > SoCFPGA A10 SoCDK.
> > > > >
> > > > > changes for v7
> > > > > - Keep minimal configs.
> > > > > ---
> > > > > include/configs/socfpga_common.h | 4 ++--
> > > > > 1 file changed, 2 insertions(+), 2 deletions(-)
> > > > >
> > > > > diff --git a/include/configs/socfpga_common.h
> > > > > b/include/configs/socfpga_common.h
> > > > > index 181af9b646..22533036ed 100644
> > > > > --- a/include/configs/socfpga_common.h
> > > > > +++ b/include/configs/socfpga_common.h
> > > > > @@ -1,6 +1,6 @@
> > > > > /* SPDX-License-Identifier: GPL-2.0+ */
> > > > > /*
> > > > > - * Copyright (C) 2012 Altera Corporation <www.altera.com>
> > > > > + * Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
> > > > > */
> > > > > #ifndef __CONFIG_SOCFPGA_COMMON_H__
> > > > > #define __CONFIG_SOCFPGA_COMMON_H__
> > > > > @@ -254,7 +254,7 @@ unsigned int
> > > > > cm_get_qspi_controller_clk_hz(void);
> > > > > #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > > > /* SPL memory allocation configuration, this is for FAT
> > > > > implementation */
> > > > > #ifndef CONFIG_SYS_SPL_MALLOC_START
> > > > > -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
> > > > > +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00015000
> > > > > #define
> > > > > CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_S
> > > > > IZE - \
> > > > > CONFIG_SYS_SPL_MALLOC_SI
> > > > > ZE + \
> > > > > CONFIG_SYS_INIT_RAM_ADDR
> > > > > )
> > > > >
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v12 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL
2019-05-03 11:54 ` Simon Goldschmidt
@ 2019-05-06 3:34 ` Chee, Tien Fong
0 siblings, 0 replies; 27+ messages in thread
From: Chee, Tien Fong @ 2019-05-06 3:34 UTC (permalink / raw)
To: u-boot
On Fri, 2019-05-03 at 13:54 +0200, Simon Goldschmidt wrote:
> On Thu, May 2, 2019 at 9:56 AM Chee, Tien Fong <tien.fong.chee@intel.
> com> wrote:
> >
> >
> > On Tue, 2019-04-30 at 14:26 +0200, Simon Goldschmidt wrote:
> > >
> > > On Tue, Apr 30, 2019 at 2:19 PM Chee, Tien Fong
> > > <tien.fong.chee@intel.com> wrote:
> > > >
> > > >
> > > >
> > > > On Sat, 2019-04-27 at 21:50 +0200, Simon Goldschmidt wrote:
> > > > >
> > > > >
> > > > >
> > > > > On 19.03.19 09:50, tien.fong.chee at intel.com wrote:
> > > > > >
> > > > > >
> > > > > >
> > > > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > >
> > > > > > Increasing Malloc pool size up to 0x15000 is required to
> > > > > > support
> > > > > > FAT in SPL
> > > > > > . The result of calculation is come from after applying
> > > > > > some
> > > > > > few
> > > > > > patches
> > > > > "Some few patches"? What should that mean? Either you refer
> > > > > to
> > > > > the
> > > > > current state or you can refer to the patchwork items.
> > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > > which are required for optimizing vfat and maximizing
> > > > > > resusable
> > > > > > of
> > > > > > the
> > > > > > memory pool, and then followed by the size required come
> > > > > > from
> > > > > > default max
> > > > > > cluster(0x10000) + others(0x2000) + additional memory for
> > > > > > headroom(0x3000).
> > > > > > Previous records of describing these few patches can be
> > > > > > checked
> > > > > > from here
> > > > > > [v7]: https://www.mail-archive.com/u-boot at lists.denx.de/msg
> > > > > > 3145
> > > > > > 11.h
> > > > > > tml .
> > > > > Why do you refer to mail-archive.com instead of patchwork?
> > > > Contains the cover letter in case reviewer need to know more
> > > > information.
> > > I think you understood that wrong. Why do you reference a 3rd
> > > party
> > > host (mail-archive.com) instead of the official list archive or
> > > patchwork?
> > >
> > > And please note patchwork keeps the cover letter as well.
> > Okay, i can't find any cover letter from this link https://patchwor
> > k.oz
> > labs.org/project/uboot/list/?series=&submitter=70549&state=*&q=&arc
> > hive
> > =both&delegate= . Do you know how to find it?
> - Go to one of the patches of v7, e.g.:
> https://patchwork.ozlabs.org/patch/1034279/
> - click "Related"
> - click the 0/7 link and you'll get the cover letter:
> https://patchwork.ozlabs.org/cover/1034282/
>
> >
> >
> > >
> > >
> > > Also note, this is the commit message which will got into the git
> > > lot.
> > > Referencing v7 and older history seems misplaced here. Better
> > > move
> > > it below the '---'.
> > Okay, noted. So, what should i do with this patch now? Should i
> > send
> > next version with new commit message?
> Well, I don't really care about which host you reference, but yes,
> please send a version that doesn't contain such a reference in
> the commit log.
>
> Other than that, the series is, well, good enough for me to be
> accepted, I guess.
>
> Regards,
> Simon
>
Okay, i will send a next version.
> >
> >
> > Thanks.
> > TF
> >
> > >
> > >
> > > >
> > > >
> > > >
> > > > Thanks.
> > > > >
> > > > >
> > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > >
> > > > > > ---
> > > > > >
> > > > > > changes for v12
> > > > > > - Improved the commit messages.
> > > > > >
> > > > > > changes for v11
> > > > > > - No changes.
> > > > > >
> > > > > > changes for v10
> > > > > > - No changes.
> > > > > >
> > > > > > changes for v9
> > > > > > - No changes.
> > > > > >
> > > > > > changes for v8
> > > > > > - Moved the FIT related configs to the patch of
> > > > > > configuration
> > > > > > for
> > > > > > FPGA
> > > > > > SoCFPGA A10 SoCDK.
> > > > > >
> > > > > > changes for v7
> > > > > > - Keep minimal configs.
> > > > > > ---
> > > > > > include/configs/socfpga_common.h | 4 ++--
> > > > > > 1 file changed, 2 insertions(+), 2 deletions(-)
> > > > > >
> > > > > > diff --git a/include/configs/socfpga_common.h
> > > > > > b/include/configs/socfpga_common.h
> > > > > > index 181af9b646..22533036ed 100644
> > > > > > --- a/include/configs/socfpga_common.h
> > > > > > +++ b/include/configs/socfpga_common.h
> > > > > > @@ -1,6 +1,6 @@
> > > > > > /* SPDX-License-Identifier: GPL-2.0+ */
> > > > > > /*
> > > > > > - * Copyright (C) 2012 Altera Corporation <www.altera.com>
> > > > > > + * Copyright (C) 2012-2019 Altera Corporation <www.altera.
> > > > > > com>
> > > > > > */
> > > > > > #ifndef __CONFIG_SOCFPGA_COMMON_H__
> > > > > > #define __CONFIG_SOCFPGA_COMMON_H__
> > > > > > @@ -254,7 +254,7 @@ unsigned int
> > > > > > cm_get_qspi_controller_clk_hz(void);
> > > > > > #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > > > > /* SPL memory allocation configuration, this is for FAT
> > > > > > implementation */
> > > > > > #ifndef CONFIG_SYS_SPL_MALLOC_START
> > > > > > -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
> > > > > > +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00015000
> > > > > > #define
> > > > > > CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_S
> > > > > > IZE - \
> > > > > > CONFIG_SYS_SPL_MALLOC_
> > > > > > SI
> > > > > > ZE + \
> > > > > > CONFIG_SYS_INIT_RAM_AD
> > > > > > DR
> > > > > > )
> > > > > >
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v12 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
2019-05-03 11:26 ` Simon Goldschmidt
@ 2019-05-06 3:36 ` Chee, Tien Fong
2019-05-06 7:14 ` Simon Goldschmidt
0 siblings, 1 reply; 27+ messages in thread
From: Chee, Tien Fong @ 2019-05-06 3:36 UTC (permalink / raw)
To: u-boot
On Fri, 2019-05-03 at 13:26 +0200, Simon Goldschmidt wrote:
> On Thu, May 2, 2019 at 9:49 AM Chee, Tien Fong <tien.fong.chee@intel.
> com> wrote:
> >
> >
> > On Tue, 2019-04-30 at 14:24 +0200, Simon Goldschmidt wrote:
> > >
> > > On Tue, Apr 30, 2019 at 2:09 PM Chee, Tien Fong
> > > <tien.fong.chee@intel.com> wrote:
> > > >
> > > >
> > > >
> > > > On Sat, 2019-04-27 at 21:57 +0200, Simon Goldschmidt wrote:
> > > > >
> > > > >
> > > > >
> > > > > On 19.03.19 09:50, tien.fong.chee at intel.com wrote:
> > > > > >
> > > > > >
> > > > > >
> > > > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > >
> > > > > > Add FPGA driver to support program FPGA with FPGA bitstream
> > > > > > loading
> > > > > > from
> > > > > > filesystem. The driver are designed based on generic
> > > > > > firmware
> > > > > > loader
> > > > > > framework. The driver can handle FPGA program operation
> > > > > > from
> > > > > > loading FPGA
> > > > > > bitstream in flash to memory and then to program FPGA.
> > > > > >
> > > > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > >
> > > > > > ---
> > > > > >
> > > > > > changes for v12
> > > > > > - No changes.
> > > > > >
> > > > > > changes for v11
> > > > > > - No changes.
> > > > > >
> > > > > > changes for v10
> > > > > > -Cleaned up the codes.
> > > > > > -Return -EPERM when programing core on non early IO release
> > > > > > mode. >
> > > > > > -Using live function to get rid of gd->
> > > > > You got rid of gd-> in v10? How come I see numerous
> > > > > references to
> > > > > it
> > > > > below?
> > > > get rid of using gd->fdt_blob for finding the node_offset.
> > > > Details in https://patchwork.ozlabs.org/patch/1044415/
> > > Ah, ok. But still, here you're introducing yet more references to
> > > gd-
> > > >
> > > > fdt_blob.
> > > That wouldn't work with a live tree, either, or would it?
> > Yeah, few direct call to config_pin function are still using gd-
> > fdt_blob as argument. But, i'm not sure i should fix this function
> > in
> > this series patch set, or separately patch after this series patch
> > set?
> >
> > What do you think?
> While I do have a strong opinion that this should be cleaned up,
> it would be kind of off-topic in this patch. I was just confused by
> the
> version log.
>
> Regards,
> Simon
Okay, how about we keep these changes. I will send out the fix
separately after this patch set.
Thanks.
>
> >
> >
> > Thanks,
> > TF
> > >
> > >
> > > >
> > > >
> > > >
> > > > -/*
> > > > - * FPGA Manager to program the FPGA. This is the interface
> > > > used by
> > > > FPGA driver.
> > > > - * Return 0 for sucess, non-zero for error.
> > > > - */
> > > > +ofnode get_fpga_mgr_ofnode(void)
> > > > +{
> > > > + int node_offset;
> > > > +
> > > > + fdtdec_find_aliases_for_id(gd->fdt_blob, "fpga_mgr",
> > > >
> > > > nit: using of live functions would be better to get rid of gd-
> > > > >.
> > > >
> > > > + COMPAT_ALTERA_SOCFPGA_FPGA0,
> > > > + &node_offset, 1);
> > > >
> > > > Thanks.
> > > > >
> > > > >
> > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > > -Removed @0 for fs-loader node
> > > > > >
> > > > > > changes for v9
> > > > > > - Support data offset
> > > > > > - Added default DDR load address
> > > > > > - Squashed the image.h
> > > > > > - Changed to phandle
> > > > > > - Ensure the DDR is fully up running by checking the gd-
> > > > > > >ram
> > > > > >
> > > > > > changes for v8
> > > > > > - Added codes to discern bitstream type based on fpga node
> > > > > > name.
> > > > > >
> > > > > > changes for v7
> > > > > > - Restructure the FPGA driver to support both peripheral
> > > > > > bitstream
> > > > > > and core
> > > > > > bitstream bundled into FIT image.
> > > > > > - Support loadable property for core bitstream. User can
> > > > > > set
> > > > > > loadable
> > > > > > in DDR for better performance. This loading would be
> > > > > > done in
> > > > > > one
> > > > > > large
> > > > > > chunk instead of chunk by chunk loading with small
> > > > > > memory
> > > > > > buffer.
> > > > > > ---
> > > > > > arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17
> > > > > > +
> > > > > > .../include/mach/fpga_manager_arria10.h | 39
> > > > > > +-
> > > > > > drivers/fpga/socfpga_arria10.c | 497
> > > > > > ++++++++++++++++++++-
> > > > > > include/image.h | 4
> > > > > > +
> > > > > > 4 files changed, 542 insertions(+), 15 deletions(-)
> > > > > >
> > > > > > diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > > > b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > > > index 998d811210..cc761967c7 100644
> > > > > > --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > > > +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > > > @@ -18,6 +18,23 @@
> > > > > > /dts-v1/;
> > > > > > #include "socfpga_arria10_socdk.dtsi"
> > > > > >
> > > > > > +/ {
> > > > > > + chosen {
> > > > > > + firmware-loader = <&fs_loader0>;
> > > > > > + };
> > > > > > +
> > > > > > + fs_loader0: fs-loader {
> > > > > > + u-boot,dm-pre-reloc;
> > > > > > + compatible = "u-boot,fs-loader";
> > > > > > + phandlepart = <&mmc 1>;
> > > > > > + };
> > > > > > +};
> > > > > > +
> > > > > > +&fpga_mgr {
> > > > > > + u-boot,dm-pre-reloc;
> > > > > > + altr,bitstream = "fit_spl_fpga.itb";
> > > > > > +};
> > > > > > +
> > > > > > &mmc {
> > > > > > u-boot,dm-pre-reloc;
> > > > > > status = "okay";
> > > > > > diff --git a/arch/arm/mach-
> > > > > > socfpga/include/mach/fpga_manager_arria10.h
> > > > > > b/arch/arm/mach-
> > > > > > socfpga/include/mach/fpga_manager_arria10.h
> > > > > > index 09d13f6fd3..c5f67714aa 100644
> > > > > > --- a/arch/arm/mach-
> > > > > > socfpga/include/mach/fpga_manager_arria10.h
> > > > > > +++ b/arch/arm/mach-
> > > > > > socfpga/include/mach/fpga_manager_arria10.h
> > > > > > @@ -1,9 +1,13 @@
> > > > > > /* SPDX-License-Identifier: GPL-2.0 */
> > > > > > /*
> > > > > > - * Copyright (C) 2017 Intel Corporation <www.intel.com>
> > > > > > + * Copyright (C) 2017-2019 Intel Corporation <www.intel.co
> > > > > > m>
> > > > > > * All rights reserved.
> > > > > > */
> > > > > >
> > > > > > +#include <asm/cache.h>
> > > > > > +#include <altera.h>
> > > > > > +#include <image.h>
> > > > > > +
> > > > > > #ifndef _FPGA_MANAGER_ARRIA10_H_
> > > > > > #define _FPGA_MANAGER_ARRIA10_H_
> > > > > >
> > > > > > @@ -51,6 +55,10 @@
> > > > > > #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK
> > > > > > BIT(24)
> > > > > > #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB
> > > > > > 16
> > > > > >
> > > > > > +#define FPGA_SOCFPGA_A10_RBF_UNENCRYPTED 0xa65c
> > > > > > +#define FPGA_SOCFPGA_A10_RBF_ENCRYPTED 0xa65d
> > > > > > +#define FPGA_SOCFPGA_A10_RBF_PERIPH 0x0001
> > > > > > +#define FPGA_SOCFPGA_A10_RBF_CORE 0x8001
> > > > > > #ifndef __ASSEMBLY__
> > > > > >
> > > > > > struct socfpga_fpga_manager {
> > > > > > @@ -88,12 +96,39 @@ struct socfpga_fpga_manager {
> > > > > > u32 imgcfg_fifo_status;
> > > > > > };
> > > > > >
> > > > > > +enum rbf_type {
> > > > > > + unknown,
> > > > > > + periph_section,
> > > > > > + core_section
> > > > > > +};
> > > > > > +
> > > > > > +enum rbf_security {
> > > > > > + invalid,
> > > > > > + unencrypted,
> > > > > > + encrypted
> > > > > > +};
> > > > > > +
> > > > > > +struct rbf_info {
> > > > > > + enum rbf_type section;
> > > > > > + enum rbf_security security;
> > > > > > +};
> > > > > > +
> > > > > > +struct fpga_loadfs_info {
> > > > > > + fpga_fs_info *fpga_fsinfo;
> > > > > > + u32 remaining;
> > > > > > + u32 offset;
> > > > > > + struct rbf_info rbfinfo;
> > > > > > +};
> > > > > > +
> > > > > > /* Functions */
> > > > > > int fpgamgr_program_init(u32 * rbf_data, size_t
> > > > > > rbf_size);
> > > > > > int fpgamgr_program_finish(void);
> > > > > > int is_fpgamgr_user_mode(void);
> > > > > > int fpgamgr_wait_early_user_mode(void);
> > > > > > -
> > > > > > +const char *get_fpga_filename(void);
> > > > > > +int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void
> > > > > > *buf,
> > > > > > size_t bsize,
> > > > > > + u32 offset);
> > > > > > +void fpgamgr_program(const void *buf, size_t bsize, u32
> > > > > > offset);
> > > > > > #endif /* __ASSEMBLY__ */
> > > > > >
> > > > > > #endif /* _FPGA_MANAGER_ARRIA10_H_ */
> > > > > > diff --git a/drivers/fpga/socfpga_arria10.c
> > > > > > b/drivers/fpga/socfpga_arria10.c
> > > > > > index 9499d1a014..9df2c430d7 100644
> > > > > > --- a/drivers/fpga/socfpga_arria10.c
> > > > > > +++ b/drivers/fpga/socfpga_arria10.c
> > > > > > @@ -1,8 +1,7 @@
> > > > > > // SPDX-License-Identifier: GPL-2.0
> > > > > > /*
> > > > > > - * Copyright (C) 2017 Intel Corporation <www.intel.com>
> > > > > > + * Copyright (C) 2017-2019 Intel Corporation <www.intel.co
> > > > > > m>
> > > > > > */
> > > > > > -
> > > > > > #include <asm/io.h>
> > > > > > #include <asm/arch/fpga_manager.h>
> > > > > > #include <asm/arch/reset_manager.h>
> > > > > > @@ -10,8 +9,11 @@
> > > > > > #include <asm/arch/sdram.h>
> > > > > > #include <asm/arch/misc.h>
> > > > > > #include <altera.h>
> > > > > > +#include <asm/arch/pinmux.h>
> > > > > > #include <common.h>
> > > > > > +#include <dm/ofnode.h>
> > > > > > #include <errno.h>
> > > > > > +#include <fs_loader.h>
> > > > > > #include <wait_bit.h>
> > > > > > #include <watchdog.h>
> > > > > >
> > > > > > @@ -21,6 +23,9 @@
> > > > > > #define COMPRESSION_OFFSET 229
> > > > > > #define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
> > > > > > #define FPGA_TIMEOUT_CNT 0x1000000
> > > > > > +#define DEFAULT_DDR_LOAD_ADDRESS 0x400
> > > > > > +
> > > > > > +DECLARE_GLOBAL_DATA_PTR;
> > > > > >
> > > > > > static const struct socfpga_fpga_manager
> > > > > > *fpga_manager_base =
> > > > > > (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
> > > > > > @@ -448,13 +453,461 @@ int fpgamgr_program_finish(void)
> > > > > > return 0;
> > > > > > }
> > > > > >
> > > > > > -/*
> > > > > > - * FPGA Manager to program the FPGA. This is the interface
> > > > > > used by
> > > > > > FPGA driver.
> > > > > > - * Return 0 for sucess, non-zero for error.
> > > > > > - */
> > > > > > +ofnode get_fpga_mgr_ofnode(ofnode from)
> > > > > > +{
> > > > > > + return ofnode_by_compatible(from, "altr,socfpga-a10-
> > > > > > fpga-
> > > > > > mgr");
> > > > > > +}
> > > > > > +
> > > > > > +const char *get_fpga_filename(void)
> > > > > > +{
> > > > > > + const char *fpga_filename = NULL;
> > > > > > +
> > > > > > + ofnode fpgamgr_node =
> > > > > > get_fpga_mgr_ofnode(ofnode_null());
> > > > > > +
> > > > > > + if (ofnode_valid(fpgamgr_node))
> > > > > > + fpga_filename =
> > > > > > ofnode_read_string(fpgamgr_node,
> > > > > > + "altr,bitstream
> > > > > > ");
> > > > > > +
> > > > > > + return fpga_filename;
> > > > > > +}
> > > > > > +
> > > > > > +static void get_rbf_image_info(struct rbf_info *rbf, u16
> > > > > > *buffer)
> > > > > > +{
> > > > > > + /*
> > > > > > + * Magic ID starting at:
> > > > > > + * -> 1st dword[15:0] in periph.rbf
> > > > > > + * -> 2nd dword[15:0] in core.rbf
> > > > > > + * Note: dword == 32 bits
> > > > > > + */
> > > > > > + u32 word_reading_max = 2;
> > > > > > + u32 i;
> > > > > > +
> > > > > > + for (i = 0; i < word_reading_max; i++) {
> > > > > > + if (*(buffer + i) ==
> > > > > > FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
> > > > > > + rbf->security = unencrypted;
> > > > > > + } else if (*(buffer + i) ==
> > > > > > FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
> > > > > > + rbf->security = encrypted;
> > > > > > + } else if (*(buffer + i + 1) ==
> > > > > > + FPGA_SOCFPGA_A10_RBF_UNENCRYPTE
> > > > > > D)
> > > > > > {
> > > > > > + rbf->security = unencrypted;
> > > > > > + } else if (*(buffer + i + 1) ==
> > > > > > + FPGA_SOCFPGA_A10_RBF_ENCRYPTED)
> > > > > > {
> > > > > > + rbf->security = encrypted;
> > > > > > + } else {
> > > > > > + rbf->security = invalid;
> > > > > > + continue;
> > > > > > + }
> > > > > > +
> > > > > > + /* PERIPH RBF(buffer + i + 1), CORE RBF(buffer
> > > > > > + i
> > > > > > + 2) */
> > > > > > + if (*(buffer + i + 1) ==
> > > > > > FPGA_SOCFPGA_A10_RBF_PERIPH) {
> > > > > > + rbf->section = periph_section;
> > > > > > + break;
> > > > > > + } else if (*(buffer + i + 1) ==
> > > > > > FPGA_SOCFPGA_A10_RBF_CORE) {
> > > > > > + rbf->section = core_section;
> > > > > > + break;
> > > > > > + } else if (*(buffer + i + 2) ==
> > > > > > FPGA_SOCFPGA_A10_RBF_PERIPH) {
> > > > > > + rbf->section = periph_section;
> > > > > > + break;
> > > > > > + } else if (*(buffer + i + 2) ==
> > > > > > FPGA_SOCFPGA_A10_RBF_CORE) {
> > > > > > + rbf->section = core_section;
> > > > > > + break;
> > > > > > + }
> > > > > > +
> > > > > > + rbf->section = unknown;
> > > > > > + break;
> > > > > > +
> > > > > > + WATCHDOG_RESET();
> > > > > > + }
> > > > > > +}
> > > > > > +
> > > > > > +#ifdef CONFIG_FS_LOADER
> > > > > > +static int first_loading_rbf_to_buffer(struct udevice
> > > > > > *dev,
> > > > > > + struct fpga_loadfs_info
> > > > > > *fpga_loadfs,
> > > > > > + u32 *buffer, size_t
> > > > > > *buffer_bsize)
> > > > > > +{
> > > > > > + u32 *buffer_p = (u32 *)*buffer;
> > > > > > + u32 *loadable = buffer_p;
> > > > > > + size_t buffer_size = *buffer_bsize;
> > > > > > + size_t fit_size;
> > > > > > + int ret, i, count, confs_noffset, images_noffset,
> > > > > > rbf_offset, rbf_size;
> > > > > > + const char *fpga_node_name = NULL;
> > > > > > + const char *uname = NULL;
> > > > > > +
> > > > > > + /* Load image header into buffer */
> > > > > > + ret = request_firmware_into_buf(dev,
> > > > > > + fpga_loadfs-
> > > > > > >fpga_fsinfo-
> > > > > > >
> > > > > > >
> > > > > > > filename,
> > > > > > + buffer_p, sizeof(struct
> > > > > > image_header),
> > > > > > + 0);
> > > > > > + if (ret < 0) {
> > > > > > + debug("FPGA: Failed to read image header from
> > > > > > flash.\n");
> > > > > > + return -ENOENT;
> > > > > > + }
> > > > > > +
> > > > > > + if (image_get_magic((struct image_header *)buffer_p) !=
> > > > > > FDT_MAGIC) {
> > > > > > + debug("FPGA: No FDT magic was found.\n");
> > > > > > + return -EBADF;
> > > > > > + }
> > > > > > +
> > > > > > + fit_size = fdt_totalsize(buffer_p);
> > > > > > +
> > > > > > + if (fit_size > buffer_size) {
> > > > > > + debug("FPGA: FIT image is larger than available
> > > > > > buffer.\n");
> > > > > > + debug("Please use FIT external data or
> > > > > > increasing
> > > > > > buffer.\n");
> > > > > > + return -ENOMEM;
> > > > > > + }
> > > > > > +
> > > > > > + /* Load entire FIT into buffer */
> > > > > > + ret = request_firmware_into_buf(dev,
> > > > > > + fpga_loadfs-
> > > > > > >fpga_fsinfo-
> > > > > > >
> > > > > > >
> > > > > > > filename,
> > > > > > + buffer_p, fit_size, 0);
> > > > > > + if (ret < 0)
> > > > > > + return ret;
> > > > > > +
> > > > > > + ret = fit_check_format(buffer_p);
> > > > > > + if (!ret) {
> > > > > > + debug("FPGA: No valid FIT image was found.\n");
> > > > > > + return -EBADF;
> > > > > > + }
> > > > > > +
> > > > > > + confs_noffset = fdt_path_offset(buffer_p,
> > > > > > FIT_CONFS_PATH);
> > > > > > + images_noffset = fdt_path_offset(buffer_p,
> > > > > > FIT_IMAGES_PATH);
> > > > > > + if (confs_noffset < 0 || images_noffset < 0) {
> > > > > > + debug("FPGA: No Configurations or images nodes
> > > > > > were found.\n");
> > > > > > + return -ENOENT;
> > > > > > + }
> > > > > > +
> > > > > > + /* Get default configuration unit name from default
> > > > > > property */
> > > > > > + confs_noffset = fit_conf_get_node(buffer_p, NULL);
> > > > > > + if (confs_noffset < 0) {
> > > > > > + debug("FPGA: No default configuration was found
> > > > > > in
> > > > > > config.\n");
> > > > > > + return -ENOENT;
> > > > > > + }
> > > > > > +
> > > > > > + count = fit_conf_get_prop_node_count(buffer_p,
> > > > > > confs_noffset,
> > > > > > + FIT_FPGA_PROP);
> > > > > > + if (count < 0) {
> > > > > > + debug("FPGA: Invalid configuration format for
> > > > > > FPGA
> > > > > > node.\n");
> > > > > > + return count;
> > > > > > + }
> > > > > > + debug("FPGA: FPGA node count: %d\n", count);
> > > > > > +
> > > > > > + for (i = 0; i < count; i++) {
> > > > > > + images_noffset =
> > > > > > fit_conf_get_prop_node_index(buffer_p,
> > > > > > + co
> > > > > > nfs
> > > > > > _noffset,
> > > > > > + FI
> > > > > > T_F
> > > > > > PGA_PROP, i);
> > > > > > + uname = fit_get_name(buffer_p, images_noffset,
> > > > > > NULL);
> > > > > > + if (uname) {
> > > > > > + debug("FPGA: %s\n", uname);
> > > > > > +
> > > > > > + if (strstr(uname, "fpga-periph") &&
> > > > > > + (!is_fpgamgr_early_user_mode()
> > > > > > ||
> > > > > > + is_fpgamgr_user_mode())) {
> > > > > > + fpga_node_name = uname;
> > > > > > + printf("FPGA: Start to program
> > > > > > ");
> > > > > > + printf("peripheral/full
> > > > > > bitstream
> > > > > > ...\n");
> > > > > > + break;
> > > > > > + } else if (strstr(uname, "fpga-core")
> > > > > > &&
> > > > > > + (is_fpgamgr_early_user_
> > > > > > mod
> > > > > > e() &&
> > > > > > + !is_fpgamgr_user_mode()
> > > > > > ))
> > > > > > {
> > > > > > + fpga_node_name = uname;
> > > > > > + printf("FPGA: Start to program
> > > > > > core ");
> > > > > > + printf("bitstream ...\n");
> > > > > > + break;
> > > > > > + }
> > > > > > + }
> > > > > > + WATCHDOG_RESET();
> > > > > > + }
> > > > > > +
> > > > > > + if (!fpga_node_name) {
> > > > > > + debug("FPGA: No suitable bitstream was found,
> > > > > > count: %d.\n", i);
> > > > > > + return 1;
> > > > > > + }
> > > > > > +
> > > > > > + images_noffset = fit_image_get_node(buffer_p,
> > > > > > fpga_node_name);
> > > > > > + if (images_noffset < 0) {
> > > > > > + debug("FPGA: No node '%s' was found in FIT.\n",
> > > > > > + fpga_node_name);
> > > > > > + return -ENOENT;
> > > > > > + }
> > > > > > +
> > > > > > + if (!fit_image_get_data_position(buffer_p,
> > > > > > images_noffset,
> > > > > > + &rbf_offset)) {
> > > > > > + debug("FPGA: Data position was found.\n");
> > > > > > + } else if (!fit_image_get_data_offset(buffer_p,
> > > > > > images_noffset,
> > > > > > + &rbf_offset)) {
> > > > > > + /*
> > > > > > + * For FIT with external data, figure out where
> > > > > > + * the external images start. This is the base
> > > > > > + * for the data-offset properties in each
> > > > > > image.
> > > > > > + */
> > > > > > + rbf_offset += ((fdt_totalsize(buffer_p) + 3) &
> > > > > > ~3);
> > > > > > + debug("FPGA: Data offset was found.\n");
> > > > > > + } else {
> > > > > > + debug("FPGA: No data position/offset was
> > > > > > found.\n");
> > > > > > + return -ENOENT;
> > > > > > + }
> > > > > > +
> > > > > > + ret = fit_image_get_data_size(buffer_p, images_noffset,
> > > > > > &rbf_size);
> > > > > > + if (ret < 0) {
> > > > > > + debug("FPGA: No data size was found
> > > > > > (err=%d).\n",
> > > > > > ret);
> > > > > > + return -ENOENT;
> > > > > > + }
> > > > > > +
> > > > > > + if (gd->ram_size < rbf_size) {
> > > > > > + debug("FPGA: Using default OCRAM buffer and
> > > > > > size.\n");
> > > > > > + } else {
> > > > > > + ret = fit_image_get_load(buffer_p,
> > > > > > images_noffset,
> > > > > > + (ulong *)loadable);
> > > > > > + if (ret < 0) {
> > > > > > + buffer_p = (u32
> > > > > > *)DEFAULT_DDR_LOAD_ADDRESS;
> > > > > > + debug("FPGA: No loadable was
> > > > > > found.\n");
> > > > > > + debug("FPGA: Using default DDR load
> > > > > > address: 0x%x .\n",
> > > > > > + DEFAULT_DDR_LOAD_ADDRESS);
> > > > > > + } else {
> > > > > > + buffer_p = (u32 *)*loadable;
> > > > > > + debug("FPGA: Found loadable address =
> > > > > > 0x%x.\n",
> > > > > > + *loadable);
> > > > > > + }
> > > > > > +
> > > > > > + buffer_size = rbf_size;
> > > > > > + }
> > > > > > +
> > > > > > + debug("FPGA: External data: offset = 0x%x, size =
> > > > > > 0x%x.\n",
> > > > > > + rbf_offset, rbf_size);
> > > > > > +
> > > > > > + fpga_loadfs->remaining = rbf_size;
> > > > > > +
> > > > > > + /*
> > > > > > + * Determine buffer size vs bitstream size, and
> > > > > > calculating number of
> > > > > > + * chunk by chunk transfer is required due to smaller
> > > > > > buffer size
> > > > > > + * compare to bitstream
> > > > > > + */
> > > > > > + if (rbf_size <= buffer_size) {
> > > > > > + /* Loading whole bitstream into buffer */
> > > > > > + buffer_size = rbf_size;
> > > > > > + fpga_loadfs->remaining = 0;
> > > > > > + } else {
> > > > > > + fpga_loadfs->remaining -= buffer_size;
> > > > > > + }
> > > > > > +
> > > > > > + fpga_loadfs->offset = rbf_offset;
> > > > > > + /* Loading bitstream into buffer */
> > > > > > + ret = request_firmware_into_buf(dev,
> > > > > > + fpga_loadfs-
> > > > > > >fpga_fsinfo-
> > > > > > >
> > > > > > >
> > > > > > > filename,
> > > > > > + buffer_p, buffer_size,
> > > > > > + fpga_loadfs->offset);
> > > > > > + if (ret < 0) {
> > > > > > + debug("FPGA: Failed to read bitstream from
> > > > > > flash.\n");
> > > > > > + return -ENOENT;
> > > > > > + }
> > > > > > +
> > > > > > + /* Getting info about bitstream types */
> > > > > > + get_rbf_image_info(&fpga_loadfs->rbfinfo, (u16
> > > > > > *)buffer_p);
> > > > > > +
> > > > > > + /* Update next reading bitstream offset */
> > > > > > + fpga_loadfs->offset += buffer_size;
> > > > > > +
> > > > > > + /* Update the final addr for bitstream */
> > > > > > + *buffer = (u32)buffer_p;
> > > > > > +
> > > > > > + /* Update the size of bitstream to be programmed into
> > > > > > FPGA
> > > > > > */
> > > > > > + *buffer_bsize = buffer_size;
> > > > > > +
> > > > > > + return 0;
> > > > > > +}
> > > > > > +
> > > > > > +static int subsequent_loading_rbf_to_buffer(struct udevice
> > > > > > *dev,
> > > > > > + struct fpga_loadfs_info
> > > > > > *fpga_loadfs,
> > > > > > + u32 *buffer, size_t
> > > > > > *buffer_bsize)
> > > > > > +{
> > > > > > + int ret = 0;
> > > > > > + u32 *buffer_p = (u32 *)*buffer;
> > > > > > +
> > > > > > + /* Read the bitstream chunk by chunk. */
> > > > > > + if (fpga_loadfs->remaining > *buffer_bsize) {
> > > > > > + fpga_loadfs->remaining -= *buffer_bsize;
> > > > > > + } else {
> > > > > > + *buffer_bsize = fpga_loadfs->remaining;
> > > > > > + fpga_loadfs->remaining = 0;
> > > > > > + }
> > > > > > +
> > > > > > + ret = request_firmware_into_buf(dev,
> > > > > > + fpga_loadfs-
> > > > > > >fpga_fsinfo-
> > > > > > >
> > > > > > >
> > > > > > > filename,
> > > > > > + buffer_p,
> > > > > > *buffer_bsize,
> > > > > > + fpga_loadfs->offset);
> > > > > > + if (ret < 0) {
> > > > > > + debug("FPGA: Failed to read bitstream from
> > > > > > flash.\n");
> > > > > > + return -ENOENT;
> > > > > > + }
> > > > > > +
> > > > > > + /* Update next reading bitstream offset */
> > > > > > + fpga_loadfs->offset += *buffer_bsize;
> > > > > > +
> > > > > > + return 0;
> > > > > > +}
> > > > > > +
> > > > > > +int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void
> > > > > > *buf,
> > > > > > size_t bsize,
> > > > > > + u32 offset)
> > > > > > +{
> > > > > > + struct fpga_loadfs_info fpga_loadfs;
> > > > > > + struct udevice *dev;
> > > > > > + int status, ret, size;
> > > > > > + u32 buffer = (uintptr_t)buf;
> > > > > > + size_t buffer_sizebytes = bsize;
> > > > > > + size_t buffer_sizebytes_ori = bsize;
> > > > > > + size_t total_sizeof_image = 0;
> > > > > > + ofnode node;
> > > > > > + const fdt32_t *phandle_p;
> > > > > > + u32 phandle;
> > > > > > +
> > > > > > + node = get_fpga_mgr_ofnode(ofnode_null());
> > > > > > +
> > > > > > + if (ofnode_valid(node)) {
> > > > > > + phandle_p = ofnode_get_property(node,
> > > > > > "firmware-
> > > > > > loader", &size);
> > > > > > + if (!phandle_p) {
> > > > > > + node = ofnode_path("/chosen");
> > > > > > + if (!ofnode_valid(node)) {
> > > > > > + debug("FPGA: /chosen node was
> > > > > > not
> > > > > > found.\n");
> > > > > > + return -ENOENT;
> > > > > > + }
> > > > > > +
> > > > > > + phandle_p = ofnode_get_property(node,
> > > > > > "firmware-loader",
> > > > > > + &size);
> > > > > > + if (!phandle_p) {
> > > > > > + debug("FPGA: firmware-loader
> > > > > > property was not");
> > > > > > + debug(" found.\n");
> > > > > > + return -ENOENT;
> > > > > > + }
> > > > > > + }
> > > > > > + } else {
> > > > > > + debug("FPGA: FPGA manager node was not
> > > > > > found.\n");
> > > > > > + return -ENOENT;
> > > > > > + }
> > > > > > +
> > > > > > + phandle = fdt32_to_cpu(*phandle_p);
> > > > > > + ret =
> > > > > > uclass_get_device_by_phandle_id(UCLASS_FS_FIRMWARE_LOADER,
> > > > > > + phandle, &dev);
> > > > > > + if (ret)
> > > > > > + return ret;
> > > > > > +
> > > > > > + memset(&fpga_loadfs, 0, sizeof(fpga_loadfs));
> > > > > > +
> > > > > > + fpga_loadfs.fpga_fsinfo = fpga_fsinfo;
> > > > > > + fpga_loadfs.offset = offset;
> > > > > > +
> > > > > > + printf("FPGA: Checking FPGA configuration setting
> > > > > > ...\n");
> > > > > > +
> > > > > > + /*
> > > > > > + * Note: Both buffer and buffer_sizebytes values can be
> > > > > > altered by
> > > > > > + * function below.
> > > > > > + */
> > > > > > + ret = first_loading_rbf_to_buffer(dev, &fpga_loadfs,
> > > > > > &buffer,
> > > > > > + &buffer_sizebytes);
> > > > > > + if (ret == 1) {
> > > > > > + printf("FPGA: Skipping configuration ...\n");
> > > > > > + return 0;
> > > > > > + } else if (ret) {
> > > > > > + return ret;
> > > > > > + }
> > > > > > +
> > > > > > + if (fpga_loadfs.rbfinfo.section == core_section &&
> > > > > > + !(is_fpgamgr_early_user_mode() &&
> > > > > > !is_fpgamgr_user_mode())) {
> > > > > > + debug("FPGA : Must be in Early Release mode to
> > > > > > program ");
> > > > > > + debug("core bitstream.\n");
> > > > > > + return -EPERM;
> > > > > > + }
> > > > > > +
> > > > > > + /* Disable all signals from HPS peripheral controller
> > > > > > to
> > > > > > FPGA */
> > > > > > + writel(0, &system_manager_base->fpgaintf_en_global);
> > > > > > +
> > > > > > + /* Disable all axi bridges (hps2fpga, lwhps2fpga &
> > > > > > fpga2hps) */
> > > > > > + socfpga_bridges_reset();
> > > > > > +
> > > > > > + if (fpga_loadfs.rbfinfo.section == periph_section) {
> > > > > > + /* Initialize the FPGA Manager */
> > > > > > + status = fpgamgr_program_init((u32 *)buffer,
> > > > > > buffer_sizebytes);
> > > > > > + if (status) {
> > > > > > + debug("FPGA: Init with peripheral
> > > > > > bitstream failed.\n");
> > > > > > + return -EPERM;
> > > > > > + }
> > > > > > + }
> > > > > > +
> > > > > > + /* Transfer bitstream to FPGA Manager */
> > > > > > + fpgamgr_program_write((void *)buffer,
> > > > > > buffer_sizebytes);
> > > > > > +
> > > > > > + total_sizeof_image += buffer_sizebytes;
> > > > > > +
> > > > > > + while (fpga_loadfs.remaining) {
> > > > > > + ret = subsequent_loading_rbf_to_buffer(dev,
> > > > > > + &fpga_l
> > > > > > oad
> > > > > > fs,
> > > > > > + &buffer
> > > > > > ,
> > > > > > + &buffer
> > > > > > _si
> > > > > > zebytes_ori);
> > > > > > +
> > > > > > + if (ret)
> > > > > > + return ret;
> > > > > > +
> > > > > > + /* Transfer data to FPGA Manager */
> > > > > > + fpgamgr_program_write((void *)buffer,
> > > > > > + buffer_sizebytes_ori);
> > > > > > +
> > > > > > + total_sizeof_image += buffer_sizebytes_ori;
> > > > > > +
> > > > > > + WATCHDOG_RESET();
> > > > > > + }
> > > > > > +
> > > > > > + if (fpga_loadfs.rbfinfo.section == periph_section) {
> > > > > > + if (fpgamgr_wait_early_user_mode() !=
> > > > > > -ETIMEDOUT)
> > > > > > {
> > > > > > + config_pins(gd->fdt_blob, "shared");
> > > > > > + puts("FPGA: Early Release
> > > > > > Succeeded.\n");
> > > > > > + } else {
> > > > > > + debug("FPGA: Failed to see Early
> > > > > > Release.\n");
> > > > > > + return -EIO;
> > > > > > + }
> > > > > > +
> > > > > > + /* For monolithic bitstream */
> > > > > > + if (is_fpgamgr_user_mode()) {
> > > > > > + /* Ensure the FPGA entering config done
> > > > > > */
> > > > > > + status = fpgamgr_program_finish();
> > > > > > + if (status)
> > > > > > + return status;
> > > > > > +
> > > > > > + config_pins(gd->fdt_blob, "fpga");
> > > > > > + puts("FPGA: Enter user mode.\n");
> > > > > > + }
> > > > > > + } else if (fpga_loadfs.rbfinfo.section == core_section)
> > > > > > {
> > > > > > + /* Ensure the FPGA entering config done */
> > > > > > + status = fpgamgr_program_finish();
> > > > > > + if (status)
> > > > > > + return status;
> > > > > > +
> > > > > > + config_pins(gd->fdt_blob, "fpga");
> > > > > > + puts("FPGA: Enter user mode.\n");
> > > > > > + } else {
> > > > > > + debug("FPGA: Config Error: Unsupported
> > > > > > bitstream
> > > > > > type.\n");
> > > > > > + return -ENOEXEC;
> > > > > > + }
> > > > > > +
> > > > > > + return (int)total_sizeof_image;
> > > > > > +}
> > > > > > +
> > > > > > +void fpgamgr_program(const void *buf, size_t bsize, u32
> > > > > > offset)
> > > > > > +{
> > > > > > + fpga_fs_info fpga_fsinfo;
> > > > > > +
> > > > > > + fpga_fsinfo.filename = get_fpga_filename();
> > > > > > +
> > > > > > + if (fpga_fsinfo.filename)
> > > > > > + socfpga_loadfs(&fpga_fsinfo, buf, bsize,
> > > > > > offset);
> > > > > > +}
> > > > > > +#endif
> > > > > > +
> > > > > > +/* This function is used to load the core bitstream from
> > > > > > the
> > > > > > OCRAM. */
> > > > > > int socfpga_load(Altera_desc *desc, const void *rbf_data,
> > > > > > size_t
> > > > > > rbf_size)
> > > > > > {
> > > > > > - int status;
> > > > > > + unsigned long status;
> > > > > > + struct rbf_info rbfinfo;
> > > > > > +
> > > > > > + memset(&rbfinfo, 0, sizeof(rbfinfo));
> > > > > >
> > > > > > /* Disable all signals from hps peripheral controller
> > > > > > to
> > > > > > fpga */
> > > > > > writel(0, &system_manager_base->fpgaintf_en_global);
> > > > > > @@ -462,13 +915,31 @@ int socfpga_load(Altera_desc *desc,
> > > > > > const
> > > > > > void *rbf_data, size_t rbf_size)
> > > > > > /* Disable all axi bridge (hps2fpga, lwhps2fpga &
> > > > > > fpga2hps) */
> > > > > > socfpga_bridges_reset();
> > > > > >
> > > > > > - /* Initialize the FPGA Manager */
> > > > > > - status = fpgamgr_program_init((u32 *)rbf_data,
> > > > > > rbf_size);
> > > > > > - if (status)
> > > > > > - return status;
> > > > > > + /* Getting info about bitstream types */
> > > > > > + get_rbf_image_info(&rbfinfo, (u16 *)rbf_data);
> > > > > > +
> > > > > > + if (rbfinfo.section == periph_section) {
> > > > > > + /* Initialize the FPGA Manager */
> > > > > > + status = fpgamgr_program_init((u32 *)rbf_data,
> > > > > > rbf_size);
> > > > > > + if (status)
> > > > > > + return status;
> > > > > > + }
> > > > > >
> > > > > > - /* Write the RBF data to FPGA Manager */
> > > > > > + if (rbfinfo.section == core_section &&
> > > > > > + !(is_fpgamgr_early_user_mode() &&
> > > > > > !is_fpgamgr_user_mode())) {
> > > > > > + debug("FPGA : Must be in early release mode to
> > > > > > program ");
> > > > > > + debug("core bitstream.\n");
> > > > > > + return -EPERM;
> > > > > > + }
> > > > > > +
> > > > > > + /* Write the bitstream to FPGA Manager */
> > > > > > fpgamgr_program_write(rbf_data, rbf_size);
> > > > > >
> > > > > > - return fpgamgr_program_finish();
> > > > > > + status = fpgamgr_program_finish();
> > > > > > + if (status) {
> > > > > > + config_pins(gd->fdt_blob, "fpga");
> > > > > > + puts("FPGA: Enter user mode.\n");
> > > > > > + }
> > > > > > +
> > > > > > + return status;
> > > > > > }
> > > > > > diff --git a/include/image.h b/include/image.h
> > > > > > index 765ffecee0..cc976f70ce 100644
> > > > > > --- a/include/image.h
> > > > > > +++ b/include/image.h
> > > > > > @@ -1046,6 +1046,10 @@ int fit_check_format(const void
> > > > > > *fit);
> > > > > >
> > > > > > int fit_conf_find_compat(const void *fit, const void
> > > > > > *fdt);
> > > > > > int fit_conf_get_node(const void *fit, const char
> > > > > > *conf_uname);
> > > > > > +int fit_conf_get_prop_node_count(const void *fit, int
> > > > > > noffset,
> > > > > > + const char *prop_name);
> > > > > > +int fit_conf_get_prop_node_index(const void *fit, int
> > > > > > noffset,
> > > > > > + const char *prop_name, int index);
> > > > > >
> > > > > > /**
> > > > > > * fit_conf_get_prop_node() - Get node refered to by a
> > > > > > configuration
> > > > > >
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v12 4/9] ARM: socfpga: Moving the watchdog reset to the for-loop status polling
2019-04-27 19:34 ` Simon Goldschmidt
2019-04-30 11:57 ` Chee, Tien Fong
@ 2019-05-06 3:36 ` Chee, Tien Fong
1 sibling, 0 replies; 27+ messages in thread
From: Chee, Tien Fong @ 2019-05-06 3:36 UTC (permalink / raw)
To: u-boot
On Sat, 2019-04-27 at 21:34 +0200, Simon Goldschmidt wrote:
>
> On 19.03.19 09:50, tien.fong.chee at intel.com wrote:
> >
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > Ensure the watchdog is reset timely on each status polling.
> I would have expected a longer commit message here explaining why
> this
> is done, and from where, where to, and why the watchdog reset has
> been
> moved.
>
> Anyway, I don't want to hold back this series again for this, but
> please
> next time: write longer commit messages. Better write too much than
> risk
> someone in the future doesn't get what or why you did things.
>
> Thanks,
> Simon
>
I will improve the commit messages in next version patch set.
Thanks.
> >
> >
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > ---
> >
> > changes for v12
> > - Improved the commit messages.
> >
> > changes for v11
> > - No changes.
> >
> > changes for v10
> > - This patch was split out from [PATCH v10 5/9]
> > ARM: socfpga: Add FPGA drivers for Arria 10 FPGA.
> > ---
> > drivers/fpga/socfpga_arria10.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/fpga/socfpga_arria10.c
> > b/drivers/fpga/socfpga_arria10.c
> > index b0abe1955c..9499d1a014 100644
> > --- a/drivers/fpga/socfpga_arria10.c
> > +++ b/drivers/fpga/socfpga_arria10.c
> > @@ -360,6 +360,7 @@ static int fpgamgr_program_poll_cd(void)
> > printf("nstatus == 0 while waiting for
> > condone\n");
> > return -EPERM;
> > }
> > + WATCHDOG_RESET();
> > }
> >
> > if (i == FPGA_TIMEOUT_CNT)
> > @@ -433,7 +434,6 @@ int fpgamgr_program_finish(void)
> > printf("FPGA: Poll CD failed with error code
> > %d\n", status);
> > return -EPERM;
> > }
> > - WATCHDOG_RESET();
> >
> > /* Ensure the FPGA entering user mode */
> > status = fpgamgr_program_poll_usermode();
> >
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH v12 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
2019-05-06 3:36 ` Chee, Tien Fong
@ 2019-05-06 7:14 ` Simon Goldschmidt
0 siblings, 0 replies; 27+ messages in thread
From: Simon Goldschmidt @ 2019-05-06 7:14 UTC (permalink / raw)
To: u-boot
On Mon, May 6, 2019 at 5:36 AM Chee, Tien Fong <tien.fong.chee@intel.com> wrote:
>
> On Fri, 2019-05-03 at 13:26 +0200, Simon Goldschmidt wrote:
> > On Thu, May 2, 2019 at 9:49 AM Chee, Tien Fong <tien.fong.chee@intel.
> > com> wrote:
> > >
> > >
> > > On Tue, 2019-04-30 at 14:24 +0200, Simon Goldschmidt wrote:
> > > >
> > > > On Tue, Apr 30, 2019 at 2:09 PM Chee, Tien Fong
> > > > <tien.fong.chee@intel.com> wrote:
> > > > >
> > > > >
> > > > >
> > > > > On Sat, 2019-04-27 at 21:57 +0200, Simon Goldschmidt wrote:
> > > > > >
> > > > > >
> > > > > >
> > > > > > On 19.03.19 09:50, tien.fong.chee at intel.com wrote:
> > > > > > >
> > > > > > >
> > > > > > >
> > > > > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > > >
> > > > > > > Add FPGA driver to support program FPGA with FPGA bitstream
> > > > > > > loading
> > > > > > > from
> > > > > > > filesystem. The driver are designed based on generic
> > > > > > > firmware
> > > > > > > loader
> > > > > > > framework. The driver can handle FPGA program operation
> > > > > > > from
> > > > > > > loading FPGA
> > > > > > > bitstream in flash to memory and then to program FPGA.
> > > > > > >
> > > > > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > > >
> > > > > > > ---
> > > > > > >
> > > > > > > changes for v12
> > > > > > > - No changes.
> > > > > > >
> > > > > > > changes for v11
> > > > > > > - No changes.
> > > > > > >
> > > > > > > changes for v10
> > > > > > > -Cleaned up the codes.
> > > > > > > -Return -EPERM when programing core on non early IO release
> > > > > > > mode. >
> > > > > > > -Using live function to get rid of gd->
> > > > > > You got rid of gd-> in v10? How come I see numerous
> > > > > > references to
> > > > > > it
> > > > > > below?
> > > > > get rid of using gd->fdt_blob for finding the node_offset.
> > > > > Details in https://patchwork.ozlabs.org/patch/1044415/
> > > > Ah, ok. But still, here you're introducing yet more references to
> > > > gd-
> > > > >
> > > > > fdt_blob.
> > > > That wouldn't work with a live tree, either, or would it?
> > > Yeah, few direct call to config_pin function are still using gd-
> > > fdt_blob as argument. But, i'm not sure i should fix this function
> > > in
> > > this series patch set, or separately patch after this series patch
> > > set?
> > >
> > > What do you think?
> > While I do have a strong opinion that this should be cleaned up,
> > it would be kind of off-topic in this patch. I was just confused by
> > the
> > version log.
> >
> > Regards,
> > Simon
> Okay, how about we keep these changes. I will send out the fix
> separately after this patch set.
That would be best, I think, yes.
Regards,
Simon
>
> Thanks.
> >
> > >
> > >
> > > Thanks,
> > > TF
> > > >
> > > >
> > > > >
> > > > >
> > > > >
> > > > > -/*
> > > > > - * FPGA Manager to program the FPGA. This is the interface
> > > > > used by
> > > > > FPGA driver.
> > > > > - * Return 0 for sucess, non-zero for error.
> > > > > - */
> > > > > +ofnode get_fpga_mgr_ofnode(void)
> > > > > +{
> > > > > + int node_offset;
> > > > > +
> > > > > + fdtdec_find_aliases_for_id(gd->fdt_blob, "fpga_mgr",
> > > > >
> > > > > nit: using of live functions would be better to get rid of gd-
> > > > > >.
> > > > >
> > > > > + COMPAT_ALTERA_SOCFPGA_FPGA0,
> > > > > + &node_offset, 1);
> > > > >
> > > > > Thanks.
> > > > > >
> > > > > >
> > > > > >
> > > > > > >
> > > > > > >
> > > > > > >
> > > > > > > -Removed @0 for fs-loader node
> > > > > > >
> > > > > > > changes for v9
> > > > > > > - Support data offset
> > > > > > > - Added default DDR load address
> > > > > > > - Squashed the image.h
> > > > > > > - Changed to phandle
> > > > > > > - Ensure the DDR is fully up running by checking the gd-
> > > > > > > >ram
> > > > > > >
> > > > > > > changes for v8
> > > > > > > - Added codes to discern bitstream type based on fpga node
> > > > > > > name.
> > > > > > >
> > > > > > > changes for v7
> > > > > > > - Restructure the FPGA driver to support both peripheral
> > > > > > > bitstream
> > > > > > > and core
> > > > > > > bitstream bundled into FIT image.
> > > > > > > - Support loadable property for core bitstream. User can
> > > > > > > set
> > > > > > > loadable
> > > > > > > in DDR for better performance. This loading would be
> > > > > > > done in
> > > > > > > one
> > > > > > > large
> > > > > > > chunk instead of chunk by chunk loading with small
> > > > > > > memory
> > > > > > > buffer.
> > > > > > > ---
> > > > > > > arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17
> > > > > > > +
> > > > > > > .../include/mach/fpga_manager_arria10.h | 39
> > > > > > > +-
> > > > > > > drivers/fpga/socfpga_arria10.c | 497
> > > > > > > ++++++++++++++++++++-
> > > > > > > include/image.h | 4
> > > > > > > +
> > > > > > > 4 files changed, 542 insertions(+), 15 deletions(-)
> > > > > > >
> > > > > > > diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > > > > b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > > > > index 998d811210..cc761967c7 100644
> > > > > > > --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > > > > +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > > > > @@ -18,6 +18,23 @@
> > > > > > > /dts-v1/;
> > > > > > > #include "socfpga_arria10_socdk.dtsi"
> > > > > > >
> > > > > > > +/ {
> > > > > > > + chosen {
> > > > > > > + firmware-loader = <&fs_loader0>;
> > > > > > > + };
> > > > > > > +
> > > > > > > + fs_loader0: fs-loader {
> > > > > > > + u-boot,dm-pre-reloc;
> > > > > > > + compatible = "u-boot,fs-loader";
> > > > > > > + phandlepart = <&mmc 1>;
> > > > > > > + };
> > > > > > > +};
> > > > > > > +
> > > > > > > +&fpga_mgr {
> > > > > > > + u-boot,dm-pre-reloc;
> > > > > > > + altr,bitstream = "fit_spl_fpga.itb";
> > > > > > > +};
> > > > > > > +
> > > > > > > &mmc {
> > > > > > > u-boot,dm-pre-reloc;
> > > > > > > status = "okay";
> > > > > > > diff --git a/arch/arm/mach-
> > > > > > > socfpga/include/mach/fpga_manager_arria10.h
> > > > > > > b/arch/arm/mach-
> > > > > > > socfpga/include/mach/fpga_manager_arria10.h
> > > > > > > index 09d13f6fd3..c5f67714aa 100644
> > > > > > > --- a/arch/arm/mach-
> > > > > > > socfpga/include/mach/fpga_manager_arria10.h
> > > > > > > +++ b/arch/arm/mach-
> > > > > > > socfpga/include/mach/fpga_manager_arria10.h
> > > > > > > @@ -1,9 +1,13 @@
> > > > > > > /* SPDX-License-Identifier: GPL-2.0 */
> > > > > > > /*
> > > > > > > - * Copyright (C) 2017 Intel Corporation <www.intel.com>
> > > > > > > + * Copyright (C) 2017-2019 Intel Corporation <www.intel.co
> > > > > > > m>
> > > > > > > * All rights reserved.
> > > > > > > */
> > > > > > >
> > > > > > > +#include <asm/cache.h>
> > > > > > > +#include <altera.h>
> > > > > > > +#include <image.h>
> > > > > > > +
> > > > > > > #ifndef _FPGA_MANAGER_ARRIA10_H_
> > > > > > > #define _FPGA_MANAGER_ARRIA10_H_
> > > > > > >
> > > > > > > @@ -51,6 +55,10 @@
> > > > > > > #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK
> > > > > > > BIT(24)
> > > > > > > #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB
> > > > > > > 16
> > > > > > >
> > > > > > > +#define FPGA_SOCFPGA_A10_RBF_UNENCRYPTED 0xa65c
> > > > > > > +#define FPGA_SOCFPGA_A10_RBF_ENCRYPTED 0xa65d
> > > > > > > +#define FPGA_SOCFPGA_A10_RBF_PERIPH 0x0001
> > > > > > > +#define FPGA_SOCFPGA_A10_RBF_CORE 0x8001
> > > > > > > #ifndef __ASSEMBLY__
> > > > > > >
> > > > > > > struct socfpga_fpga_manager {
> > > > > > > @@ -88,12 +96,39 @@ struct socfpga_fpga_manager {
> > > > > > > u32 imgcfg_fifo_status;
> > > > > > > };
> > > > > > >
> > > > > > > +enum rbf_type {
> > > > > > > + unknown,
> > > > > > > + periph_section,
> > > > > > > + core_section
> > > > > > > +};
> > > > > > > +
> > > > > > > +enum rbf_security {
> > > > > > > + invalid,
> > > > > > > + unencrypted,
> > > > > > > + encrypted
> > > > > > > +};
> > > > > > > +
> > > > > > > +struct rbf_info {
> > > > > > > + enum rbf_type section;
> > > > > > > + enum rbf_security security;
> > > > > > > +};
> > > > > > > +
> > > > > > > +struct fpga_loadfs_info {
> > > > > > > + fpga_fs_info *fpga_fsinfo;
> > > > > > > + u32 remaining;
> > > > > > > + u32 offset;
> > > > > > > + struct rbf_info rbfinfo;
> > > > > > > +};
> > > > > > > +
> > > > > > > /* Functions */
> > > > > > > int fpgamgr_program_init(u32 * rbf_data, size_t
> > > > > > > rbf_size);
> > > > > > > int fpgamgr_program_finish(void);
> > > > > > > int is_fpgamgr_user_mode(void);
> > > > > > > int fpgamgr_wait_early_user_mode(void);
> > > > > > > -
> > > > > > > +const char *get_fpga_filename(void);
> > > > > > > +int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void
> > > > > > > *buf,
> > > > > > > size_t bsize,
> > > > > > > + u32 offset);
> > > > > > > +void fpgamgr_program(const void *buf, size_t bsize, u32
> > > > > > > offset);
> > > > > > > #endif /* __ASSEMBLY__ */
> > > > > > >
> > > > > > > #endif /* _FPGA_MANAGER_ARRIA10_H_ */
> > > > > > > diff --git a/drivers/fpga/socfpga_arria10.c
> > > > > > > b/drivers/fpga/socfpga_arria10.c
> > > > > > > index 9499d1a014..9df2c430d7 100644
> > > > > > > --- a/drivers/fpga/socfpga_arria10.c
> > > > > > > +++ b/drivers/fpga/socfpga_arria10.c
> > > > > > > @@ -1,8 +1,7 @@
> > > > > > > // SPDX-License-Identifier: GPL-2.0
> > > > > > > /*
> > > > > > > - * Copyright (C) 2017 Intel Corporation <www.intel.com>
> > > > > > > + * Copyright (C) 2017-2019 Intel Corporation <www.intel.co
> > > > > > > m>
> > > > > > > */
> > > > > > > -
> > > > > > > #include <asm/io.h>
> > > > > > > #include <asm/arch/fpga_manager.h>
> > > > > > > #include <asm/arch/reset_manager.h>
> > > > > > > @@ -10,8 +9,11 @@
> > > > > > > #include <asm/arch/sdram.h>
> > > > > > > #include <asm/arch/misc.h>
> > > > > > > #include <altera.h>
> > > > > > > +#include <asm/arch/pinmux.h>
> > > > > > > #include <common.h>
> > > > > > > +#include <dm/ofnode.h>
> > > > > > > #include <errno.h>
> > > > > > > +#include <fs_loader.h>
> > > > > > > #include <wait_bit.h>
> > > > > > > #include <watchdog.h>
> > > > > > >
> > > > > > > @@ -21,6 +23,9 @@
> > > > > > > #define COMPRESSION_OFFSET 229
> > > > > > > #define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
> > > > > > > #define FPGA_TIMEOUT_CNT 0x1000000
> > > > > > > +#define DEFAULT_DDR_LOAD_ADDRESS 0x400
> > > > > > > +
> > > > > > > +DECLARE_GLOBAL_DATA_PTR;
> > > > > > >
> > > > > > > static const struct socfpga_fpga_manager
> > > > > > > *fpga_manager_base =
> > > > > > > (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
> > > > > > > @@ -448,13 +453,461 @@ int fpgamgr_program_finish(void)
> > > > > > > return 0;
> > > > > > > }
> > > > > > >
> > > > > > > -/*
> > > > > > > - * FPGA Manager to program the FPGA. This is the interface
> > > > > > > used by
> > > > > > > FPGA driver.
> > > > > > > - * Return 0 for sucess, non-zero for error.
> > > > > > > - */
> > > > > > > +ofnode get_fpga_mgr_ofnode(ofnode from)
> > > > > > > +{
> > > > > > > + return ofnode_by_compatible(from, "altr,socfpga-a10-
> > > > > > > fpga-
> > > > > > > mgr");
> > > > > > > +}
> > > > > > > +
> > > > > > > +const char *get_fpga_filename(void)
> > > > > > > +{
> > > > > > > + const char *fpga_filename = NULL;
> > > > > > > +
> > > > > > > + ofnode fpgamgr_node =
> > > > > > > get_fpga_mgr_ofnode(ofnode_null());
> > > > > > > +
> > > > > > > + if (ofnode_valid(fpgamgr_node))
> > > > > > > + fpga_filename =
> > > > > > > ofnode_read_string(fpgamgr_node,
> > > > > > > + "altr,bitstream
> > > > > > > ");
> > > > > > > +
> > > > > > > + return fpga_filename;
> > > > > > > +}
> > > > > > > +
> > > > > > > +static void get_rbf_image_info(struct rbf_info *rbf, u16
> > > > > > > *buffer)
> > > > > > > +{
> > > > > > > + /*
> > > > > > > + * Magic ID starting at:
> > > > > > > + * -> 1st dword[15:0] in periph.rbf
> > > > > > > + * -> 2nd dword[15:0] in core.rbf
> > > > > > > + * Note: dword == 32 bits
> > > > > > > + */
> > > > > > > + u32 word_reading_max = 2;
> > > > > > > + u32 i;
> > > > > > > +
> > > > > > > + for (i = 0; i < word_reading_max; i++) {
> > > > > > > + if (*(buffer + i) ==
> > > > > > > FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
> > > > > > > + rbf->security = unencrypted;
> > > > > > > + } else if (*(buffer + i) ==
> > > > > > > FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
> > > > > > > + rbf->security = encrypted;
> > > > > > > + } else if (*(buffer + i + 1) ==
> > > > > > > + FPGA_SOCFPGA_A10_RBF_UNENCRYPTE
> > > > > > > D)
> > > > > > > {
> > > > > > > + rbf->security = unencrypted;
> > > > > > > + } else if (*(buffer + i + 1) ==
> > > > > > > + FPGA_SOCFPGA_A10_RBF_ENCRYPTED)
> > > > > > > {
> > > > > > > + rbf->security = encrypted;
> > > > > > > + } else {
> > > > > > > + rbf->security = invalid;
> > > > > > > + continue;
> > > > > > > + }
> > > > > > > +
> > > > > > > + /* PERIPH RBF(buffer + i + 1), CORE RBF(buffer
> > > > > > > + i
> > > > > > > + 2) */
> > > > > > > + if (*(buffer + i + 1) ==
> > > > > > > FPGA_SOCFPGA_A10_RBF_PERIPH) {
> > > > > > > + rbf->section = periph_section;
> > > > > > > + break;
> > > > > > > + } else if (*(buffer + i + 1) ==
> > > > > > > FPGA_SOCFPGA_A10_RBF_CORE) {
> > > > > > > + rbf->section = core_section;
> > > > > > > + break;
> > > > > > > + } else if (*(buffer + i + 2) ==
> > > > > > > FPGA_SOCFPGA_A10_RBF_PERIPH) {
> > > > > > > + rbf->section = periph_section;
> > > > > > > + break;
> > > > > > > + } else if (*(buffer + i + 2) ==
> > > > > > > FPGA_SOCFPGA_A10_RBF_CORE) {
> > > > > > > + rbf->section = core_section;
> > > > > > > + break;
> > > > > > > + }
> > > > > > > +
> > > > > > > + rbf->section = unknown;
> > > > > > > + break;
> > > > > > > +
> > > > > > > + WATCHDOG_RESET();
> > > > > > > + }
> > > > > > > +}
> > > > > > > +
> > > > > > > +#ifdef CONFIG_FS_LOADER
> > > > > > > +static int first_loading_rbf_to_buffer(struct udevice
> > > > > > > *dev,
> > > > > > > + struct fpga_loadfs_info
> > > > > > > *fpga_loadfs,
> > > > > > > + u32 *buffer, size_t
> > > > > > > *buffer_bsize)
> > > > > > > +{
> > > > > > > + u32 *buffer_p = (u32 *)*buffer;
> > > > > > > + u32 *loadable = buffer_p;
> > > > > > > + size_t buffer_size = *buffer_bsize;
> > > > > > > + size_t fit_size;
> > > > > > > + int ret, i, count, confs_noffset, images_noffset,
> > > > > > > rbf_offset, rbf_size;
> > > > > > > + const char *fpga_node_name = NULL;
> > > > > > > + const char *uname = NULL;
> > > > > > > +
> > > > > > > + /* Load image header into buffer */
> > > > > > > + ret = request_firmware_into_buf(dev,
> > > > > > > + fpga_loadfs-
> > > > > > > >fpga_fsinfo-
> > > > > > > >
> > > > > > > >
> > > > > > > > filename,
> > > > > > > + buffer_p, sizeof(struct
> > > > > > > image_header),
> > > > > > > + 0);
> > > > > > > + if (ret < 0) {
> > > > > > > + debug("FPGA: Failed to read image header from
> > > > > > > flash.\n");
> > > > > > > + return -ENOENT;
> > > > > > > + }
> > > > > > > +
> > > > > > > + if (image_get_magic((struct image_header *)buffer_p) !=
> > > > > > > FDT_MAGIC) {
> > > > > > > + debug("FPGA: No FDT magic was found.\n");
> > > > > > > + return -EBADF;
> > > > > > > + }
> > > > > > > +
> > > > > > > + fit_size = fdt_totalsize(buffer_p);
> > > > > > > +
> > > > > > > + if (fit_size > buffer_size) {
> > > > > > > + debug("FPGA: FIT image is larger than available
> > > > > > > buffer.\n");
> > > > > > > + debug("Please use FIT external data or
> > > > > > > increasing
> > > > > > > buffer.\n");
> > > > > > > + return -ENOMEM;
> > > > > > > + }
> > > > > > > +
> > > > > > > + /* Load entire FIT into buffer */
> > > > > > > + ret = request_firmware_into_buf(dev,
> > > > > > > + fpga_loadfs-
> > > > > > > >fpga_fsinfo-
> > > > > > > >
> > > > > > > >
> > > > > > > > filename,
> > > > > > > + buffer_p, fit_size, 0);
> > > > > > > + if (ret < 0)
> > > > > > > + return ret;
> > > > > > > +
> > > > > > > + ret = fit_check_format(buffer_p);
> > > > > > > + if (!ret) {
> > > > > > > + debug("FPGA: No valid FIT image was found.\n");
> > > > > > > + return -EBADF;
> > > > > > > + }
> > > > > > > +
> > > > > > > + confs_noffset = fdt_path_offset(buffer_p,
> > > > > > > FIT_CONFS_PATH);
> > > > > > > + images_noffset = fdt_path_offset(buffer_p,
> > > > > > > FIT_IMAGES_PATH);
> > > > > > > + if (confs_noffset < 0 || images_noffset < 0) {
> > > > > > > + debug("FPGA: No Configurations or images nodes
> > > > > > > were found.\n");
> > > > > > > + return -ENOENT;
> > > > > > > + }
> > > > > > > +
> > > > > > > + /* Get default configuration unit name from default
> > > > > > > property */
> > > > > > > + confs_noffset = fit_conf_get_node(buffer_p, NULL);
> > > > > > > + if (confs_noffset < 0) {
> > > > > > > + debug("FPGA: No default configuration was found
> > > > > > > in
> > > > > > > config.\n");
> > > > > > > + return -ENOENT;
> > > > > > > + }
> > > > > > > +
> > > > > > > + count = fit_conf_get_prop_node_count(buffer_p,
> > > > > > > confs_noffset,
> > > > > > > + FIT_FPGA_PROP);
> > > > > > > + if (count < 0) {
> > > > > > > + debug("FPGA: Invalid configuration format for
> > > > > > > FPGA
> > > > > > > node.\n");
> > > > > > > + return count;
> > > > > > > + }
> > > > > > > + debug("FPGA: FPGA node count: %d\n", count);
> > > > > > > +
> > > > > > > + for (i = 0; i < count; i++) {
> > > > > > > + images_noffset =
> > > > > > > fit_conf_get_prop_node_index(buffer_p,
> > > > > > > + co
> > > > > > > nfs
> > > > > > > _noffset,
> > > > > > > + FI
> > > > > > > T_F
> > > > > > > PGA_PROP, i);
> > > > > > > + uname = fit_get_name(buffer_p, images_noffset,
> > > > > > > NULL);
> > > > > > > + if (uname) {
> > > > > > > + debug("FPGA: %s\n", uname);
> > > > > > > +
> > > > > > > + if (strstr(uname, "fpga-periph") &&
> > > > > > > + (!is_fpgamgr_early_user_mode()
> > > > > > > ||
> > > > > > > + is_fpgamgr_user_mode())) {
> > > > > > > + fpga_node_name = uname;
> > > > > > > + printf("FPGA: Start to program
> > > > > > > ");
> > > > > > > + printf("peripheral/full
> > > > > > > bitstream
> > > > > > > ...\n");
> > > > > > > + break;
> > > > > > > + } else if (strstr(uname, "fpga-core")
> > > > > > > &&
> > > > > > > + (is_fpgamgr_early_user_
> > > > > > > mod
> > > > > > > e() &&
> > > > > > > + !is_fpgamgr_user_mode()
> > > > > > > ))
> > > > > > > {
> > > > > > > + fpga_node_name = uname;
> > > > > > > + printf("FPGA: Start to program
> > > > > > > core ");
> > > > > > > + printf("bitstream ...\n");
> > > > > > > + break;
> > > > > > > + }
> > > > > > > + }
> > > > > > > + WATCHDOG_RESET();
> > > > > > > + }
> > > > > > > +
> > > > > > > + if (!fpga_node_name) {
> > > > > > > + debug("FPGA: No suitable bitstream was found,
> > > > > > > count: %d.\n", i);
> > > > > > > + return 1;
> > > > > > > + }
> > > > > > > +
> > > > > > > + images_noffset = fit_image_get_node(buffer_p,
> > > > > > > fpga_node_name);
> > > > > > > + if (images_noffset < 0) {
> > > > > > > + debug("FPGA: No node '%s' was found in FIT.\n",
> > > > > > > + fpga_node_name);
> > > > > > > + return -ENOENT;
> > > > > > > + }
> > > > > > > +
> > > > > > > + if (!fit_image_get_data_position(buffer_p,
> > > > > > > images_noffset,
> > > > > > > + &rbf_offset)) {
> > > > > > > + debug("FPGA: Data position was found.\n");
> > > > > > > + } else if (!fit_image_get_data_offset(buffer_p,
> > > > > > > images_noffset,
> > > > > > > + &rbf_offset)) {
> > > > > > > + /*
> > > > > > > + * For FIT with external data, figure out where
> > > > > > > + * the external images start. This is the base
> > > > > > > + * for the data-offset properties in each
> > > > > > > image.
> > > > > > > + */
> > > > > > > + rbf_offset += ((fdt_totalsize(buffer_p) + 3) &
> > > > > > > ~3);
> > > > > > > + debug("FPGA: Data offset was found.\n");
> > > > > > > + } else {
> > > > > > > + debug("FPGA: No data position/offset was
> > > > > > > found.\n");
> > > > > > > + return -ENOENT;
> > > > > > > + }
> > > > > > > +
> > > > > > > + ret = fit_image_get_data_size(buffer_p, images_noffset,
> > > > > > > &rbf_size);
> > > > > > > + if (ret < 0) {
> > > > > > > + debug("FPGA: No data size was found
> > > > > > > (err=%d).\n",
> > > > > > > ret);
> > > > > > > + return -ENOENT;
> > > > > > > + }
> > > > > > > +
> > > > > > > + if (gd->ram_size < rbf_size) {
> > > > > > > + debug("FPGA: Using default OCRAM buffer and
> > > > > > > size.\n");
> > > > > > > + } else {
> > > > > > > + ret = fit_image_get_load(buffer_p,
> > > > > > > images_noffset,
> > > > > > > + (ulong *)loadable);
> > > > > > > + if (ret < 0) {
> > > > > > > + buffer_p = (u32
> > > > > > > *)DEFAULT_DDR_LOAD_ADDRESS;
> > > > > > > + debug("FPGA: No loadable was
> > > > > > > found.\n");
> > > > > > > + debug("FPGA: Using default DDR load
> > > > > > > address: 0x%x .\n",
> > > > > > > + DEFAULT_DDR_LOAD_ADDRESS);
> > > > > > > + } else {
> > > > > > > + buffer_p = (u32 *)*loadable;
> > > > > > > + debug("FPGA: Found loadable address =
> > > > > > > 0x%x.\n",
> > > > > > > + *loadable);
> > > > > > > + }
> > > > > > > +
> > > > > > > + buffer_size = rbf_size;
> > > > > > > + }
> > > > > > > +
> > > > > > > + debug("FPGA: External data: offset = 0x%x, size =
> > > > > > > 0x%x.\n",
> > > > > > > + rbf_offset, rbf_size);
> > > > > > > +
> > > > > > > + fpga_loadfs->remaining = rbf_size;
> > > > > > > +
> > > > > > > + /*
> > > > > > > + * Determine buffer size vs bitstream size, and
> > > > > > > calculating number of
> > > > > > > + * chunk by chunk transfer is required due to smaller
> > > > > > > buffer size
> > > > > > > + * compare to bitstream
> > > > > > > + */
> > > > > > > + if (rbf_size <= buffer_size) {
> > > > > > > + /* Loading whole bitstream into buffer */
> > > > > > > + buffer_size = rbf_size;
> > > > > > > + fpga_loadfs->remaining = 0;
> > > > > > > + } else {
> > > > > > > + fpga_loadfs->remaining -= buffer_size;
> > > > > > > + }
> > > > > > > +
> > > > > > > + fpga_loadfs->offset = rbf_offset;
> > > > > > > + /* Loading bitstream into buffer */
> > > > > > > + ret = request_firmware_into_buf(dev,
> > > > > > > + fpga_loadfs-
> > > > > > > >fpga_fsinfo-
> > > > > > > >
> > > > > > > >
> > > > > > > > filename,
> > > > > > > + buffer_p, buffer_size,
> > > > > > > + fpga_loadfs->offset);
> > > > > > > + if (ret < 0) {
> > > > > > > + debug("FPGA: Failed to read bitstream from
> > > > > > > flash.\n");
> > > > > > > + return -ENOENT;
> > > > > > > + }
> > > > > > > +
> > > > > > > + /* Getting info about bitstream types */
> > > > > > > + get_rbf_image_info(&fpga_loadfs->rbfinfo, (u16
> > > > > > > *)buffer_p);
> > > > > > > +
> > > > > > > + /* Update next reading bitstream offset */
> > > > > > > + fpga_loadfs->offset += buffer_size;
> > > > > > > +
> > > > > > > + /* Update the final addr for bitstream */
> > > > > > > + *buffer = (u32)buffer_p;
> > > > > > > +
> > > > > > > + /* Update the size of bitstream to be programmed into
> > > > > > > FPGA
> > > > > > > */
> > > > > > > + *buffer_bsize = buffer_size;
> > > > > > > +
> > > > > > > + return 0;
> > > > > > > +}
> > > > > > > +
> > > > > > > +static int subsequent_loading_rbf_to_buffer(struct udevice
> > > > > > > *dev,
> > > > > > > + struct fpga_loadfs_info
> > > > > > > *fpga_loadfs,
> > > > > > > + u32 *buffer, size_t
> > > > > > > *buffer_bsize)
> > > > > > > +{
> > > > > > > + int ret = 0;
> > > > > > > + u32 *buffer_p = (u32 *)*buffer;
> > > > > > > +
> > > > > > > + /* Read the bitstream chunk by chunk. */
> > > > > > > + if (fpga_loadfs->remaining > *buffer_bsize) {
> > > > > > > + fpga_loadfs->remaining -= *buffer_bsize;
> > > > > > > + } else {
> > > > > > > + *buffer_bsize = fpga_loadfs->remaining;
> > > > > > > + fpga_loadfs->remaining = 0;
> > > > > > > + }
> > > > > > > +
> > > > > > > + ret = request_firmware_into_buf(dev,
> > > > > > > + fpga_loadfs-
> > > > > > > >fpga_fsinfo-
> > > > > > > >
> > > > > > > >
> > > > > > > > filename,
> > > > > > > + buffer_p,
> > > > > > > *buffer_bsize,
> > > > > > > + fpga_loadfs->offset);
> > > > > > > + if (ret < 0) {
> > > > > > > + debug("FPGA: Failed to read bitstream from
> > > > > > > flash.\n");
> > > > > > > + return -ENOENT;
> > > > > > > + }
> > > > > > > +
> > > > > > > + /* Update next reading bitstream offset */
> > > > > > > + fpga_loadfs->offset += *buffer_bsize;
> > > > > > > +
> > > > > > > + return 0;
> > > > > > > +}
> > > > > > > +
> > > > > > > +int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void
> > > > > > > *buf,
> > > > > > > size_t bsize,
> > > > > > > + u32 offset)
> > > > > > > +{
> > > > > > > + struct fpga_loadfs_info fpga_loadfs;
> > > > > > > + struct udevice *dev;
> > > > > > > + int status, ret, size;
> > > > > > > + u32 buffer = (uintptr_t)buf;
> > > > > > > + size_t buffer_sizebytes = bsize;
> > > > > > > + size_t buffer_sizebytes_ori = bsize;
> > > > > > > + size_t total_sizeof_image = 0;
> > > > > > > + ofnode node;
> > > > > > > + const fdt32_t *phandle_p;
> > > > > > > + u32 phandle;
> > > > > > > +
> > > > > > > + node = get_fpga_mgr_ofnode(ofnode_null());
> > > > > > > +
> > > > > > > + if (ofnode_valid(node)) {
> > > > > > > + phandle_p = ofnode_get_property(node,
> > > > > > > "firmware-
> > > > > > > loader", &size);
> > > > > > > + if (!phandle_p) {
> > > > > > > + node = ofnode_path("/chosen");
> > > > > > > + if (!ofnode_valid(node)) {
> > > > > > > + debug("FPGA: /chosen node was
> > > > > > > not
> > > > > > > found.\n");
> > > > > > > + return -ENOENT;
> > > > > > > + }
> > > > > > > +
> > > > > > > + phandle_p = ofnode_get_property(node,
> > > > > > > "firmware-loader",
> > > > > > > + &size);
> > > > > > > + if (!phandle_p) {
> > > > > > > + debug("FPGA: firmware-loader
> > > > > > > property was not");
> > > > > > > + debug(" found.\n");
> > > > > > > + return -ENOENT;
> > > > > > > + }
> > > > > > > + }
> > > > > > > + } else {
> > > > > > > + debug("FPGA: FPGA manager node was not
> > > > > > > found.\n");
> > > > > > > + return -ENOENT;
> > > > > > > + }
> > > > > > > +
> > > > > > > + phandle = fdt32_to_cpu(*phandle_p);
> > > > > > > + ret =
> > > > > > > uclass_get_device_by_phandle_id(UCLASS_FS_FIRMWARE_LOADER,
> > > > > > > + phandle, &dev);
> > > > > > > + if (ret)
> > > > > > > + return ret;
> > > > > > > +
> > > > > > > + memset(&fpga_loadfs, 0, sizeof(fpga_loadfs));
> > > > > > > +
> > > > > > > + fpga_loadfs.fpga_fsinfo = fpga_fsinfo;
> > > > > > > + fpga_loadfs.offset = offset;
> > > > > > > +
> > > > > > > + printf("FPGA: Checking FPGA configuration setting
> > > > > > > ...\n");
> > > > > > > +
> > > > > > > + /*
> > > > > > > + * Note: Both buffer and buffer_sizebytes values can be
> > > > > > > altered by
> > > > > > > + * function below.
> > > > > > > + */
> > > > > > > + ret = first_loading_rbf_to_buffer(dev, &fpga_loadfs,
> > > > > > > &buffer,
> > > > > > > + &buffer_sizebytes);
> > > > > > > + if (ret == 1) {
> > > > > > > + printf("FPGA: Skipping configuration ...\n");
> > > > > > > + return 0;
> > > > > > > + } else if (ret) {
> > > > > > > + return ret;
> > > > > > > + }
> > > > > > > +
> > > > > > > + if (fpga_loadfs.rbfinfo.section == core_section &&
> > > > > > > + !(is_fpgamgr_early_user_mode() &&
> > > > > > > !is_fpgamgr_user_mode())) {
> > > > > > > + debug("FPGA : Must be in Early Release mode to
> > > > > > > program ");
> > > > > > > + debug("core bitstream.\n");
> > > > > > > + return -EPERM;
> > > > > > > + }
> > > > > > > +
> > > > > > > + /* Disable all signals from HPS peripheral controller
> > > > > > > to
> > > > > > > FPGA */
> > > > > > > + writel(0, &system_manager_base->fpgaintf_en_global);
> > > > > > > +
> > > > > > > + /* Disable all axi bridges (hps2fpga, lwhps2fpga &
> > > > > > > fpga2hps) */
> > > > > > > + socfpga_bridges_reset();
> > > > > > > +
> > > > > > > + if (fpga_loadfs.rbfinfo.section == periph_section) {
> > > > > > > + /* Initialize the FPGA Manager */
> > > > > > > + status = fpgamgr_program_init((u32 *)buffer,
> > > > > > > buffer_sizebytes);
> > > > > > > + if (status) {
> > > > > > > + debug("FPGA: Init with peripheral
> > > > > > > bitstream failed.\n");
> > > > > > > + return -EPERM;
> > > > > > > + }
> > > > > > > + }
> > > > > > > +
> > > > > > > + /* Transfer bitstream to FPGA Manager */
> > > > > > > + fpgamgr_program_write((void *)buffer,
> > > > > > > buffer_sizebytes);
> > > > > > > +
> > > > > > > + total_sizeof_image += buffer_sizebytes;
> > > > > > > +
> > > > > > > + while (fpga_loadfs.remaining) {
> > > > > > > + ret = subsequent_loading_rbf_to_buffer(dev,
> > > > > > > + &fpga_l
> > > > > > > oad
> > > > > > > fs,
> > > > > > > + &buffer
> > > > > > > ,
> > > > > > > + &buffer
> > > > > > > _si
> > > > > > > zebytes_ori);
> > > > > > > +
> > > > > > > + if (ret)
> > > > > > > + return ret;
> > > > > > > +
> > > > > > > + /* Transfer data to FPGA Manager */
> > > > > > > + fpgamgr_program_write((void *)buffer,
> > > > > > > + buffer_sizebytes_ori);
> > > > > > > +
> > > > > > > + total_sizeof_image += buffer_sizebytes_ori;
> > > > > > > +
> > > > > > > + WATCHDOG_RESET();
> > > > > > > + }
> > > > > > > +
> > > > > > > + if (fpga_loadfs.rbfinfo.section == periph_section) {
> > > > > > > + if (fpgamgr_wait_early_user_mode() !=
> > > > > > > -ETIMEDOUT)
> > > > > > > {
> > > > > > > + config_pins(gd->fdt_blob, "shared");
> > > > > > > + puts("FPGA: Early Release
> > > > > > > Succeeded.\n");
> > > > > > > + } else {
> > > > > > > + debug("FPGA: Failed to see Early
> > > > > > > Release.\n");
> > > > > > > + return -EIO;
> > > > > > > + }
> > > > > > > +
> > > > > > > + /* For monolithic bitstream */
> > > > > > > + if (is_fpgamgr_user_mode()) {
> > > > > > > + /* Ensure the FPGA entering config done
> > > > > > > */
> > > > > > > + status = fpgamgr_program_finish();
> > > > > > > + if (status)
> > > > > > > + return status;
> > > > > > > +
> > > > > > > + config_pins(gd->fdt_blob, "fpga");
> > > > > > > + puts("FPGA: Enter user mode.\n");
> > > > > > > + }
> > > > > > > + } else if (fpga_loadfs.rbfinfo.section == core_section)
> > > > > > > {
> > > > > > > + /* Ensure the FPGA entering config done */
> > > > > > > + status = fpgamgr_program_finish();
> > > > > > > + if (status)
> > > > > > > + return status;
> > > > > > > +
> > > > > > > + config_pins(gd->fdt_blob, "fpga");
> > > > > > > + puts("FPGA: Enter user mode.\n");
> > > > > > > + } else {
> > > > > > > + debug("FPGA: Config Error: Unsupported
> > > > > > > bitstream
> > > > > > > type.\n");
> > > > > > > + return -ENOEXEC;
> > > > > > > + }
> > > > > > > +
> > > > > > > + return (int)total_sizeof_image;
> > > > > > > +}
> > > > > > > +
> > > > > > > +void fpgamgr_program(const void *buf, size_t bsize, u32
> > > > > > > offset)
> > > > > > > +{
> > > > > > > + fpga_fs_info fpga_fsinfo;
> > > > > > > +
> > > > > > > + fpga_fsinfo.filename = get_fpga_filename();
> > > > > > > +
> > > > > > > + if (fpga_fsinfo.filename)
> > > > > > > + socfpga_loadfs(&fpga_fsinfo, buf, bsize,
> > > > > > > offset);
> > > > > > > +}
> > > > > > > +#endif
> > > > > > > +
> > > > > > > +/* This function is used to load the core bitstream from
> > > > > > > the
> > > > > > > OCRAM. */
> > > > > > > int socfpga_load(Altera_desc *desc, const void *rbf_data,
> > > > > > > size_t
> > > > > > > rbf_size)
> > > > > > > {
> > > > > > > - int status;
> > > > > > > + unsigned long status;
> > > > > > > + struct rbf_info rbfinfo;
> > > > > > > +
> > > > > > > + memset(&rbfinfo, 0, sizeof(rbfinfo));
> > > > > > >
> > > > > > > /* Disable all signals from hps peripheral controller
> > > > > > > to
> > > > > > > fpga */
> > > > > > > writel(0, &system_manager_base->fpgaintf_en_global);
> > > > > > > @@ -462,13 +915,31 @@ int socfpga_load(Altera_desc *desc,
> > > > > > > const
> > > > > > > void *rbf_data, size_t rbf_size)
> > > > > > > /* Disable all axi bridge (hps2fpga, lwhps2fpga &
> > > > > > > fpga2hps) */
> > > > > > > socfpga_bridges_reset();
> > > > > > >
> > > > > > > - /* Initialize the FPGA Manager */
> > > > > > > - status = fpgamgr_program_init((u32 *)rbf_data,
> > > > > > > rbf_size);
> > > > > > > - if (status)
> > > > > > > - return status;
> > > > > > > + /* Getting info about bitstream types */
> > > > > > > + get_rbf_image_info(&rbfinfo, (u16 *)rbf_data);
> > > > > > > +
> > > > > > > + if (rbfinfo.section == periph_section) {
> > > > > > > + /* Initialize the FPGA Manager */
> > > > > > > + status = fpgamgr_program_init((u32 *)rbf_data,
> > > > > > > rbf_size);
> > > > > > > + if (status)
> > > > > > > + return status;
> > > > > > > + }
> > > > > > >
> > > > > > > - /* Write the RBF data to FPGA Manager */
> > > > > > > + if (rbfinfo.section == core_section &&
> > > > > > > + !(is_fpgamgr_early_user_mode() &&
> > > > > > > !is_fpgamgr_user_mode())) {
> > > > > > > + debug("FPGA : Must be in early release mode to
> > > > > > > program ");
> > > > > > > + debug("core bitstream.\n");
> > > > > > > + return -EPERM;
> > > > > > > + }
> > > > > > > +
> > > > > > > + /* Write the bitstream to FPGA Manager */
> > > > > > > fpgamgr_program_write(rbf_data, rbf_size);
> > > > > > >
> > > > > > > - return fpgamgr_program_finish();
> > > > > > > + status = fpgamgr_program_finish();
> > > > > > > + if (status) {
> > > > > > > + config_pins(gd->fdt_blob, "fpga");
> > > > > > > + puts("FPGA: Enter user mode.\n");
> > > > > > > + }
> > > > > > > +
> > > > > > > + return status;
> > > > > > > }
> > > > > > > diff --git a/include/image.h b/include/image.h
> > > > > > > index 765ffecee0..cc976f70ce 100644
> > > > > > > --- a/include/image.h
> > > > > > > +++ b/include/image.h
> > > > > > > @@ -1046,6 +1046,10 @@ int fit_check_format(const void
> > > > > > > *fit);
> > > > > > >
> > > > > > > int fit_conf_find_compat(const void *fit, const void
> > > > > > > *fdt);
> > > > > > > int fit_conf_get_node(const void *fit, const char
> > > > > > > *conf_uname);
> > > > > > > +int fit_conf_get_prop_node_count(const void *fit, int
> > > > > > > noffset,
> > > > > > > + const char *prop_name);
> > > > > > > +int fit_conf_get_prop_node_index(const void *fit, int
> > > > > > > noffset,
> > > > > > > + const char *prop_name, int index);
> > > > > > >
> > > > > > > /**
> > > > > > > * fit_conf_get_prop_node() - Get node refered to by a
> > > > > > > configuration
> > > > > > >
^ permalink raw reply [flat|nested] 27+ messages in thread
end of thread, other threads:[~2019-05-06 7:14 UTC | newest]
Thread overview: 27+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-03-19 8:50 [U-Boot] [PATCH v12 0/9] Add support for loading FPGA bitstream tien.fong.chee at intel.com
2019-03-19 8:50 ` [U-Boot] [PATCH v12 1/9] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10 tien.fong.chee at intel.com
2019-03-19 8:50 ` [U-Boot] [PATCH v12 2/9] ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK tien.fong.chee at intel.com
2019-03-19 8:50 ` [U-Boot] [PATCH v12 3/9] ARM: socfpga: Cleaning up and ensuring consistent format messages in driver tien.fong.chee at intel.com
2019-03-19 8:50 ` [U-Boot] [PATCH v12 4/9] ARM: socfpga: Moving the watchdog reset to the for-loop status polling tien.fong.chee at intel.com
2019-04-27 19:34 ` Simon Goldschmidt
2019-04-30 11:57 ` Chee, Tien Fong
2019-05-06 3:36 ` Chee, Tien Fong
2019-03-19 8:50 ` [U-Boot] [PATCH v12 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading tien.fong.chee at intel.com
2019-04-27 19:57 ` Simon Goldschmidt
2019-04-30 12:09 ` Chee, Tien Fong
2019-04-30 12:24 ` Simon Goldschmidt
2019-05-02 7:49 ` Chee, Tien Fong
2019-05-03 11:26 ` Simon Goldschmidt
2019-05-06 3:36 ` Chee, Tien Fong
2019-05-06 7:14 ` Simon Goldschmidt
2019-03-19 8:50 ` [U-Boot] [PATCH v12 6/9] ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK tien.fong.chee at intel.com
2019-03-19 8:50 ` [U-Boot] [PATCH v12 7/9] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs tien.fong.chee at intel.com
2019-03-19 8:50 ` [U-Boot] [PATCH v12 8/9] ARM: socfpga: Synchronize the configuration for A10 SoCDK tien.fong.chee at intel.com
2019-03-19 8:50 ` [U-Boot] [PATCH v12 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL tien.fong.chee at intel.com
2019-04-27 19:50 ` Simon Goldschmidt
2019-04-30 12:13 ` Chee, Tien Fong
2019-04-30 12:26 ` Simon Goldschmidt
2019-05-02 7:56 ` Chee, Tien Fong
2019-05-03 11:54 ` Simon Goldschmidt
2019-05-06 3:34 ` Chee, Tien Fong
2019-04-15 3:52 ` [U-Boot] [PATCH v12 0/9] Add support for loading FPGA bitstream Chee, Tien Fong
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