[igt-dev] [PATCH v15 0/5] new engine discovery interface

[igt-dev] [PATCH v15 0/5] new engine discovery interface

[Andi Shyti]

Hi,

In this patchset I propose an alternative way of engine discovery
thanks to the new interfaces developed by Tvrtko and Chris[4].

Thanks Tvrtko, Chris, Antonio and Petri for your comments in the
previous RFCs.

Andi

v14 --> v15
===========
PATCH v14: [16]

 - virtual engines will be called "virtual" like unrecognised
   engines will be called "unknown"

 - renamed the for_each loops to more meaningful names
   (__for_each_static_engine and for_each_context_engine) and
   moved into gem_engine_topology.h

 - minor changes about data types.

v13 --> v14
===========
PATCH v13: [15]
minor changes this time:
 - squashed patch 2 and 3 (from v13) with a little rename and
   added Chris r-b

 - fixed some index issues and string assignement leaks

 - squashed patches 5, 6, 7 and 8 from v13

v12 --> v13
===========
PATCH v12: [14]
This patch is also very different from the previous other than
some reorganization of the code these are the main changes:

 - the previous version lacked the case when the context had its
   engines mapped. checks in the following order

 if the driver doesn't have the new API
  -> get the engines from the static list
 if the driver has the API but the context has nothing mapped
  -> get the engines from "query" and map them
 if the driver has the API and the context has engines mapped
  -> get the engines from the context

 - the helper functions have been removed as they were of no use.

v11 --> v12
===========
PATCH v11: [13]
This 12th version starts from a completely different thought.
Here's the main differences:

 - The list of engines is provided in an engine_data structure
   which contains an index (useful for looping through and for
   engine/context index mapping) instead of an array of engines.

 - The list of engines is generated every time the init function
   is called and nothing is allocated in heap memory.

 - The ioctl check is done already during the initialization part
   and if the new ioctls are not implemented, then the init
   function still stores only those present in the GPU.

 - The for_each loop is implemented by re-using the previous
   'for_each_engine_class_instance()' implemented by Tvrtko.

 - The gem_topology library offers few helper functions for
   checking the engine presence, checking the implementation of
   the ioctls and executing the buffer, in order to be completely
   unaware of the driver implementation.

Thanks Tvrtko for all your inputs.

v10 --> v11
===========
RFC v10: [12]
few cosmetic changes in v11 and minor architectural details.
Thanks Tvrtko.

- the 'query_engines()' functions are static as no one is using
  them yet.

- removed the 'gem_has_engine_topology()' function because it's
  very little used, 'get_active_engines()' can be used instead.

- a minor ring -> engine renaming coming from Chris. 

v9 --> v10
==========
RFC v9: [11]
also this time quite many changes, thanks Chris for the reviews,
here the most relevant of them.

- gem_query.[ch] have been renamed to gem_engine_topology.[ch]
  and all the functions ended up there as they are referring to
  the topology of the engines.

- the functions 'get_active_engines()',
  'gem_set_context_get_engines()' and
  'igt_require_gem_engine_list()' will be the main interface to
  the gem_engine_topology library, refer to patch 2 for details.

- the define 'for_each_engine2()' doesn't expose anymore the
  iterator.

- 'gem_context_has_engine()' has been moved from ioctl_wrappers.c
  to gem_context.c.

- the gem_exec_basic exec-ctx subtest does not abort if the new
  getparam/setparam and query apis are not implemented as it can
  work with both (as it was done at the beginning).

v8 --> v9
=========
RFC v8: [10]
quite many changes, please refer to the review in [10]. Thanks
Chris for the review. These are the most relevant:

- all the allocation in gem_query have been made in stack, not
  anymore allocated dynamically.

- removed get/set_context as it was already implemented and I
  didn't know.

- renamed some functions and variables to hopefully more
  meaningful names.

V7 --> v8
=========
RFC v7: [9]

- all functions have been moved from lib/igt_gt.{c,h} and
  lib/ioctl_wrappers.{c,h} to lib/i916/gem_query.{c,h}. (thanks
  Chris)

- 'for_each_engine_ctx' has been renamed to 'for_each_engine2' to
  be consistent with the '2' that indicates the new 'struct
  intel_execution_engine2' data structure.

V6 --> V7
=========
RFC v6: [8]

- a new patch has been added (patch 3) which adds a new
  requirement check through the igt_require_gem_engine_list()
  function. (thanks Chris) This function will initialize the
  engine list instead of the instead of igt_require_gem() as it
  was in v6

- all the ioctls have been wrapped (thanks Chris and Antonio) and
  new library functions have been added and assert the ioctls

- gem_init_engine_list() function returns the errno from the
  GETPARAM ioctl in order to be used as a requirement. (thanks
  Chris)

- fixed few requires/asserts

- The engine list "intel_active_engines2" is allocated of the
  number of engines instead of a political 64 (thanks Antonio).

- some parameter renaming in gem_has_ring_by_idx(). (thanks
  Chris).

- the original "intel_execution_engines2" has not been renamed,
  because it is used to create subtests before even executing any
  test/ioctl. By renaming it, some subtest generations failed.
  (thanks Petri)

V5 --> V6
=========
RFC v5: [7]
- Chris implemented the getparam ioctl which allows to the test
  to figure otu whether the new interface has been implemented.
  This way the for_each_engine_ctx() is able to work with new and
  old kernel uapi (thanks Chris)

V4 --> V5
=========
RFC v4: [6]

- the engine list is now built in 'igt_require_gem()' instead of
  '__open_driver()' so that we keep this discovery method
  specific to the i915 driver (thanks Chris).

- All the query/setparam structures dynamic allocation based on
  the number of engines, now are politically allocated 64 times,
  to avoid extra ioctl calls that retrieve the engine number
  (thanks Chris)

- use igt_ioctl instead of ioctl (thanks Chris)

- allocate intel_execution_engines2 dynamically instead of
  statically (thanks Tvrtko)

- simplify the test in 'gem_exec_basic()' so that simply checks
  the presence of the engine instead of executing a buffer
  (thank Chris)

- a new patch has been added (patch 3) that extends the
  'gem_has_ring()' boolean function. The new version sets the
  index as it's mapped in the kernel.The previous function is now
  a wrapper to the new function.

V3 --> V4
=========
PATCH v3: [3]

- re-architectured the discovery mechanism based on Tvrtko's
  sugestion and reviews.. In this version the discovery is done
  during the device opening and stored in a NULL terminated
  array, which replaces the existing intel_execution_engines2
  that is mainly used as a reference.

V2 --> V3
=========
RFC v2: [2]

- removed a standalone gem_query_engines_demo test and added the
  exec-ctx subtest inside gem_exec_basic (thanks Tvrtko).

- fixed most of Tvrtko's comments in [5], which consist in
  putting the mallocs igt_assert and ictls in igt_require and few
  refactoring (thanks Tvrtko).

V1 --> V2
=========
RFC v1: [1]

- added a demo test that simply queries the driver about the
  engines and executes a buffer (thanks Tvrtko)

- refactored the for_each_engine_ctx() macro so that what in the
  previous version was done by the "bind" function, now it's done
  in the first iteration. (Thanks Crhis)

- removed the "gem_has_ring_ctx()" because it was out of the
  scope.

- rename functions to more meaningful names

[1] RFC v1: https://lists.freedesktop.org/archives/igt-dev/2018-November/007025.html
[2] RFC v2: https://lists.freedesktop.org/archives/igt-dev/2018-November/007079.html
[3] PATCH v3: https://lists.freedesktop.org/archives/igt-dev/2018-November/007148.html
[4] https://cgit.freedesktop.org/~tursulin/drm-intel/log/?h=media
[5] https://lists.freedesktop.org/archives/igt-dev/2018-November/007100.html
[6] https://lists.freedesktop.org/archives/igt-dev/2019-January/008029.html
[7] https://lists.freedesktop.org/archives/igt-dev/2019-January/008165.html
[8] https://lists.freedesktop.org/archives/igt-dev/2019-February/008902.html
[9] https://lists.freedesktop.org/archives/igt-dev/2019-February/009185.html
[10] https://lists.freedesktop.org/archives/igt-dev/2019-February/009205.html
[11] https://lists.freedesktop.org/archives/igt-dev/2019-February/009277.html
[12] https://lists.freedesktop.org/archives/igt-dev/2019-March/010197.html
[13] https://lists.freedesktop.org/archives/igt-dev/2019-March/010467.html
[14] https://lists.freedesktop.org/archives/igt-dev/2019-March/010776.html
[15] https://lists.freedesktop.org/archives/igt-dev/2019-March/010827.html
[16] https://lists.freedesktop.org/archives/igt-dev/2019-March/010916.html

Andi Shyti (5):
  lib/igt_gt: remove unnecessary argument
  lib: ioctl_wrappers: reach engines by index as well
  include/drm-uapi: import i915_drm.h header file
  lib/i915: add gem_engine_topology library and for_each loop definition
  tests: gem_exec_basic: add "exec-ctx" buffer execution demo test

 include/drm-uapi/i915_drm.h    | 361 +++++++++++++++++++++++++++------
 lib/Makefile.sources           |   2 +
 lib/i915/gem_context.c         |  21 ++
 lib/i915/gem_context.h         |   2 +
 lib/i915/gem_engine_topology.c | 222 ++++++++++++++++++++
 lib/i915/gem_engine_topology.h |  63 ++++++
 lib/igt.h                      |   1 +
 lib/igt_gt.h                   |   8 +-
 lib/ioctl_wrappers.c           |  19 --
 lib/ioctl_wrappers.h           |   3 +-
 lib/meson.build                |   1 +
 tests/i915/gem_exec_basic.c    |  13 ++
 tests/perf_pmu.c               |  12 +-
 13 files changed, 638 insertions(+), 90 deletions(-)
 create mode 100644 lib/i915/gem_engine_topology.c
 create mode 100644 lib/i915/gem_engine_topology.h

-- 
2.20.1

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[igt-dev] [PATCH v15 1/5] lib/igt_gt: remove unnecessary argument

[Andi Shyti]

__for_each_engine_class_instance(fd, e) doesn't need and doesn't
use the fd argument. Remove it.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 lib/igt_gt.h     | 2 +-
 tests/perf_pmu.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 54e95da98084..475c0b3c3cc6 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -114,7 +114,7 @@ void gem_require_engine(int gem_fd,
 	igt_require(gem_has_engine(gem_fd, class, instance));
 }
 
-#define __for_each_engine_class_instance(fd__, e__) \
+#define __for_each_engine_class_instance(e__) \
 	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
 
 #define for_each_engine_class_instance(fd__, e__) \
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 1a08f564b066..4f552bc2ae28 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -1693,7 +1693,7 @@ igt_main
 	igt_subtest("invalid-init")
 		invalid_init();
 
-	__for_each_engine_class_instance(fd, e) {
+	__for_each_engine_class_instance(e) {
 		const unsigned int pct[] = { 2, 50, 98 };
 
 		/**
@@ -1897,7 +1897,7 @@ igt_main
 			gem_quiescent_gpu(fd);
 		}
 
-		__for_each_engine_class_instance(render_fd, e) {
+		__for_each_engine_class_instance(e) {
 			igt_subtest_group {
 				igt_fixture {
 					gem_require_engine(render_fd,
-- 
2.20.1

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[igt-dev] [PATCH v15 2/5] lib: ioctl_wrappers: reach engines by index as well

[Andi Shyti]

With the new engine query method engines are reachable through
an index and context they are combined with.

The 'gem_has_ring()' becomes 'gem_context_has_engine()' that
requires the index that the engine is mapped within the driver.
The function has been moved from lib/ioctl_wappers to
lib/i915/gem_context where it is more appropriate.

The previous 'gem_has_ring()' function becomes a wrapper to the
new 'gem_context_has_engine()'.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/i915/gem_context.c | 21 +++++++++++++++++++++
 lib/i915/gem_context.h |  2 ++
 lib/ioctl_wrappers.c   | 19 -------------------
 lib/ioctl_wrappers.h   |  3 ++-
 4 files changed, 25 insertions(+), 20 deletions(-)

diff --git a/lib/i915/gem_context.c b/lib/i915/gem_context.c
index 16004685e920..94ccb74b6aea 100644
--- a/lib/i915/gem_context.c
+++ b/lib/i915/gem_context.c
@@ -275,3 +275,24 @@ void gem_context_set_priority(int fd, uint32_t ctx_id, int prio)
 {
 	igt_assert(__gem_context_set_priority(fd, ctx_id, prio) == 0);
 }
+
+bool gem_context_has_engine(int fd, uint32_t ctx, uint32_t engine)
+{
+	struct drm_i915_gem_execbuffer2 execbuf;
+	struct drm_i915_gem_exec_object2 exec;
+
+	/* silly ABI, the kernel thinks everyone who has BSD also has BSD2 */
+	if ((engine & ~(3<<13)) == I915_EXEC_BSD) {
+		if (engine & (3 << 13) && !gem_has_bsd2(fd))
+			return false;
+	}
+
+	memset(&exec, 0, sizeof(exec));
+	memset(&execbuf, 0, sizeof(execbuf));
+	execbuf.buffers_ptr = to_user_pointer(&exec);
+	execbuf.buffer_count = 1;
+	execbuf.flags = engine;
+	execbuf.rsvd1 = ctx;
+
+	return __gem_execbuf(fd, &execbuf) == -ENOENT;
+}
diff --git a/lib/i915/gem_context.h b/lib/i915/gem_context.h
index aef68dda6b26..dd64ebf17fbd 100644
--- a/lib/i915/gem_context.h
+++ b/lib/i915/gem_context.h
@@ -45,4 +45,6 @@ int __gem_context_get_param(int fd, struct drm_i915_gem_context_param *p);
 int __gem_context_set_priority(int fd, uint32_t ctx, int prio);
 void gem_context_set_priority(int fd, uint32_t ctx, int prio);
 
+bool gem_context_has_engine(int fd, unsigned engine, unsigned ctx);
+
 #endif /* GEM_CONTEXT_H */
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index a66eb4bc0f4f..3f8f0874bc4b 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -1253,25 +1253,6 @@ void igt_require_gem(int fd)
 	igt_require_f(err == 0, "Unresponsive i915/GEM device\n");
 }
 
-bool gem_has_ring(int fd, unsigned ring)
-{
-	struct drm_i915_gem_execbuffer2 execbuf;
-	struct drm_i915_gem_exec_object2 exec;
-
-	/* silly ABI, the kernel thinks everyone who has BSD also has BSD2 */
-	if ((ring & ~(3<<13)) == I915_EXEC_BSD) {
-		if (ring & (3 << 13) && !gem_has_bsd2(fd))
-			return false;
-	}
-
-	memset(&exec, 0, sizeof(exec));
-	memset(&execbuf, 0, sizeof(execbuf));
-	execbuf.buffers_ptr = to_user_pointer(&exec);
-	execbuf.buffer_count = 1;
-	execbuf.flags = ring;
-	return __gem_execbuf(fd, &execbuf) == -ENOENT;
-}
-
 /**
  * gem_require_ring:
  * @fd: open i915 drm file descriptor
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index ad93daffcfd5..e712f1973142 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -142,11 +142,12 @@ bool gem_has_exec_fence(int fd);
 
 /* check functions which auto-skip tests by calling igt_skip() */
 void gem_require_caching(int fd);
-bool gem_has_ring(int fd, unsigned ring);
 void gem_require_ring(int fd, unsigned ring);
 bool gem_has_mocs_registers(int fd);
 void gem_require_mocs_registers(int fd);
 
+#define gem_has_ring(f, r) gem_context_has_engine(f, 0, r)
+
 /* prime */
 struct local_dma_buf_sync {
 	uint64_t flags;
-- 
2.20.1

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[igt-dev] [PATCH v15 3/5] include/drm-uapi: import i915_drm.h header file

[Andi Shyti]

This header file is imported in order to include the two new
ioctls DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM,
DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM and DRM_IOCTL_I915_QUERY.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 include/drm-uapi/i915_drm.h | 361 ++++++++++++++++++++++++++++++------
 1 file changed, 304 insertions(+), 57 deletions(-)

diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 4ae1c6ff6ae6..2bbad08eb9d2 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -62,6 +62,26 @@ extern "C" {
 #define I915_ERROR_UEVENT		"ERROR"
 #define I915_RESET_UEVENT		"RESET"
 
+/*
+ * i915_user_extension: Base class for defining a chain of extensions
+ *
+ * Many interfaces need to grow over time. In most cases we can simply
+ * extend the struct and have userspace pass in more data. Another option,
+ * as demonstrated by Vulkan's approach to providing extensions for forward
+ * and backward compatibility, is to use a list of optional structs to
+ * provide those extra details.
+ *
+ * The key advantage to using an extension chain is that it allows us to
+ * redefine the interface more easily than an ever growing struct of
+ * increasing complexity, and for large parts of that interface to be
+ * entirely optional. The downside is more pointer chasing; chasing across
+ * the boundary with pointers encapsulated inside u64.
+ */
+struct i915_user_extension {
+	__u64 next_extension;
+	__u64 name;
+};
+
 /*
  * MOCS indexes used for GPU surfaces, defining the cacheability of the
  * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
@@ -104,6 +124,9 @@ enum drm_i915_gem_engine_class {
 	I915_ENGINE_CLASS_INVALID	= -1
 };
 
+#define I915_ENGINE_CLASS_INVALID_NONE -1
+#define I915_ENGINE_CLASS_INVALID_VIRTUAL 0
+
 /**
  * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
  *
@@ -321,6 +344,8 @@ typedef struct _drm_i915_sarea {
 #define DRM_I915_PERF_ADD_CONFIG	0x37
 #define DRM_I915_PERF_REMOVE_CONFIG	0x38
 #define DRM_I915_QUERY			0x39
+#define DRM_I915_GEM_VM_CREATE		0x3a
+#define DRM_I915_GEM_VM_DESTROY		0x3b
 /* Must be kept compact -- no holes */
 
 #define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
@@ -370,6 +395,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
 #define DRM_IOCTL_I915_GEM_WAIT		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
+#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
 #define DRM_IOCTL_I915_REG_READ			DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
 #define DRM_IOCTL_I915_GET_RESET_STATS		DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
@@ -380,6 +406,8 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_PERF_ADD_CONFIG	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
 #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
 #define DRM_IOCTL_I915_QUERY			DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
+#define DRM_IOCTL_I915_GEM_VM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
+#define DRM_IOCTL_I915_GEM_VM_DESTROY	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
 
 /* Allow drivers to submit batchbuffers directly to hardware, relying
  * on the security mechanisms provided by hardware.
@@ -563,6 +591,12 @@ typedef struct drm_i915_irq_wait {
  */
 #define I915_PARAM_MMAP_GTT_COHERENT	52
 
+/*
+ * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel
+ * execution through use of explicit fence support.
+ * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
+ */
+#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
 /* Must be kept compact -- no holes and well documented */
 
 typedef struct drm_i915_getparam {
@@ -1085,7 +1119,16 @@ struct drm_i915_gem_execbuffer2 {
  */
 #define I915_EXEC_FENCE_ARRAY   (1<<19)
 
-#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1))
+/*
+ * Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent
+ * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
+ * the batch.
+ *
+ * Returns -EINVAL if the sync_file fd cannot be found.
+ */
+#define I915_EXEC_FENCE_SUBMIT		(1 << 20)
+
+#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SUBMIT << 1))
 
 #define I915_EXEC_CONTEXT_ID_MASK	(0xffffffff)
 #define i915_execbuffer2_set_context_id(eb2, context) \
@@ -1421,65 +1464,18 @@ struct drm_i915_gem_wait {
 };
 
 struct drm_i915_gem_context_create {
-	/*  output: id of new context*/
-	__u32 ctx_id;
-	__u32 pad;
-};
-
-struct drm_i915_gem_context_destroy {
-	__u32 ctx_id;
-	__u32 pad;
-};
-
-struct drm_i915_reg_read {
-	/*
-	 * Register offset.
-	 * For 64bit wide registers where the upper 32bits don't immediately
-	 * follow the lower 32bits, the offset of the lower 32bits must
-	 * be specified
-	 */
-	__u64 offset;
-#define I915_REG_READ_8B_WA (1ul << 0)
-
-	__u64 val; /* Return value */
-};
-/* Known registers:
- *
- * Render engine timestamp - 0x2358 + 64bit - gen7+
- * - Note this register returns an invalid value if using the default
- *   single instruction 8byte read, in order to workaround that pass
- *   flag I915_REG_READ_8B_WA in offset field.
- *
- */
-
-struct drm_i915_reset_stats {
-	__u32 ctx_id;
-	__u32 flags;
-
-	/* All resets since boot/module reload, for all contexts */
-	__u32 reset_count;
-
-	/* Number of batches lost when active in GPU, for this context */
-	__u32 batch_active;
-
-	/* Number of batches lost pending for execution, for this context */
-	__u32 batch_pending;
-
+	__u32 ctx_id; /* output: id of new context*/
 	__u32 pad;
 };
 
-struct drm_i915_gem_userptr {
-	__u64 user_ptr;
-	__u64 user_size;
+struct drm_i915_gem_context_create_ext {
+	__u32 ctx_id; /* output: id of new context*/
 	__u32 flags;
-#define I915_USERPTR_READ_ONLY 0x1
-#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
-	/**
-	 * Returned handle for the object.
-	 *
-	 * Object handles are nonzero.
-	 */
-	__u32 handle;
+#define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS	(1u << 0)
+#define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE	(1u << 1)
+#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
+	(-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1))
+	__u64 extensions;
 };
 
 struct drm_i915_gem_context_param {
@@ -1520,7 +1516,43 @@ struct drm_i915_gem_context_param {
  * On creation, all new contexts are marked as recoverable.
  */
 #define I915_CONTEXT_PARAM_RECOVERABLE	0x8
+
+	/*
+	 * The id of the associated virtual memory address space (ppGTT) of
+	 * this context. Can be retrieved and passed to another context
+	 * (on the same fd) for both to use the same ppGTT and so share
+	 * address layouts, and avoid reloading the page tables on context
+	 * switches between themselves.
+	 *
+	 * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY.
+	 */
+#define I915_CONTEXT_PARAM_VM		0x9
+
+/*
+ * I915_CONTEXT_PARAM_ENGINES:
+ *
+ * Bind this context to operate on this subset of available engines. Henceforth,
+ * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as
+ * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0]
+ * and upwards. Slots 0...N are filled in using the specified (class, instance).
+ * Use
+ *	engine_class: I915_ENGINE_CLASS_INVALID,
+ *	engine_instance: I915_ENGINE_CLASS_INVALID_NONE
+ * to specify a gap in the array that can be filled in later, e.g. by a
+ * virtual engine used for load balancing.
+ *
+ * Setting the number of engines bound to the context to 0, by passing a zero
+ * sized argument, will revert back to default settings.
+ *
+ * See struct i915_context_param_engines.
+ *
+ * Extensions:
+ *   i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)
+ *   i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
+ */
+#define I915_CONTEXT_PARAM_ENGINES	0xa
 /* Must be kept compact -- no holes and well documented */
+
 	__u64 value;
 };
 
@@ -1553,9 +1585,10 @@ struct drm_i915_gem_context_param_sseu {
 	__u16 engine_instance;
 
 	/*
-	 * Unused for now. Must be cleared to zero.
+	 * Unknown flags must be cleared to zero.
 	 */
 	__u32 flags;
+#define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)
 
 	/*
 	 * Mask of slices to enable for the context. Valid values are a subset
@@ -1583,6 +1616,175 @@ struct drm_i915_gem_context_param_sseu {
 	__u32 rsvd;
 };
 
+/*
+ * i915_context_engines_load_balance:
+ *
+ * Enable load balancing across this set of engines.
+ *
+ * Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when
+ * used will proxy the execbuffer request onto one of the set of engines
+ * in such a way as to distribute the load evenly across the set.
+ *
+ * The set of engines must be compatible (e.g. the same HW class) as they
+ * will share the same logical GPU context and ring.
+ *
+ * To intermix rendering with the virtual engine and direct rendering onto
+ * the backing engines (bypassing the load balancing proxy), the context must
+ * be defined to use a single timeline for all engines.
+ */
+struct i915_context_engines_load_balance {
+	struct i915_user_extension base;
+
+	__u16 engine_index;
+	__u16 mbz16; /* reserved for future use; must be zero */
+	__u32 flags; /* all undefined flags must be zero */
+
+	__u64 engines_mask; /* selection mask of engines[] */
+
+	__u64 mbz64[4]; /* reserved for future use; must be zero */
+};
+
+/*
+ * i915_context_engines_bond:
+ *
+ */
+struct i915_context_engines_bond {
+	struct i915_user_extension base;
+
+	__u16 engine_index;
+	__u16 mbz;
+
+	__u16 master_class;
+	__u16 master_instance;
+
+	__u64 sibling_mask;
+	__u64 flags; /* all undefined flags must be zero */
+};
+
+struct i915_context_param_engines {
+	__u64 extensions; /* linked chain of extension blocks, 0 terminates */
+#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0
+#define I915_CONTEXT_ENGINES_EXT_BOND 1
+
+	struct {
+		__u16 engine_class; /* see enum drm_i915_gem_engine_class */
+		__u16 engine_instance;
+	} class_instance[0];
+} __attribute__((packed));
+
+#define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \
+	__u64 extensions; \
+	struct { \
+		__u16 engine_class; \
+		__u16 engine_instance; \
+	} class_instance[N__]; \
+} __attribute__((packed)) name__
+
+struct drm_i915_gem_context_create_ext_setparam {
+#define I915_CONTEXT_CREATE_EXT_SETPARAM 0
+	struct i915_user_extension base;
+	struct drm_i915_gem_context_param setparam;
+};
+
+struct drm_i915_gem_context_create_ext_clone {
+#define I915_CONTEXT_CREATE_EXT_CLONE 1
+	struct i915_user_extension base;
+	__u32 clone_id;
+	__u32 flags;
+#define I915_CONTEXT_CLONE_FLAGS	(1u << 0)
+#define I915_CONTEXT_CLONE_SCHED	(1u << 1)
+#define I915_CONTEXT_CLONE_SSEU		(1u << 2)
+#define I915_CONTEXT_CLONE_TIMELINE	(1u << 3)
+#define I915_CONTEXT_CLONE_VM		(1u << 4)
+#define I915_CONTEXT_CLONE_ENGINES	(1u << 5)
+#define I915_CONTEXT_CLONE_UNKNOWN -(I915_CONTEXT_CLONE_ENGINES << 1)
+	__u64 rsvd;
+};
+
+struct drm_i915_gem_context_destroy {
+	__u32 ctx_id;
+	__u32 pad;
+};
+
+/*
+ * DRM_I915_GEM_VM_CREATE -
+ *
+ * Create a new virtual memory address space (ppGTT) for use within a context
+ * on the same file. Extensions can be provided to configure exactly how the
+ * address space is setup upon creation.
+ *
+ * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is
+ * returned in the outparam @id.
+ *
+ * No flags are defined, with all bits reserved and must be zero.
+ *
+ * An extension chain maybe provided, starting with @extensions, and terminated
+ * by the @next_extension being 0. Currently, no extensions are defined.
+ *
+ * DRM_I915_GEM_VM_DESTROY -
+ *
+ * Destroys a previously created VM id, specified in @id.
+ *
+ * No extensions or flags are allowed currently, and so must be zero.
+ */
+struct drm_i915_gem_vm_control {
+	__u64 extensions;
+	__u32 flags;
+	__u32 id;
+};
+
+struct drm_i915_reg_read {
+	/*
+	 * Register offset.
+	 * For 64bit wide registers where the upper 32bits don't immediately
+	 * follow the lower 32bits, the offset of the lower 32bits must
+	 * be specified
+	 */
+	__u64 offset;
+#define I915_REG_READ_8B_WA (1ul << 0)
+
+	__u64 val; /* Return value */
+};
+
+/* Known registers:
+ *
+ * Render engine timestamp - 0x2358 + 64bit - gen7+
+ * - Note this register returns an invalid value if using the default
+ *   single instruction 8byte read, in order to workaround that pass
+ *   flag I915_REG_READ_8B_WA in offset field.
+ *
+ */
+
+struct drm_i915_reset_stats {
+	__u32 ctx_id;
+	__u32 flags;
+
+	/* All resets since boot/module reload, for all contexts */
+	__u32 reset_count;
+
+	/* Number of batches lost when active in GPU, for this context */
+	__u32 batch_active;
+
+	/* Number of batches lost pending for execution, for this context */
+	__u32 batch_pending;
+
+	__u32 pad;
+};
+
+struct drm_i915_gem_userptr {
+	__u64 user_ptr;
+	__u64 user_size;
+	__u32 flags;
+#define I915_USERPTR_READ_ONLY 0x1
+#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
+	/**
+	 * Returned handle for the object.
+	 *
+	 * Object handles are nonzero.
+	 */
+	__u32 handle;
+};
+
 enum drm_i915_oa_format {
 	I915_OA_FORMAT_A13 = 1,	    /* HSW only */
 	I915_OA_FORMAT_A29,	    /* HSW only */
@@ -1744,6 +1946,7 @@ struct drm_i915_perf_oa_config {
 struct drm_i915_query_item {
 	__u64 query_id;
 #define DRM_I915_QUERY_TOPOLOGY_INFO    1
+#define DRM_I915_QUERY_ENGINE_INFO	2
 /* Must be kept compact -- no holes and well documented */
 
 	/*
@@ -1842,6 +2045,50 @@ struct drm_i915_query_topology_info {
 	__u8 data[];
 };
 
+/**
+ * struct drm_i915_engine_info
+ *
+ * Describes one engine and it's capabilities as known to the driver.
+ */
+struct drm_i915_engine_info {
+	/** Engine class as in enum drm_i915_gem_engine_class. */
+	__u16 engine_class;
+
+	/** Engine instance number. */
+	__u16 engine_instance;
+
+	/** Reserved field. */
+	__u32 rsvd0;
+
+	/** Engine flags. */
+	__u64 flags;
+
+	/** Capabilities of this engine. */
+	__u64 capabilities;
+#define I915_VIDEO_CLASS_CAPABILITY_HEVC		(1 << 0)
+#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC	(1 << 1)
+
+	/** Reserved fields. */
+	__u64 rsvd1[4];
+};
+
+/**
+ * struct drm_i915_query_engine_info
+ *
+ * Engine info query enumerates all engines known to the driver by filling in
+ * an array of struct drm_i915_engine_info structures.
+ */
+struct drm_i915_query_engine_info {
+	/** Number of struct drm_i915_engine_info structs following. */
+	__u32 num_engines;
+
+	/** MBZ */
+	__u32 rsvd[3];
+
+	/** Marker for drm_i915_engine_info structures. */
+	struct drm_i915_engine_info engines[];
+};
+
 #if defined(__cplusplus)
 }
 #endif
-- 
2.20.1

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[igt-dev] [PATCH v15 4/5] lib/i915: add gem_engine_topology library and for_each loop definition

[Andi Shyti]

The gem_engine_topology library is a set of functions that
interface with the query and getparam/setparam ioctls.

The library's access point is the 'intel_init_engine_list()'
function that, everytime is called, generates the list of active
engines and returns them in a 'struct intel_engine_data'. The
structure contains only the engines that are actively present in
the GPU.

The function can work in both the cases that the query and
getparam ioctls are implemented or not by the running kernel. In
case they are implemented, a query is made to the driver to fetch
the list of active engines. In case they are not implemented, the
list is taken from the 'intel_execution_engines2' array and
stored only after checking their presence.

The gem_engine_topology library provides some iteration helpers:

 - intel_get_current_engine(): provides the current engine in the
   iteration.

 - intel_get_current_physical_engine(): provides the current
   physical engine, if the current engine is a virtual engine,
   it moves forward until it finds a physical engine.

 - intel_next_engine() it just increments the counter so that it
   points to the next engine.

Extend the 'for_each_engine_class_instance' so that it can loop
using the new 'intel_init_engine_list()' and rename it to
'for_each_context_engine'.

Move '__for_each_engine_class_instance' to gem_engine_topology.h
and rename it to '__for_each_static_engine'.

Update accordingly tests/perf_pmu.c to use correctly the new
for_each lopps.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 lib/Makefile.sources           |   2 +
 lib/i915/gem_engine_topology.c | 222 +++++++++++++++++++++++++++++++++
 lib/i915/gem_engine_topology.h |  63 ++++++++++
 lib/igt.h                      |   1 +
 lib/igt_gt.h                   |   8 +-
 lib/meson.build                |   1 +
 tests/perf_pmu.c               |  12 +-
 7 files changed, 296 insertions(+), 13 deletions(-)
 create mode 100644 lib/i915/gem_engine_topology.c
 create mode 100644 lib/i915/gem_engine_topology.h

diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index cf2720981707..757bd7a17ebe 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -13,6 +13,8 @@ lib_source_list =	 	\
 	i915/gem_ring.c	\
 	i915/gem_mman.c	\
 	i915/gem_mman.h	\
+	i915/gem_engine_topology.c	\
+	i915/gem_engine_topology.h	\
 	i915_3d.h		\
 	i915_reg.h		\
 	i915_pciids.h		\
diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
new file mode 100644
index 000000000000..1144c49a1993
--- /dev/null
+++ b/lib/i915/gem_engine_topology.c
@@ -0,0 +1,222 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "drmtest.h"
+#include "ioctl_wrappers.h"
+
+#include "i915/gem_engine_topology.h"
+
+#define SIZEOF_CTX_PARAM	offsetof(struct i915_context_param_engines, \
+					class_instance[I915_EXEC_RING_MASK + 1])
+#define SIZEOF_QUERY		offsetof(struct drm_i915_query_engine_info, \
+					engines[I915_EXEC_RING_MASK + 1])
+
+static int __gem_query(int fd, struct drm_i915_query *q)
+{
+	int err = 0;
+
+	if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
+		err = -errno;
+
+	errno = 0;
+	return err;
+}
+
+static void gem_query(int fd, struct drm_i915_query *q)
+{
+	igt_assert_eq(__gem_query(fd, q), 0);
+}
+
+static void query_engines(int fd,
+			  struct drm_i915_query_engine_info *query_engines,
+			  int length)
+{
+	struct drm_i915_query_item item = { };
+	struct drm_i915_query query = { };
+
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	query.items_ptr = to_user_pointer(&item);
+	query.num_items = 1;
+	item.length = length;
+
+	item.data_ptr = to_user_pointer(query_engines);
+
+	gem_query(fd, &query);
+}
+
+static void ctx_map_engines(int fd, struct intel_engine_data *ed,
+			    struct drm_i915_gem_context_param *ctx_param)
+{
+	struct i915_context_param_engines *ctx_engine =
+			(struct i915_context_param_engines*) ctx_param->value;
+	int i = 0;
+
+	for (typeof(ctx_engine->class_instance[0]) *p =
+			&ctx_engine->class_instance[0];
+						i < ed->nengines; i++, p++) {
+		p->engine_class = ed->engines[i].class;
+		p->engine_instance = ed->engines[i].instance;
+	}
+
+	ctx_param->size = offsetof(typeof(*ctx_engine), class_instance[i]);
+
+	gem_context_set_param(fd, ctx_param);
+}
+
+static void init_engine(struct intel_execution_engine2 *e2, const char *name,
+			uint16_t class, uint16_t instance, uint64_t flags)
+{
+	static const char *unknown_name = "unknown",
+			  *virtual_name = "virtual";
+
+	e2->class    = class;
+	e2->instance = instance;
+	e2->flags    = flags;
+
+	if (class < 0 && instance < 0) {
+		e2->name = virtual_name;
+	} else {
+		const struct intel_execution_engine2 *__e2;
+
+		__for_each_static_engine(__e2)
+			if (__e2->class == class && __e2->instance == instance)
+				break;
+
+		e2->name = __e2->name ? __e2->name : unknown_name;
+	}
+}
+
+static void query_engine_list(int fd, struct intel_engine_data *ed)
+{
+	uint8_t query_buffer[SIZEOF_QUERY] = { };
+	struct drm_i915_query_engine_info *query_engine =
+			(struct drm_i915_query_engine_info *) query_buffer;
+	int i;
+
+	query_engines(fd, query_engine, SIZEOF_QUERY);
+
+	for (i = 0; i < query_engine->num_engines; i++)
+		init_engine(&ed->engines[i], NULL,
+			   query_engine->engines[i].engine_class,
+			   query_engine->engines[i].engine_instance, i);
+
+	ed->nengines = query_engine->num_engines;
+}
+
+struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id)
+{
+	struct intel_engine_data engine_data = { };
+	uint8_t buff[SIZEOF_CTX_PARAM] = { };
+
+	struct i915_context_param_engines *engines =
+		(struct i915_context_param_engines *) buff;
+
+	struct drm_i915_gem_context_param param = {
+		.param = I915_CONTEXT_PARAM_ENGINES,
+		.ctx_id = ctx_id,
+		.size = SIZEOF_CTX_PARAM,
+		.value = to_user_pointer(engines),
+	};
+
+	int i, ret;
+	unsigned int nengines;
+
+	ret = __gem_context_get_param(fd, &param);
+
+	nengines = param.size > sizeof(struct i915_context_param_engines) ?
+		   (param.size - sizeof(struct i915_context_param_engines)) /
+		   sizeof(engines->class_instance[0]) :
+		   0;
+
+	if (nengines > I915_EXEC_RING_MASK + 1) {
+		engine_data.error = ret ? ret : -EINVAL;
+		return engine_data;
+	}
+
+	if (__gem_context_get_param(fd, &param)) {
+		/* if kernel does not support engine/context mapping */
+		const struct intel_execution_engine2 *e2;
+
+		igt_debug("using pre-allocated engine list\n");
+
+		__for_each_static_engine(e2) {
+			struct intel_execution_engine2 *__e2;
+
+			__e2 = &engine_data.engines[engine_data.nengines];
+			__e2->flags = gem_class_instance_to_eb_flags(fd,
+						e2->class, e2->instance);
+
+			if (!gem_has_ring(fd, __e2->flags))
+				continue;
+
+			__e2->name = e2->name;
+			__e2->instance = e2->instance;
+			__e2->class = e2->class;
+			engine_data.nengines++;
+		}
+
+	} else if (!param.size) {
+		/* else if context doesn't have mapped engines */
+		query_engine_list(fd, &engine_data);
+		ctx_map_engines(fd, &engine_data, &param);
+
+	} else {
+		/* context has a list of mapped engines */
+
+		for (i = 0; i < nengines; i++)
+			init_engine(&engine_data.engines[i], NULL,
+				    engines->class_instance[i].engine_class,
+				    engines->class_instance[i].engine_instance,
+				    i);
+
+		engine_data.nengines = i;
+	}
+
+	return engine_data;
+}
+
+struct intel_execution_engine2
+	*intel_get_current_engine(struct intel_engine_data *ed)
+{
+	return (ed->n < ed->nengines) && !ed->error ?
+		&ed->engines[ed->n] :
+		NULL;
+}
+
+void intel_next_engine(struct intel_engine_data *ed)
+{
+	ed->n++;
+}
+
+struct intel_execution_engine2
+	*intel_get_current_physical_engine(struct intel_engine_data *ed)
+{
+	struct intel_execution_engine2 *e;
+
+	for (e = intel_get_current_engine(ed);
+	     e && !IS_PHYSICAL_ENGINE(e);
+	     intel_next_engine(ed))
+		;
+
+	return e;
+}
diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
new file mode 100644
index 000000000000..f662a4601ecd
--- /dev/null
+++ b/lib/i915/gem_engine_topology.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef GEM_ENGINE_TOPOLOGY_H
+#define GEM_ENGINE_TOPOLOGY_H
+
+#include "igt_gt.h"
+#include "i915_drm.h"
+
+struct intel_engine_data {
+	uint32_t nengines;
+	uint32_t n;
+	int error;
+	struct intel_execution_engine2 engines[I915_EXEC_RING_MASK + 1];
+};
+
+struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id);
+
+/* iteration functions */
+struct intel_execution_engine2
+	*intel_get_current_engine(struct intel_engine_data *ed);
+struct intel_execution_engine2
+	*intel_get_current_physical_engine(struct intel_engine_data *ed);
+void intel_next_engine(struct intel_engine_data *ed);
+
+#define IS_PHYSICAL_ENGINE(e2) ((e2->class >= 0) && (e2->instance >= 0))
+
+/* needs to replace "__for_each_engine_class_instance" when conflicts are fixed */
+#define __for_each_static_engine(e__) \
+	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
+
+#define for_each_context_engine(fd__, ctx__, e__) \
+	for (struct intel_engine_data i__ = intel_init_engine_list(fd__, ctx__); \
+	     ((e__) = intel_get_current_engine(&i__)); \
+	     intel_next_engine(&i__))
+
+/* needs to replace "for_each_physical_engine" when conflicts are fixed */
+#define __for_each_physical_engine__(fd__, e__) \
+	for (struct intel_engine_data i__ = intel_init_engine_list(fd__, 0); \
+	     ((e__) = intel_get_current_physical_engine(&i__)); \
+	     intel_next_engine(&i__))
+
+#endif /* GEM_ENGINE_TOPOLOGY_H */
diff --git a/lib/igt.h b/lib/igt.h
index 6654a659c062..03f19ca2dfb6 100644
--- a/lib/igt.h
+++ b/lib/igt.h
@@ -53,5 +53,6 @@
 #include "media_spin.h"
 #include "rendercopy.h"
 #include "i915/gem_mman.h"
+#include "i915/gem_engine_topology.h"
 
 #endif /* IGT_H */
diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 475c0b3c3cc6..2a7032d4b262 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -95,6 +95,7 @@ extern const struct intel_execution_engine2 {
 	const char *name;
 	int class;
 	int instance;
+	uint64_t flags;
 } intel_execution_engines2[];
 
 unsigned int
@@ -114,11 +115,4 @@ void gem_require_engine(int gem_fd,
 	igt_require(gem_has_engine(gem_fd, class, instance));
 }
 
-#define __for_each_engine_class_instance(e__) \
-	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
-
-#define for_each_engine_class_instance(fd__, e__) \
-	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++) \
-		for_if (gem_has_engine((fd__), (e__)->class, (e__)->instance))
-
 #endif /* IGT_GT_H */
diff --git a/lib/meson.build b/lib/meson.build
index 0eb5585d72b9..3cc52f97c8bf 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -5,6 +5,7 @@ lib_sources = [
 	'i915/gem_submission.c',
 	'i915/gem_ring.c',
 	'i915/gem_mman.c',
+	'i915/gem_engine_topology.c',
 	'igt_color_encoding.c',
 	'igt_debugfs.c',
 	'igt_device.c',
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 4f552bc2ae28..0e10bcfd1693 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -434,7 +434,7 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 
 	i = 0;
 	fd[0] = -1;
-	for_each_engine_class_instance(gem_fd, e_) {
+	for_each_context_engine(gem_fd, 0, e_) {
 		if (e == e_)
 			busy_idx = i;
 
@@ -497,7 +497,7 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 	unsigned int idle_idx, i;
 
 	i = 0;
-	for_each_engine_class_instance(gem_fd, e_) {
+	for_each_context_engine(gem_fd, 0, e_) {
 		if (e == e_)
 			idle_idx = i;
 		else if (spin)
@@ -554,7 +554,7 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
 	unsigned int i;
 
 	i = 0;
-	for_each_engine_class_instance(gem_fd, e) {
+	for_each_context_engine(gem_fd, 0, e) {
 		if (spin)
 			__submit_spin_batch(gem_fd, spin, e, 64);
 		else
@@ -1683,7 +1683,7 @@ igt_main
 		igt_require_gem(fd);
 		igt_require(i915_type_id() > 0);
 
-		for_each_engine_class_instance(fd, e)
+		for_each_context_engine(fd, 0, e)
 			num_engines++;
 	}
 
@@ -1693,7 +1693,7 @@ igt_main
 	igt_subtest("invalid-init")
 		invalid_init();
 
-	__for_each_engine_class_instance(e) {
+	__for_each_static_engine(e) {
 		const unsigned int pct[] = { 2, 50, 98 };
 
 		/**
@@ -1897,7 +1897,7 @@ igt_main
 			gem_quiescent_gpu(fd);
 		}
 
-		__for_each_engine_class_instance(e) {
+		__for_each_static_engine(e) {
 			igt_subtest_group {
 				igt_fixture {
 					gem_require_engine(render_fd,
-- 
2.20.1

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[igt-dev] [PATCH v15 5/5] tests: gem_exec_basic: add "exec-ctx" buffer execution demo test

[Andi Shyti]

The "exec-ctx" is a demo subtest inserted in the gem_exec_basic
test. The main goal is to reach the engines by using
the new uapi interfacing with 'gem_topology_has_engine()'.

The "exec-ctx" subtest simply gets the list of engines, binds
them to a context and executes a buffer. This is done through a
new "for_each_engine2" loop which iterates through the
engines.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 tests/i915/gem_exec_basic.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/tests/i915/gem_exec_basic.c b/tests/i915/gem_exec_basic.c
index dcb83864b1c1..7149452a72f0 100644
--- a/tests/i915/gem_exec_basic.c
+++ b/tests/i915/gem_exec_basic.c
@@ -135,6 +135,19 @@ igt_main
 			gtt(fd, e->exec_id | e->flags);
 	}
 
+	igt_subtest("exec-ctx") {
+		uint32_t ctx_id;
+		struct intel_execution_engine2 *e2;
+
+		ctx_id = gem_context_create(fd);
+
+		for_each_context_engine(fd, ctx_id, e2)
+			igt_assert(gem_context_has_engine(fd, e2->flags,
+							  ctx_id));
+
+		gem_context_destroy(fd, ctx_id);
+	}
+
 	igt_fixture {
 		igt_stop_hang_detector();
 		close(fd);
-- 
2.20.1

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Re: [igt-dev] [PATCH v15 2/5] lib: ioctl_wrappers: reach engines by index as well

[Chris Wilson]

Quoting Andi Shyti (2019-03-21 16:05:25)
> +bool gem_context_has_engine(int fd, uint32_t ctx, uint32_t engine)
> +{
> +       struct drm_i915_gem_execbuffer2 execbuf;
> +       struct drm_i915_gem_exec_object2 exec;
> +
> +       /* silly ABI, the kernel thinks everyone who has BSD also has BSD2 */
> +       if ((engine & ~(3<<13)) == I915_EXEC_BSD) {
> +               if (engine & (3 << 13) && !gem_has_bsd2(fd))
> +                       return false;
> +       }
> +
> +       memset(&exec, 0, sizeof(exec));
> +       memset(&execbuf, 0, sizeof(execbuf));
> +       execbuf.buffers_ptr = to_user_pointer(&exec);
> +       execbuf.buffer_count = 1;
> +       execbuf.flags = engine;
> +       execbuf.rsvd1 = ctx;
> +
> +       return __gem_execbuf(fd, &execbuf) == -ENOENT;
> +}
> diff --git a/lib/i915/gem_context.h b/lib/i915/gem_context.h
> index aef68dda6b26..dd64ebf17fbd 100644
> --- a/lib/i915/gem_context.h
> +++ b/lib/i915/gem_context.h
> @@ -45,4 +45,6 @@ int __gem_context_get_param(int fd, struct drm_i915_gem_context_param *p);
>  int __gem_context_set_priority(int fd, uint32_t ctx, int prio);
>  void gem_context_set_priority(int fd, uint32_t ctx, int prio);
>  
> +bool gem_context_has_engine(int fd, unsigned engine, unsigned ctx);

Hmm. Do we have ILP64 or LP64? I think we're LP64. Let's see what CI
thinks.
-Chris
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Re: [igt-dev] [PATCH v15 2/5] lib: ioctl_wrappers: reach engines by index as well

[Andi Shyti]

> > +bool gem_context_has_engine(int fd, unsigned engine, unsigned ctx);
> 
> Hmm. Do we have ILP64 or LP64? I think we're LP64. Let's see what CI
> thinks.

sorry, I forgot to update the prototype... my distraction will
kill me one day

this is taking more time than the rest :)

Andi
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Re: [igt-dev] [PATCH v15 2/5] lib: ioctl_wrappers: reach engines by index as well

[Chris Wilson]

Quoting Andi Shyti (2019-03-21 16:14:32)
> > > +bool gem_context_has_engine(int fd, unsigned engine, unsigned ctx);
> > 
> > Hmm. Do we have ILP64 or LP64? I think we're LP64. Let's see what CI
> > thinks.
> 
> sorry, I forgot to update the prototype... my distraction will
> kill me one day
> 
> this is taking more time than the rest :)

Depends if you notice patch 5/5 or not.
-Chris
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Re: [igt-dev] [PATCH v15 2/5] lib: ioctl_wrappers: reach engines by index as well

[Tvrtko Ursulin]

On 21/03/2019 16:05, Andi Shyti wrote:
> With the new engine query method engines are reachable through
> an index and context they are combined with.
> 
> The 'gem_has_ring()' becomes 'gem_context_has_engine()' that
> requires the index that the engine is mapped within the driver.
> The function has been moved from lib/ioctl_wappers to
> lib/i915/gem_context where it is more appropriate.
> 
> The previous 'gem_has_ring()' function becomes a wrapper to the
> new 'gem_context_has_engine()'.
> 
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>   lib/i915/gem_context.c | 21 +++++++++++++++++++++
>   lib/i915/gem_context.h |  2 ++
>   lib/ioctl_wrappers.c   | 19 -------------------
>   lib/ioctl_wrappers.h   |  3 ++-
>   4 files changed, 25 insertions(+), 20 deletions(-)
> 
> diff --git a/lib/i915/gem_context.c b/lib/i915/gem_context.c
> index 16004685e920..94ccb74b6aea 100644
> --- a/lib/i915/gem_context.c
> +++ b/lib/i915/gem_context.c
> @@ -275,3 +275,24 @@ void gem_context_set_priority(int fd, uint32_t ctx_id, int prio)
>   {
>   	igt_assert(__gem_context_set_priority(fd, ctx_id, prio) == 0);
>   }
> +
> +bool gem_context_has_engine(int fd, uint32_t ctx, uint32_t engine)
> +{
> +	struct drm_i915_gem_execbuffer2 execbuf;
> +	struct drm_i915_gem_exec_object2 exec;
> +
> +	/* silly ABI, the kernel thinks everyone who has BSD also has BSD2 */

Can you add the comment here as I suggested in the previous round? 
Something like:

"
Engine can be either execbuf flags engine selector, or context map 
index, but in the following case we can still safely check against 
I915_EXEC_BSD since we don't expect 1 << 13 or more engines in the map.
"

Regards,

Tvrtko

> +	if ((engine & ~(3<<13)) == I915_EXEC_BSD) {
> +		if (engine & (3 << 13) && !gem_has_bsd2(fd))
> +			return false;
> +	}
> +
> +	memset(&exec, 0, sizeof(exec));
> +	memset(&execbuf, 0, sizeof(execbuf));
> +	execbuf.buffers_ptr = to_user_pointer(&exec);
> +	execbuf.buffer_count = 1;
> +	execbuf.flags = engine;
> +	execbuf.rsvd1 = ctx;
> +
> +	return __gem_execbuf(fd, &execbuf) == -ENOENT;
> +}
> diff --git a/lib/i915/gem_context.h b/lib/i915/gem_context.h
> index aef68dda6b26..dd64ebf17fbd 100644
> --- a/lib/i915/gem_context.h
> +++ b/lib/i915/gem_context.h
> @@ -45,4 +45,6 @@ int __gem_context_get_param(int fd, struct drm_i915_gem_context_param *p);
>   int __gem_context_set_priority(int fd, uint32_t ctx, int prio);
>   void gem_context_set_priority(int fd, uint32_t ctx, int prio);
>   
> +bool gem_context_has_engine(int fd, unsigned engine, unsigned ctx);
> +
>   #endif /* GEM_CONTEXT_H */
> diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
> index a66eb4bc0f4f..3f8f0874bc4b 100644
> --- a/lib/ioctl_wrappers.c
> +++ b/lib/ioctl_wrappers.c
> @@ -1253,25 +1253,6 @@ void igt_require_gem(int fd)
>   	igt_require_f(err == 0, "Unresponsive i915/GEM device\n");
>   }
>   
> -bool gem_has_ring(int fd, unsigned ring)
> -{
> -	struct drm_i915_gem_execbuffer2 execbuf;
> -	struct drm_i915_gem_exec_object2 exec;
> -
> -	/* silly ABI, the kernel thinks everyone who has BSD also has BSD2 */
> -	if ((ring & ~(3<<13)) == I915_EXEC_BSD) {
> -		if (ring & (3 << 13) && !gem_has_bsd2(fd))
> -			return false;
> -	}
> -
> -	memset(&exec, 0, sizeof(exec));
> -	memset(&execbuf, 0, sizeof(execbuf));
> -	execbuf.buffers_ptr = to_user_pointer(&exec);
> -	execbuf.buffer_count = 1;
> -	execbuf.flags = ring;
> -	return __gem_execbuf(fd, &execbuf) == -ENOENT;
> -}
> -
>   /**
>    * gem_require_ring:
>    * @fd: open i915 drm file descriptor
> diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
> index ad93daffcfd5..e712f1973142 100644
> --- a/lib/ioctl_wrappers.h
> +++ b/lib/ioctl_wrappers.h
> @@ -142,11 +142,12 @@ bool gem_has_exec_fence(int fd);
>   
>   /* check functions which auto-skip tests by calling igt_skip() */
>   void gem_require_caching(int fd);
> -bool gem_has_ring(int fd, unsigned ring);
>   void gem_require_ring(int fd, unsigned ring);
>   bool gem_has_mocs_registers(int fd);
>   void gem_require_mocs_registers(int fd);
>   
> +#define gem_has_ring(f, r) gem_context_has_engine(f, 0, r)
> +
>   /* prime */
>   struct local_dma_buf_sync {
>   	uint64_t flags;
> 
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[igt-dev] ✓ Fi.CI.BAT: success for new engine discovery interface

[Patchwork]

== Series Details ==

Series: new engine discovery interface
URL   : https://patchwork.freedesktop.org/series/58365/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5789 -> IGTPW_2684
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/58365/revisions/1/mbox/

Known issues
------------

  Here are the changes found in IGTPW_2684 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@query-info:
    - fi-bsw-kefka:       NOTRUN -> SKIP [fdo#109271] +55

  * igt@amdgpu/amd_cs_nop@sync-fork-compute0:
    - fi-icl-u3:          NOTRUN -> SKIP [fdo#109315] +17

  * igt@gem_ctx_create@basic-files:
    - fi-gdg-551:         NOTRUN -> SKIP [fdo#109271] +106

  * igt@gem_exec_basic@gtt-bsd1:
    - fi-icl-u3:          NOTRUN -> SKIP [fdo#109276] +7

  * igt@gem_exec_parse@basic-rejected:
    - fi-icl-u3:          NOTRUN -> SKIP [fdo#109289] +1

  * igt@i915_selftest@live_contexts:
    - fi-icl-u3:          NOTRUN -> DMESG-FAIL [fdo#108569]

  * igt@i915_selftest@live_uncore:
    - fi-skl-gvtdvm:      PASS -> DMESG-FAIL [fdo#110210]

  * igt@kms_busy@basic-flip-a:
    - fi-gdg-551:         NOTRUN -> FAIL [fdo#103182] +1

  * igt@kms_busy@basic-flip-c:
    - fi-blb-e6850:       NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
    - fi-byt-j1900:       NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
    - fi-gdg-551:         NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
    - fi-bsw-kefka:       NOTRUN -> SKIP [fdo#109271] / [fdo#109278]

  * igt@kms_chamelium@hdmi-crc-fast:
    - fi-byt-j1900:       NOTRUN -> SKIP [fdo#109271] +52

  * igt@kms_chamelium@hdmi-edid-read:
    - fi-icl-u3:          NOTRUN -> SKIP [fdo#109284] +8

  * igt@kms_force_connector_basic@prune-stale-modes:
    - fi-icl-u3:          NOTRUN -> SKIP [fdo#109285] +3

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u3:          NOTRUN -> FAIL [fdo#103167]

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c:
    - fi-blb-e6850:       NOTRUN -> SKIP [fdo#109271] +48

  * igt@prime_vgem@basic-fence-flip:
    - fi-gdg-551:         NOTRUN -> DMESG-FAIL [fdo#103182]

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-blb-e6850:       INCOMPLETE [fdo#107718] -> PASS

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-hsw-4770:        SKIP [fdo#109271] -> PASS +2

  * igt@i915_selftest@live_execlists:
    - fi-apl-guc:         INCOMPLETE [fdo#103927] / [fdo#109720] -> PASS

  * igt@kms_frontbuffer_tracking@basic:
    - fi-byt-clapper:     FAIL [fdo#103167] -> PASS

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
    - fi-byt-clapper:     FAIL [fdo#103191] / [fdo#107362] -> PASS +1

  
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
  [fdo#110210]: https://bugs.freedesktop.org/show_bug.cgi?id=110210


Participating hosts (41 -> 38)
------------------------------

  Additional (4): fi-byt-j1900 fi-gdg-551 fi-bsw-kefka fi-icl-u3 
  Missing    (7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-ctg-p8600 fi-byt-n2820 fi-bdw-samus 


Build changes
-------------

    * IGT: IGT_4896 -> IGTPW_2684

  CI_DRM_5789: 93b3614e8c493860dc63c3028460efb02036c6ea @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_2684: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2684/
  IGT_4896: 0f9c061247fb7aba21c9459f19f437927a28f32c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools



== Testlist changes ==

+igt@gem_exec_basic@exec-ctx

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2684/
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Re: [igt-dev] [PATCH v15 4/5] lib/i915: add gem_engine_topology library and for_each loop definition

[Tvrtko Ursulin]

On 21/03/2019 16:05, Andi Shyti wrote:
> The gem_engine_topology library is a set of functions that
> interface with the query and getparam/setparam ioctls.
> 
> The library's access point is the 'intel_init_engine_list()'
> function that, everytime is called, generates the list of active
> engines and returns them in a 'struct intel_engine_data'. The
> structure contains only the engines that are actively present in
> the GPU.
> 
> The function can work in both the cases that the query and
> getparam ioctls are implemented or not by the running kernel. In
> case they are implemented, a query is made to the driver to fetch
> the list of active engines. In case they are not implemented, the
> list is taken from the 'intel_execution_engines2' array and
> stored only after checking their presence.
> 
> The gem_engine_topology library provides some iteration helpers:
> 
>   - intel_get_current_engine(): provides the current engine in the
>     iteration.
> 
>   - intel_get_current_physical_engine(): provides the current
>     physical engine, if the current engine is a virtual engine,
>     it moves forward until it finds a physical engine.
> 
>   - intel_next_engine() it just increments the counter so that it
>     points to the next engine.
> 
> Extend the 'for_each_engine_class_instance' so that it can loop
> using the new 'intel_init_engine_list()' and rename it to
> 'for_each_context_engine'.
> 
> Move '__for_each_engine_class_instance' to gem_engine_topology.h
> and rename it to '__for_each_static_engine'.
> 
> Update accordingly tests/perf_pmu.c to use correctly the new
> for_each lopps.
> 
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> ---
>   lib/Makefile.sources           |   2 +
>   lib/i915/gem_engine_topology.c | 222 +++++++++++++++++++++++++++++++++
>   lib/i915/gem_engine_topology.h |  63 ++++++++++
>   lib/igt.h                      |   1 +
>   lib/igt_gt.h                   |   8 +-
>   lib/meson.build                |   1 +
>   tests/perf_pmu.c               |  12 +-
>   7 files changed, 296 insertions(+), 13 deletions(-)
>   create mode 100644 lib/i915/gem_engine_topology.c
>   create mode 100644 lib/i915/gem_engine_topology.h
> 
> diff --git a/lib/Makefile.sources b/lib/Makefile.sources
> index cf2720981707..757bd7a17ebe 100644
> --- a/lib/Makefile.sources
> +++ b/lib/Makefile.sources
> @@ -13,6 +13,8 @@ lib_source_list =	 	\
>   	i915/gem_ring.c	\
>   	i915/gem_mman.c	\
>   	i915/gem_mman.h	\
> +	i915/gem_engine_topology.c	\
> +	i915/gem_engine_topology.h	\
>   	i915_3d.h		\
>   	i915_reg.h		\
>   	i915_pciids.h		\
> diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
> new file mode 100644
> index 000000000000..1144c49a1993
> --- /dev/null
> +++ b/lib/i915/gem_engine_topology.c
> @@ -0,0 +1,222 @@
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include "drmtest.h"
> +#include "ioctl_wrappers.h"
> +
> +#include "i915/gem_engine_topology.h"
> +
> +#define SIZEOF_CTX_PARAM	offsetof(struct i915_context_param_engines, \
> +					class_instance[I915_EXEC_RING_MASK + 1])
> +#define SIZEOF_QUERY		offsetof(struct drm_i915_query_engine_info, \
> +					engines[I915_EXEC_RING_MASK + 1])

Since we now have four instances of I915_EXEC_RING_MASK + 1, and I 
dislike it anyway, I suggest you add something like:

/*
  * Limit what we support for simplicity due limitation in how much we
  * can address via execbuf2.
  */
#define __MAX_ENGINE_DATA (I915_EXEC_RING_MASK + 1)

> +
> +static int __gem_query(int fd, struct drm_i915_query *q)
> +{
> +	int err = 0;
> +
> +	if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
> +		err = -errno;
> +
> +	errno = 0;
> +	return err;
> +}
> +
> +static void gem_query(int fd, struct drm_i915_query *q)
> +{
> +	igt_assert_eq(__gem_query(fd, q), 0);
> +}
> +
> +static void query_engines(int fd,
> +			  struct drm_i915_query_engine_info *query_engines,
> +			  int length)
> +{
> +	struct drm_i915_query_item item = { };
> +	struct drm_i915_query query = { };
> +
> +	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
> +	query.items_ptr = to_user_pointer(&item);
> +	query.num_items = 1;
> +	item.length = length;
> +
> +	item.data_ptr = to_user_pointer(query_engines);
> +
> +	gem_query(fd, &query);
> +}
> +
> +static void ctx_map_engines(int fd, struct intel_engine_data *ed,
> +			    struct drm_i915_gem_context_param *ctx_param)
> +{
> +	struct i915_context_param_engines *ctx_engine =
> +			(struct i915_context_param_engines*) ctx_param->value;
> +	int i = 0;
> +
> +	for (typeof(ctx_engine->class_instance[0]) *p =
> +			&ctx_engine->class_instance[0];
> +						i < ed->nengines; i++, p++) {
> +		p->engine_class = ed->engines[i].class;
> +		p->engine_instance = ed->engines[i].instance;
> +	}
> +
> +	ctx_param->size = offsetof(typeof(*ctx_engine), class_instance[i]);
> +
> +	gem_context_set_param(fd, ctx_param);
> +}
> +
> +static void init_engine(struct intel_execution_engine2 *e2, const char *name,
> +			uint16_t class, uint16_t instance, uint64_t flags)

You are keeping name for the future? (It is unused at the moment.)

> +{
> +	static const char *unknown_name = "unknown",
> +			  *virtual_name = "virtual";

Unusual style but it is actually readable so I think I like it.

> +
> +	e2->class    = class;
> +	e2->instance = instance;
> +	e2->flags    = flags;
> +
> +	if (class < 0 && instance < 0) {
> +		e2->name = virtual_name;
> +	} else {
> +		const struct intel_execution_engine2 *__e2;
> +
> +		__for_each_static_engine(__e2)
> +			if (__e2->class == class && __e2->instance == instance)
> +				break;
> +
> +		e2->name = __e2->name ? __e2->name : unknown_name;

I've now started to worry about how will CI/buglog handle us forgetting 
to expand the static list. (More than one subtest of a same name for 
"test-$engine_name" ones?) Do we want and igt_warn on unknown engines to 
make it more visible? Or even just crash?

> +	}
> +}
> +
> +static void query_engine_list(int fd, struct intel_engine_data *ed)
> +{
> +	uint8_t query_buffer[SIZEOF_QUERY] = { };
> +	struct drm_i915_query_engine_info *query_engine =
> +			(struct drm_i915_query_engine_info *) query_buffer;
> +	int i;
> +
> +	query_engines(fd, query_engine, SIZEOF_QUERY);
> +
> +	for (i = 0; i < query_engine->num_engines; i++)
> +		init_engine(&ed->engines[i], NULL,
> +			   query_engine->engines[i].engine_class,
> +			   query_engine->engines[i].engine_instance, i);
> +
> +	ed->nengines = query_engine->num_engines;
> +}
> +
> +struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id)
> +{
> +	struct intel_engine_data engine_data = { };
> +	uint8_t buff[SIZEOF_CTX_PARAM] = { };
> +
> +	struct i915_context_param_engines *engines =
> +		(struct i915_context_param_engines *) buff;
> +
> +	struct drm_i915_gem_context_param param = {
> +		.param = I915_CONTEXT_PARAM_ENGINES,
> +		.ctx_id = ctx_id,
> +		.size = SIZEOF_CTX_PARAM,
> +		.value = to_user_pointer(engines),
> +	};
> +
> +	int i, ret;
> +	unsigned int nengines;
> +
> +	ret = __gem_context_get_param(fd, &param);
> +
> +	nengines = param.size > sizeof(struct i915_context_param_engines) ?
> +		   (param.size - sizeof(struct i915_context_param_engines)) /
> +		   sizeof(engines->class_instance[0]) :
> +		   0;
> +
> +	if (nengines > I915_EXEC_RING_MASK + 1) {
> +		engine_data.error = ret ? ret : -EINVAL;
> +		return engine_data;
> +	}

If we one day allow more engines in the map than the current limit?

It looks this would make the iterator not work. Was that the intention? 
What is the point of continuing then rather than just asserting?

> +
> +	if (__gem_context_get_param(fd, &param)) {
> +		/* if kernel does not support engine/context mapping */
> +		const struct intel_execution_engine2 *e2;
> +
> +		igt_debug("using pre-allocated engine list\n");
> +
> +		__for_each_static_engine(e2) {
> +			struct intel_execution_engine2 *__e2;
> +
> +			__e2 = &engine_data.engines[engine_data.nengines];
> +			__e2->flags = gem_class_instance_to_eb_flags(fd,
> +						e2->class, e2->instance);
> +
> +			if (!gem_has_ring(fd, __e2->flags))
> +				continue;
> +
> +			__e2->name = e2->name;
> +			__e2->instance = e2->instance;
> +			__e2->class = e2->class;
> +			engine_data.nengines++;
> +		}
> +
> +	} else if (!param.size) {
> +		/* else if context doesn't have mapped engines */
> +		query_engine_list(fd, &engine_data);
> +		ctx_map_engines(fd, &engine_data, &param);
> +
> +	} else {
> +		/* context has a list of mapped engines */
> +
> +		for (i = 0; i < nengines; i++)
> +			init_engine(&engine_data.engines[i], NULL,
> +				    engines->class_instance[i].engine_class,
> +				    engines->class_instance[i].engine_instance,
> +				    i);
> +
> +		engine_data.nengines = i;
> +	}
> +
> +	return engine_data;
> +}
> +
> +struct intel_execution_engine2
> +	*intel_get_current_engine(struct intel_engine_data *ed)

Unusual coding style, we use:

type
func(params)

or:

type func(params)

> +{
> +	return (ed->n < ed->nengines) && !ed->error ?
> +		&ed->engines[ed->n] :
> +		NULL;

So could store the pointer to current engine in the iterator?

> +}
> +
> +void intel_next_engine(struct intel_engine_data *ed)
> +{
> +	ed->n++;
> +}
> +
> +struct intel_execution_engine2
> +	*intel_get_current_physical_engine(struct intel_engine_data *ed)
> +{
> +	struct intel_execution_engine2 *e;
> +
> +	for (e = intel_get_current_engine(ed);
> +	     e && !IS_PHYSICAL_ENGINE(e);
> +	     intel_next_engine(ed))
> +		;
> +
> +	return e;
> +}
> diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
> new file mode 100644
> index 000000000000..f662a4601ecd
> --- /dev/null
> +++ b/lib/i915/gem_engine_topology.h
> @@ -0,0 +1,63 @@
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#ifndef GEM_ENGINE_TOPOLOGY_H
> +#define GEM_ENGINE_TOPOLOGY_H
> +
> +#include "igt_gt.h"
> +#include "i915_drm.h"
> +
> +struct intel_engine_data {
> +	uint32_t nengines;
> +	uint32_t n;
> +	int error;
> +	struct intel_execution_engine2 engines[I915_EXEC_RING_MASK + 1];
> +};
> +
> +struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id);
> +
> +/* iteration functions */
> +struct intel_execution_engine2
> +	*intel_get_current_engine(struct intel_engine_data *ed);
> +struct intel_execution_engine2
> +	*intel_get_current_physical_engine(struct intel_engine_data *ed);

Same coding style issue to correct.

> +void intel_next_engine(struct intel_engine_data *ed);
> +
> +#define IS_PHYSICAL_ENGINE(e2) ((e2->class >= 0) && (e2->instance >= 0))

Chris, do you think this will be future proof enough?

I remembered how at one point I had "IS_PHYSICAL" as a flag in engine query.

Or we make this here more explicit by being "IS_VIRTUAL" and invert the 
test in the caller?

> +
> +/* needs to replace "__for_each_engine_class_instance" when conflicts are fixed */
> +#define __for_each_static_engine(e__) \
> +	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
> +
> +#define for_each_context_engine(fd__, ctx__, e__) \
> +	for (struct intel_engine_data i__ = intel_init_engine_list(fd__, ctx__); \
> +	     ((e__) = intel_get_current_engine(&i__)); \
> +	     intel_next_engine(&i__))
> +
> +/* needs to replace "for_each_physical_engine" when conflicts are fixed */
> +#define __for_each_physical_engine__(fd__, e__) \
> +	for (struct intel_engine_data i__ = intel_init_engine_list(fd__, 0); \
> +	     ((e__) = intel_get_current_physical_engine(&i__)); \
> +	     intel_next_engine(&i__))
> +
> +#endif /* GEM_ENGINE_TOPOLOGY_H */
> diff --git a/lib/igt.h b/lib/igt.h
> index 6654a659c062..03f19ca2dfb6 100644
> --- a/lib/igt.h
> +++ b/lib/igt.h
> @@ -53,5 +53,6 @@
>   #include "media_spin.h"
>   #include "rendercopy.h"
>   #include "i915/gem_mman.h"
> +#include "i915/gem_engine_topology.h"
>   
>   #endif /* IGT_H */
> diff --git a/lib/igt_gt.h b/lib/igt_gt.h
> index 475c0b3c3cc6..2a7032d4b262 100644
> --- a/lib/igt_gt.h
> +++ b/lib/igt_gt.h
> @@ -95,6 +95,7 @@ extern const struct intel_execution_engine2 {
>   	const char *name;
>   	int class;
>   	int instance;
> +	uint64_t flags;
>   } intel_execution_engines2[];
>   
>   unsigned int
> @@ -114,11 +115,4 @@ void gem_require_engine(int gem_fd,
>   	igt_require(gem_has_engine(gem_fd, class, instance));
>   }
>   
> -#define __for_each_engine_class_instance(e__) \
> -	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
> -
> -#define for_each_engine_class_instance(fd__, e__) \
> -	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++) \
> -		for_if (gem_has_engine((fd__), (e__)->class, (e__)->instance))
> -
>   #endif /* IGT_GT_H */
> diff --git a/lib/meson.build b/lib/meson.build
> index 0eb5585d72b9..3cc52f97c8bf 100644
> --- a/lib/meson.build
> +++ b/lib/meson.build
> @@ -5,6 +5,7 @@ lib_sources = [
>   	'i915/gem_submission.c',
>   	'i915/gem_ring.c',
>   	'i915/gem_mman.c',
> +	'i915/gem_engine_topology.c',
>   	'igt_color_encoding.c',
>   	'igt_debugfs.c',
>   	'igt_device.c',
> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
> index 4f552bc2ae28..0e10bcfd1693 100644
> --- a/tests/perf_pmu.c
> +++ b/tests/perf_pmu.c
> @@ -434,7 +434,7 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
>   
>   	i = 0;
>   	fd[0] = -1;
> -	for_each_engine_class_instance(gem_fd, e_) {
> +	for_each_context_engine(gem_fd, 0, e_) {

Make perf_pmu use for_each_physical_engine, apart from the test enumeration.

>   		if (e == e_)
>   			busy_idx = i;
>   
> @@ -497,7 +497,7 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
>   	unsigned int idle_idx, i;
>   
>   	i = 0;
> -	for_each_engine_class_instance(gem_fd, e_) {
> +	for_each_context_engine(gem_fd, 0, e_) {
>   		if (e == e_)
>   			idle_idx = i;
>   		else if (spin)
> @@ -554,7 +554,7 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
>   	unsigned int i;
>   
>   	i = 0;
> -	for_each_engine_class_instance(gem_fd, e) {
> +	for_each_context_engine(gem_fd, 0, e) {
>   		if (spin)
>   			__submit_spin_batch(gem_fd, spin, e, 64);
>   		else
> @@ -1683,7 +1683,7 @@ igt_main
>   		igt_require_gem(fd);
>   		igt_require(i915_type_id() > 0);
>   
> -		for_each_engine_class_instance(fd, e)
> +		for_each_context_engine(fd, 0, e)
>   			num_engines++;
>   	}
>   
> @@ -1693,7 +1693,7 @@ igt_main
>   	igt_subtest("invalid-init")
>   		invalid_init();
>   
> -	__for_each_engine_class_instance(e) {
> +	__for_each_static_engine(e) {
>   		const unsigned int pct[] = { 2, 50, 98 };
>   
>   		/**
> @@ -1897,7 +1897,7 @@ igt_main
>   			gem_quiescent_gpu(fd);
>   		}
>   
> -		__for_each_engine_class_instance(e) {
> +		__for_each_static_engine(e) {
>   			igt_subtest_group {
>   				igt_fixture {
>   					gem_require_engine(render_fd,
> 

Regards,

Tvrtko
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Re: [igt-dev] [PATCH v15 4/5] lib/i915: add gem_engine_topology library and for_each loop definition

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-03-22 07:47:02)
> 
> On 21/03/2019 16:05, Andi Shyti wrote:
> > +{
> > +     static const char *unknown_name = "unknown",
> > +                       *virtual_name = "virtual";
> 
> Unusual style but it is actually readable so I think I like it.

Bah, if I can't find a cino= setting, I'm not adopting it ;)

> > +
> > +     e2->class    = class;
> > +     e2->instance = instance;
> > +     e2->flags    = flags;
> > +
> > +     if (class < 0 && instance < 0) {
> > +             e2->name = virtual_name;
> > +     } else {
> > +             const struct intel_execution_engine2 *__e2;
> > +
> > +             __for_each_static_engine(__e2)
> > +                     if (__e2->class == class && __e2->instance == instance)
> > +                             break;
> > +
> > +             e2->name = __e2->name ? __e2->name : unknown_name;
> 
> I've now started to worry about how will CI/buglog handle us forgetting 
> to expand the static list. (More than one subtest of a same name for 
> "test-$engine_name" ones?) Do we want and igt_warn on unknown engines to 
> make it more visible? Or even just crash?

Set flags to -1ull. That should cause EINVAL forever one hopes.

We shouldn't get any test (atm) with unknown as we only use the static
table for test generation. For runtime test discovery, we can apply the
filter of does this engine actually exist.

> > +void intel_next_engine(struct intel_engine_data *ed);
> > +
> > +#define IS_PHYSICAL_ENGINE(e2) ((e2->class >= 0) && (e2->instance >= 0))
> 
> Chris, do you think this will be future proof enough?

At the moment, we've reserved just the one identifier for placeholders
(class == I915_ENGINE_CLASS_INVALID). And I feel confident that should
be enough.

The problem is if something else gave us multiple instances of a logical
engine for which we have no means to determine the physical mapping,
which is vvv

> I remembered how at one point I had "IS_PHYSICAL" as a flag in engine query.
> 
> Or we make this here more explicit by being "IS_VIRTUAL" and invert the 
> test in the caller?

Aye. I think you are right here, and we need to put a caps field into
the engine_data (filled in by i915_query for valid classes and default
to !phys for invalid slots). A lot of the for_each_physical_engine()
tests do not make sense if there is automagic engine mapping going on
behind the scenes.
-Chris
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[igt-dev] ✗ Fi.CI.IGT: failure for new engine discovery interface

[Patchwork]

== Series Details ==

Series: new engine discovery interface
URL   : https://patchwork.freedesktop.org/series/58365/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_5789_full -> IGTPW_2684_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_2684_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_2684_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/58365/revisions/1/mbox/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_2684_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_busy@extended-modeset-hang-newfb-render-a:
    - shard-snb:          PASS -> DMESG-WARN

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
    - shard-hsw:          PASS -> DMESG-WARN
    - shard-kbl:          PASS -> DMESG-WARN

  * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
    - shard-glk:          NOTRUN -> DMESG-WARN

  * igt@perf_pmu@busy-check-all-vcs0:
    - shard-kbl:          PASS -> FAIL +7
    - shard-hsw:          PASS -> FAIL +4

  * igt@perf_pmu@busy-check-all-vecs0:
    - shard-apl:          PASS -> FAIL +5
    - shard-glk:          PASS -> FAIL +3

  * igt@perf_pmu@busy-idle-check-all-bcs0:
    - shard-snb:          PASS -> FAIL +1

  * igt@perf_pmu@busy-idle-check-all-vcs0:
    - shard-glk:          NOTRUN -> FAIL

  
New tests
---------

  New tests have been introduced between CI_DRM_5789_full and IGTPW_2684_full:

### New IGT tests (1) ###

  * igt@gem_exec_basic@exec-ctx:
    - Statuses : 5 pass(s)
    - Exec time: [0.0, 0.00] s

  

Known issues
------------

  Here are the changes found in IGTPW_2684_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_create@create-clear:
    - shard-snb:          PASS -> INCOMPLETE [fdo#105411]

  * igt@gem_ctx_sseu@invalid-args:
    - shard-apl:          NOTRUN -> SKIP [fdo#109271] +19

  * igt@gem_eio@reset-stress:
    - shard-snb:          PASS -> FAIL [fdo#109661]

  * igt@gem_wait@write-busy-bsd2:
    - shard-hsw:          NOTRUN -> SKIP [fdo#109271] +40

  * igt@kms_atomic_transition@6x-modeset-transitions-fencing:
    - shard-kbl:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2

  * igt@kms_atomic_transition@6x-modeset-transitions-nonblocking:
    - shard-apl:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2

  * igt@kms_available_modes_crc@available_mode_test_crc:
    - shard-glk:          NOTRUN -> FAIL [fdo#106641]

  * igt@kms_busy@basic-flip-d:
    - shard-glk:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +13

  * igt@kms_color@pipe-c-ctm-max:
    - shard-glk:          NOTRUN -> FAIL [fdo#108147] +1

  * igt@kms_color@pipe-c-degamma:
    - shard-glk:          NOTRUN -> FAIL [fdo#104782] +1

  * igt@kms_cursor_crc@cursor-256x256-suspend:
    - shard-glk:          NOTRUN -> FAIL [fdo#103232] +2

  * igt@kms_cursor_crc@cursor-alpha-opaque:
    - shard-kbl:          PASS -> FAIL [fdo#109350]
    - shard-apl:          PASS -> FAIL [fdo#109350]

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt:
    - shard-kbl:          NOTRUN -> SKIP [fdo#109271] +55

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-blt:
    - shard-glk:          NOTRUN -> SKIP [fdo#109271] +122

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt:
    - shard-snb:          NOTRUN -> SKIP [fdo#109271] +71

  * igt@kms_invalid_dotclock:
    - shard-glk:          NOTRUN -> DMESG-WARN [fdo#109373]

  * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
    - shard-kbl:          NOTRUN -> FAIL [fdo#108145] / [fdo#108590]

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
    - shard-glk:          PASS -> FAIL [fdo#108145]
    - shard-kbl:          PASS -> FAIL [fdo#108145]
    - shard-apl:          PASS -> FAIL [fdo#108145]

  * igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
    - shard-kbl:          PASS -> DMESG-FAIL [fdo#105763]

  * igt@kms_universal_plane@disable-primary-vs-flip-pipe-d:
    - shard-snb:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +10

  * igt@kms_universal_plane@universal-plane-gen9-features-pipe-f:
    - shard-hsw:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +3

  * igt@kms_vblank@pipe-b-ts-continuation-modeset-hang:
    - shard-apl:          PASS -> FAIL [fdo#104894] +1

  * igt@perf_pmu@busy-check-all-vcs0:
    - shard-snb:          PASS -> FAIL [fdo#105106] +1

  * igt@runner@aborted:
    - shard-glk:          NOTRUN -> FAIL [fdo#109373] / [k.org#202321]

  
#### Possible fixes ####

  * igt@gem_tiled_swapping@non-threaded:
    - shard-hsw:          FAIL [fdo#108686] -> PASS

  * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-apl:          DMESG-WARN -> PASS

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-apl:          INCOMPLETE [fdo#103927] -> PASS

  * igt@kms_busy@extended-modeset-hang-newfb-render-a:
    - shard-hsw:          DMESG-WARN -> PASS +1

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
    - shard-kbl:          DMESG-WARN -> PASS +1
    - shard-snb:          DMESG-WARN -> PASS

  * igt@kms_cursor_crc@cursor-128x42-sliding:
    - shard-kbl:          FAIL [fdo#103232] -> PASS +1
    - shard-apl:          FAIL [fdo#103232] -> PASS +1

  * igt@kms_flip@modeset-vs-vblank-race-interruptible:
    - shard-glk:          FAIL [fdo#103060] -> PASS

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
    - shard-kbl:          INCOMPLETE [fdo#103665] -> PASS

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-kbl:          FAIL [fdo#109016] -> PASS

  * igt@kms_setmode@basic:
    - shard-hsw:          FAIL [fdo#99912] -> PASS

  * igt@perf_pmu@rc6-runtime-pm-long:
    - shard-apl:          FAIL [fdo#105010] -> PASS
    - shard-kbl:          FAIL [fdo#105010] -> PASS

  * igt@tools_test@tools_test:
    - shard-snb:          SKIP [fdo#109271] -> PASS

  
#### Warnings ####

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-pwrite:
    - shard-hsw:          INCOMPLETE [fdo#103540] -> SKIP [fdo#109271]

  
  [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
  [fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
  [fdo#105010]: https://bugs.freedesktop.org/show_bug.cgi?id=105010
  [fdo#105106]: https://bugs.freedesktop.org/show_bug.cgi?id=105106
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
  [fdo#106641]: https://bugs.freedesktop.org/show_bug.cgi?id=106641
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147
  [fdo#108590]: https://bugs.freedesktop.org/show_bug.cgi?id=108590
  [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
  [fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109350]: https://bugs.freedesktop.org/show_bug.cgi?id=109350
  [fdo#109373]: https://bugs.freedesktop.org/show_bug.cgi?id=109373
  [fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
  [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321


Participating hosts (10 -> 5)
------------------------------

  Missing    (5): shard-skl pig-hsw-4770r pig-glk-j5005 shard-iclb pig-skl-6260u 


Build changes
-------------

    * IGT: IGT_4896 -> IGTPW_2684
    * Piglit: piglit_4509 -> None

  CI_DRM_5789: 93b3614e8c493860dc63c3028460efb02036c6ea @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_2684: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2684/
  IGT_4896: 0f9c061247fb7aba21c9459f19f437927a28f32c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2684/
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Re: [igt-dev] [PATCH v15 4/5] lib/i915: add gem_engine_topology library and for_each loop definition

[Andi Shyti]

Hi Tvrtko,

> > +static void init_engine(struct intel_execution_engine2 *e2, const char *name,
> > +			uint16_t class, uint16_t instance, uint64_t flags)
> 
> You are keeping name for the future? (It is unused at the moment.)

I simply forgot to remove it :)

> > +{
> > +	static const char *unknown_name = "unknown",
> > +			  *virtual_name = "virtual";
> 
> Unusual style but it is actually readable so I think I like it.

like the function below, it doesn't happen everyday to declare
variables/functions where the longest part of the line is the
type.

Need to come out with something :)

> > +
> > +	e2->class    = class;
> > +	e2->instance = instance;
> > +	e2->flags    = flags;
> > +
> > +	if (class < 0 && instance < 0) {
> > +		e2->name = virtual_name;
> > +	} else {
> > +		const struct intel_execution_engine2 *__e2;
> > +
> > +		__for_each_static_engine(__e2)
> > +			if (__e2->class == class && __e2->instance == instance)
> > +				break;
> > +
> > +		e2->name = __e2->name ? __e2->name : unknown_name;
> 
> I've now started to worry about how will CI/buglog handle us forgetting to
> expand the static list. (More than one subtest of a same name for
> "test-$engine_name" ones?) Do we want and igt_warn on unknown engines to
> make it more visible? Or even just crash?

Right! I guess just a warning would be nice, we can gather more
information from the logs about unkown engines... I guess.

> > +	if (nengines > I915_EXEC_RING_MASK + 1) {
> > +		engine_data.error = ret ? ret : -EINVAL;
> > +		return engine_data;
> > +	}
> 
> If we one day allow more engines in the map than the current limit?

for now this is a driver limitation and that's what igt checks. I
guess the right approach would be to update igt according to the
driver, right?

> It looks this would make the iterator not work. Was that the intention? What
> is the point of continuing then rather than just asserting?

yes, the iterator wouldn't loop and would provide a 0 size list
of engines. Asserting makes more sense.

> > +struct intel_execution_engine2
> > +	*intel_get_current_engine(struct intel_engine_data *ed)
> 
> Unusual coding style, we use:
> 
> type
> func(params)
> 
> or:
> 
> type func(params)

yes, I've seen it around, I personally don't like it, but I will
do it as the style is.

> > +	return (ed->n < ed->nengines) && !ed->error ?
> > +		&ed->engines[ed->n] :
> > +		NULL;
> 
> So could store the pointer to current engine in the iterator?

I still don't see the use of it, but of course, I can add it. It
might make more sense now that I have a "_current" and a "_next"
function.

> > @@ -434,7 +434,7 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
> >   	i = 0;
> >   	fd[0] = -1;
> > -	for_each_engine_class_instance(gem_fd, e_) {
> > +	for_each_context_engine(gem_fd, 0, e_) {
> 
> Make perf_pmu use for_each_physical_engine, apart from the test enumeration.

the reason I didn't replace it right away is that still to many
functions are using the current implementation of
for_each_physical_engine and I wanted to avoid, in this patchset,
touching too many files. I'm already changing more than I
wished.

that's why I called it:

   #define __for_each_physical_engine__(fd__, e__)

at the beginning I wanted to call it

   #define __DO_NOT_USE_for_each_physical_engine_YET__(fd__, e__) \

Besides, none of all those functions is using the new e2
structure.

If it's OK with you, I would swap everything to use either
__for_each_static_engine or the new for_each_physical_engine
right after this patch goes in.

Andi
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Re: [igt-dev] [PATCH v15 4/5] lib/i915: add gem_engine_topology library and for_each loop definition

[Tvrtko Ursulin]

On 22/03/2019 07:59, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-03-22 07:47:02)
>>
>> On 21/03/2019 16:05, Andi Shyti wrote:
>>> +{
>>> +     static const char *unknown_name = "unknown",
>>> +                       *virtual_name = "virtual";
>>
>> Unusual style but it is actually readable so I think I like it.
> 
> Bah, if I can't find a cino= setting, I'm not adopting it ;)
> 
>>> +
>>> +     e2->class    = class;
>>> +     e2->instance = instance;
>>> +     e2->flags    = flags;
>>> +
>>> +     if (class < 0 && instance < 0) {
>>> +             e2->name = virtual_name;
>>> +     } else {
>>> +             const struct intel_execution_engine2 *__e2;
>>> +
>>> +             __for_each_static_engine(__e2)
>>> +                     if (__e2->class == class && __e2->instance == instance)
>>> +                             break;
>>> +
>>> +             e2->name = __e2->name ? __e2->name : unknown_name;
>>
>> I've now started to worry about how will CI/buglog handle us forgetting
>> to expand the static list. (More than one subtest of a same name for
>> "test-$engine_name" ones?) Do we want and igt_warn on unknown engines to
>> make it more visible? Or even just crash?
> 
> Set flags to -1ull. That should cause EINVAL forever one hopes.
> 
> We shouldn't get any test (atm) with unknown as we only use the static
> table for test generation. For runtime test discovery, we can apply the
> filter of does this engine actually exist.

Yes I got confused.

>>> +void intel_next_engine(struct intel_engine_data *ed);
>>> +
>>> +#define IS_PHYSICAL_ENGINE(e2) ((e2->class >= 0) && (e2->instance >= 0))
>>
>> Chris, do you think this will be future proof enough?
> 
> At the moment, we've reserved just the one identifier for placeholders
> (class == I915_ENGINE_CLASS_INVALID). And I feel confident that should
> be enough.
> 
> The problem is if something else gave us multiple instances of a logical
> engine for which we have no means to determine the physical mapping,
> which is vvv
> 
>> I remembered how at one point I had "IS_PHYSICAL" as a flag in engine query.
>>
>> Or we make this here more explicit by being "IS_VIRTUAL" and invert the
>> test in the caller?
> 
> Aye. I think you are right here, and we need to put a caps field into
> the engine_data (filled in by i915_query for valid classes and default
> to !phys for invalid slots). A lot of the for_each_physical_engine()
> tests do not make sense if there is automagic engine mapping going on
> behind the scenes.

You are simply saying to move the "IS_PHYISICAL" test to init_engine 
here and store it in a flag per engine?

Regards,

Tvrtko


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Re: [igt-dev] [PATCH v15 4/5] lib/i915: add gem_engine_topology library and for_each loop definition

[Tvrtko Ursulin]

On 21/03/2019 16:05, Andi Shyti wrote:
> The gem_engine_topology library is a set of functions that
> interface with the query and getparam/setparam ioctls.
> 
> The library's access point is the 'intel_init_engine_list()'
> function that, everytime is called, generates the list of active
> engines and returns them in a 'struct intel_engine_data'. The
> structure contains only the engines that are actively present in
> the GPU.
> 
> The function can work in both the cases that the query and
> getparam ioctls are implemented or not by the running kernel. In
> case they are implemented, a query is made to the driver to fetch
> the list of active engines. In case they are not implemented, the
> list is taken from the 'intel_execution_engines2' array and
> stored only after checking their presence.
> 
> The gem_engine_topology library provides some iteration helpers:
> 
>   - intel_get_current_engine(): provides the current engine in the
>     iteration.
> 
>   - intel_get_current_physical_engine(): provides the current
>     physical engine, if the current engine is a virtual engine,
>     it moves forward until it finds a physical engine.
> 
>   - intel_next_engine() it just increments the counter so that it
>     points to the next engine.
> 
> Extend the 'for_each_engine_class_instance' so that it can loop
> using the new 'intel_init_engine_list()' and rename it to
> 'for_each_context_engine'.
> 
> Move '__for_each_engine_class_instance' to gem_engine_topology.h
> and rename it to '__for_each_static_engine'.
> 
> Update accordingly tests/perf_pmu.c to use correctly the new
> for_each lopps.
> 
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> ---
>   lib/Makefile.sources           |   2 +
>   lib/i915/gem_engine_topology.c | 222 +++++++++++++++++++++++++++++++++
>   lib/i915/gem_engine_topology.h |  63 ++++++++++
>   lib/igt.h                      |   1 +
>   lib/igt_gt.h                   |   8 +-
>   lib/meson.build                |   1 +
>   tests/perf_pmu.c               |  12 +-
>   7 files changed, 296 insertions(+), 13 deletions(-)
>   create mode 100644 lib/i915/gem_engine_topology.c
>   create mode 100644 lib/i915/gem_engine_topology.h
> 
> diff --git a/lib/Makefile.sources b/lib/Makefile.sources
> index cf2720981707..757bd7a17ebe 100644
> --- a/lib/Makefile.sources
> +++ b/lib/Makefile.sources
> @@ -13,6 +13,8 @@ lib_source_list =	 	\
>   	i915/gem_ring.c	\
>   	i915/gem_mman.c	\
>   	i915/gem_mman.h	\
> +	i915/gem_engine_topology.c	\
> +	i915/gem_engine_topology.h	\
>   	i915_3d.h		\
>   	i915_reg.h		\
>   	i915_pciids.h		\
> diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
> new file mode 100644
> index 000000000000..1144c49a1993
> --- /dev/null
> +++ b/lib/i915/gem_engine_topology.c
> @@ -0,0 +1,222 @@
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include "drmtest.h"
> +#include "ioctl_wrappers.h"
> +
> +#include "i915/gem_engine_topology.h"
> +
> +#define SIZEOF_CTX_PARAM	offsetof(struct i915_context_param_engines, \
> +					class_instance[I915_EXEC_RING_MASK + 1])
> +#define SIZEOF_QUERY		offsetof(struct drm_i915_query_engine_info, \
> +					engines[I915_EXEC_RING_MASK + 1])
> +
> +static int __gem_query(int fd, struct drm_i915_query *q)
> +{
> +	int err = 0;
> +
> +	if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
> +		err = -errno;
> +
> +	errno = 0;
> +	return err;
> +}
> +
> +static void gem_query(int fd, struct drm_i915_query *q)
> +{
> +	igt_assert_eq(__gem_query(fd, q), 0);
> +}
> +
> +static void query_engines(int fd,
> +			  struct drm_i915_query_engine_info *query_engines,
> +			  int length)
> +{
> +	struct drm_i915_query_item item = { };
> +	struct drm_i915_query query = { };
> +
> +	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
> +	query.items_ptr = to_user_pointer(&item);
> +	query.num_items = 1;
> +	item.length = length;
> +
> +	item.data_ptr = to_user_pointer(query_engines);
> +
> +	gem_query(fd, &query);
> +}
> +
> +static void ctx_map_engines(int fd, struct intel_engine_data *ed,
> +			    struct drm_i915_gem_context_param *ctx_param)
> +{
> +	struct i915_context_param_engines *ctx_engine =
> +			(struct i915_context_param_engines*) ctx_param->value;
> +	int i = 0;
> +
> +	for (typeof(ctx_engine->class_instance[0]) *p =
> +			&ctx_engine->class_instance[0];
> +						i < ed->nengines; i++, p++) {
> +		p->engine_class = ed->engines[i].class;
> +		p->engine_instance = ed->engines[i].instance;
> +	}
> +
> +	ctx_param->size = offsetof(typeof(*ctx_engine), class_instance[i]);
> +
> +	gem_context_set_param(fd, ctx_param);
> +}
> +
> +static void init_engine(struct intel_execution_engine2 *e2, const char *name,
> +			uint16_t class, uint16_t instance, uint64_t flags)
> +{
> +	static const char *unknown_name = "unknown",
> +			  *virtual_name = "virtual";
> +
> +	e2->class    = class;
> +	e2->instance = instance;
> +	e2->flags    = flags;
> +
> +	if (class < 0 && instance < 0) {
> +		e2->name = virtual_name;
> +	} else {
> +		const struct intel_execution_engine2 *__e2;
> +
> +		__for_each_static_engine(__e2)
> +			if (__e2->class == class && __e2->instance == instance)
> +				break;
> +
> +		e2->name = __e2->name ? __e2->name : unknown_name;
> +	}
> +}
> +
> +static void query_engine_list(int fd, struct intel_engine_data *ed)
> +{
> +	uint8_t query_buffer[SIZEOF_QUERY] = { };
> +	struct drm_i915_query_engine_info *query_engine =
> +			(struct drm_i915_query_engine_info *) query_buffer;
> +	int i;
> +
> +	query_engines(fd, query_engine, SIZEOF_QUERY);
> +
> +	for (i = 0; i < query_engine->num_engines; i++)
> +		init_engine(&ed->engines[i], NULL,
> +			   query_engine->engines[i].engine_class,
> +			   query_engine->engines[i].engine_instance, i);
> +
> +	ed->nengines = query_engine->num_engines;
> +}
> +
> +struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id)
> +{
> +	struct intel_engine_data engine_data = { };
> +	uint8_t buff[SIZEOF_CTX_PARAM] = { };
> +
> +	struct i915_context_param_engines *engines =
> +		(struct i915_context_param_engines *) buff;
> +
> +	struct drm_i915_gem_context_param param = {
> +		.param = I915_CONTEXT_PARAM_ENGINES,
> +		.ctx_id = ctx_id,
> +		.size = SIZEOF_CTX_PARAM,
> +		.value = to_user_pointer(engines),
> +	};
> +
> +	int i, ret;
> +	unsigned int nengines;
> +
> +	ret = __gem_context_get_param(fd, &param);
> +
> +	nengines = param.size > sizeof(struct i915_context_param_engines) ?
> +		   (param.size - sizeof(struct i915_context_param_engines)) /
> +		   sizeof(engines->class_instance[0]) :
> +		   0;
> +
> +	if (nengines > I915_EXEC_RING_MASK + 1) {
> +		engine_data.error = ret ? ret : -EINVAL;
> +		return engine_data;
> +	}
> +
> +	if (__gem_context_get_param(fd, &param)) {

Why are you calling get_param twice btw?

Regards,

Tvrtko

> +		/* if kernel does not support engine/context mapping */
> +		const struct intel_execution_engine2 *e2;
> +
> +		igt_debug("using pre-allocated engine list\n");
> +
> +		__for_each_static_engine(e2) {
> +			struct intel_execution_engine2 *__e2;
> +
> +			__e2 = &engine_data.engines[engine_data.nengines];
> +			__e2->flags = gem_class_instance_to_eb_flags(fd,
> +						e2->class, e2->instance);
> +
> +			if (!gem_has_ring(fd, __e2->flags))
> +				continue;
> +
> +			__e2->name = e2->name;
> +			__e2->instance = e2->instance;
> +			__e2->class = e2->class;
> +			engine_data.nengines++;
> +		}
> +
> +	} else if (!param.size) {
> +		/* else if context doesn't have mapped engines */
> +		query_engine_list(fd, &engine_data);
> +		ctx_map_engines(fd, &engine_data, &param);
> +
> +	} else {
> +		/* context has a list of mapped engines */
> +
> +		for (i = 0; i < nengines; i++)
> +			init_engine(&engine_data.engines[i], NULL,
> +				    engines->class_instance[i].engine_class,
> +				    engines->class_instance[i].engine_instance,
> +				    i);
> +
> +		engine_data.nengines = i;
> +	}
> +
> +	return engine_data;
> +}
> +
> +struct intel_execution_engine2
> +	*intel_get_current_engine(struct intel_engine_data *ed)
> +{
> +	return (ed->n < ed->nengines) && !ed->error ?
> +		&ed->engines[ed->n] :
> +		NULL;
> +}
> +
> +void intel_next_engine(struct intel_engine_data *ed)
> +{
> +	ed->n++;
> +}
> +
> +struct intel_execution_engine2
> +	*intel_get_current_physical_engine(struct intel_engine_data *ed)
> +{
> +	struct intel_execution_engine2 *e;
> +
> +	for (e = intel_get_current_engine(ed);
> +	     e && !IS_PHYSICAL_ENGINE(e);
> +	     intel_next_engine(ed))
> +		;
> +
> +	return e;
> +}
> diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
> new file mode 100644
> index 000000000000..f662a4601ecd
> --- /dev/null
> +++ b/lib/i915/gem_engine_topology.h
> @@ -0,0 +1,63 @@
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#ifndef GEM_ENGINE_TOPOLOGY_H
> +#define GEM_ENGINE_TOPOLOGY_H
> +
> +#include "igt_gt.h"
> +#include "i915_drm.h"
> +
> +struct intel_engine_data {
> +	uint32_t nengines;
> +	uint32_t n;
> +	int error;
> +	struct intel_execution_engine2 engines[I915_EXEC_RING_MASK + 1];
> +};
> +
> +struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id);
> +
> +/* iteration functions */
> +struct intel_execution_engine2
> +	*intel_get_current_engine(struct intel_engine_data *ed);
> +struct intel_execution_engine2
> +	*intel_get_current_physical_engine(struct intel_engine_data *ed);
> +void intel_next_engine(struct intel_engine_data *ed);
> +
> +#define IS_PHYSICAL_ENGINE(e2) ((e2->class >= 0) && (e2->instance >= 0))
> +
> +/* needs to replace "__for_each_engine_class_instance" when conflicts are fixed */
> +#define __for_each_static_engine(e__) \
> +	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
> +
> +#define for_each_context_engine(fd__, ctx__, e__) \
> +	for (struct intel_engine_data i__ = intel_init_engine_list(fd__, ctx__); \
> +	     ((e__) = intel_get_current_engine(&i__)); \
> +	     intel_next_engine(&i__))
> +
> +/* needs to replace "for_each_physical_engine" when conflicts are fixed */
> +#define __for_each_physical_engine__(fd__, e__) \
> +	for (struct intel_engine_data i__ = intel_init_engine_list(fd__, 0); \
> +	     ((e__) = intel_get_current_physical_engine(&i__)); \
> +	     intel_next_engine(&i__))
> +
> +#endif /* GEM_ENGINE_TOPOLOGY_H */
> diff --git a/lib/igt.h b/lib/igt.h
> index 6654a659c062..03f19ca2dfb6 100644
> --- a/lib/igt.h
> +++ b/lib/igt.h
> @@ -53,5 +53,6 @@
>   #include "media_spin.h"
>   #include "rendercopy.h"
>   #include "i915/gem_mman.h"
> +#include "i915/gem_engine_topology.h"
>   
>   #endif /* IGT_H */
> diff --git a/lib/igt_gt.h b/lib/igt_gt.h
> index 475c0b3c3cc6..2a7032d4b262 100644
> --- a/lib/igt_gt.h
> +++ b/lib/igt_gt.h
> @@ -95,6 +95,7 @@ extern const struct intel_execution_engine2 {
>   	const char *name;
>   	int class;
>   	int instance;
> +	uint64_t flags;
>   } intel_execution_engines2[];
>   
>   unsigned int
> @@ -114,11 +115,4 @@ void gem_require_engine(int gem_fd,
>   	igt_require(gem_has_engine(gem_fd, class, instance));
>   }
>   
> -#define __for_each_engine_class_instance(e__) \
> -	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
> -
> -#define for_each_engine_class_instance(fd__, e__) \
> -	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++) \
> -		for_if (gem_has_engine((fd__), (e__)->class, (e__)->instance))
> -
>   #endif /* IGT_GT_H */
> diff --git a/lib/meson.build b/lib/meson.build
> index 0eb5585d72b9..3cc52f97c8bf 100644
> --- a/lib/meson.build
> +++ b/lib/meson.build
> @@ -5,6 +5,7 @@ lib_sources = [
>   	'i915/gem_submission.c',
>   	'i915/gem_ring.c',
>   	'i915/gem_mman.c',
> +	'i915/gem_engine_topology.c',
>   	'igt_color_encoding.c',
>   	'igt_debugfs.c',
>   	'igt_device.c',
> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
> index 4f552bc2ae28..0e10bcfd1693 100644
> --- a/tests/perf_pmu.c
> +++ b/tests/perf_pmu.c
> @@ -434,7 +434,7 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
>   
>   	i = 0;
>   	fd[0] = -1;
> -	for_each_engine_class_instance(gem_fd, e_) {
> +	for_each_context_engine(gem_fd, 0, e_) {
>   		if (e == e_)
>   			busy_idx = i;
>   
> @@ -497,7 +497,7 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
>   	unsigned int idle_idx, i;
>   
>   	i = 0;
> -	for_each_engine_class_instance(gem_fd, e_) {
> +	for_each_context_engine(gem_fd, 0, e_) {
>   		if (e == e_)
>   			idle_idx = i;
>   		else if (spin)
> @@ -554,7 +554,7 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
>   	unsigned int i;
>   
>   	i = 0;
> -	for_each_engine_class_instance(gem_fd, e) {
> +	for_each_context_engine(gem_fd, 0, e) {
>   		if (spin)
>   			__submit_spin_batch(gem_fd, spin, e, 64);
>   		else
> @@ -1683,7 +1683,7 @@ igt_main
>   		igt_require_gem(fd);
>   		igt_require(i915_type_id() > 0);
>   
> -		for_each_engine_class_instance(fd, e)
> +		for_each_context_engine(fd, 0, e)
>   			num_engines++;
>   	}
>   
> @@ -1693,7 +1693,7 @@ igt_main
>   	igt_subtest("invalid-init")
>   		invalid_init();
>   
> -	__for_each_engine_class_instance(e) {
> +	__for_each_static_engine(e) {
>   		const unsigned int pct[] = { 2, 50, 98 };
>   
>   		/**
> @@ -1897,7 +1897,7 @@ igt_main
>   			gem_quiescent_gpu(fd);
>   		}
>   
> -		__for_each_engine_class_instance(e) {
> +		__for_each_static_engine(e) {
>   			igt_subtest_group {
>   				igt_fixture {
>   					gem_require_engine(render_fd,
> 
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Re: [igt-dev] [PATCH v15 4/5] lib/i915: add gem_engine_topology library and for_each loop definition

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-03-22 09:56:49)
> 
> On 22/03/2019 07:59, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-03-22 07:47:02)
> >>> +void intel_next_engine(struct intel_engine_data *ed);
> >>> +
> >>> +#define IS_PHYSICAL_ENGINE(e2) ((e2->class >= 0) && (e2->instance >= 0))
> >>
> >> Chris, do you think this will be future proof enough?
> > 
> > At the moment, we've reserved just the one identifier for placeholders
> > (class == I915_ENGINE_CLASS_INVALID). And I feel confident that should
> > be enough.
> > 
> > The problem is if something else gave us multiple instances of a logical
> > engine for which we have no means to determine the physical mapping,
> > which is vvv
> > 
> >> I remembered how at one point I had "IS_PHYSICAL" as a flag in engine query.
> >>
> >> Or we make this here more explicit by being "IS_VIRTUAL" and invert the
> >> test in the caller?
> > 
> > Aye. I think you are right here, and we need to put a caps field into
> > the engine_data (filled in by i915_query for valid classes and default
> > to !phys for invalid slots). A lot of the for_each_physical_engine()
> > tests do not make sense if there is automagic engine mapping going on
> > behind the scenes.
> 
> You are simply saying to move the "IS_PHYISICAL" test to init_engine 
> here and store it in a flag per engine?

Yes, with a view to supplying that information from the kernel if the
future landscape changes for the actual engines.
-Chris
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Re: [igt-dev] [PATCH v15 4/5] lib/i915: add gem_engine_topology library and for_each loop definition

[Andi Shyti]

> > > +
> > > +     e2->class    = class;
> > > +     e2->instance = instance;
> > > +     e2->flags    = flags;
> > > +
> > > +     if (class < 0 && instance < 0) {
> > > +             e2->name = virtual_name;
> > > +     } else {
> > > +             const struct intel_execution_engine2 *__e2;
> > > +
> > > +             __for_each_static_engine(__e2)
> > > +                     if (__e2->class == class && __e2->instance == instance)
> > > +                             break;
> > > +
> > > +             e2->name = __e2->name ? __e2->name : unknown_name;
> > 
> > I've now started to worry about how will CI/buglog handle us forgetting 
> > to expand the static list. (More than one subtest of a same name for 
> > "test-$engine_name" ones?) Do we want and igt_warn on unknown engines to 
> > make it more visible? Or even just crash?
> 
> Set flags to -1ull. That should cause EINVAL forever one hopes.
> 
> We shouldn't get any test (atm) with unknown as we only use the static
> table for test generation. For runtime test discovery, we can apply the
> filter of does this engine actually exist.

make sense, we could check it with gem_has_ring() and if it doesn't
exist print a warning and discard it.

> > I remembered how at one point I had "IS_PHYSICAL" as a flag in engine query.
> > 
> > Or we make this here more explicit by being "IS_VIRTUAL" and invert the 
> > test in the caller?
> 
> Aye. I think you are right here, and we need to put a caps field into
> the engine_data (filled in by i915_query for valid classes and default
> to !phys for invalid slots).

what do you mean exactly?

Andi
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Re: [igt-dev] [PATCH v15 4/5] lib/i915: add gem_engine_topology library and for_each loop definition

[Andi Shyti]

> > +	ret = __gem_context_get_param(fd, &param);
> > +
> > +	nengines = param.size > sizeof(struct i915_context_param_engines) ?
> > +		   (param.size - sizeof(struct i915_context_param_engines)) /
> > +		   sizeof(engines->class_instance[0]) :
> > +		   0;
> > +
> > +	if (nengines > I915_EXEC_RING_MASK + 1) {
> > +		engine_data.error = ret ? ret : -EINVAL;
> > +		return engine_data;
> > +	}
> > +
> > +	if (__gem_context_get_param(fd, &param)) {
> 
> Why are you calling get_param twice btw?

yes... please, don't bother... while moving things around I
forgot it. Thanks!

I told Chris yeterday, my distraction will kill me once :)

Andi
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Re: [igt-dev] [PATCH v15 4/5] lib/i915: add gem_engine_topology library and for_each loop definition

[Tvrtko Ursulin]

On 22/03/2019 09:51, Andi Shyti wrote:
> Hi Tvrtko,
> 
>>> +static void init_engine(struct intel_execution_engine2 *e2, const char *name,
>>> +			uint16_t class, uint16_t instance, uint64_t flags)
>>
>> You are keeping name for the future? (It is unused at the moment.)
> 
> I simply forgot to remove it :)
> 
>>> +{
>>> +	static const char *unknown_name = "unknown",
>>> +			  *virtual_name = "virtual";
>>
>> Unusual style but it is actually readable so I think I like it.
> 
> like the function below, it doesn't happen everyday to declare
> variables/functions where the longest part of the line is the
> type.
> 
> Need to come out with something :)
> 
>>> +
>>> +	e2->class    = class;
>>> +	e2->instance = instance;
>>> +	e2->flags    = flags;
>>> +
>>> +	if (class < 0 && instance < 0) {
>>> +		e2->name = virtual_name;
>>> +	} else {
>>> +		const struct intel_execution_engine2 *__e2;
>>> +
>>> +		__for_each_static_engine(__e2)
>>> +			if (__e2->class == class && __e2->instance == instance)
>>> +				break;
>>> +
>>> +		e2->name = __e2->name ? __e2->name : unknown_name;
>>
>> I've now started to worry about how will CI/buglog handle us forgetting to
>> expand the static list. (More than one subtest of a same name for
>> "test-$engine_name" ones?) Do we want and igt_warn on unknown engines to
>> make it more visible? Or even just crash?
> 
> Right! I guess just a warning would be nice, we can gather more
> information from the logs about unkown engines... I guess.
> 
>>> +	if (nengines > I915_EXEC_RING_MASK + 1) {
>>> +		engine_data.error = ret ? ret : -EINVAL;
>>> +		return engine_data;
>>> +	}
>>
>> If we one day allow more engines in the map than the current limit?
> 
> for now this is a driver limitation and that's what igt checks. I
> guess the right approach would be to update igt according to the
> driver, right?

Yes, I think old IGT on newer kernels is not something we need to 
support. Old kernel with new IGT we sometimes, like in this series do.

>> It looks this would make the iterator not work. Was that the intention? What
>> is the point of continuing then rather than just asserting?
> 
> yes, the iterator wouldn't loop and would provide a 0 size list
> of engines. Asserting makes more sense.

I think so, or igt_warn. But there is also the query which will fail if 
this limit is surpassed, due limited passed in buffer size.

Maybe assert in the query on -EINVAL and assert here instead of the 
error complication?

>>> +struct intel_execution_engine2
>>> +	*intel_get_current_engine(struct intel_engine_data *ed)
>>
>> Unusual coding style, we use:
>>
>> type
>> func(params)
>>
>> or:
>>
>> type func(params)
> 
> yes, I've seen it around, I personally don't like it, but I will
> do it as the style is.

Yep, have to comply with our style.

>>> +	return (ed->n < ed->nengines) && !ed->error ?
>>> +		&ed->engines[ed->n] :
>>> +		NULL;
>>
>> So could store the pointer to current engine in the iterator?
> 
> I still don't see the use of it, but of course, I can add it. It
> might make more sense now that I have a "_current" and a "_next"
> function.

That exactly why I mentioned it again, but it is of a minor importance 
as long as we are going with the explicit engine pointer in the for loop 
iterator. Do as you prefer.

>>> @@ -434,7 +434,7 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
>>>    	i = 0;
>>>    	fd[0] = -1;
>>> -	for_each_engine_class_instance(gem_fd, e_) {
>>> +	for_each_context_engine(gem_fd, 0, e_) {
>>
>> Make perf_pmu use for_each_physical_engine, apart from the test enumeration.
> 
> the reason I didn't replace it right away is that still to many
> functions are using the current implementation of
> for_each_physical_engine and I wanted to avoid, in this patchset,
> touching too many files. I'm already changing more than I
> wished.

It doesn't seem like a lot to me. And you have to change something so we 
know it works. :)

> that's why I called it:
> 
>     #define __for_each_physical_engine__(fd__, e__)
> 
> at the beginning I wanted to call it
> 
>     #define __DO_NOT_USE_for_each_physical_engine_YET__(fd__, e__) \
> 
> Besides, none of all those functions is using the new e2
> structure.
> 
> If it's OK with you, I would swap everything to use either
> __for_each_static_engine or the new for_each_physical_engine
> right after this patch goes in.

Oh I missed it is __for_each_physical_engine in this patch.

I don't like the intermediate step of perf_pmu using the context 
iterator. Make it use __for_each_physical_engine then for now? It's just 
a trivial find and replace.

Regards,

Tvrtko
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Re: [igt-dev] [PATCH v15 4/5] lib/i915: add gem_engine_topology library and for_each loop definition

[Tvrtko Ursulin]

On 21/03/2019 16:05, Andi Shyti wrote:
> The gem_engine_topology library is a set of functions that
> interface with the query and getparam/setparam ioctls.
> 
> The library's access point is the 'intel_init_engine_list()'
> function that, everytime is called, generates the list of active
> engines and returns them in a 'struct intel_engine_data'. The
> structure contains only the engines that are actively present in
> the GPU.
> 
> The function can work in both the cases that the query and
> getparam ioctls are implemented or not by the running kernel. In
> case they are implemented, a query is made to the driver to fetch
> the list of active engines. In case they are not implemented, the
> list is taken from the 'intel_execution_engines2' array and
> stored only after checking their presence.
> 
> The gem_engine_topology library provides some iteration helpers:
> 
>   - intel_get_current_engine(): provides the current engine in the
>     iteration.
> 
>   - intel_get_current_physical_engine(): provides the current
>     physical engine, if the current engine is a virtual engine,
>     it moves forward until it finds a physical engine.
> 
>   - intel_next_engine() it just increments the counter so that it
>     points to the next engine.
> 
> Extend the 'for_each_engine_class_instance' so that it can loop
> using the new 'intel_init_engine_list()' and rename it to
> 'for_each_context_engine'.
> 
> Move '__for_each_engine_class_instance' to gem_engine_topology.h
> and rename it to '__for_each_static_engine'.
> 
> Update accordingly tests/perf_pmu.c to use correctly the new
> for_each lopps.
> 
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> ---
>   lib/Makefile.sources           |   2 +
>   lib/i915/gem_engine_topology.c | 222 +++++++++++++++++++++++++++++++++
>   lib/i915/gem_engine_topology.h |  63 ++++++++++
>   lib/igt.h                      |   1 +
>   lib/igt_gt.h                   |   8 +-
>   lib/meson.build                |   1 +
>   tests/perf_pmu.c               |  12 +-
>   7 files changed, 296 insertions(+), 13 deletions(-)
>   create mode 100644 lib/i915/gem_engine_topology.c
>   create mode 100644 lib/i915/gem_engine_topology.h
> 
> diff --git a/lib/Makefile.sources b/lib/Makefile.sources
> index cf2720981707..757bd7a17ebe 100644
> --- a/lib/Makefile.sources
> +++ b/lib/Makefile.sources
> @@ -13,6 +13,8 @@ lib_source_list =	 	\
>   	i915/gem_ring.c	\
>   	i915/gem_mman.c	\
>   	i915/gem_mman.h	\
> +	i915/gem_engine_topology.c	\
> +	i915/gem_engine_topology.h	\
>   	i915_3d.h		\
>   	i915_reg.h		\
>   	i915_pciids.h		\
> diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
> new file mode 100644
> index 000000000000..1144c49a1993
> --- /dev/null
> +++ b/lib/i915/gem_engine_topology.c
> @@ -0,0 +1,222 @@
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include "drmtest.h"
> +#include "ioctl_wrappers.h"
> +
> +#include "i915/gem_engine_topology.h"
> +
> +#define SIZEOF_CTX_PARAM	offsetof(struct i915_context_param_engines, \
> +					class_instance[I915_EXEC_RING_MASK + 1])
> +#define SIZEOF_QUERY		offsetof(struct drm_i915_query_engine_info, \
> +					engines[I915_EXEC_RING_MASK + 1])
> +
> +static int __gem_query(int fd, struct drm_i915_query *q)
> +{
> +	int err = 0;
> +
> +	if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
> +		err = -errno;
> +
> +	errno = 0;
> +	return err;
> +}
> +
> +static void gem_query(int fd, struct drm_i915_query *q)
> +{
> +	igt_assert_eq(__gem_query(fd, q), 0);
> +}
> +
> +static void query_engines(int fd,
> +			  struct drm_i915_query_engine_info *query_engines,
> +			  int length)
> +{
> +	struct drm_i915_query_item item = { };
> +	struct drm_i915_query query = { };
> +
> +	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
> +	query.items_ptr = to_user_pointer(&item);
> +	query.num_items = 1;
> +	item.length = length;
> +
> +	item.data_ptr = to_user_pointer(query_engines);
> +
> +	gem_query(fd, &query);
> +}
> +
> +static void ctx_map_engines(int fd, struct intel_engine_data *ed,
> +			    struct drm_i915_gem_context_param *ctx_param)
> +{
> +	struct i915_context_param_engines *ctx_engine =
> +			(struct i915_context_param_engines*) ctx_param->value;
> +	int i = 0;
> +
> +	for (typeof(ctx_engine->class_instance[0]) *p =
> +			&ctx_engine->class_instance[0];
> +						i < ed->nengines; i++, p++) {
> +		p->engine_class = ed->engines[i].class;
> +		p->engine_instance = ed->engines[i].instance;
> +	}
> +
> +	ctx_param->size = offsetof(typeof(*ctx_engine), class_instance[i]);
> +
> +	gem_context_set_param(fd, ctx_param);
> +}
> +
> +static void init_engine(struct intel_execution_engine2 *e2, const char *name,
> +			uint16_t class, uint16_t instance, uint64_t flags)
> +{
> +	static const char *unknown_name = "unknown",
> +			  *virtual_name = "virtual";
> +
> +	e2->class    = class;
> +	e2->instance = instance;
> +	e2->flags    = flags;
> +
> +	if (class < 0 && instance < 0) {
> +		e2->name = virtual_name;
> +	} else {
> +		const struct intel_execution_engine2 *__e2;
> +
> +		__for_each_static_engine(__e2)
> +			if (__e2->class == class && __e2->instance == instance)
> +				break;
> +
> +		e2->name = __e2->name ? __e2->name : unknown_name;
> +	}
> +}
> +
> +static void query_engine_list(int fd, struct intel_engine_data *ed)
> +{
> +	uint8_t query_buffer[SIZEOF_QUERY] = { };
> +	struct drm_i915_query_engine_info *query_engine =
> +			(struct drm_i915_query_engine_info *) query_buffer;
> +	int i;
> +
> +	query_engines(fd, query_engine, SIZEOF_QUERY);
> +
> +	for (i = 0; i < query_engine->num_engines; i++)
> +		init_engine(&ed->engines[i], NULL,
> +			   query_engine->engines[i].engine_class,
> +			   query_engine->engines[i].engine_instance, i);
> +
> +	ed->nengines = query_engine->num_engines;
> +}
> +
> +struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id)
> +{
> +	struct intel_engine_data engine_data = { };
> +	uint8_t buff[SIZEOF_CTX_PARAM] = { };
> +
> +	struct i915_context_param_engines *engines =
> +		(struct i915_context_param_engines *) buff;
> +
> +	struct drm_i915_gem_context_param param = {
> +		.param = I915_CONTEXT_PARAM_ENGINES,
> +		.ctx_id = ctx_id,
> +		.size = SIZEOF_CTX_PARAM,
> +		.value = to_user_pointer(engines),
> +	};
> +
> +	int i, ret;
> +	unsigned int nengines;
> +
> +	ret = __gem_context_get_param(fd, &param);
> +
> +	nengines = param.size > sizeof(struct i915_context_param_engines) ?
> +		   (param.size - sizeof(struct i915_context_param_engines)) /
> +		   sizeof(engines->class_instance[0]) :
> +		   0;
> +
> +	if (nengines > I915_EXEC_RING_MASK + 1) {
> +		engine_data.error = ret ? ret : -EINVAL;
> +		return engine_data;
> +	}
> +
> +	if (__gem_context_get_param(fd, &param)) {
> +		/* if kernel does not support engine/context mapping */
> +		const struct intel_execution_engine2 *e2;
> +
> +		igt_debug("using pre-allocated engine list\n");
> +
> +		__for_each_static_engine(e2) {
> +			struct intel_execution_engine2 *__e2;
> +
> +			__e2 = &engine_data.engines[engine_data.nengines];
> +			__e2->flags = gem_class_instance_to_eb_flags(fd,
> +						e2->class, e2->instance);
> +
> +			if (!gem_has_ring(fd, __e2->flags))
> +				continue;
> +
> +			__e2->name = e2->name;
> +			__e2->instance = e2->instance;
> +			__e2->class = e2->class;
> +			engine_data.nengines++;
> +		}
> +
> +	} else if (!param.size) {
> +		/* else if context doesn't have mapped engines */
> +		query_engine_list(fd, &engine_data);
> +		ctx_map_engines(fd, &engine_data, &param);
> +
> +	} else {
> +		/* context has a list of mapped engines */
> +
> +		for (i = 0; i < nengines; i++)
> +			init_engine(&engine_data.engines[i], NULL,
> +				    engines->class_instance[i].engine_class,
> +				    engines->class_instance[i].engine_instance,
> +				    i);
> +
> +		engine_data.nengines = i;
> +	}
> +
> +	return engine_data;
> +}
> +
> +struct intel_execution_engine2
> +	*intel_get_current_engine(struct intel_engine_data *ed)
> +{
> +	return (ed->n < ed->nengines) && !ed->error ?
> +		&ed->engines[ed->n] :
> +		NULL;
> +}
> +
> +void intel_next_engine(struct intel_engine_data *ed)
> +{
> +	ed->n++;
> +}
> +
> +struct intel_execution_engine2
> +	*intel_get_current_physical_engine(struct intel_engine_data *ed)
> +{
> +	struct intel_execution_engine2 *e;
> +
> +	for (e = intel_get_current_engine(ed);
> +	     e && !IS_PHYSICAL_ENGINE(e);
> +	     intel_next_engine(ed))
> +		;
> +
> +	return e;
> +}
> diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
> new file mode 100644
> index 000000000000..f662a4601ecd
> --- /dev/null
> +++ b/lib/i915/gem_engine_topology.h
> @@ -0,0 +1,63 @@
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#ifndef GEM_ENGINE_TOPOLOGY_H
> +#define GEM_ENGINE_TOPOLOGY_H
> +
> +#include "igt_gt.h"
> +#include "i915_drm.h"
> +
> +struct intel_engine_data {
> +	uint32_t nengines;
> +	uint32_t n;
> +	int error;
> +	struct intel_execution_engine2 engines[I915_EXEC_RING_MASK + 1];
> +};
> +
> +struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id);
> +
> +/* iteration functions */
> +struct intel_execution_engine2
> +	*intel_get_current_engine(struct intel_engine_data *ed);
> +struct intel_execution_engine2
> +	*intel_get_current_physical_engine(struct intel_engine_data *ed);
> +void intel_next_engine(struct intel_engine_data *ed);
> +
> +#define IS_PHYSICAL_ENGINE(e2) ((e2->class >= 0) && (e2->instance >= 0))
> +
> +/* needs to replace "__for_each_engine_class_instance" when conflicts are fixed */
> +#define __for_each_static_engine(e__) \
> +	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
> +
> +#define for_each_context_engine(fd__, ctx__, e__) \
> +	for (struct intel_engine_data i__ = intel_init_engine_list(fd__, ctx__); \
> +	     ((e__) = intel_get_current_engine(&i__)); \
> +	     intel_next_engine(&i__))
> +
> +/* needs to replace "for_each_physical_engine" when conflicts are fixed */
> +#define __for_each_physical_engine__(fd__, e__) \
> +	for (struct intel_engine_data i__ = intel_init_engine_list(fd__, 0); \
> +	     ((e__) = intel_get_current_physical_engine(&i__)); \
> +	     intel_next_engine(&i__))
> +
> +#endif /* GEM_ENGINE_TOPOLOGY_H */
> diff --git a/lib/igt.h b/lib/igt.h
> index 6654a659c062..03f19ca2dfb6 100644
> --- a/lib/igt.h
> +++ b/lib/igt.h
> @@ -53,5 +53,6 @@
>   #include "media_spin.h"
>   #include "rendercopy.h"
>   #include "i915/gem_mman.h"
> +#include "i915/gem_engine_topology.h"
>   
>   #endif /* IGT_H */
> diff --git a/lib/igt_gt.h b/lib/igt_gt.h
> index 475c0b3c3cc6..2a7032d4b262 100644
> --- a/lib/igt_gt.h
> +++ b/lib/igt_gt.h
> @@ -95,6 +95,7 @@ extern const struct intel_execution_engine2 {
>   	const char *name;
>   	int class;
>   	int instance;
> +	uint64_t flags;
>   } intel_execution_engines2[];
>   
>   unsigned int
> @@ -114,11 +115,4 @@ void gem_require_engine(int gem_fd,
>   	igt_require(gem_has_engine(gem_fd, class, instance));
>   }
>   
> -#define __for_each_engine_class_instance(e__) \
> -	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
> -
> -#define for_each_engine_class_instance(fd__, e__) \
> -	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++) \
> -		for_if (gem_has_engine((fd__), (e__)->class, (e__)->instance))
> -
>   #endif /* IGT_GT_H */
> diff --git a/lib/meson.build b/lib/meson.build
> index 0eb5585d72b9..3cc52f97c8bf 100644
> --- a/lib/meson.build
> +++ b/lib/meson.build
> @@ -5,6 +5,7 @@ lib_sources = [
>   	'i915/gem_submission.c',
>   	'i915/gem_ring.c',
>   	'i915/gem_mman.c',
> +	'i915/gem_engine_topology.c',
>   	'igt_color_encoding.c',
>   	'igt_debugfs.c',
>   	'igt_device.c',
> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
> index 4f552bc2ae28..0e10bcfd1693 100644
> --- a/tests/perf_pmu.c
> +++ b/tests/perf_pmu.c
> @@ -434,7 +434,7 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
>   
>   	i = 0;
>   	fd[0] = -1;
> -	for_each_engine_class_instance(gem_fd, e_) {
> +	for_each_context_engine(gem_fd, 0, e_) {
>   		if (e == e_)
>   			busy_idx = i;

As mentioned on IRC this check needs to be converted into class and 
instance comparison.

>   
> @@ -497,7 +497,7 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
>   	unsigned int idle_idx, i;
>   
>   	i = 0;
> -	for_each_engine_class_instance(gem_fd, e_) {
> +	for_each_context_engine(gem_fd, 0, e_) {
>   		if (e == e_)
>   			idle_idx = i;

And this one.

>   		else if (spin)
> @@ -554,7 +554,7 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
>   	unsigned int i;
>   
>   	i = 0;
> -	for_each_engine_class_instance(gem_fd, e) {
> +	for_each_context_engine(gem_fd, 0, e) {
>   		if (spin)
>   			__submit_spin_batch(gem_fd, spin, e, 64);

And e2ring needs to be converted (or replaced) with e->flags.

One complication will be gem_can_store_dword in __spin_poll and another 
igt_spin_factory assumptions on engine flags. Which I think resolves 
only on gem_can_store_dword again.. Ugh.

Would this work:

igt_dummyload.c/emit_recursive_batch

  for_each_physical_engine
replace with:
   for_each_context_engine(opts->ctx)

ALL_ENGINES now means all context or all physical, depending on context.

Add a helper:

gem_engine_can_store_dword(class, instance)

In igt_spin_batch_factory:

Remove "if (opts->engine != ALL_ENGINES)" check, we'll try to handle it 
in emit_recursive batch.

In the latter change the else block of the first if-else to be something 
like:

// ioctl and stuff.. bummer... :(
ret = gem_context_get_engine_map_class_instance(fd, opts->ctx, 
opts->engine, &class, &instance);
if (ret) // error = no map = means opts->engine is eb flags
	check legacy gem_can_store_dword
else
	check using new gem_engine_can_store_dword(class, instance)

It is not pretty but unless I missed something it could work. :I

Regards,

Tvrtko

>   		else
> @@ -1683,7 +1683,7 @@ igt_main
>   		igt_require_gem(fd);
>   		igt_require(i915_type_id() > 0);
>   
> -		for_each_engine_class_instance(fd, e)
> +		for_each_context_engine(fd, 0, e)
>   			num_engines++;
>   	}
>   
> @@ -1693,7 +1693,7 @@ igt_main
>   	igt_subtest("invalid-init")
>   		invalid_init();
>   
> -	__for_each_engine_class_instance(e) {
> +	__for_each_static_engine(e) {
>   		const unsigned int pct[] = { 2, 50, 98 };
>   
>   		/**
> @@ -1897,7 +1897,7 @@ igt_main
>   			gem_quiescent_gpu(fd);
>   		}
>   
> -		__for_each_engine_class_instance(e) {
> +		__for_each_static_engine(e) {
>   			igt_subtest_group {
>   				igt_fixture {
>   					gem_require_engine(render_fd,
> 
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