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From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Subject: [PATCH 2/8] drm/i915: Move PSR mmio base to PSR struct
Date: Thu, 21 Mar 2019 11:01:37 -0700	[thread overview]
Message-ID: <20190321180143.22519-2-jose.souza@intel.com> (raw)
In-Reply-To: <20190321180143.22519-1-jose.souza@intel.com>

Lets keep all PSR variables packed in this struct.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h  |  3 +--
 drivers/gpu/drm/i915/i915_reg.h  | 12 ++++++------
 drivers/gpu/drm/i915/intel_psr.c |  2 +-
 3 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b6d674aa2786..5f60ad4d4296 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -496,6 +496,7 @@ struct i915_drrs {
 };
 
 struct i915_psr {
+	u32 mmio_base;
 	struct mutex lock;
 
 #define I915_PSR_DEBUG_MODE_MASK	0x0f
@@ -1535,8 +1536,6 @@ struct drm_i915_private {
 	/* MMIO base address for MIPI regs */
 	u32 mipi_mmio_base;
 
-	u32 psr_mmio_base;
-
 	u32 pps_mmio_base;
 
 	wait_queue_head_t gmbus_wait_queue;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d0ca6ef6d630..28728399e607 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4248,7 +4248,7 @@ enum {
 /* HSW+ eDP PSR registers */
 #define HSW_EDP_PSR_BASE	0x64800
 #define BDW_EDP_PSR_BASE	0x6f800
-#define EDP_PSR_CTL				_MMIO(dev_priv->psr_mmio_base + 0)
+#define EDP_PSR_CTL				_MMIO(dev_priv->psr.mmio_base + 0)
 #define   EDP_PSR_ENABLE			(1 << 31)
 #define   BDW_PSR_SINGLE_FRAME			(1 << 30)
 #define   EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK	(1 << 29) /* SW can't modify */
@@ -4281,16 +4281,16 @@ enum {
 #define   EDP_PSR_POST_EXIT			(1 << 1)
 #define   EDP_PSR_PRE_ENTRY			(1 << 0)
 
-#define EDP_PSR_AUX_CTL				_MMIO(dev_priv->psr_mmio_base + 0x10)
+#define EDP_PSR_AUX_CTL				_MMIO(dev_priv->psr.mmio_base + 0x10)
 #define   EDP_PSR_AUX_CTL_TIME_OUT_MASK		(3 << 26)
 #define   EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK	(0x1f << 20)
 #define   EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK	(0xf << 16)
 #define   EDP_PSR_AUX_CTL_ERROR_INTERRUPT	(1 << 11)
 #define   EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK	(0x7ff)
 
-#define EDP_PSR_AUX_DATA(i)			_MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
+#define EDP_PSR_AUX_DATA(i)			_MMIO(dev_priv->psr.mmio_base + 0x14 + (i) * 4) /* 5 registers */
 
-#define EDP_PSR_STATUS				_MMIO(dev_priv->psr_mmio_base + 0x40)
+#define EDP_PSR_STATUS				_MMIO(dev_priv->psr.mmio_base + 0x40)
 #define   EDP_PSR_STATUS_STATE_MASK		(7 << 29)
 #define   EDP_PSR_STATUS_STATE_SHIFT		29
 #define   EDP_PSR_STATUS_STATE_IDLE		(0 << 29)
@@ -4315,10 +4315,10 @@ enum {
 #define   EDP_PSR_STATUS_SENDING_TP1		(1 << 4)
 #define   EDP_PSR_STATUS_IDLE_MASK		0xf
 
-#define EDP_PSR_PERF_CNT		_MMIO(dev_priv->psr_mmio_base + 0x44)
+#define EDP_PSR_PERF_CNT		_MMIO(dev_priv->psr.mmio_base + 0x44)
 #define   EDP_PSR_PERF_CNT_MASK		0xffffff
 
-#define EDP_PSR_DEBUG				_MMIO(dev_priv->psr_mmio_base + 0x60) /* PSR_MASK on SKL+ */
+#define EDP_PSR_DEBUG				_MMIO(dev_priv->psr.mmio_base + 0x60) /* PSR_MASK on SKL+ */
 #define   EDP_PSR_DEBUG_MASK_MAX_SLEEP         (1 << 28)
 #define   EDP_PSR_DEBUG_MASK_LPSP              (1 << 27)
 #define   EDP_PSR_DEBUG_MASK_MEMUP             (1 << 26)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index dc9fdb515a54..3bf887ef8573 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -1135,7 +1135,7 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
 	if (!HAS_PSR(dev_priv))
 		return;
 
-	dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
+	dev_priv->psr.mmio_base = IS_HASWELL(dev_priv) ?
 		HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;
 
 	if (!dev_priv->psr.sink_support)
-- 
2.21.0

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  reply	other threads:[~2019-03-21 18:01 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-21 18:01 [PATCH 1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders José Roberto de Souza
2019-03-21 18:01 ` José Roberto de Souza [this message]
2019-03-21 18:01 ` [PATCH 3/8] drm/i915/psr: Make all PSR register relative to mmio base José Roberto de Souza
2019-03-22  9:15   ` Jani Nikula
2019-03-22 17:27     ` Dhinakaran Pandiyan
2019-03-26 20:44       ` Souza, Jose
2019-03-21 18:01 ` [PATCH 4/8] drm/i915/psr: Make mmio base relative to transcoder offset José Roberto de Souza
2019-03-21 18:01 ` [PATCH 5/8] drm/i915/psr: Initialize PSR mutex even when sink is not reliable José Roberto de Souza
2019-03-21 18:01 ` [PATCH 6/8] drm/i915/psr: Do not enable PSR in interlaced mode for all GENs José Roberto de Souza
2019-03-21 18:01 ` [PATCH 7/8] drm/i915: Remove unused VLV/CHV PSR registers José Roberto de Souza
2019-03-21 18:01 ` [PATCH 8/8] drm/i915/bdw+: Move misc display IRQ handling to it own function José Roberto de Souza
2019-03-21 18:20 ` [PATCH 1/8] drm/i915/psr: Remove partial PSR support on multiple transcoders Ville Syrjälä
2019-03-21 21:54 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/8] " Patchwork
2019-03-21 21:58 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-03-21 22:24 ` ✓ Fi.CI.BAT: success " Patchwork
2019-03-22 16:14 ` ✓ Fi.CI.IGT: " Patchwork

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