* [PATCH] drm/i915: set vdbox/vebox enable masks on all gens
@ 2019-03-21 22:02 Daniele Ceraolo Spurio
2019-03-21 22:11 ` Chris Wilson
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-03-21 22:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Eric Betancourt
The upcoming unified GuC FW will require us to send video engine enable
masks to GuC for its initialization.
For consistency, just set the runtime_info enable masks for all gens.
We'll then be able to directly use those in the GuC setup
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: John Spotswood <john.a.spotswood@intel.com>
Cc: Eric Betancourt <eric.s.betancourt@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/intel_device_info.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index eddf83807957..836184d6538e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -872,8 +872,14 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
unsigned int i;
u32 media_fuse;
- if (INTEL_GEN(dev_priv) < 11)
+ if (INTEL_GEN(dev_priv) < 11) {
+ RUNTIME_INFO(dev_priv)->vdbox_enable =
+ (info->engine_mask & GENMASK(VCS0 + I915_MAX_VCS, VCS0)) >> VCS0;
+
+ RUNTIME_INFO(dev_priv)->vebox_enable =
+ (info->engine_mask & GENMASK(VECS0 + I915_MAX_VECS, VECS0)) >> VECS0;
return;
+ }
media_fuse = ~I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE);
--
2.20.1
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^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH] drm/i915: set vdbox/vebox enable masks on all gens
2019-03-21 22:02 [PATCH] drm/i915: set vdbox/vebox enable masks on all gens Daniele Ceraolo Spurio
@ 2019-03-21 22:11 ` Chris Wilson
2019-03-21 22:14 ` Daniele Ceraolo Spurio
2019-03-21 22:14 ` Chris Wilson
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Chris Wilson @ 2019-03-21 22:11 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx; +Cc: Eric Betancourt
Quoting Daniele Ceraolo Spurio (2019-03-21 22:02:06)
> The upcoming unified GuC FW will require us to send video engine enable
> masks to GuC for its initialization.
>
> For consistency, just set the runtime_info enable masks for all gens.
> We'll then be able to directly use those in the GuC setup
>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: John Spotswood <john.a.spotswood@intel.com>
> Cc: Eric Betancourt <eric.s.betancourt@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> ---
> drivers/gpu/drm/i915/intel_device_info.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index eddf83807957..836184d6538e 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -872,8 +872,14 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
> unsigned int i;
> u32 media_fuse;
>
> - if (INTEL_GEN(dev_priv) < 11)
> + if (INTEL_GEN(dev_priv) < 11) {
> + RUNTIME_INFO(dev_priv)->vdbox_enable =
> + (info->engine_mask & GENMASK(VCS0 + I915_MAX_VCS, VCS0)) >> VCS0;
I915_MAX_V[E]CS is actually number of VCS, so this needs -1 on the high bit
as it is inclusive.
-Chris
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^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH] drm/i915: set vdbox/vebox enable masks on all gens
2019-03-21 22:11 ` Chris Wilson
@ 2019-03-21 22:14 ` Daniele Ceraolo Spurio
2019-03-21 22:39 ` Chris Wilson
0 siblings, 1 reply; 8+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-03-21 22:14 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Eric Betancourt
On 3/21/19 3:11 PM, Chris Wilson wrote:
> Quoting Daniele Ceraolo Spurio (2019-03-21 22:02:06)
>> The upcoming unified GuC FW will require us to send video engine enable
>> masks to GuC for its initialization.
>>
>> For consistency, just set the runtime_info enable masks for all gens.
>> We'll then be able to directly use those in the GuC setup
>>
>> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
>> Cc: John Spotswood <john.a.spotswood@intel.com>
>> Cc: Eric Betancourt <eric.s.betancourt@intel.com>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_device_info.c | 8 +++++++-
>> 1 file changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>> index eddf83807957..836184d6538e 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -872,8 +872,14 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
>> unsigned int i;
>> u32 media_fuse;
>>
>> - if (INTEL_GEN(dev_priv) < 11)
>> + if (INTEL_GEN(dev_priv) < 11) {
>> + RUNTIME_INFO(dev_priv)->vdbox_enable =
>> + (info->engine_mask & GENMASK(VCS0 + I915_MAX_VCS, VCS0)) >> VCS0;
D'oh!
Thanks for catching this, GuC just ignores the higher bits and didn't
complain, so I missed it.
Daniele
>
> I915_MAX_V[E]CS is actually number of VCS, so this needs -1 on the high bit
> as it is inclusive.
> -Chris
>
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH] drm/i915: set vdbox/vebox enable masks on all gens
2019-03-21 22:14 ` Daniele Ceraolo Spurio
@ 2019-03-21 22:39 ` Chris Wilson
2019-03-21 22:43 ` Daniele Ceraolo Spurio
0 siblings, 1 reply; 8+ messages in thread
From: Chris Wilson @ 2019-03-21 22:39 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx; +Cc: Eric Betancourt
Quoting Daniele Ceraolo Spurio (2019-03-21 22:14:20)
>
>
> On 3/21/19 3:11 PM, Chris Wilson wrote:
> > Quoting Daniele Ceraolo Spurio (2019-03-21 22:02:06)
> >> The upcoming unified GuC FW will require us to send video engine enable
> >> masks to GuC for its initialization.
> >>
> >> For consistency, just set the runtime_info enable masks for all gens.
> >> We'll then be able to directly use those in the GuC setup
> >>
> >> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> >> Cc: John Spotswood <john.a.spotswood@intel.com>
> >> Cc: Eric Betancourt <eric.s.betancourt@intel.com>
> >> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/intel_device_info.c | 8 +++++++-
> >> 1 file changed, 7 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> >> index eddf83807957..836184d6538e 100644
> >> --- a/drivers/gpu/drm/i915/intel_device_info.c
> >> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> >> @@ -872,8 +872,14 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
> >> unsigned int i;
> >> u32 media_fuse;
> >>
> >> - if (INTEL_GEN(dev_priv) < 11)
> >> + if (INTEL_GEN(dev_priv) < 11) {
> >> + RUNTIME_INFO(dev_priv)->vdbox_enable =
> >> + (info->engine_mask & GENMASK(VCS0 + I915_MAX_VCS, VCS0)) >> VCS0;
>
> D'oh!
>
> Thanks for catching this, GuC just ignores the higher bits and didn't
> complain, so I missed it.
Having demonstrated it's a simple mapping, do we need to store it
separately?
#define VDBOX_MASK(info) \
(((info)->engine_mask & \
GENMASK(VCS0 + I915_MAX_VCS - 1, VCS0)) >> VCS0)
etc
-Chris
_______________________________________________
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH] drm/i915: set vdbox/vebox enable masks on all gens
2019-03-21 22:39 ` Chris Wilson
@ 2019-03-21 22:43 ` Daniele Ceraolo Spurio
0 siblings, 0 replies; 8+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-03-21 22:43 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Eric Betancourt
On 3/21/19 3:39 PM, Chris Wilson wrote:
> Quoting Daniele Ceraolo Spurio (2019-03-21 22:14:20)
>>
>>
>> On 3/21/19 3:11 PM, Chris Wilson wrote:
>>> Quoting Daniele Ceraolo Spurio (2019-03-21 22:02:06)
>>>> The upcoming unified GuC FW will require us to send video engine enable
>>>> masks to GuC for its initialization.
>>>>
>>>> For consistency, just set the runtime_info enable masks for all gens.
>>>> We'll then be able to directly use those in the GuC setup
>>>>
>>>> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
>>>> Cc: John Spotswood <john.a.spotswood@intel.com>
>>>> Cc: Eric Betancourt <eric.s.betancourt@intel.com>
>>>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/intel_device_info.c | 8 +++++++-
>>>> 1 file changed, 7 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>>>> index eddf83807957..836184d6538e 100644
>>>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>>>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>>>> @@ -872,8 +872,14 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
>>>> unsigned int i;
>>>> u32 media_fuse;
>>>>
>>>> - if (INTEL_GEN(dev_priv) < 11)
>>>> + if (INTEL_GEN(dev_priv) < 11) {
>>>> + RUNTIME_INFO(dev_priv)->vdbox_enable =
>>>> + (info->engine_mask & GENMASK(VCS0 + I915_MAX_VCS, VCS0)) >> VCS0;
>>
>> D'oh!
>>
>> Thanks for catching this, GuC just ignores the higher bits and didn't
>> complain, so I missed it.
>
> Having demonstrated it's a simple mapping, do we need to store it
> separately?
>
> #define VDBOX_MASK(info) \
> (((info)->engine_mask & \
> GENMASK(VCS0 + I915_MAX_VCS - 1, VCS0)) >> VCS0)
>
LGTM, will do the changes.
Daniele
> etc
> -Chris
>
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915: set vdbox/vebox enable masks on all gens
2019-03-21 22:02 [PATCH] drm/i915: set vdbox/vebox enable masks on all gens Daniele Ceraolo Spurio
2019-03-21 22:11 ` Chris Wilson
@ 2019-03-21 22:14 ` Chris Wilson
2019-03-22 1:33 ` ✓ Fi.CI.BAT: success for " Patchwork
2019-03-22 18:28 ` ✓ Fi.CI.IGT: " Patchwork
3 siblings, 0 replies; 8+ messages in thread
From: Chris Wilson @ 2019-03-21 22:14 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx; +Cc: Eric Betancourt
Quoting Daniele Ceraolo Spurio (2019-03-21 22:02:06)
> The upcoming unified GuC FW will require us to send video engine enable
> masks to GuC for its initialization.
>
> For consistency, just set the runtime_info enable masks for all gens.
> We'll then be able to directly use those in the GuC setup
>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: John Spotswood <john.a.spotswood@intel.com>
> Cc: Eric Betancourt <eric.s.betancourt@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> ---
> drivers/gpu/drm/i915/intel_device_info.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index eddf83807957..836184d6538e 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -872,8 +872,14 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
> unsigned int i;
> u32 media_fuse;
>
> - if (INTEL_GEN(dev_priv) < 11)
> + if (INTEL_GEN(dev_priv) < 11) {
> + RUNTIME_INFO(dev_priv)->vdbox_enable =
> + (info->engine_mask & GENMASK(VCS0 + I915_MAX_VCS, VCS0)) >> VCS0;
> +
> + RUNTIME_INFO(dev_priv)->vebox_enable =
> + (info->engine_mask & GENMASK(VECS0 + I915_MAX_VECS, VECS0)) >> VECS0;
Should we do this unconditionally as it seems reasonably
self-desciptive, with a follow to say that on gen11+ we can query the hw
fuses to see what is actually available?
-Chris
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^ permalink raw reply [flat|nested] 8+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915: set vdbox/vebox enable masks on all gens
2019-03-21 22:02 [PATCH] drm/i915: set vdbox/vebox enable masks on all gens Daniele Ceraolo Spurio
2019-03-21 22:11 ` Chris Wilson
2019-03-21 22:14 ` Chris Wilson
@ 2019-03-22 1:33 ` Patchwork
2019-03-22 18:28 ` ✓ Fi.CI.IGT: " Patchwork
3 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2019-03-22 1:33 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: set vdbox/vebox enable masks on all gens
URL : https://patchwork.freedesktop.org/series/58381/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5791 -> Patchwork_12561
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/58381/revisions/1/mbox/
Known issues
------------
Here are the changes found in Patchwork_12561 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_basic@basic-bsd2:
- fi-kbl-7500u: NOTRUN -> SKIP [fdo#109271] +9
* igt@gem_exec_basic@readonly-bsd1:
- fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] +57
* igt@i915_selftest@live_uncore:
- fi-ivb-3770: PASS -> DMESG-FAIL [fdo#110210]
* igt@kms_busy@basic-flip-c:
- fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: NOTRUN -> DMESG-WARN [fdo#103841]
* igt@kms_psr@primary_mmap_gtt:
- fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +27
* igt@runner@aborted:
- fi-kbl-7500u: NOTRUN -> FAIL [fdo#103841]
- fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720]
#### Possible fixes ####
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
[fdo#103841]: https://bugs.freedesktop.org/show_bug.cgi?id=103841
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
[fdo#110210]: https://bugs.freedesktop.org/show_bug.cgi?id=110210
Participating hosts (44 -> 38)
------------------------------
Additional (2): fi-snb-2520m fi-kbl-7500u
Missing (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_5791 -> Patchwork_12561
CI_DRM_5791: 3b6d09692ea282a3487bdf972a068d312a67ca00 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4897: e12d69496a6bef09ac6c0f792b8d60a65cf5e0bf @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12561: d6b348da5ebc4a294c2910573fa3659716c25ecb @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d6b348da5ebc drm/i915: set vdbox/vebox enable masks on all gens
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12561/
_______________________________________________
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^ permalink raw reply [flat|nested] 8+ messages in thread* ✓ Fi.CI.IGT: success for drm/i915: set vdbox/vebox enable masks on all gens
2019-03-21 22:02 [PATCH] drm/i915: set vdbox/vebox enable masks on all gens Daniele Ceraolo Spurio
` (2 preceding siblings ...)
2019-03-22 1:33 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2019-03-22 18:28 ` Patchwork
3 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2019-03-22 18:28 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: set vdbox/vebox enable masks on all gens
URL : https://patchwork.freedesktop.org/series/58381/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5791_full -> Patchwork_12561_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_12561_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@read_all_entries_display_off:
- shard-skl: PASS -> INCOMPLETE [fdo#104108]
* igt@gem_eio@suspend:
- shard-kbl: PASS -> DMESG-WARN [fdo#103313] / [fdo#103558] / [fdo#105079] / [fdo#105602]
* igt@gem_pwrite@big-cpu-fbr:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +142
* igt@i915_hangman@error-state-capture-bsd2:
- shard-iclb: NOTRUN -> SKIP [fdo#109276]
* igt@i915_suspend@sysfs-reader:
- shard-kbl: PASS -> INCOMPLETE [fdo#103665]
* igt@kms_atomic_transition@plane-all-modeset-transition:
- shard-apl: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#110222] +2
* igt@kms_busy@extended-modeset-hang-newfb-render-c:
- shard-apl: NOTRUN -> DMESG-WARN [fdo#110222]
* igt@kms_busy@extended-modeset-hang-oldfb-render-d:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +11
* igt@kms_busy@extended-modeset-hang-oldfb-render-f:
- shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +3
* igt@kms_busy@extended-pageflip-hang-newfb-render-c:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +6
* igt@kms_color@pipe-a-legacy-gamma:
- shard-kbl: PASS -> DMESG-WARN [fdo#103558] / [fdo#105602] +20
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-iclb: PASS -> FAIL [fdo#103355]
* igt@kms_flip@2x-flip-vs-suspend-interruptible:
- shard-glk: PASS -> INCOMPLETE [fdo#103359] / [k.org#198133]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render:
- shard-kbl: PASS -> DMESG-WARN [fdo#103313] / [fdo#103558] / [fdo#105602] +5
* igt@kms_frontbuffer_tracking@fbc-1p-rte:
- shard-iclb: PASS -> FAIL [fdo#103167] / [fdo#105682]
- shard-kbl: PASS -> DMESG-WARN [fdo#103313] / [fdo#103558]
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-pwrite:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +36
* igt@kms_frontbuffer_tracking@fbc-stridechange:
- shard-iclb: PASS -> FAIL [fdo#105682] / [fdo#108040]
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite:
- shard-iclb: PASS -> FAIL [fdo#109247] +33
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite:
- shard-iclb: PASS -> FAIL [fdo#103167] +3
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +28
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render:
- shard-iclb: PASS -> FAIL [fdo#105682] / [fdo#109247] +1
* igt@kms_frontbuffer_tracking@fbcpsr-stridechange:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] +8
- shard-skl: NOTRUN -> FAIL [fdo#105683]
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-iclb: NOTRUN -> SKIP [fdo#109280]
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +2
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-glk: PASS -> FAIL [fdo#108145] +1
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145]
* igt@kms_plane_scaling@pipe-a-scaler-with-rotation:
- shard-glk: PASS -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_psr@primary_page_flip:
- shard-iclb: PASS -> FAIL [fdo#107383] / [fdo#110215] +2
* igt@kms_psr@psr2_basic:
- shard-iclb: PASS -> SKIP [fdo#109441] +2
* igt@kms_rotation_crc@multiplane-rotation:
- shard-kbl: NOTRUN -> INCOMPLETE [fdo#103665]
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-kbl: PASS -> DMESG-FAIL [fdo#105763]
* igt@kms_universal_plane@universal-plane-gen9-features-pipe-d:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
#### Possible fixes ####
* igt@gem_tiled_pread_pwrite:
- shard-iclb: TIMEOUT [fdo#109673] -> PASS
* igt@i915_pm_rpm@i2c:
- shard-iclb: DMESG-WARN [fdo#109982] -> PASS
* igt@i915_pm_rpm@reg-read-ioctl:
- shard-skl: INCOMPLETE [fdo#107807] -> PASS
* igt@i915_suspend@fence-restore-untiled:
- shard-apl: DMESG-WARN [fdo#108566] -> PASS +1
* igt@kms_busy@extended-pageflip-hang-newfb-render-c:
- shard-apl: DMESG-WARN [fdo#110222] -> PASS
* igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
- shard-glk: FAIL [fdo#103060] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-skl: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-iclb: FAIL [fdo#103167] -> PASS +6
* igt@kms_frontbuffer_tracking@fbc-1p-rte:
- shard-skl: FAIL [fdo#105682] -> PASS
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt:
- shard-iclb: FAIL [fdo#109247] -> PASS +18
* {igt@kms_plane@pixel-format-pipe-c-planes-source-clamping}:
- shard-glk: SKIP [fdo#109271] -> PASS +1
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: FAIL [fdo#108145] -> PASS
* igt@kms_plane_scaling@pipe-b-scaler-with-rotation:
- shard-glk: SKIP [fdo#109271] / [fdo#109278] -> PASS
* igt@kms_psr2_su@page_flip:
- shard-iclb: SKIP [fdo#109642] -> PASS
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: SKIP [fdo#109441] -> PASS +2
* igt@kms_psr@sprite_mmap_cpu:
- shard-iclb: FAIL [fdo#107383] / [fdo#110215] -> PASS +1
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: FAIL [fdo#109016] -> PASS
* igt@kms_setmode@basic:
- shard-apl: FAIL [fdo#99912] -> PASS
- shard-kbl: FAIL [fdo#99912] -> PASS
* igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm:
- shard-apl: FAIL [fdo#104894] -> PASS
#### Warnings ####
* igt@kms_available_modes_crc@available_mode_test_crc:
- shard-kbl: FAIL [fdo#106641] -> DMESG-FAIL [fdo#103558] / [fdo#105602] / [fdo#106641]
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: SKIP [fdo#109349] -> FAIL [fdo#109358]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103313]: https://bugs.freedesktop.org/show_bug.cgi?id=103313
[fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
[fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
[fdo#105683]: https://bugs.freedesktop.org/show_bug.cgi?id=105683
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#106641]: https://bugs.freedesktop.org/show_bug.cgi?id=106641
[fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
[fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
[fdo#109247]: https://bugs.freedesktop.org/show_bug.cgi?id=109247
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109358]: https://bugs.freedesktop.org/show_bug.cgi?id=109358
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
[fdo#109982]: https://bugs.freedesktop.org/show_bug.cgi?id=109982
[fdo#110215]: https://bugs.freedesktop.org/show_bug.cgi?id=110215
[fdo#110222]: https://bugs.freedesktop.org/show_bug.cgi?id=110222
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (10 -> 9)
------------------------------
Missing (1): shard-hsw
Build changes
-------------
* Linux: CI_DRM_5791 -> Patchwork_12561
CI_DRM_5791: 3b6d09692ea282a3487bdf972a068d312a67ca00 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4897: e12d69496a6bef09ac6c0f792b8d60a65cf5e0bf @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12561: d6b348da5ebc4a294c2910573fa3659716c25ecb @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12561/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2019-03-22 18:28 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-03-21 22:02 [PATCH] drm/i915: set vdbox/vebox enable masks on all gens Daniele Ceraolo Spurio
2019-03-21 22:11 ` Chris Wilson
2019-03-21 22:14 ` Daniele Ceraolo Spurio
2019-03-21 22:39 ` Chris Wilson
2019-03-21 22:43 ` Daniele Ceraolo Spurio
2019-03-21 22:14 ` Chris Wilson
2019-03-22 1:33 ` ✓ Fi.CI.BAT: success for " Patchwork
2019-03-22 18:28 ` ✓ Fi.CI.IGT: " Patchwork
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