[igt-dev] [RFT v4 1/6] lib/i915/gem_mman: Remove static variables

[igt-dev] [RFT v4 1/6] lib/i915/gem_mman: Remove static variables

[Antonio Argenziano]

Since the IOCTL wrappers implemented in gem_mman should only be called
once at fixture time there is no need to save the state across multiple
calls.

Signed-off-by: Antonio Argenziano <antonio.argenziano@intel.com>
Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/i915/gem_mman.c | 61 +++++++++++++++++++++------------------------
 1 file changed, 28 insertions(+), 33 deletions(-)

diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
index 3cf9a6bb..b43ccd95 100644
--- a/lib/i915/gem_mman.c
+++ b/lib/i915/gem_mman.c
@@ -103,40 +103,35 @@ int gem_munmap(void *ptr, uint64_t size)
 
 bool gem_mmap__has_wc(int fd)
 {
-	static int has_wc = -1;
-
-	if (has_wc == -1) {
-		struct drm_i915_getparam gp;
-		int mmap_version = -1;
-		int gtt_version = -1;
-
-		has_wc = 0;
-
-		memset(&gp, 0, sizeof(gp));
-		gp.param = I915_PARAM_MMAP_GTT_VERSION;
-		gp.value = &gtt_version;
-		ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
-
-		memset(&gp, 0, sizeof(gp));
-		gp.param = I915_PARAM_MMAP_VERSION;
-		gp.value = &mmap_version;
-		ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
-
-		/* Do we have the new mmap_ioctl with DOMAIN_WC? */
-		if (mmap_version >= 1 && gtt_version >= 2) {
-			struct drm_i915_gem_mmap arg;
-
-			/* Does this device support wc-mmaps ? */
-			memset(&arg, 0, sizeof(arg));
-			arg.handle = gem_create(fd, 4096);
-			arg.offset = 0;
-			arg.size = 4096;
-			arg.flags = I915_MMAP_WC;
-			has_wc = igt_ioctl(fd, DRM_IOCTL_I915_GEM_MMAP, &arg) == 0;
-			gem_close(fd, arg.handle);
-		}
-		errno = 0;
+	struct drm_i915_getparam gp;
+	int mmap_version = -1;
+	int gtt_version = -1;
+	int has_wc = 0;
+
+	memset(&gp, 0, sizeof(gp));
+	gp.param = I915_PARAM_MMAP_GTT_VERSION;
+	gp.value = &gtt_version;
+	ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
+
+	memset(&gp, 0, sizeof(gp));
+	gp.param = I915_PARAM_MMAP_VERSION;
+	gp.value = &mmap_version;
+	ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
+
+	/* Do we have the new mmap_ioctl with DOMAIN_WC? */
+	if (mmap_version >= 1 && gtt_version >= 2) {
+		struct drm_i915_gem_mmap arg;
+
+		/* Does this device support wc-mmaps ? */
+		memset(&arg, 0, sizeof(arg));
+		arg.handle = gem_create(fd, 4096);
+		arg.offset = 0;
+		arg.size = 4096;
+		arg.flags = I915_MMAP_WC;
+		has_wc = igt_ioctl(fd, DRM_IOCTL_I915_GEM_MMAP, &arg) == 0;
+		gem_close(fd, arg.handle);
 	}
+	errno = 0;
 
 	return has_wc > 0;
 }
-- 
2.20.1

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[igt-dev] [RFT v4 2/6] lib/i915: Add mmap_offset support

[Antonio Argenziano]

From: "Kalamarz, Lukasz" <lukasz.kalamarz@intel.com>

With recently proposed changes, IGT need to start supporting new
way of mmaping object, which will be used from now by default.
This patch modify gem_mmap_wc and gem_mmap functions to be
in sync with those changes.

v2:
	- Fix IOCTL number. (Daniele)
	- Move wrappers to new file. (Chris)

v3:
	- Use mmap IOCTL for lower level wrappers. (Chris)

v4:
	- Don't use static variables. (Chris)
	- Remember gem_ prefix. (Chris)

Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Cc: Janulgue Abdiel <abdiel.janulgue@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Michal Winiarski <michal.winiarski@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Daniele Spurio Ceraolo <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Antonio Argenziano <antonio.argenziano@intel.com>
---
 lib/i915/gem_mman.c | 118 ++++++++++++++++++++++++++++++++++++--------
 lib/i915/gem_mman.h |  33 +++++++++++++
 2 files changed, 130 insertions(+), 21 deletions(-)

diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
index b43ccd95..429de912 100644
--- a/lib/i915/gem_mman.c
+++ b/lib/i915/gem_mman.c
@@ -103,34 +103,49 @@ int gem_munmap(void *ptr, uint64_t size)
 
 bool gem_mmap__has_wc(int fd)
 {
-	struct drm_i915_getparam gp;
-	int mmap_version = -1;
-	int gtt_version = -1;
 	int has_wc = 0;
 
-	memset(&gp, 0, sizeof(gp));
-	gp.param = I915_PARAM_MMAP_GTT_VERSION;
-	gp.value = &gtt_version;
-	ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
-
-	memset(&gp, 0, sizeof(gp));
-	gp.param = I915_PARAM_MMAP_VERSION;
-	gp.value = &mmap_version;
-	ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
-
-	/* Do we have the new mmap_ioctl with DOMAIN_WC? */
-	if (mmap_version >= 1 && gtt_version >= 2) {
-		struct drm_i915_gem_mmap arg;
+	/* Do we have the new mmap_offset ioctl? */
+	if (gem_has_mmap_offset(fd)) {
+		struct local_drm_i915_gem_mmap_offset arg;
 
 		/* Does this device support wc-mmaps ? */
 		memset(&arg, 0, sizeof(arg));
 		arg.handle = gem_create(fd, 4096);
 		arg.offset = 0;
-		arg.size = 4096;
-		arg.flags = I915_MMAP_WC;
-		has_wc = igt_ioctl(fd, DRM_IOCTL_I915_GEM_MMAP, &arg) == 0;
+		arg.flags = LOCAL_I915_MMAP_OFFSET_WC;
+		has_wc = igt_ioctl(fd, LOCAL_DRM_IOCTL_I915_GEM_MMAP_OFFSET, &arg) == 0;
 		gem_close(fd, arg.handle);
+	} else {
+		struct drm_i915_getparam gp;
+		int mmap_version = -1;
+		int gtt_version = -1;
+
+		memset(&gp, 0, sizeof(gp));
+		gp.param = I915_PARAM_MMAP_GTT_VERSION;
+		gp.value = &gtt_version;
+		ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
+
+		memset(&gp, 0, sizeof(gp));
+		gp.param = I915_PARAM_MMAP_VERSION;
+		gp.value = &mmap_version;
+		ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
+
+		/* Do we have the mmap_ioctl with DOMAIN_WC? */
+		if (mmap_version >= 1 && gtt_version >= 2) {
+			struct drm_i915_gem_mmap arg;
+
+			/* Does this device support wc-mmaps ? */
+			memset(&arg, 0, sizeof(arg));
+			arg.handle = gem_create(fd, 4096);
+			arg.offset = 0;
+			arg.size = 4096;
+			arg.flags = I915_MMAP_WC;
+			has_wc = igt_ioctl(fd, DRM_IOCTL_I915_GEM_MMAP, &arg) == 0;
+			gem_close(fd, arg.handle);
+		}
 	}
+
 	errno = 0;
 
 	return has_wc > 0;
@@ -206,7 +221,12 @@ void *__gem_mmap__wc(int fd, uint32_t handle, uint64_t offset, uint64_t size, un
  */
 void *gem_mmap__wc(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned prot)
 {
-	void *ptr = __gem_mmap__wc(fd, handle, offset, size, prot);
+	void *ptr;
+
+	ptr = __gem_mmap_offset(fd, handle, offset, size, prot, LOCAL_I915_MMAP_OFFSET_WC);
+	if (!ptr)
+		ptr = __gem_mmap__wc(fd, handle, offset, size, prot);
+
 	igt_assert(ptr);
 	return ptr;
 }
@@ -243,7 +263,63 @@ void *__gem_mmap__cpu(int fd, uint32_t handle, uint64_t offset, uint64_t size, u
  */
 void *gem_mmap__cpu(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned prot)
 {
-	void *ptr = __gem_mmap__cpu(fd, handle, offset, size, prot);
+	void *ptr;
+
+	ptr = __gem_mmap_offset(fd, handle, offset, size, prot, LOCAL_I915_MMAP_OFFSET_WB);
+	if (!ptr)
+		ptr = __gem_mmap(fd, handle, offset, size, prot, 0);
+
 	igt_assert(ptr);
 	return ptr;
 }
+
+bool gem_has_mmap_offset(int fd)
+{
+	struct drm_i915_getparam gp;
+	int has_mmap_offset = 0;
+
+	memset(&gp, 0, sizeof(gp));
+	gp.param = 0x55; /* I915_PARAM_MMAP_OFFSET_VERSION */
+	gp.value = &has_mmap_offset;
+	ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
+
+	return has_mmap_offset > 0;
+}
+
+/**
+ * __gem_mmap_offset:
+ * @fd: open i915 drm file descriptor
+ * @handle: gem buffer object handle
+ * @offset: offset in the gem buffer of the mmap arena
+ * @size: size of the mmap arena
+ * @prot: memory protection bits as used by mmap()
+ * @flags: flags used to determine caching
+ *
+ * Similar to __gem_mmap but use MMAP_OFFSET IOCTL.
+ *
+ * Returns: A pointer to the created memory mapping, NULL on failure.
+ */
+void
+*__gem_mmap_offset(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned int prot, uint64_t flags)
+{
+	struct local_drm_i915_gem_mmap_offset arg;
+	void *ptr;
+
+	memset(&arg, 0, sizeof(arg));
+	arg.handle = handle;
+	arg.offset = offset;
+	arg.flags = flags;
+
+	if (igt_ioctl(fd, LOCAL_DRM_IOCTL_I915_GEM_MMAP_OFFSET, &arg))
+		return NULL;
+
+	ptr = mmap64(0, size, prot, MAP_SHARED, fd, arg.offset);
+
+	if (ptr == MAP_FAILED)
+		ptr = NULL;
+	else
+		errno = 0;
+
+	return ptr;
+}
+
diff --git a/lib/i915/gem_mman.h b/lib/i915/gem_mman.h
index f7242ed7..fff2ecab 100644
--- a/lib/i915/gem_mman.h
+++ b/lib/i915/gem_mman.h
@@ -51,5 +51,38 @@ int gem_munmap(void *ptr, uint64_t size);
  */
 #define gem_require_mmap_wc(fd) igt_require(gem_mmap__has_wc(fd))
 
+struct local_drm_i915_gem_mmap_offset {
+	/** Handle for the object being mapped. */
+	__u32 handle;
+	__u32 pad;
+	/**
+	 * Fake offset to use for subsequent mmap call
+	 *
+	 * This is a fixed-size type for 32/64 compatibility.
+	 */
+	__u64 offset;
+
+	/**
+	 * Flags for extended behaviour.
+	 *
+	 * It is mandatory that either one of the _WC/_WB flags
+	 * should be passed here.
+	 */
+	__u64 flags;
+};
+
+#define LOCAL_DRM_I915_GEM_MMAP_OFFSET 0x24
+#define LOCAL_I915_MMAP_OFFSET_WC (1 << 0)
+#define LOCAL_I915_MMAP_OFFSET_WB (1 << 1)
+#define LOCAL_I915_MMAP_OFFSET_UC (1 << 2)
+
+#define LOCAL_DRM_IOCTL_I915_GEM_MMAP_OFFSET \
+		DRM_IOWR(DRM_COMMAND_BASE + LOCAL_DRM_I915_GEM_MMAP_OFFSET, struct local_drm_i915_gem_mmap_offset)
+
+bool gem_has_mmap_offset(int fd);
+
+void *__gem_mmap_offset(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned int prot, uint64_t flags);
+
+
 #endif /* GEM_MMAN_H */
 
-- 
2.20.1

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[igt-dev] [RFT v4 3/6] igt/lib: Add wrapper to check if gtt mapping is available

[Antonio Argenziano]

Add wrapper to get mmap_gtt version number and another to check if
gtt mapping is at all available.

v2:
	- Check errno only after failed syscall. (Chris)

Cc: Katarzyna Dec <katarzyna.dec@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Antonio Argenziano <antonio.argenziano@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
 lib/i915/gem_mman.c | 40 +++++++++++++++++++++++++++++++++++++++-
 lib/i915/gem_mman.h | 11 +++++++++++
 2 files changed, 50 insertions(+), 1 deletion(-)

diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
index 429de912..4d41a66d 100644
--- a/lib/i915/gem_mman.c
+++ b/lib/i915/gem_mman.c
@@ -40,6 +40,41 @@
 #define VG(x) do {} while (0)
 #endif
 
+/**
+ * gem_mmap__gtt_version:
+ * @fd: open i915 drm file descriptor
+ *
+ * This wraps I915_PARAM_MMAP_GTT_VERSION. It will return the supported feature
+ * set for gtt mapping. Since the mappable aperture in not always present, this
+ * function will return '-1' in case there is none.
+ */
+static int gem_mmap__gtt_version(int fd)
+{
+	static int gtt_version = ~0;
+
+	if (gtt_version == ~0) {
+			struct drm_i915_getparam gp;
+
+			gtt_version = 0;
+
+			memset(&gp, 0, sizeof(gp));
+			gp.param = I915_PARAM_MMAP_GTT_VERSION;
+			gp.value = &gtt_version;
+
+			if(ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp) && errno == -ENODEV)
+				gtt_version = -1; /* No mappable aperture */
+
+			errno = 0;
+	}
+
+	return gtt_version;
+}
+
+bool gem_mmap__has_gtt(int fd)
+{
+	return gem_mmap__gtt_version(fd) >= 0;
+}
+
 /**
  * __gem_mmap__gtt:
  * @fd: open i915 drm file descriptor
@@ -121,6 +156,9 @@ bool gem_mmap__has_wc(int fd)
 		int mmap_version = -1;
 		int gtt_version = -1;
 
+		bool compatible_gtt_version =
+			(!gem_mmap__has_gtt(fd) || gem_mmap__gtt_version(fd) >= 2);
+
 		memset(&gp, 0, sizeof(gp));
 		gp.param = I915_PARAM_MMAP_GTT_VERSION;
 		gp.value = &gtt_version;
@@ -132,7 +170,7 @@ bool gem_mmap__has_wc(int fd)
 		ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
 
 		/* Do we have the mmap_ioctl with DOMAIN_WC? */
-		if (mmap_version >= 1 && gtt_version >= 2) {
+		if (mmap_version >= 1 && compatible_gtt_version) {
 			struct drm_i915_gem_mmap arg;
 
 			/* Does this device support wc-mmaps ? */
diff --git a/lib/i915/gem_mman.h b/lib/i915/gem_mman.h
index fff2ecab..d13bffae 100644
--- a/lib/i915/gem_mman.h
+++ b/lib/i915/gem_mman.h
@@ -31,6 +31,8 @@ void *gem_mmap__cpu(int fd, uint32_t handle, uint64_t offset, uint64_t size, uns
 bool gem_mmap__has_wc(int fd);
 void *gem_mmap__wc(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned prot);
 
+bool gem_mmap__has_gtt(int fd);
+
 #ifndef I915_GEM_DOMAIN_WC
 #define I915_GEM_DOMAIN_WC 0x80
 #endif
@@ -51,6 +53,15 @@ int gem_munmap(void *ptr, uint64_t size);
  */
 #define gem_require_mmap_wc(fd) igt_require(gem_mmap__has_wc(fd))
 
+/**
+ * gem_require_mmap_gtt:
+ * @fd: open i915 drm file descriptor
+ *
+ * Feature test macro to query whether memory mappings through the  mappable
+ * aperture are available. Automatically skips through igt_require() if not.
+ */
+#define gem_require_mmap_gtt(fd) igt_require(gem_mmap__has_gtt(fd))
+
 struct local_drm_i915_gem_mmap_offset {
 	/** Handle for the object being mapped. */
 	__u32 handle;
-- 
2.20.1

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Re: [igt-dev] [RFT v4 3/6] igt/lib: Add wrapper to check if gtt mapping is available

[Katarzyna Dec]

Sorry Antonio for entering this patchset discussion so late :).

On Mon, Mar 25, 2019 at 04:20:40PM -0700, Antonio Argenziano wrote:
> Add wrapper to get mmap_gtt version number and another to check if
> gtt mapping is at all available.
> 
> v2:
> 	- Check errno only after failed syscall. (Chris)
> 
> Cc: Katarzyna Dec <katarzyna.dec@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Signed-off-by: Antonio Argenziano <antonio.argenziano@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> ---
>  lib/i915/gem_mman.c | 40 +++++++++++++++++++++++++++++++++++++++-
>  lib/i915/gem_mman.h | 11 +++++++++++
>  2 files changed, 50 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
> index 429de912..4d41a66d 100644
> --- a/lib/i915/gem_mman.c
> +++ b/lib/i915/gem_mman.c
> @@ -40,6 +40,41 @@
>  #define VG(x) do {} while (0)
>  #endif
>  
> +/**
> + * gem_mmap__gtt_version:
> + * @fd: open i915 drm file descriptor
> + *
> + * This wraps I915_PARAM_MMAP_GTT_VERSION. It will return the supported feature
> + * set for gtt mapping. Since the mappable aperture in not always present, this
> + * function will return '-1' in case there is none.
> + */
This doc is explicit enough, although I would prefer to unify it with the rest
of the file - 'Returns' section is missing.
> +static int gem_mmap__gtt_version(int fd)
> +{
> +	static int gtt_version = ~0;
What is the reason that you are using '~0' value here and not -1?
> +
> +	if (gtt_version == ~0) {

Kasia :)
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Re: [igt-dev] [RFT v4 3/6] igt/lib: Add wrapper to check if gtt mapping is available

[Chris Wilson]

Quoting Katarzyna Dec (2019-04-16 14:25:28)
> Sorry Antonio for entering this patchset discussion so late :).
> 
> On Mon, Mar 25, 2019 at 04:20:40PM -0700, Antonio Argenziano wrote:
> > +static int gem_mmap__gtt_version(int fd)
> > +{
> > +     static int gtt_version = ~0;
> What is the reason that you are using '~0' value here and not -1?

The real question is why is it still a static int at all.
-Chris
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Re: [igt-dev] [RFT v4 3/6] igt/lib: Add wrapper to check if gtt mapping is available

[Antonio Argenziano]

On 16/04/19 06:28, Chris Wilson wrote:
> Quoting Katarzyna Dec (2019-04-16 14:25:28)
>> Sorry Antonio for entering this patchset discussion so late :).
>>
>> On Mon, Mar 25, 2019 at 04:20:40PM -0700, Antonio Argenziano wrote:
>>> +static int gem_mmap__gtt_version(int fd)
>>> +{
>>> +     static int gtt_version = ~0;
>> What is the reason that you are using '~0' value here and not -1?

I use -1 for when there is no mappable aperture.

> 
> The real question is why is it still a static int at all.

Ops, I guess I forgot about that.

Antonio

> -Chris
> 
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[igt-dev] [RFT v4 4/6] igt/i915: Require GTT mapping to be available when needed.

[Antonio Argenziano]

With the GTT aperture becoming unavailable on certain platforms, tests
that target that mapping need to skip if such mapping is not available.

Cc: Katarzyna Dec <katarzyna.dec@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Antonio Argenziano <antonio.argenziano@intel.com>
---
 lib/igt_dummyload.c                     |  4 +++-
 lib/igt_fb.c                            |  5 +++--
 tests/i915/gem_concurrent_all.c         |  1 +
 tests/i915/gem_ctx_sseu.c               |  4 +++-
 tests/i915/gem_exec_basic.c             |  1 +
 tests/i915/gem_exec_faulting_reloc.c    |  2 ++
 tests/i915/gem_exec_flush.c             |  6 ++++++
 tests/i915/gem_exec_reloc.c             |  7 +++++++
 tests/i915/gem_exec_schedule.c          |  5 ++++-
 tests/i915/gem_fence_thrash.c           |  6 ++++++
 tests/i915/gem_gtt_cpu_tlb.c            |  1 +
 tests/i915/gem_gtt_hog.c                |  1 +
 tests/i915/gem_gtt_speed.c              |  1 +
 tests/i915/gem_largeobject.c            |  2 ++
 tests/i915/gem_madvise.c                |  4 ++++
 tests/i915/gem_mmap_gtt.c               |  4 +++-
 tests/i915/gem_mmap_offset_exhaustion.c |  2 ++
 tests/i915/gem_mmap_wc.c                |  2 ++
 tests/i915/gem_persistent_relocs.c      |  2 ++
 tests/i915/gem_pwrite_pread.c           |  6 ++++++
 tests/i915/gem_reloc_vs_gpu.c           | 21 ++++++++++++---------
 tests/i915/gem_render_copy.c            |  2 ++
 tests/i915/gem_set_tiling_vs_gtt.c      |  2 ++
 tests/i915/gem_set_tiling_vs_pwrite.c   |  2 ++
 tests/i915/gem_shrink.c                 | 14 +++++++++++---
 tests/i915/gem_storedw_loop.c           |  9 +++++++++
 tests/i915/gem_streaming_writes.c       | 16 ++++++++++++++--
 tests/i915/gem_tiled_fence_blits.c      |  1 +
 tests/i915/gem_tiled_pread_basic.c      |  1 +
 tests/i915/gem_tiled_pread_pwrite.c     |  4 +++-
 tests/i915/gem_tiled_swapping.c         |  2 ++
 tests/i915/gem_tiled_wb.c               |  2 ++
 tests/i915/gem_tiled_wc.c               |  1 +
 tests/i915/gem_tiling_max_stride.c      |  3 ++-
 tests/i915/gem_userptr_blits.c          | 10 +++++++++-
 tests/i915/i915_pm_rpm.c                |  9 +++++++++
 tests/i915/i915_suspend.c               |  2 ++
 tests/kms_draw_crc.c                    |  8 ++++++--
 tests/kms_fence_pin_leak.c              |  2 ++
 tests/kms_frontbuffer_tracking.c        |  3 +++
 tests/kms_psr.c                         |  4 ++++
 tests/prime_mmap.c                      |  2 ++
 tests/prime_mmap_coherency.c            |  1 +
 tests/prime_vgem.c                      |  5 +++++
 44 files changed, 167 insertions(+), 25 deletions(-)

diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
index 47f6b92b..2e4c0335 100644
--- a/lib/igt_dummyload.c
+++ b/lib/igt_dummyload.c
@@ -117,9 +117,11 @@ emit_recursive_batch(igt_spin_t *spin,
 	obj[BATCH].handle = gem_create(fd, BATCH_SIZE);
 	batch = __gem_mmap__wc(fd, obj[BATCH].handle,
 			       0, BATCH_SIZE, PROT_WRITE);
-	if (!batch)
+	if (!batch) {
+		gem_require_mmap_gtt(fd);
 		batch = gem_mmap__gtt(fd, obj[BATCH].handle,
 				       	BATCH_SIZE, PROT_WRITE);
+	}
 	gem_set_domain(fd, obj[BATCH].handle,
 			I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
 	execbuf->buffer_count++;
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index bad1d1fb..068cd7fe 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -1746,10 +1746,11 @@ static void *map_bo(int fd, struct igt_fb *fb)
 	if (fb->is_dumb)
 		ptr = kmstest_dumb_map_buffer(fd, fb->gem_handle, fb->size,
 					      PROT_READ | PROT_WRITE);
-	else if (is_i915_device(fd))
+	else if (is_i915_device(fd)) {
+		gem_require_mmap_gtt(fd);
 		ptr = gem_mmap__gtt(fd, fb->gem_handle, fb->size,
 				    PROT_READ | PROT_WRITE);
-	else if (is_vc4_device(fd))
+	} else if (is_vc4_device(fd))
 		ptr = igt_vc4_mmap_bo(fd, fb->gem_handle, fb->size,
 				      PROT_READ | PROT_WRITE);
 	else
diff --git a/tests/i915/gem_concurrent_all.c b/tests/i915/gem_concurrent_all.c
index f719b0a1..e4fc1426 100644
--- a/tests/i915/gem_concurrent_all.c
+++ b/tests/i915/gem_concurrent_all.c
@@ -1422,6 +1422,7 @@ static void cpu_require(void)
 
 static void gtt_require(void)
 {
+	gem_require_mmap_gtt(fd);
 }
 
 static void bcs_require(void)
diff --git a/tests/i915/gem_ctx_sseu.c b/tests/i915/gem_ctx_sseu.c
index 3afa5c15..bf1b50d5 100644
--- a/tests/i915/gem_ctx_sseu.c
+++ b/tests/i915/gem_ctx_sseu.c
@@ -528,8 +528,10 @@ igt_main
 		igt_subtest("invalid-sseu")
 			test_invalid_sseu(fd);
 
-		igt_subtest("ggtt-args")
+		igt_subtest("ggtt-args") {
+			gem_require_mmap_gtt(fd);
 			test_ggtt_args(fd);
+		}
 
 		igt_subtest("engines")
 			test_engines(fd);
diff --git a/tests/i915/gem_exec_basic.c b/tests/i915/gem_exec_basic.c
index dcb83864..8537665f 100644
--- a/tests/i915/gem_exec_basic.c
+++ b/tests/i915/gem_exec_basic.c
@@ -93,6 +93,7 @@ static void gtt(int fd, unsigned ring)
 	struct drm_i915_gem_exec_object2 *exec;
 	uint32_t handle;
 
+	gem_require_mmap_gtt(fd);
 	gem_require_ring(fd, ring);
 
 	handle = gem_create(fd, 4096);
diff --git a/tests/i915/gem_exec_faulting_reloc.c b/tests/i915/gem_exec_faulting_reloc.c
index 6b05e43f..9db80f54 100644
--- a/tests/i915/gem_exec_faulting_reloc.c
+++ b/tests/i915/gem_exec_faulting_reloc.c
@@ -173,6 +173,8 @@ static void run(int object_size)
 
 	fd = drm_open_driver(DRIVER_INTEL);
 	igt_require_gem(fd);
+	gem_require_mmap_gtt(fd);
+
 	devid = intel_get_drm_devid(fd);
 	handle = gem_create(fd, 4096);
 	src = gem_create(fd, object_size);
diff --git a/tests/i915/gem_exec_flush.c b/tests/i915/gem_exec_flush.c
index f820b2a8..29b13803 100644
--- a/tests/i915/gem_exec_flush.c
+++ b/tests/i915/gem_exec_flush.c
@@ -79,6 +79,9 @@ static void run(int fd, unsigned ring, int nchild, int timeout,
 {
 	const int gen = intel_gen(intel_get_drm_devid(fd));
 
+	if (!(flags & COHERENT) && !(flags & WC))
+		gem_require_mmap_gtt(fd);
+
 	/* The crux of this testing is whether writes by the GPU are coherent
 	 * from the CPU.
 	 *
@@ -586,6 +589,7 @@ igt_main
 		fd = drm_open_driver(DRIVER_INTEL);
 		igt_require_gem(fd);
 		gem_require_mmap_wc(fd);
+		gem_require_mmap_gtt(fd);
 		igt_require(gem_can_store_dword(fd, 0));
 		igt_info("Has LLC? %s\n", yesno(gem_has_llc(fd)));
 
@@ -614,11 +618,13 @@ igt_main
 				      b->name,
 				      e->name)
 				batch(fd, ring, ncpus, timeout, b->mode, 0);
+
 			igt_subtest_f("%sbatch-%s-%s-wb",
 				      b == batches && e->exec_id == 0 ? "basic-" : "",
 				      b->name,
 				      e->name)
 				batch(fd, ring, ncpus, timeout, b->mode, COHERENT);
+
 			igt_subtest_f("%sbatch-%s-%s-cmd",
 				      b == batches && e->exec_id == 0 ? "basic-" : "",
 				      b->name,
diff --git a/tests/i915/gem_exec_reloc.c b/tests/i915/gem_exec_reloc.c
index 837f60a6..bb4eec31 100644
--- a/tests/i915/gem_exec_reloc.c
+++ b/tests/i915/gem_exec_reloc.c
@@ -115,6 +115,9 @@ static void from_mmap(int fd, uint64_t size, enum mode mode)
 	 */
 	intel_require_memory(2, size, CHECK_RAM);
 
+	if ((mode & ~RO) == GTT)
+		gem_require_mmap_gtt(fd);
+
 	memset(&obj, 0, sizeof(obj));
 	obj.handle = gem_create(fd, 4096);
 	gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
@@ -342,6 +345,9 @@ static void basic_reloc(int fd, unsigned before, unsigned after, unsigned flags)
 	const uint32_t bbe = MI_BATCH_BUFFER_END;
 	unsigned int reloc_offset;
 
+	if ((before | after) & I915_GEM_DOMAIN_GTT)
+		gem_require_mmap_gtt(fd);
+
 	memset(&obj, 0, sizeof(obj));
 	obj.handle = gem_create(fd, OBJSZ);
 	obj.relocs_ptr = to_user_pointer(&reloc);
@@ -711,6 +717,7 @@ igt_main
 					      f->name) {
 					if ((m->before | m->after) & I915_GEM_DOMAIN_WC)
 						igt_require(gem_mmap__has_wc(fd));
+
 					basic_reloc(fd, m->before, m->after, f->flags);
 				}
 			}
diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
index a9383000..15c8440f 100644
--- a/tests/i915/gem_exec_schedule.c
+++ b/tests/i915/gem_exec_schedule.c
@@ -1236,6 +1236,7 @@ igt_main
 			igt_subtest_f("independent-%s", e->name) {
 				igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
 				igt_require(gem_can_store_dword(fd, e->exec_id | e->flags));
+				gem_require_mmap_gtt(fd);
 				independent(fd, e->exec_id | e->flags);
 			}
 		}
@@ -1328,8 +1329,10 @@ igt_main
 				igt_subtest_f("wide-%s", e->name)
 					wide(fd, e->exec_id | e->flags);
 
-				igt_subtest_f("reorder-wide-%s", e->name)
+				igt_subtest_f("reorder-wide-%s", e->name) {
+					gem_require_mmap_gtt(fd);
 					reorder_wide(fd, e->exec_id | e->flags);
+				}
 
 				igt_subtest_f("smoketest-%s", e->name)
 					smoketest(fd, e->exec_id | e->flags, 5);
diff --git a/tests/i915/gem_fence_thrash.c b/tests/i915/gem_fence_thrash.c
index 2d7fb2ff..5567e37e 100644
--- a/tests/i915/gem_fence_thrash.c
+++ b/tests/i915/gem_fence_thrash.c
@@ -236,6 +236,12 @@ igt_main
 {
 	igt_skip_on_simulation();
 
+	igt_fixture {
+		int fd = drm_open_driver(DRIVER_INTEL);
+		igt_require(gem_available_fences(fd) > 0); /* GTT mapping available */
+		close(fd);
+	}
+
 	igt_subtest("bo-write-verify-none")
 		igt_assert(run_test(0, bo_write_verify, I915_TILING_NONE, 80) == 0);
 
diff --git a/tests/i915/gem_gtt_cpu_tlb.c b/tests/i915/gem_gtt_cpu_tlb.c
index cf3c543d..02682a0d 100644
--- a/tests/i915/gem_gtt_cpu_tlb.c
+++ b/tests/i915/gem_gtt_cpu_tlb.c
@@ -79,6 +79,7 @@ igt_simple_main
 	igt_skip_on_simulation();
 
 	fd = drm_open_driver(DRIVER_INTEL);
+	gem_require_mmap_gtt(fd);
 
 	handle = gem_create(fd, OBJ_SIZE);
 
diff --git a/tests/i915/gem_gtt_hog.c b/tests/i915/gem_gtt_hog.c
index ca730649..b2eea679 100644
--- a/tests/i915/gem_gtt_hog.c
+++ b/tests/i915/gem_gtt_hog.c
@@ -161,6 +161,7 @@ igt_simple_main
 	/* check for an intel gpu before goint nuts. */
 	int fd = drm_open_driver(DRIVER_INTEL);
 	igt_require_gem(fd);
+	gem_require_mmap_gtt(fd);
 	close(fd);
 
 	igt_skip_on_simulation();
diff --git a/tests/i915/gem_gtt_speed.c b/tests/i915/gem_gtt_speed.c
index 3d726c4e..f1778370 100644
--- a/tests/i915/gem_gtt_speed.c
+++ b/tests/i915/gem_gtt_speed.c
@@ -116,6 +116,7 @@ int main(int argc, char **argv)
 	buf = malloc(size);
 	memset(buf, 0, size);
 	fd = drm_open_driver(DRIVER_INTEL);
+	gem_require_mmap_gtt(fd);
 
 	handle = gem_create(fd, size);
 	igt_assert(handle);
diff --git a/tests/i915/gem_largeobject.c b/tests/i915/gem_largeobject.c
index 518396fa..a2d47edc 100644
--- a/tests/i915/gem_largeobject.c
+++ b/tests/i915/gem_largeobject.c
@@ -84,6 +84,8 @@ igt_simple_main
 
 	fd = drm_open_driver(DRIVER_INTEL);
 
+	gem_require_mmap_gtt(fd);
+
 	test_large_object(fd);
 
 	free(data);
diff --git a/tests/i915/gem_madvise.c b/tests/i915/gem_madvise.c
index 729a4d33..f4226a84 100644
--- a/tests/i915/gem_madvise.c
+++ b/tests/i915/gem_madvise.c
@@ -61,6 +61,8 @@ dontneed_before_mmap(void)
 	uint32_t handle;
 	char *ptr;
 
+	gem_require_mmap_gtt(fd);
+
 	handle = gem_create(fd, OBJECT_SIZE);
 	gem_madvise(fd, handle, I915_MADV_DONTNEED);
 	ptr = gem_mmap__gtt(fd, handle, OBJECT_SIZE, PROT_READ | PROT_WRITE);
@@ -89,6 +91,8 @@ dontneed_after_mmap(void)
 	uint32_t handle;
 	char *ptr;
 
+	gem_require_mmap_gtt(fd);
+
 	handle = gem_create(fd, OBJECT_SIZE);
 	ptr = gem_mmap__gtt(fd, handle, OBJECT_SIZE, PROT_READ | PROT_WRITE);
 	igt_assert(ptr);
diff --git a/tests/i915/gem_mmap_gtt.c b/tests/i915/gem_mmap_gtt.c
index 639de190..de4a5bb5 100644
--- a/tests/i915/gem_mmap_gtt.c
+++ b/tests/i915/gem_mmap_gtt.c
@@ -874,8 +874,10 @@ igt_main
 	if (igt_run_in_simulation())
 		OBJECT_SIZE = 1 * 1024 * 1024;
 
-	igt_fixture
+	igt_fixture {
 		fd = drm_open_driver(DRIVER_INTEL);
+		gem_require_mmap_gtt(fd);
+	}
 
 	igt_subtest("bad-object") {
 		uint32_t real_handle = gem_create(fd, 4096);
diff --git a/tests/i915/gem_mmap_offset_exhaustion.c b/tests/i915/gem_mmap_offset_exhaustion.c
index 8c8e3fa2..86464231 100644
--- a/tests/i915/gem_mmap_offset_exhaustion.c
+++ b/tests/i915/gem_mmap_offset_exhaustion.c
@@ -82,6 +82,8 @@ igt_simple_main
 
 	fd = drm_open_driver(DRIVER_INTEL);
 
+	gem_require_mmap_gtt(fd);
+
 	/* we have 32bit of address space, so try to fit one MB more
 	 * than that. */
 	for (i = 0; i < 4096 + 1; i++)
diff --git a/tests/i915/gem_mmap_wc.c b/tests/i915/gem_mmap_wc.c
index e3ffc5ad..3c33034c 100644
--- a/tests/i915/gem_mmap_wc.c
+++ b/tests/i915/gem_mmap_wc.c
@@ -334,6 +334,8 @@ test_write_gtt_read_wc(int fd)
 	uint32_t handle;
 	uint32_t *src, *dst;
 
+	gem_require_mmap_gtt(fd);
+
 	handle = gem_create(fd, OBJECT_SIZE);
 	set_domain(fd, handle);
 
diff --git a/tests/i915/gem_persistent_relocs.c b/tests/i915/gem_persistent_relocs.c
index 452fe686..17266c48 100644
--- a/tests/i915/gem_persistent_relocs.c
+++ b/tests/i915/gem_persistent_relocs.c
@@ -199,6 +199,8 @@ static void do_test(int fd, bool faulting_reloc)
 	uint32_t test;
 	int i, repeat;
 
+	gem_require_mmap_gtt(fd);
+
 	if (faulting_reloc)
 		igt_disable_prefault();
 
diff --git a/tests/i915/gem_pwrite_pread.c b/tests/i915/gem_pwrite_pread.c
index f91fc7c4..43b3987a 100644
--- a/tests/i915/gem_pwrite_pread.c
+++ b/tests/i915/gem_pwrite_pread.c
@@ -182,6 +182,8 @@ static void test_as_gtt_mmap(int fd, uint32_t src, uint32_t dst, int len)
 	int i;
 	BUILD_EXEC;
 
+	gem_require_mmap_gtt(fd);
+
 	src_ptr = gem_mmap__gtt(fd, src, OBJECT_SIZE, PROT_WRITE);
 	dst_ptr = gem_mmap__gtt(fd, dst, OBJECT_SIZE, PROT_READ);
 
@@ -309,6 +311,8 @@ int main(int argc, char **argv)
 		for (count = 1; count <= 1<<17; count <<= 1) {
 			struct timeval start, end;
 
+			gem_require_mmap_gtt(fd);
+
 			gettimeofday(&start, NULL);
 			as_gtt_mmap(fd, src, dst, tmp, object_size, count);
 			gettimeofday(&end, NULL);
@@ -387,6 +391,8 @@ int main(int argc, char **argv)
 		for (count = 1; count <= 1<<17; count <<= 1) {
 			struct timeval start, end;
 
+			gem_require_mmap_gtt(fd);
+
 			gettimeofday(&start, NULL);
 			as_gtt_mmap(fd, src, dst, tmp, object_size, count);
 			gettimeofday(&end, NULL);
diff --git a/tests/i915/gem_reloc_vs_gpu.c b/tests/i915/gem_reloc_vs_gpu.c
index d421e434..e1475a1f 100644
--- a/tests/i915/gem_reloc_vs_gpu.c
+++ b/tests/i915/gem_reloc_vs_gpu.c
@@ -159,17 +159,17 @@ static void reloc_and_emit(int fd, drm_intel_bo *target_bo, bool faulting_reloc)
 	 */
 	reloc[0].presumed_offset = -1;
 
-	handle_relocs = gem_create(fd, 4096);
-	gem_write(fd, handle_relocs, 0, reloc, sizeof(reloc));
-	gtt_relocs = gem_mmap__gtt(fd, handle_relocs, 4096,
-				   PROT_READ | PROT_WRITE);
-
 	exec[1].handle = special_bo->handle;
 	exec[1].relocation_count = 1;
 	/* A newly mmap gtt bo will fault on first access. */
-	if (faulting_reloc)
+	if (faulting_reloc) {
+		handle_relocs = gem_create(fd, 4096);
+		gem_write(fd, handle_relocs, 0, reloc, sizeof(reloc));
+		gtt_relocs = gem_mmap__gtt(fd, handle_relocs, 4096,
+						PROT_READ | PROT_WRITE);
+
 		exec[1].relocs_ptr = to_user_pointer(gtt_relocs);
-	else
+	} else
 		exec[1].relocs_ptr = to_user_pointer(reloc);
 
 	execbuf.buffers_ptr = to_user_pointer(exec);
@@ -180,7 +180,8 @@ static void reloc_and_emit(int fd, drm_intel_bo *target_bo, bool faulting_reloc)
 
 	gem_execbuf(fd, &execbuf);
 
-	gem_close(fd, handle_relocs);
+	if (faulting_reloc)
+		gem_close(fd, handle_relocs);
 }
 
 static igt_hang_t no_hang(int fd)
@@ -201,8 +202,10 @@ static void do_test(int fd, bool faulting_reloc,
 	uint32_t test;
 	int i;
 
-	if (faulting_reloc)
+	if (faulting_reloc) {
+		gem_require_mmap_gtt(fd);
 		igt_disable_prefault();
+	}
 
 	act_size = 2048;
 	dummy_bo = drm_intel_bo_alloc_tiled(bufmgr, "tiled dummy_bo", act_size, act_size,
diff --git a/tests/i915/gem_render_copy.c b/tests/i915/gem_render_copy.c
index 8d62a0f4..5757c547 100644
--- a/tests/i915/gem_render_copy.c
+++ b/tests/i915/gem_render_copy.c
@@ -572,6 +572,8 @@ static void test(data_t *data, uint32_t tiling, uint64_t ccs_modifier)
 	int opt_dump_aub = igt_aub_dump_enabled();
 	int num_src = ARRAY_SIZE(src);
 
+	gem_require_mmap_gtt(data->drm_fd);
+
 	/* no Yf before gen9 */
 	if (intel_gen(data->devid) < 9)
 		num_src--;
diff --git a/tests/i915/gem_set_tiling_vs_gtt.c b/tests/i915/gem_set_tiling_vs_gtt.c
index 2611ec55..210d5358 100644
--- a/tests/i915/gem_set_tiling_vs_gtt.c
+++ b/tests/i915/gem_set_tiling_vs_gtt.c
@@ -60,6 +60,8 @@ igt_simple_main
 
 	fd = drm_open_driver(DRIVER_INTEL);
 
+	gem_require_mmap_gtt(fd);
+
 	if (IS_GEN2(intel_get_drm_devid(fd)))
 		tile_height = 16;
 	else
diff --git a/tests/i915/gem_set_tiling_vs_pwrite.c b/tests/i915/gem_set_tiling_vs_pwrite.c
index f0126b64..d82e20b4 100644
--- a/tests/i915/gem_set_tiling_vs_pwrite.c
+++ b/tests/i915/gem_set_tiling_vs_pwrite.c
@@ -58,6 +58,8 @@ igt_simple_main
 
 	fd = drm_open_driver(DRIVER_INTEL);
 
+	gem_require_mmap_gtt(fd);
+
 	for (i = 0; i < OBJECT_SIZE/4; i++)
 		data[i] = i;
 
diff --git a/tests/i915/gem_shrink.c b/tests/i915/gem_shrink.c
index f71a1fcb..e97e0981 100644
--- a/tests/i915/gem_shrink.c
+++ b/tests/i915/gem_shrink.c
@@ -396,6 +396,8 @@ igt_main
 	uint64_t alloc_size = 0;
 	int num_processes = 0;
 
+	bool has_gtt = false;
+
 	igt_skip_on_simulation();
 
 	igt_fixture {
@@ -427,6 +429,8 @@ igt_main
 			engines[nengine++] = engine;
 		igt_require(nengine);
 
+		has_gtt = gem_mmap__has_gtt(fd);
+
 		close(fd);
 	}
 
@@ -435,9 +439,13 @@ igt_main
 
 	for(const struct test *t = tests; t->name; t++) {
 		for(const struct mode *m = modes; m->suffix; m++) {
-			igt_subtest_f("%s%s", t->name, m->suffix)
-				run_test(num_processes, alloc_size,
-					 t->func, m->flags);
+			igt_subtest_f("%s%s", t->name, m->suffix) {
+					if (t->func == mmap_gtt)
+						igt_require(has_gtt);
+
+					run_test(num_processes, alloc_size,
+						 t->func, m->flags);
+			}
 		}
 	}
 }
diff --git a/tests/i915/gem_storedw_loop.c b/tests/i915/gem_storedw_loop.c
index b00555e0..d16a1a6b 100644
--- a/tests/i915/gem_storedw_loop.c
+++ b/tests/i915/gem_storedw_loop.c
@@ -49,6 +49,12 @@ static int devid;
 
 static unsigned coherent_domain;
 
+static bool
+uses_coherent_gtt(int fd)
+{
+	return (!gem_has_llc(fd) || gem_mmap__has_wc(fd));
+}
+
 static void *
 mmap_coherent(int fd, uint32_t handle, int size)
 {
@@ -164,6 +170,9 @@ check_test_requirements(int fd, int ringid)
 {
 	gem_require_ring(fd, ringid);
 	igt_require(gem_can_store_dword(fd, ringid));
+
+	if (uses_coherent_gtt(fd))
+		gem_require_mmap_gtt(fd);
 }
 
 igt_main
diff --git a/tests/i915/gem_streaming_writes.c b/tests/i915/gem_streaming_writes.c
index e83d69de..159cb7a6 100644
--- a/tests/i915/gem_streaming_writes.c
+++ b/tests/i915/gem_streaming_writes.c
@@ -48,6 +48,8 @@
 
 #define LOCAL_I915_EXEC_HANDLE_LUT (1<<12)
 
+#define NEEDS_GTT(mode) (mode == 1)
+
 IGT_TEST_DESCRIPTION("Test of streaming writes into active GPU sources");
 
 #define SRC 0
@@ -75,6 +77,9 @@ static void test_streaming(int fd, int mode, int sync)
 	} *batch;
 	int i, n;
 
+	if (NEEDS_GTT(mode))
+		gem_require_mmap_gtt(fd);
+
 	memset(exec, 0, sizeof(exec));
 	exec[SRC].handle = gem_create(fd, OBJECT_SIZE);
 	exec[DST].handle = gem_create(fd, OBJECT_SIZE);
@@ -245,6 +250,9 @@ static void test_batch(int fd, int mode, int reverse)
 	uint32_t *base;
 	uint32_t offset;
 
+	if (NEEDS_GTT(mode))
+		gem_require_mmap_gtt(fd);
+
 	memset(exec, 0, sizeof(exec));
 	exec[DST].handle = gem_create(fd, OBJECT_SIZE);
 	exec[SRC].handle = gem_create(fd, OBJECT_SIZE);
@@ -389,14 +397,18 @@ igt_main
 
 	igt_subtest("batch-cpu")
 		test_batch(fd, 0, 0);
-	igt_subtest("batch-gtt")
+	igt_subtest("batch-gtt") {
+		gem_require_mmap_gtt(fd);
 		test_batch(fd, 1, 0);
+	}
 	igt_subtest("batch-wc")
 		test_batch(fd, 2, 0);
 	igt_subtest("batch-reverse-cpu")
 		test_batch(fd, 0, 1);
-	igt_subtest("batch-reverse-gtt")
+	igt_subtest("batch-reverse-gtt") {
+		gem_require_mmap_gtt(fd);
 		test_batch(fd, 1, 1);
+	}
 	igt_subtest("batch-reverse-wc")
 		test_batch(fd, 2, 1);
 
diff --git a/tests/i915/gem_tiled_fence_blits.c b/tests/i915/gem_tiled_fence_blits.c
index aacd42b7..249456e8 100644
--- a/tests/i915/gem_tiled_fence_blits.c
+++ b/tests/i915/gem_tiled_fence_blits.c
@@ -213,6 +213,7 @@ igt_main
 	igt_fixture {
 		fd = drm_open_driver(DRIVER_INTEL);
 		igt_require_gem(fd);
+		gem_require_mmap_gtt(fd);
 	}
 
 	igt_subtest("basic")
diff --git a/tests/i915/gem_tiled_pread_basic.c b/tests/i915/gem_tiled_pread_basic.c
index 1ac9eccd..b5a4e348 100644
--- a/tests/i915/gem_tiled_pread_basic.c
+++ b/tests/i915/gem_tiled_pread_basic.c
@@ -124,6 +124,7 @@ igt_simple_main
 	uint32_t devid;
 
 	fd = drm_open_driver(DRIVER_INTEL);
+	gem_require_mmap_gtt(fd);
 
 	handle = create_bo(fd);
 	igt_require(gem_get_tiling(fd, handle, &tiling, &swizzle));
diff --git a/tests/i915/gem_tiled_pread_pwrite.c b/tests/i915/gem_tiled_pread_pwrite.c
index 0988a4e8..0c0cde7f 100644
--- a/tests/i915/gem_tiled_pread_pwrite.c
+++ b/tests/i915/gem_tiled_pread_pwrite.c
@@ -111,8 +111,10 @@ igt_simple_main
 	uint32_t tiling, swizzle;
 	int count;
 	int fd;
-	
+
 	fd = drm_open_driver(DRIVER_INTEL);
+	gem_require_mmap_gtt(fd);
+
 	count = SLOW_QUICK(intel_get_total_ram_mb() * 9 / 10, 8) ;
 
 	for (int i = 0; i < count/2; i++) {
diff --git a/tests/i915/gem_tiled_swapping.c b/tests/i915/gem_tiled_swapping.c
index ddf2a748..29783aba 100644
--- a/tests/i915/gem_tiled_swapping.c
+++ b/tests/i915/gem_tiled_swapping.c
@@ -175,6 +175,8 @@ igt_main
 
 		fd = drm_open_driver(DRIVER_INTEL);
 
+		gem_require_mmap_gtt(fd);
+
 		intel_purge_vm_caches(fd);
 		check_memory_layout(fd);
 
diff --git a/tests/i915/gem_tiled_wb.c b/tests/i915/gem_tiled_wb.c
index b7f352fc..61aa1675 100644
--- a/tests/i915/gem_tiled_wb.c
+++ b/tests/i915/gem_tiled_wb.c
@@ -140,6 +140,8 @@ igt_simple_main
 
 	fd = drm_open_driver(DRIVER_INTEL);
 
+	gem_require_mmap_gtt(fd);
+
 	handle = create_bo(fd);
 	get_tiling(fd, handle, &tiling, &swizzle);
 
diff --git a/tests/i915/gem_tiled_wc.c b/tests/i915/gem_tiled_wc.c
index 845ec228..86e9bf46 100644
--- a/tests/i915/gem_tiled_wc.c
+++ b/tests/i915/gem_tiled_wc.c
@@ -113,6 +113,7 @@ igt_simple_main
 	uint32_t handle;
 
 	fd = drm_open_driver(DRIVER_INTEL);
+	gem_require_mmap_gtt(fd);
 	gem_require_mmap_wc(fd);
 
 	handle = create_bo(fd);
diff --git a/tests/i915/gem_tiling_max_stride.c b/tests/i915/gem_tiling_max_stride.c
index a6f97a91..b5dc053d 100644
--- a/tests/i915/gem_tiling_max_stride.c
+++ b/tests/i915/gem_tiling_max_stride.c
@@ -70,8 +70,9 @@ igt_simple_main
 
 	fd = drm_open_driver(DRIVER_INTEL);
 
-	devid = intel_get_drm_devid(fd);
+	gem_require_mmap_wc(fd);
 
+	devid = intel_get_drm_devid(fd);
 	if (intel_gen(devid) >= 7)
 		stride = 256 * 1024;
 	else if (intel_gen(devid) >= 4)
diff --git a/tests/i915/gem_userptr_blits.c b/tests/i915/gem_userptr_blits.c
index 8f8ddf43..9962e539 100644
--- a/tests/i915/gem_userptr_blits.c
+++ b/tests/i915/gem_userptr_blits.c
@@ -554,6 +554,8 @@ static int test_invalid_gtt_mapping(int fd)
 	uint32_t handle;
 	char *gtt, *map;
 
+	gem_require_mmap_gtt(fd);
+
 	/* Anonymous mapping to find a hole */
 	map = mmap(NULL, sizeof(linear) + 2 * PAGE_SIZE,
 		   PROT_READ | PROT_WRITE,
@@ -616,8 +618,10 @@ static int test_invalid_gtt_mapping(int fd)
 #define PE_BUSY 0x2
 static void test_process_exit(int fd, int flags)
 {
-	if (flags & PE_GTT_MAP)
+	if (flags & PE_GTT_MAP) {
 		igt_require(gem_has_llc(fd));
+		gem_require_mmap_gtt(fd);
+	}
 
 	igt_fork(child, 1) {
 		uint32_t handle;
@@ -700,6 +704,8 @@ static int test_map_fixed_invalidate(int fd, uint32_t flags)
 	uint32_t handle[num_handles];
 	uint32_t *ptr;
 
+	gem_require_mmap_gtt(fd);
+
 	ptr = mmap(NULL, ptr_size,
 		   PROT_READ | PROT_WRITE,
 		   MAP_SHARED | MAP_ANONYMOUS,
@@ -944,6 +950,7 @@ static int test_dmabuf(void)
 	int ret;
 
 	fd1 = drm_open_driver(DRIVER_INTEL);
+	gem_require_mmap_gtt(fd1);
 
 	handle = create_userptr_bo(fd1, sizeof(linear));
 	memset(get_handle_ptr(handle), counter, sizeof(linear));
@@ -1212,6 +1219,7 @@ static void test_readonly_mmap(int i915)
 	 */
 
 	igt_require(igt_setup_clflush());
+	gem_require_mmap_gtt(i915);
 
 	sz = 16 << 12;
 	pages = mmap(NULL, sz, PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1, 0);
diff --git a/tests/i915/i915_pm_rpm.c b/tests/i915/i915_pm_rpm.c
index 18adaf6b..97b57ca2 100644
--- a/tests/i915/i915_pm_rpm.c
+++ b/tests/i915/i915_pm_rpm.c
@@ -1006,6 +1006,7 @@ static void gem_mmap_subtest(bool gtt_mmap)
 	handle = gem_create(drm_fd, buf_size);
 
 	if (gtt_mmap) {
+		gem_require_mmap_gtt(drm_fd);
 		gem_buf = gem_mmap__gtt(drm_fd, handle, buf_size,
 					PROT_READ | PROT_WRITE);
 	}
@@ -1368,6 +1369,8 @@ static void gem_evict_pwrite_subtest(void)
 	unsigned int num_trash_bos, n;
 	uint32_t buf;
 
+	gem_require_mmap_gtt(drm_fd);
+
 	num_trash_bos = gem_mappable_aperture_size(drm_fd) / (1024*1024) + 1;
 	trash_bos = malloc(num_trash_bos * sizeof(*trash_bos));
 	igt_assert(trash_bos);
@@ -1532,6 +1535,7 @@ static void cursor_subtest(bool dpms)
 
 	disable_all_screens_and_wait(&ms_data);
 
+	gem_require_mmap_gtt(drm_fd);
 	igt_require(default_mode_params);
 	crtc_id = default_mode_params->crtc_id;
 
@@ -1649,6 +1653,7 @@ static void test_one_plane(bool dpms, uint32_t plane_id,
 	int32_t crtc_x = 0, crtc_y = 0;
 	uint64_t tiling;
 
+	gem_require_mmap_gtt(drm_fd);
 	disable_all_screens_and_wait(&ms_data);
 
 	crtc_id = default_mode_params->crtc_id;
@@ -1796,6 +1801,8 @@ static void pm_test_tiling(void)
 	/* default stride value */
 	uint32_t stride = 512;
 
+	gem_require_mmap_gtt(drm_fd);
+
 	/* calculate how many objects we can map */
 	for (i = 1 << off_bit; i <= gtt_obj_max_size; i <<= 1, max_gem_objs++)
 		;
@@ -1850,6 +1857,7 @@ static void pm_test_caching(void)
 		I915_CACHING_DISPLAY,           /* eDRAM caching */
 	};
 
+	gem_require_mmap_gtt(drm_fd);
 	disable_all_screens(&ms_data);
 
 	handle = gem_create(drm_fd, gtt_obj_max_size);
@@ -1887,6 +1895,7 @@ static void fences_subtest(bool dpms)
 
 	disable_all_screens_and_wait(&ms_data);
 
+	igt_require(gem_available_fences(drm_fd));
 	igt_require(default_mode_params);
 	params.crtc_id = default_mode_params->crtc_id;
 	params.connector_id = default_mode_params->connector_id;
diff --git a/tests/i915/i915_suspend.c b/tests/i915/i915_suspend.c
index 17c68cc1..09cf5542 100644
--- a/tests/i915/i915_suspend.c
+++ b/tests/i915/i915_suspend.c
@@ -50,6 +50,8 @@ test_fence_restore(int fd, bool tiled2untiled, bool hibernate)
 	uint32_t *ptr1, *ptr2, *ptr_tiled;
 	int i;
 
+	igt_require(gem_available_fences(fd));
+
 	/* We wall the tiled object with untiled canary objects to make sure
 	 * that we detect tile leaking in both directions. */
 	handle1 = gem_create(fd, OBJECT_SIZE);
diff --git a/tests/kms_draw_crc.c b/tests/kms_draw_crc.c
index ea14db9a..1a2e2d4f 100644
--- a/tests/kms_draw_crc.c
+++ b/tests/kms_draw_crc.c
@@ -329,13 +329,17 @@ igt_main
 		igt_subtest_f("draw-method-%s-%s-%s",
 			      format_str(format_idx),
 			      igt_draw_get_method_name(method),
-			      tiling_str(tiling_idx))
+			      tiling_str(tiling_idx)) {
+			gem_require_mmap_gtt(drm_fd);
 			draw_method_subtest(method, format_idx,
 					    tilings[tiling_idx]);
+		}
 	} } }
 
-	igt_subtest("fill-fb")
+	igt_subtest("fill-fb") {
+		gem_require_mmap_gtt(drm_fd);
 		fill_fb_subtest();
+	}
 
 	igt_fixture
 		teardown_environment();
diff --git a/tests/kms_fence_pin_leak.c b/tests/kms_fence_pin_leak.c
index 62c52b62..ac0f605c 100644
--- a/tests/kms_fence_pin_leak.c
+++ b/tests/kms_fence_pin_leak.c
@@ -202,6 +202,8 @@ igt_simple_main
 
 	data.drm_fd = drm_open_driver_master(DRIVER_INTEL);
 
+	gem_require_mmap_gtt(data.drm_fd);
+
 	data.devid = intel_get_drm_devid(data.drm_fd);
 
 	kmstest_set_vt_graphics_mode();
diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index 4d15ce1c..78299438 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -1758,6 +1758,9 @@ static void check_test_requirements(const struct test_mode *t)
 
 	if (opt.only_pipes != PIPE_COUNT)
 		igt_require(t->pipes == opt.only_pipes);
+
+	if (t->method == IGT_DRAW_MMAP_GTT)
+		gem_require_mmap_gtt(drm.fd);
 }
 
 static void set_crtc_fbs(const struct test_mode *t)
diff --git a/tests/kms_psr.c b/tests/kms_psr.c
index 3e16a6bf..66f4fcd8 100644
--- a/tests/kms_psr.c
+++ b/tests/kms_psr.c
@@ -41,6 +41,8 @@ enum operations {
 	PLANE_ONOFF,
 };
 
+#define needs_gtt(op) if (op == MMAP_GTT) {gem_require_mmap_gtt(data.drm_fd);}
+
 static const char *op_str(enum operations op)
 {
 	static const char * const name[] = {
@@ -474,6 +476,7 @@ int main(int argc, char *argv[])
 			igt_subtest_f("%sprimary_%s",
 				      append_subtest_name[data.op_psr_mode],
 				      op_str(op)) {
+				needs_gtt(op);
 				data.op = op;
 				data.test_plane_id = DRM_PLANE_TYPE_PRIMARY;
 				test_setup(&data);
@@ -486,6 +489,7 @@ int main(int argc, char *argv[])
 			igt_subtest_f("%ssprite_%s",
 				      append_subtest_name[data.op_psr_mode],
 				      op_str(op)) {
+				needs_gtt(op);
 				data.op = op;
 				data.test_plane_id = DRM_PLANE_TYPE_OVERLAY;
 				test_setup(&data);
diff --git a/tests/prime_mmap.c b/tests/prime_mmap.c
index 06a66cab..33f97b84 100644
--- a/tests/prime_mmap.c
+++ b/tests/prime_mmap.c
@@ -79,6 +79,8 @@ test_correct(void)
 	char *ptr1, *ptr2;
 	uint32_t handle;
 
+	gem_require_mmap_gtt(fd);
+
 	handle = gem_create(fd, BO_SIZE);
 	fill_bo(handle, BO_SIZE);
 
diff --git a/tests/prime_mmap_coherency.c b/tests/prime_mmap_coherency.c
index 04b15ddd..9c344df9 100644
--- a/tests/prime_mmap_coherency.c
+++ b/tests/prime_mmap_coherency.c
@@ -295,6 +295,7 @@ int main(int argc, char **argv)
 	 * reproducing boils down to trial and error to hit different scenarios.
 	 * TODO: We may want to improve tests a bit by picking random subranges. */
 	igt_subtest("read") {
+		gem_require_mmap_gtt(fd);
 		igt_until_timeout(5) {
 			int stale = test_read_flush();
 			igt_fail_on_f(stale,
diff --git a/tests/prime_vgem.c b/tests/prime_vgem.c
index 60bb951c..0c60d569 100644
--- a/tests/prime_vgem.c
+++ b/tests/prime_vgem.c
@@ -125,6 +125,8 @@ static void test_fence_mmap(int i915, int vgem)
 	int dmabuf, i;
 	int master[2], slave[2];
 
+	gem_require_mmap_gtt(i915);
+
 	igt_assert(pipe(master) == 0);
 	igt_assert(pipe(slave) == 0);
 
@@ -207,6 +209,8 @@ static void test_gtt(int vgem, int i915)
 	uint32_t *ptr;
 	int dmabuf, i;
 
+	gem_require_mmap_gtt(i915);
+
 	scratch.width = 1024;
 	scratch.height = 1024;
 	scratch.bpp = 32;
@@ -282,6 +286,7 @@ static void test_gtt_interleaved(int vgem, int i915)
 	uint32_t *ptr, *gtt;
 	int dmabuf, i;
 
+	gem_require_mmap_gtt(i915);
 	igt_require(is_coherent(i915));
 
 	scratch.width = 1024;
-- 
2.20.1

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Re: [igt-dev] [RFT v4 4/6] igt/i915: Require GTT mapping to be available when needed.

[Chris Wilson]

Quoting Antonio Argenziano (2019-03-25 23:20:41)
> diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
> index 47f6b92b..2e4c0335 100644
> --- a/lib/igt_dummyload.c
> +++ b/lib/igt_dummyload.c
> @@ -117,9 +117,11 @@ emit_recursive_batch(igt_spin_t *spin,
>         obj[BATCH].handle = gem_create(fd, BATCH_SIZE);
>         batch = __gem_mmap__wc(fd, obj[BATCH].handle,
>                                0, BATCH_SIZE, PROT_WRITE);
> -       if (!batch)
> +       if (!batch) {
> +               gem_require_mmap_gtt(fd);
>                 batch = gem_mmap__gtt(fd, obj[BATCH].handle,
>                                         BATCH_SIZE, PROT_WRITE);

batch = __gem_mmap__gtt();
igt_require(batch) ?

Possibly not as informative as gem_require_mmap_gtt() So ~o~

> diff --git a/tests/i915/gem_concurrent_all.c b/tests/i915/gem_concurrent_all.c
> index f719b0a1..e4fc1426 100644
> --- a/tests/i915/gem_concurrent_all.c
> +++ b/tests/i915/gem_concurrent_all.c
> @@ -1422,6 +1422,7 @@ static void cpu_require(void)
>  
>  static void gtt_require(void)
>  {
> +       gem_require_mmap_gtt(fd);
>  }

Needs the combinatorial explosion to exercise accessing via mmap-offset.
If you only update one stress test, update this one.

>  static void bcs_require(void)
> diff --git a/tests/i915/gem_ctx_sseu.c b/tests/i915/gem_ctx_sseu.c
> index 3afa5c15..bf1b50d5 100644
> --- a/tests/i915/gem_ctx_sseu.c
> +++ b/tests/i915/gem_ctx_sseu.c
> @@ -528,8 +528,10 @@ igt_main
>                 igt_subtest("invalid-sseu")
>                         test_invalid_sseu(fd);
>  
> -               igt_subtest("ggtt-args")
> +               igt_subtest("ggtt-args") {
> +                       gem_require_mmap_gtt(fd);
>                         test_ggtt_args(fd);
> +               }
>  
>                 igt_subtest("engines")
>                         test_engines(fd);

> diff --git a/tests/i915/gem_exec_reloc.c b/tests/i915/gem_exec_reloc.c
> index 837f60a6..bb4eec31 100644
> --- a/tests/i915/gem_exec_reloc.c
> +++ b/tests/i915/gem_exec_reloc.c
> @@ -115,6 +115,9 @@ static void from_mmap(int fd, uint64_t size, enum mode mode)
>          */
>         intel_require_memory(2, size, CHECK_RAM);
>  
> +       if ((mode & ~RO) == GTT)
> +               gem_require_mmap_gtt(fd);
> +

We need to stick arguments into mmap-offset buffers. Same is true for
several of the "do we survive userspace being nasty with __user pointers"
tests.

> diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
> index a9383000..15c8440f 100644
> --- a/tests/i915/gem_exec_schedule.c
> +++ b/tests/i915/gem_exec_schedule.c
> @@ -1236,6 +1236,7 @@ igt_main
>                         igt_subtest_f("independent-%s", e->name) {
>                                 igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
>                                 igt_require(gem_can_store_dword(fd, e->exec_id | e->flags));
> +                               gem_require_mmap_gtt(fd);
>                                 independent(fd, e->exec_id | e->flags);
>                         }
>                 }
> @@ -1328,8 +1329,10 @@ igt_main
>                                 igt_subtest_f("wide-%s", e->name)
>                                         wide(fd, e->exec_id | e->flags);
>  
> -                               igt_subtest_f("reorder-wide-%s", e->name)
> +                               igt_subtest_f("reorder-wide-%s", e->name) {
> +                                       gem_require_mmap_gtt(fd);
>                                         reorder_wide(fd, e->exec_id | e->flags);
> +                               }
>  
>                                 igt_subtest_f("smoketest-%s", e->name)
>                                         smoketest(fd, e->exec_id | e->flags, 5);

Hmm. I would rather the basic scheduling tests remained functioning.

> diff --git a/tests/i915/gem_largeobject.c b/tests/i915/gem_largeobject.c
> index 518396fa..a2d47edc 100644
> --- a/tests/i915/gem_largeobject.c
> +++ b/tests/i915/gem_largeobject.c
> @@ -84,6 +84,8 @@ igt_simple_main
>  
>         fd = drm_open_driver(DRIVER_INTEL);
>  
> +       gem_require_mmap_gtt(fd);

Ok, not mmap-offset specific in future, but one of those fun challenges.

> diff --git a/tests/i915/gem_madvise.c b/tests/i915/gem_madvise.c
> index 729a4d33..f4226a84 100644
> --- a/tests/i915/gem_madvise.c
> +++ b/tests/i915/gem_madvise.c
> @@ -61,6 +61,8 @@ dontneed_before_mmap(void)
>         uint32_t handle;
>         char *ptr;
>  
> +       gem_require_mmap_gtt(fd);

Needs mmap-offset integration.

> diff --git a/tests/i915/gem_mmap_offset_exhaustion.c b/tests/i915/gem_mmap_offset_exhaustion.c
> index 8c8e3fa2..86464231 100644
> --- a/tests/i915/gem_mmap_offset_exhaustion.c
> +++ b/tests/i915/gem_mmap_offset_exhaustion.c
> @@ -82,6 +82,8 @@ igt_simple_main
>  
>         fd = drm_open_driver(DRIVER_INTEL);
>  
> +       gem_require_mmap_gtt(fd);

Some might say this became a more important test. Not sure if the test
itself is the best strategy (vs the selftest approach), but it
definitely shouldn't just be skipped for mmap-offset.

> diff --git a/tests/i915/gem_render_copy.c b/tests/i915/gem_render_copy.c
> index 8d62a0f4..5757c547 100644
> --- a/tests/i915/gem_render_copy.c
> +++ b/tests/i915/gem_render_copy.c
> @@ -572,6 +572,8 @@ static void test(data_t *data, uint32_t tiling, uint64_t ccs_modifier)
>         int opt_dump_aub = igt_aub_dump_enabled();
>         int num_src = ARRAY_SIZE(src);
>  
> +       gem_require_mmap_gtt(data->drm_fd);

We should make sure gem_render_copy remains available for debugging the
rendercopy routines, I doubt they are going away.

> diff --git a/tests/i915/gem_userptr_blits.c b/tests/i915/gem_userptr_blits.c
> index 8f8ddf43..9962e539 100644
> --- a/tests/i915/gem_userptr_blits.c
> +++ b/tests/i915/gem_userptr_blits.c
> @@ -554,6 +554,8 @@ static int test_invalid_gtt_mapping(int fd)
>         uint32_t handle;
>         char *gtt, *map;
>  
> +       gem_require_mmap_gtt(fd);

userptr-blits needs mmap-offset enhancements. Principally, if we can
mmap(MAP_FIXED) over top of an active userptr, we need to resolve that
amicably.
-Chris
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Re: [igt-dev] [RFT v4 4/6] igt/i915: Require GTT mapping to be available when needed.

[Antonio Argenziano]

On 25/03/19 16:36, Chris Wilson wrote:
> Quoting Antonio Argenziano (2019-03-25 23:20:41)
>> diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
>> index 47f6b92b..2e4c0335 100644
>> --- a/lib/igt_dummyload.c
>> +++ b/lib/igt_dummyload.c
>> @@ -117,9 +117,11 @@ emit_recursive_batch(igt_spin_t *spin,
>>          obj[BATCH].handle = gem_create(fd, BATCH_SIZE);
>>          batch = __gem_mmap__wc(fd, obj[BATCH].handle,
>>                                 0, BATCH_SIZE, PROT_WRITE);
>> -       if (!batch)
>> +       if (!batch) {
>> +               gem_require_mmap_gtt(fd);
>>                  batch = gem_mmap__gtt(fd, obj[BATCH].handle,
>>                                          BATCH_SIZE, PROT_WRITE);
> 
> batch = __gem_mmap__gtt();
> igt_require(batch) ?
> 
> Possibly not as informative as gem_require_mmap_gtt() So ~o~
> 
>> diff --git a/tests/i915/gem_concurrent_all.c b/tests/i915/gem_concurrent_all.c
>> index f719b0a1..e4fc1426 100644
>> --- a/tests/i915/gem_concurrent_all.c
>> +++ b/tests/i915/gem_concurrent_all.c
>> @@ -1422,6 +1422,7 @@ static void cpu_require(void)
>>   
>>   static void gtt_require(void)
>>   {
>> +       gem_require_mmap_gtt(fd);
>>   }
> 
> Needs the combinatorial explosion to exercise accessing via mmap-offset.
> If you only update one stress test, update this one.

Don't we get the mmap-offset coverage by default in the wc test cases or 
do you mean to use the mmap_offset IOCTL to mmap GTT?

> 
>>   static void bcs_require(void)
>> diff --git a/tests/i915/gem_ctx_sseu.c b/tests/i915/gem_ctx_sseu.c
>> index 3afa5c15..bf1b50d5 100644
>> --- a/tests/i915/gem_ctx_sseu.c
>> +++ b/tests/i915/gem_ctx_sseu.c
>> @@ -528,8 +528,10 @@ igt_main
>>                  igt_subtest("invalid-sseu")
>>                          test_invalid_sseu(fd);
>>   
>> -               igt_subtest("ggtt-args")
>> +               igt_subtest("ggtt-args") {
>> +                       gem_require_mmap_gtt(fd);
>>                          test_ggtt_args(fd);
>> +               }
>>   
>>                  igt_subtest("engines")
>>                          test_engines(fd);
> 
>> diff --git a/tests/i915/gem_exec_reloc.c b/tests/i915/gem_exec_reloc.c
>> index 837f60a6..bb4eec31 100644
>> --- a/tests/i915/gem_exec_reloc.c
>> +++ b/tests/i915/gem_exec_reloc.c
>> @@ -115,6 +115,9 @@ static void from_mmap(int fd, uint64_t size, enum mode mode)
>>           */
>>          intel_require_memory(2, size, CHECK_RAM);
>>   
>> +       if ((mode & ~RO) == GTT)
>> +               gem_require_mmap_gtt(fd);
>> +
> 
> We need to stick arguments into mmap-offset buffers. Same is true for
> several of the "do we survive userspace being nasty with __user pointers"
> tests.
> 
>> diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
>> index a9383000..15c8440f 100644
>> --- a/tests/i915/gem_exec_schedule.c
>> +++ b/tests/i915/gem_exec_schedule.c
>> @@ -1236,6 +1236,7 @@ igt_main
>>                          igt_subtest_f("independent-%s", e->name) {
>>                                  igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
>>                                  igt_require(gem_can_store_dword(fd, e->exec_id | e->flags));
>> +                               gem_require_mmap_gtt(fd);
>>                                  independent(fd, e->exec_id | e->flags);
>>                          }
>>                  }
>> @@ -1328,8 +1329,10 @@ igt_main
>>                                  igt_subtest_f("wide-%s", e->name)
>>                                          wide(fd, e->exec_id | e->flags);
>>   
>> -                               igt_subtest_f("reorder-wide-%s", e->name)
>> +                               igt_subtest_f("reorder-wide-%s", e->name) {
>> +                                       gem_require_mmap_gtt(fd);
>>                                          reorder_wide(fd, e->exec_id | e->flags);
>> +                               }
>>   
>>                                  igt_subtest_f("smoketest-%s", e->name)
>>                                          smoketest(fd, e->exec_id | e->flags, 5);
> 
> Hmm. I would rather the basic scheduling tests remained functioning.

Didn't we have a convincing argument against using wc + sync?

Antonio

> 
>> diff --git a/tests/i915/gem_largeobject.c b/tests/i915/gem_largeobject.c
>> index 518396fa..a2d47edc 100644
>> --- a/tests/i915/gem_largeobject.c
>> +++ b/tests/i915/gem_largeobject.c
>> @@ -84,6 +84,8 @@ igt_simple_main
>>   
>>          fd = drm_open_driver(DRIVER_INTEL);
>>   
>> +       gem_require_mmap_gtt(fd);
> 
> Ok, not mmap-offset specific in future, but one of those fun challenges.
> 
>> diff --git a/tests/i915/gem_madvise.c b/tests/i915/gem_madvise.c
>> index 729a4d33..f4226a84 100644
>> --- a/tests/i915/gem_madvise.c
>> +++ b/tests/i915/gem_madvise.c
>> @@ -61,6 +61,8 @@ dontneed_before_mmap(void)
>>          uint32_t handle;
>>          char *ptr;
>>   
>> +       gem_require_mmap_gtt(fd);
> 
> Needs mmap-offset integration.
> 
>> diff --git a/tests/i915/gem_mmap_offset_exhaustion.c b/tests/i915/gem_mmap_offset_exhaustion.c
>> index 8c8e3fa2..86464231 100644
>> --- a/tests/i915/gem_mmap_offset_exhaustion.c
>> +++ b/tests/i915/gem_mmap_offset_exhaustion.c
>> @@ -82,6 +82,8 @@ igt_simple_main
>>   
>>          fd = drm_open_driver(DRIVER_INTEL);
>>   
>> +       gem_require_mmap_gtt(fd);
> 
> Some might say this became a more important test. Not sure if the test
> itself is the best strategy (vs the selftest approach), but it
> definitely shouldn't just be skipped for mmap-offset.
> 
>> diff --git a/tests/i915/gem_render_copy.c b/tests/i915/gem_render_copy.c
>> index 8d62a0f4..5757c547 100644
>> --- a/tests/i915/gem_render_copy.c
>> +++ b/tests/i915/gem_render_copy.c
>> @@ -572,6 +572,8 @@ static void test(data_t *data, uint32_t tiling, uint64_t ccs_modifier)
>>          int opt_dump_aub = igt_aub_dump_enabled();
>>          int num_src = ARRAY_SIZE(src);
>>   
>> +       gem_require_mmap_gtt(data->drm_fd);
> 
> We should make sure gem_render_copy remains available for debugging the
> rendercopy routines, I doubt they are going away.
> 
>> diff --git a/tests/i915/gem_userptr_blits.c b/tests/i915/gem_userptr_blits.c
>> index 8f8ddf43..9962e539 100644
>> --- a/tests/i915/gem_userptr_blits.c
>> +++ b/tests/i915/gem_userptr_blits.c
>> @@ -554,6 +554,8 @@ static int test_invalid_gtt_mapping(int fd)
>>          uint32_t handle;
>>          char *gtt, *map;
>>   
>> +       gem_require_mmap_gtt(fd);
> 
> userptr-blits needs mmap-offset enhancements. Principally, if we can
> mmap(MAP_FIXED) over top of an active userptr, we need to resolve that
> amicably.
> -Chris
> 
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Re: [igt-dev] [RFT v4 4/6] igt/i915: Require GTT mapping to be available when needed.

[Chris Wilson]

Quoting Antonio Argenziano (2019-03-27 21:05:52)
> 
> 
> On 25/03/19 16:36, Chris Wilson wrote:
> > Quoting Antonio Argenziano (2019-03-25 23:20:41)
> >> diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
> >> index a9383000..15c8440f 100644
> >> --- a/tests/i915/gem_exec_schedule.c
> >> +++ b/tests/i915/gem_exec_schedule.c
> >> @@ -1236,6 +1236,7 @@ igt_main
> >>                          igt_subtest_f("independent-%s", e->name) {
> >>                                  igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
> >>                                  igt_require(gem_can_store_dword(fd, e->exec_id | e->flags));
> >> +                               gem_require_mmap_gtt(fd);
> >>                                  independent(fd, e->exec_id | e->flags);
> >>                          }
> >>                  }
> >> @@ -1328,8 +1329,10 @@ igt_main
> >>                                  igt_subtest_f("wide-%s", e->name)
> >>                                          wide(fd, e->exec_id | e->flags);
> >>   
> >> -                               igt_subtest_f("reorder-wide-%s", e->name)
> >> +                               igt_subtest_f("reorder-wide-%s", e->name) {
> >> +                                       gem_require_mmap_gtt(fd);
> >>                                          reorder_wide(fd, e->exec_id | e->flags);
> >> +                               }
> >>   
> >>                                  igt_subtest_f("smoketest-%s", e->name)
> >>                                          smoketest(fd, e->exec_id | e->flags, 5);
> > 
> > Hmm. I would rather the basic scheduling tests remained functioning.
> 
> Didn't we have a convincing argument against using wc + sync?

Just the sync part iirc. So you just need to come up with an alternative
solution. What I've used elsewhere is to write the ring timestamp from
each batch and verify they are in the order I expect. That should work
just fine with anything... (The most complicated thing there is actually
determining the engine->mmio_base, and really we'd be better exporting
that from the kernel for simplicity.)

That's the start of a plan at least.
-Chris
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Re: [igt-dev] [RFT v4 4/6] igt/i915: Require GTT mapping to be available when needed.

[Antonio Argenziano]

On 27/03/19 14:19, Chris Wilson wrote:
> Quoting Antonio Argenziano (2019-03-27 21:05:52)
>>
>>
>> On 25/03/19 16:36, Chris Wilson wrote:
>>> Quoting Antonio Argenziano (2019-03-25 23:20:41)
>>>> diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
>>>> index a9383000..15c8440f 100644
>>>> --- a/tests/i915/gem_exec_schedule.c
>>>> +++ b/tests/i915/gem_exec_schedule.c
>>>> @@ -1236,6 +1236,7 @@ igt_main
>>>>                           igt_subtest_f("independent-%s", e->name) {
>>>>                                   igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
>>>>                                   igt_require(gem_can_store_dword(fd, e->exec_id | e->flags));
>>>> +                               gem_require_mmap_gtt(fd);
>>>>                                   independent(fd, e->exec_id | e->flags);
>>>>                           }
>>>>                   }
>>>> @@ -1328,8 +1329,10 @@ igt_main
>>>>                                   igt_subtest_f("wide-%s", e->name)
>>>>                                           wide(fd, e->exec_id | e->flags);
>>>>    
>>>> -                               igt_subtest_f("reorder-wide-%s", e->name)
>>>> +                               igt_subtest_f("reorder-wide-%s", e->name) {
>>>> +                                       gem_require_mmap_gtt(fd);
>>>>                                           reorder_wide(fd, e->exec_id | e->flags);
>>>> +                               }
>>>>    
>>>>                                   igt_subtest_f("smoketest-%s", e->name)
>>>>                                           smoketest(fd, e->exec_id | e->flags, 5);
>>>
>>> Hmm. I would rather the basic scheduling tests remained functioning.
>>
>> Didn't we have a convincing argument against using wc + sync?
> 
> Just the sync part iirc. So you just need to come up with an alternative
> solution. What I've used elsewhere is to write the ring timestamp from
> each batch and verify they are in the order I expect. That should work
> just fine with anything... (The most complicated thing there is actually
> determining the engine->mmio_base, and really we'd be better exporting
> that from the kernel for simplicity.)

I think I'm missing something, the issue we had was the async update of 
the single BO we use for all submissions (at least for reorder-wide) 
needed to go though gtt mapping, wouldn't that still be there even if we 
change the contents of the batch?

Antonio

> 
> That's the start of a plan at least.
> -Chris
> 
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Re: [igt-dev] [RFT v4 4/6] igt/i915: Require GTT mapping to be available when needed.

[Chris Wilson]

Quoting Antonio Argenziano (2019-04-11 19:13:13)
> 
> 
> On 27/03/19 14:19, Chris Wilson wrote:
> > Quoting Antonio Argenziano (2019-03-27 21:05:52)
> >>
> >>
> >> On 25/03/19 16:36, Chris Wilson wrote:
> >>> Quoting Antonio Argenziano (2019-03-25 23:20:41)
> >>>> diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
> >>>> index a9383000..15c8440f 100644
> >>>> --- a/tests/i915/gem_exec_schedule.c
> >>>> +++ b/tests/i915/gem_exec_schedule.c
> >>>> @@ -1236,6 +1236,7 @@ igt_main
> >>>>                           igt_subtest_f("independent-%s", e->name) {
> >>>>                                   igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
> >>>>                                   igt_require(gem_can_store_dword(fd, e->exec_id | e->flags));
> >>>> +                               gem_require_mmap_gtt(fd);
> >>>>                                   independent(fd, e->exec_id | e->flags);
> >>>>                           }
> >>>>                   }
> >>>> @@ -1328,8 +1329,10 @@ igt_main
> >>>>                                   igt_subtest_f("wide-%s", e->name)
> >>>>                                           wide(fd, e->exec_id | e->flags);
> >>>>    
> >>>> -                               igt_subtest_f("reorder-wide-%s", e->name)
> >>>> +                               igt_subtest_f("reorder-wide-%s", e->name) {
> >>>> +                                       gem_require_mmap_gtt(fd);
> >>>>                                           reorder_wide(fd, e->exec_id | e->flags);
> >>>> +                               }
> >>>>    
> >>>>                                   igt_subtest_f("smoketest-%s", e->name)
> >>>>                                           smoketest(fd, e->exec_id | e->flags, 5);
> >>>
> >>> Hmm. I would rather the basic scheduling tests remained functioning.
> >>
> >> Didn't we have a convincing argument against using wc + sync?
> > 
> > Just the sync part iirc. So you just need to come up with an alternative
> > solution. What I've used elsewhere is to write the ring timestamp from
> > each batch and verify they are in the order I expect. That should work
> > just fine with anything... (The most complicated thing there is actually
> > determining the engine->mmio_base, and really we'd be better exporting
> > that from the kernel for simplicity.)
> 
> I think I'm missing something, the issue we had was the async update of 
> the single BO we use for all submissions (at least for reorder-wide) 
> needed to go though gtt mapping, wouldn't that still be there even if we 
> change the contents of the batch?

I mean it should be possible to prove the scheduling order without
relying on modifying the batches. The timestamp is a good indicator of
the order, the only question is in setting up the submission to force a
scheduling decision -- and that usually means a fence to delay HW
submission until after all execbufs.

Losing these tests for future gen should be enough motivation to devise
a new set that exercise the same paths through the scheduler without the
drawable of needing async gtt modifications (if it was just async gtt,
async wc should be fine though -- I've forgotten the problem we ran into!).
-Chris
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Re: [igt-dev] [RFT v4 4/6] igt/i915: Require GTT mapping to be available when needed.

[Antonio Argenziano]

On 11/04/19 13:07, Chris Wilson wrote:
> Quoting Antonio Argenziano (2019-04-11 19:13:13)
>>
>>
>> On 27/03/19 14:19, Chris Wilson wrote:
>>> Quoting Antonio Argenziano (2019-03-27 21:05:52)
>>>>
>>>>
>>>> On 25/03/19 16:36, Chris Wilson wrote:
>>>>> Quoting Antonio Argenziano (2019-03-25 23:20:41)
>>>>>> diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
>>>>>> index a9383000..15c8440f 100644
>>>>>> --- a/tests/i915/gem_exec_schedule.c
>>>>>> +++ b/tests/i915/gem_exec_schedule.c
>>>>>> @@ -1236,6 +1236,7 @@ igt_main
>>>>>>                            igt_subtest_f("independent-%s", e->name) {
>>>>>>                                    igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
>>>>>>                                    igt_require(gem_can_store_dword(fd, e->exec_id | e->flags));
>>>>>> +                               gem_require_mmap_gtt(fd);
>>>>>>                                    independent(fd, e->exec_id | e->flags);
>>>>>>                            }
>>>>>>                    }
>>>>>> @@ -1328,8 +1329,10 @@ igt_main
>>>>>>                                    igt_subtest_f("wide-%s", e->name)
>>>>>>                                            wide(fd, e->exec_id | e->flags);
>>>>>>     
>>>>>> -                               igt_subtest_f("reorder-wide-%s", e->name)
>>>>>> +                               igt_subtest_f("reorder-wide-%s", e->name) {
>>>>>> +                                       gem_require_mmap_gtt(fd);
>>>>>>                                            reorder_wide(fd, e->exec_id | e->flags);
>>>>>> +                               }
>>>>>>     
>>>>>>                                    igt_subtest_f("smoketest-%s", e->name)
>>>>>>                                            smoketest(fd, e->exec_id | e->flags, 5);
>>>>>
>>>>> Hmm. I would rather the basic scheduling tests remained functioning.
>>>>
>>>> Didn't we have a convincing argument against using wc + sync?
>>>
>>> Just the sync part iirc. So you just need to come up with an alternative
>>> solution. What I've used elsewhere is to write the ring timestamp from
>>> each batch and verify they are in the order I expect. That should work
>>> just fine with anything... (The most complicated thing there is actually
>>> determining the engine->mmio_base, and really we'd be better exporting
>>> that from the kernel for simplicity.)
>>
>> I think I'm missing something, the issue we had was the async update of
>> the single BO we use for all submissions (at least for reorder-wide)
>> needed to go though gtt mapping, wouldn't that still be there even if we
>> change the contents of the batch?
> 
> I mean it should be possible to prove the scheduling order without
> relying on modifying the batches. The timestamp is a good indicator of
> the order, the only question is in setting up the submission to force a
> scheduling decision -- and that usually means a fence to delay HW
> submission until after all execbufs.

Oh, now I get it.

> 
> Losing these tests for future gen should be enough motivation to devise
> a new set that exercise the same paths through the scheduler without the
> drawable of needing async gtt modifications (if it was just async gtt,
> async wc should be fine though -- I've forgotten the problem we ran into!).

Then we should be fine, it was just a concern, we didn't actually hit an 
error. If I send it again, will fi-skl-lmem run it with all the lmem 
patches applied?

Antonio

> -Chris
> 
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Re: [igt-dev] [RFT v4 4/6] igt/i915: Require GTT mapping to be available when needed.

[Chris Wilson]

Quoting Antonio Argenziano (2019-03-27 21:05:52)
> 
> 
> On 25/03/19 16:36, Chris Wilson wrote:
> > Quoting Antonio Argenziano (2019-03-25 23:20:41)
> >> diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
> >> index 47f6b92b..2e4c0335 100644
> >> --- a/lib/igt_dummyload.c
> >> +++ b/lib/igt_dummyload.c
> >> @@ -117,9 +117,11 @@ emit_recursive_batch(igt_spin_t *spin,
> >>          obj[BATCH].handle = gem_create(fd, BATCH_SIZE);
> >>          batch = __gem_mmap__wc(fd, obj[BATCH].handle,
> >>                                 0, BATCH_SIZE, PROT_WRITE);
> >> -       if (!batch)
> >> +       if (!batch) {
> >> +               gem_require_mmap_gtt(fd);
> >>                  batch = gem_mmap__gtt(fd, obj[BATCH].handle,
> >>                                          BATCH_SIZE, PROT_WRITE);
> > 
> > batch = __gem_mmap__gtt();
> > igt_require(batch) ?
> > 
> > Possibly not as informative as gem_require_mmap_gtt() So ~o~
> > 
> >> diff --git a/tests/i915/gem_concurrent_all.c b/tests/i915/gem_concurrent_all.c
> >> index f719b0a1..e4fc1426 100644
> >> --- a/tests/i915/gem_concurrent_all.c
> >> +++ b/tests/i915/gem_concurrent_all.c
> >> @@ -1422,6 +1422,7 @@ static void cpu_require(void)
> >>   
> >>   static void gtt_require(void)
> >>   {
> >> +       gem_require_mmap_gtt(fd);
> >>   }
> > 
> > Needs the combinatorial explosion to exercise accessing via mmap-offset.
> > If you only update one stress test, update this one.
> 
> Don't we get the mmap-offset coverage by default in the wc test cases or 
> do you mean to use the mmap_offset IOCTL to mmap GTT?

No, I forgot that the library was going to automatic replacement of
gem_mmap__wc and friends. Must update this stress test, it is useful
simply because it runs forever and ends up being quite quite brutal.
(Even the trivial starting tests are too often enough to reveal issues.)
-Chris
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Re: [igt-dev] [RFT v4 4/6] igt/i915: Require GTT mapping to be available when needed.

[Antonio Argenziano]

On 27/03/19 14:24, Chris Wilson wrote:
> Quoting Antonio Argenziano (2019-03-27 21:05:52)
>>
>>
>> On 25/03/19 16:36, Chris Wilson wrote:
>>> Quoting Antonio Argenziano (2019-03-25 23:20:41)
>>>> diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
>>>> index 47f6b92b..2e4c0335 100644
>>>> --- a/lib/igt_dummyload.c
>>>> +++ b/lib/igt_dummyload.c
>>>> @@ -117,9 +117,11 @@ emit_recursive_batch(igt_spin_t *spin,
>>>>           obj[BATCH].handle = gem_create(fd, BATCH_SIZE);
>>>>           batch = __gem_mmap__wc(fd, obj[BATCH].handle,
>>>>                                  0, BATCH_SIZE, PROT_WRITE);
>>>> -       if (!batch)
>>>> +       if (!batch) {
>>>> +               gem_require_mmap_gtt(fd);
>>>>                   batch = gem_mmap__gtt(fd, obj[BATCH].handle,
>>>>                                           BATCH_SIZE, PROT_WRITE);
>>>
>>> batch = __gem_mmap__gtt();
>>> igt_require(batch) ?
>>>
>>> Possibly not as informative as gem_require_mmap_gtt() So ~o~
>>>
>>>> diff --git a/tests/i915/gem_concurrent_all.c b/tests/i915/gem_concurrent_all.c
>>>> index f719b0a1..e4fc1426 100644
>>>> --- a/tests/i915/gem_concurrent_all.c
>>>> +++ b/tests/i915/gem_concurrent_all.c
>>>> @@ -1422,6 +1422,7 @@ static void cpu_require(void)
>>>>    
>>>>    static void gtt_require(void)
>>>>    {
>>>> +       gem_require_mmap_gtt(fd);
>>>>    }
>>>
>>> Needs the combinatorial explosion to exercise accessing via mmap-offset.
>>> If you only update one stress test, update this one.
>>
>> Don't we get the mmap-offset coverage by default in the wc test cases or
>> do you mean to use the mmap_offset IOCTL to mmap GTT?
> 
> No, I forgot that the library was going to automatic replacement of
> gem_mmap__wc and friends. Must update this stress test, it is useful
> simply because it runs forever and ends up being quite quite brutal.
> (Even the trivial starting tests are too often enough to reveal issues.)

AFAICT it already iterates over all mappings which include WC and CPU. 
We only skip gtt when gtt mapping is not available. What needs updating?

Antonio

> -Chris
> 
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Re: [igt-dev] [RFT v4 4/6] igt/i915: Require GTT mapping to be available when needed.

[Chris Wilson]

Quoting Antonio Argenziano (2019-04-05 19:00:57)
> 
> 
> On 27/03/19 14:24, Chris Wilson wrote:
> > Quoting Antonio Argenziano (2019-03-27 21:05:52)
> >>
> >>
> >> On 25/03/19 16:36, Chris Wilson wrote:
> >>> Quoting Antonio Argenziano (2019-03-25 23:20:41)
> >>>> diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
> >>>> index 47f6b92b..2e4c0335 100644
> >>>> --- a/lib/igt_dummyload.c
> >>>> +++ b/lib/igt_dummyload.c
> >>>> @@ -117,9 +117,11 @@ emit_recursive_batch(igt_spin_t *spin,
> >>>>           obj[BATCH].handle = gem_create(fd, BATCH_SIZE);
> >>>>           batch = __gem_mmap__wc(fd, obj[BATCH].handle,
> >>>>                                  0, BATCH_SIZE, PROT_WRITE);
> >>>> -       if (!batch)
> >>>> +       if (!batch) {
> >>>> +               gem_require_mmap_gtt(fd);
> >>>>                   batch = gem_mmap__gtt(fd, obj[BATCH].handle,
> >>>>                                           BATCH_SIZE, PROT_WRITE);
> >>>
> >>> batch = __gem_mmap__gtt();
> >>> igt_require(batch) ?
> >>>
> >>> Possibly not as informative as gem_require_mmap_gtt() So ~o~
> >>>
> >>>> diff --git a/tests/i915/gem_concurrent_all.c b/tests/i915/gem_concurrent_all.c
> >>>> index f719b0a1..e4fc1426 100644
> >>>> --- a/tests/i915/gem_concurrent_all.c
> >>>> +++ b/tests/i915/gem_concurrent_all.c
> >>>> @@ -1422,6 +1422,7 @@ static void cpu_require(void)
> >>>>    
> >>>>    static void gtt_require(void)
> >>>>    {
> >>>> +       gem_require_mmap_gtt(fd);
> >>>>    }
> >>>
> >>> Needs the combinatorial explosion to exercise accessing via mmap-offset.
> >>> If you only update one stress test, update this one.
> >>
> >> Don't we get the mmap-offset coverage by default in the wc test cases or
> >> do you mean to use the mmap_offset IOCTL to mmap GTT?
> > 
> > No, I forgot that the library was going to automatic replacement of
> > gem_mmap__wc and friends. Must update this stress test, it is useful
> > simply because it runs forever and ends up being quite quite brutal.
> > (Even the trivial starting tests are too often enough to reveal issues.)
> 
> AFAICT it already iterates over all mappings which include WC and CPU. 
> We only skip gtt when gtt mapping is not available. What needs updating?

I just meant that this is one of those "must haves". It's simply too
useful for finding GEM instabilities (mostly because it runs for such a
long time ;).
-Chris
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Re: [igt-dev] [RFT v4 4/6] igt/i915: Require GTT mapping to be available when needed.

[Antonio Argenziano]

On 27/03/19 14:05, Antonio Argenziano wrote:
> 
> 
> On 25/03/19 16:36, Chris Wilson wrote:
>> Quoting Antonio Argenziano (2019-03-25 23:20:41)

>>> diff --git a/tests/i915/gem_render_copy.c b/tests/i915/gem_render_copy.c
>>> index 8d62a0f4..5757c547 100644
>>> --- a/tests/i915/gem_render_copy.c
>>> +++ b/tests/i915/gem_render_copy.c
>>> @@ -572,6 +572,8 @@ static void test(data_t *data, uint32_t tiling, 
>>> uint64_t ccs_modifier)
>>>          int opt_dump_aub = igt_aub_dump_enabled();
>>>          int num_src = ARRAY_SIZE(src);
>>> +       gem_require_mmap_gtt(data->drm_fd);
>>
>> We should make sure gem_render_copy remains available for debugging the
>> rendercopy routines, I doubt they are going away.

We can only keep the one that doesn't do tiling AFAICT.

Antonio

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Re: [igt-dev] [RFT v4 4/6] igt/i915: Require GTT mapping to be available when needed.

[Chris Wilson]

Quoting Antonio Argenziano (2019-04-11 19:13:20)
> 
> 
> On 27/03/19 14:05, Antonio Argenziano wrote:
> > 
> > 
> > On 25/03/19 16:36, Chris Wilson wrote:
> >> Quoting Antonio Argenziano (2019-03-25 23:20:41)
> 
> >>> diff --git a/tests/i915/gem_render_copy.c b/tests/i915/gem_render_copy.c
> >>> index 8d62a0f4..5757c547 100644
> >>> --- a/tests/i915/gem_render_copy.c
> >>> +++ b/tests/i915/gem_render_copy.c
> >>> @@ -572,6 +572,8 @@ static void test(data_t *data, uint32_t tiling, 
> >>> uint64_t ccs_modifier)
> >>>          int opt_dump_aub = igt_aub_dump_enabled();
> >>>          int num_src = ARRAY_SIZE(src);
> >>> +       gem_require_mmap_gtt(data->drm_fd);
> >>
> >> We should make sure gem_render_copy remains available for debugging the
> >> rendercopy routines, I doubt they are going away.
> 
> We can only keep the one that doesn't do tiling AFAICT.

Detiling on the cpu is easy enough, or detile on the gpu. The latter is
a little less bullet proof (2 rendercopies to debug for the price of 1).
-Chris
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Re: [igt-dev] [RFT v4 4/6] igt/i915: Require GTT mapping to be available when needed.

[Katarzyna Dec]

On Mon, Mar 25, 2019 at 04:20:41PM -0700, Antonio Argenziano wrote:
> With the GTT aperture becoming unavailable on certain platforms, tests
> that target that mapping need to skip if such mapping is not available.
> 
> Cc: Katarzyna Dec <katarzyna.dec@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Signed-off-by: Antonio Argenziano <antonio.argenziano@intel.com>
> ---
>  lib/igt_dummyload.c                     |  4 +++-
>  lib/igt_fb.c                            |  5 +++--
>  tests/i915/gem_concurrent_all.c         |  1 +
>  tests/i915/gem_ctx_sseu.c               |  4 +++-
>  tests/i915/gem_exec_basic.c             |  1 +
>  tests/i915/gem_exec_faulting_reloc.c    |  2 ++
>  tests/i915/gem_exec_flush.c             |  6 ++++++
>  tests/i915/gem_exec_reloc.c             |  7 +++++++
>  tests/i915/gem_exec_schedule.c          |  5 ++++-
>  tests/i915/gem_fence_thrash.c           |  6 ++++++
>  tests/i915/gem_gtt_cpu_tlb.c            |  1 +
>  tests/i915/gem_gtt_hog.c                |  1 +
>  tests/i915/gem_gtt_speed.c              |  1 +
>  tests/i915/gem_largeobject.c            |  2 ++
>  tests/i915/gem_madvise.c                |  4 ++++
>  tests/i915/gem_mmap_gtt.c               |  4 +++-
>  tests/i915/gem_mmap_offset_exhaustion.c |  2 ++
>  tests/i915/gem_mmap_wc.c                |  2 ++
>  tests/i915/gem_persistent_relocs.c      |  2 ++
>  tests/i915/gem_pwrite_pread.c           |  6 ++++++
>  tests/i915/gem_reloc_vs_gpu.c           | 21 ++++++++++++---------
>  tests/i915/gem_render_copy.c            |  2 ++
>  tests/i915/gem_set_tiling_vs_gtt.c      |  2 ++
>  tests/i915/gem_set_tiling_vs_pwrite.c   |  2 ++
>  tests/i915/gem_shrink.c                 | 14 +++++++++++---
>  tests/i915/gem_storedw_loop.c           |  9 +++++++++
>  tests/i915/gem_streaming_writes.c       | 16 ++++++++++++++--
>  tests/i915/gem_tiled_fence_blits.c      |  1 +
>  tests/i915/gem_tiled_pread_basic.c      |  1 +
>  tests/i915/gem_tiled_pread_pwrite.c     |  4 +++-
>  tests/i915/gem_tiled_swapping.c         |  2 ++
>  tests/i915/gem_tiled_wb.c               |  2 ++
>  tests/i915/gem_tiled_wc.c               |  1 +
>  tests/i915/gem_tiling_max_stride.c      |  3 ++-
>  tests/i915/gem_userptr_blits.c          | 10 +++++++++-
>  tests/i915/i915_pm_rpm.c                |  9 +++++++++
>  tests/i915/i915_suspend.c               |  2 ++
>  tests/kms_draw_crc.c                    |  8 ++++++--
>  tests/kms_fence_pin_leak.c              |  2 ++
>  tests/kms_frontbuffer_tracking.c        |  3 +++
>  tests/kms_psr.c                         |  4 ++++
>  tests/prime_mmap.c                      |  2 ++
>  tests/prime_mmap_coherency.c            |  1 +
>  tests/prime_vgem.c                      |  5 +++++
>  44 files changed, 167 insertions(+), 25 deletions(-)
> 
> diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
> index 47f6b92b..2e4c0335 100644
> --- a/lib/igt_dummyload.c
> +++ b/lib/igt_dummyload.c
> @@ -117,9 +117,11 @@ emit_recursive_batch(igt_spin_t *spin,
>  	obj[BATCH].handle = gem_create(fd, BATCH_SIZE);
>  	batch = __gem_mmap__wc(fd, obj[BATCH].handle,
>  			       0, BATCH_SIZE, PROT_WRITE);
> -	if (!batch)
> +	if (!batch) {
> +		gem_require_mmap_gtt(fd);
>  		batch = gem_mmap__gtt(fd, obj[BATCH].handle,
>  				       	BATCH_SIZE, PROT_WRITE);
> +	}
>  	gem_set_domain(fd, obj[BATCH].handle,
>  			I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
>  	execbuf->buffer_count++;
> diff --git a/lib/igt_fb.c b/lib/igt_fb.c
> index bad1d1fb..068cd7fe 100644
> --- a/lib/igt_fb.c
> +++ b/lib/igt_fb.c
> @@ -1746,10 +1746,11 @@ static void *map_bo(int fd, struct igt_fb *fb)
>  	if (fb->is_dumb)
>  		ptr = kmstest_dumb_map_buffer(fd, fb->gem_handle, fb->size,
>  					      PROT_READ | PROT_WRITE);
> -	else if (is_i915_device(fd))
> +	else if (is_i915_device(fd)) {
> +		gem_require_mmap_gtt(fd);
>  		ptr = gem_mmap__gtt(fd, fb->gem_handle, fb->size,
>  				    PROT_READ | PROT_WRITE);
I wasn't able to easily apply this patch see how it looks in the code, but from
here it is like closing '}' is missing. Please double check :)
> -	else if (is_vc4_device(fd))
> +	} else if (is_vc4_device(fd))
>  		ptr = igt_vc4_mmap_bo(fd, fb->gem_handle, fb->size,
>  				      PROT_READ | PROT_WRITE);
>  	else
> diff --git a/tests/i915/gem_concurrent_all.c b/tests/i915/gem_concurrent_all.c
> index f719b0a1..e4fc1426 100644
> --- a/tests/i915/gem_concurrent_all.c
> +++ b/tests/i915/gem_concurrent_all.c
> @@ -1422,6 +1422,7 @@ static void cpu_require(void)
>  
>  static void gtt_require(void)
>  {
> +	gem_require_mmap_gtt(fd);
>  }
>  
>  static void bcs_require(void)
> diff --git a/tests/i915/gem_ctx_sseu.c b/tests/i915/gem_ctx_sseu.c
> index 3afa5c15..bf1b50d5 100644
> --- a/tests/i915/gem_ctx_sseu.c
> +++ b/tests/i915/gem_ctx_sseu.c
> @@ -528,8 +528,10 @@ igt_main
>  		igt_subtest("invalid-sseu")
>  			test_invalid_sseu(fd);
>  
> -		igt_subtest("ggtt-args")
> +		igt_subtest("ggtt-args") {
> +			gem_require_mmap_gtt(fd);
>  			test_ggtt_args(fd);
> +		}
>  
>  		igt_subtest("engines")
>  			test_engines(fd);
> diff --git a/tests/i915/gem_exec_basic.c b/tests/i915/gem_exec_basic.c
> index dcb83864..8537665f 100644
> --- a/tests/i915/gem_exec_basic.c
> +++ b/tests/i915/gem_exec_basic.c
> @@ -93,6 +93,7 @@ static void gtt(int fd, unsigned ring)
>  	struct drm_i915_gem_exec_object2 *exec;
>  	uint32_t handle;
>  
> +	gem_require_mmap_gtt(fd);
>  	gem_require_ring(fd, ring);
>  
>  	handle = gem_create(fd, 4096);
> diff --git a/tests/i915/gem_exec_faulting_reloc.c b/tests/i915/gem_exec_faulting_reloc.c
> index 6b05e43f..9db80f54 100644
> --- a/tests/i915/gem_exec_faulting_reloc.c
> +++ b/tests/i915/gem_exec_faulting_reloc.c
> @@ -173,6 +173,8 @@ static void run(int object_size)
>  
>  	fd = drm_open_driver(DRIVER_INTEL);
>  	igt_require_gem(fd);
> +	gem_require_mmap_gtt(fd);
> +
>  	devid = intel_get_drm_devid(fd);
>  	handle = gem_create(fd, 4096);
>  	src = gem_create(fd, object_size);
> diff --git a/tests/i915/gem_exec_flush.c b/tests/i915/gem_exec_flush.c
> index f820b2a8..29b13803 100644
> --- a/tests/i915/gem_exec_flush.c
> +++ b/tests/i915/gem_exec_flush.c
> @@ -79,6 +79,9 @@ static void run(int fd, unsigned ring, int nchild, int timeout,
>  {
>  	const int gen = intel_gen(intel_get_drm_devid(fd));
>  
> +	if (!(flags & COHERENT) && !(flags & WC))
> +		gem_require_mmap_gtt(fd);
> +
>  	/* The crux of this testing is whether writes by the GPU are coherent
>  	 * from the CPU.
>  	 *
> @@ -586,6 +589,7 @@ igt_main
>  		fd = drm_open_driver(DRIVER_INTEL);
>  		igt_require_gem(fd);
>  		gem_require_mmap_wc(fd);
> +		gem_require_mmap_gtt(fd);
Is mmap_gtt in conflict with mmap_wc (we use both here)? Or I am wrong?
>  		igt_require(gem_can_store_dword(fd, 0));
>  		igt_info("Has LLC? %s\n", yesno(gem_has_llc(fd)));
>  
> @@ -614,11 +618,13 @@ igt_main
>  				      b->name,
>  				      e->name)
>  				batch(fd, ring, ncpus, timeout, b->mode, 0);
> +
>  			igt_subtest_f("%sbatch-%s-%s-wb",
>  				      b == batches && e->exec_id == 0 ? "basic-" : "",
>  				      b->name,
>  				      e->name)
>  				batch(fd, ring, ncpus, timeout, b->mode, COHERENT);
> +
>  			igt_subtest_f("%sbatch-%s-%s-cmd",
>  				      b == batches && e->exec_id == 0 ? "basic-" : "",
>  				      b->name,
> diff --git a/tests/i915/gem_exec_reloc.c b/tests/i915/gem_exec_reloc.c
> index 837f60a6..bb4eec31 100644
> --- a/tests/i915/gem_exec_reloc.c
> +++ b/tests/i915/gem_exec_reloc.c
> @@ -115,6 +115,9 @@ static void from_mmap(int fd, uint64_t size, enum mode mode)
>  	 */
>  	intel_require_memory(2, size, CHECK_RAM);
>  
> +	if ((mode & ~RO) == GTT)
> +		gem_require_mmap_gtt(fd);
> +
>  	memset(&obj, 0, sizeof(obj));
>  	obj.handle = gem_create(fd, 4096);
>  	gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
> @@ -342,6 +345,9 @@ static void basic_reloc(int fd, unsigned before, unsigned after, unsigned flags)
>  	const uint32_t bbe = MI_BATCH_BUFFER_END;
>  	unsigned int reloc_offset;
>  
> +	if ((before | after) & I915_GEM_DOMAIN_GTT)
> +		gem_require_mmap_gtt(fd);
Why do we need such check here?
> +
>  	memset(&obj, 0, sizeof(obj));
>  	obj.handle = gem_create(fd, OBJSZ);
>  	obj.relocs_ptr = to_user_pointer(&reloc);
> @@ -711,6 +717,7 @@ igt_main
>  					      f->name) {
>  					if ((m->before | m->after) & I915_GEM_DOMAIN_WC)
>  						igt_require(gem_mmap__has_wc(fd));
> +
>  					basic_reloc(fd, m->before, m->after, f->flags);
>  				}
>  			}
> diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
> index a9383000..15c8440f 100644
> --- a/tests/i915/gem_exec_schedule.c
> +++ b/tests/i915/gem_exec_schedule.c
> @@ -1236,6 +1236,7 @@ igt_main
>  			igt_subtest_f("independent-%s", e->name) {
>  				igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags));
>  				igt_require(gem_can_store_dword(fd, e->exec_id | e->flags));
> +				gem_require_mmap_gtt(fd);
>  				independent(fd, e->exec_id | e->flags);
>  			}
>  		}
> @@ -1328,8 +1329,10 @@ igt_main
>  				igt_subtest_f("wide-%s", e->name)
>  					wide(fd, e->exec_id | e->flags);
>  
> -				igt_subtest_f("reorder-wide-%s", e->name)
> +				igt_subtest_f("reorder-wide-%s", e->name) {
> +					gem_require_mmap_gtt(fd);
>  					reorder_wide(fd, e->exec_id | e->flags);
> +				}
>  
>  				igt_subtest_f("smoketest-%s", e->name)
>  					smoketest(fd, e->exec_id | e->flags, 5);
> diff --git a/tests/i915/gem_fence_thrash.c b/tests/i915/gem_fence_thrash.c
> index 2d7fb2ff..5567e37e 100644
> --- a/tests/i915/gem_fence_thrash.c
> +++ b/tests/i915/gem_fence_thrash.c
> @@ -236,6 +236,12 @@ igt_main
>  {
>  	igt_skip_on_simulation();
>  
> +	igt_fixture {
> +		int fd = drm_open_driver(DRIVER_INTEL);
> +		igt_require(gem_available_fences(fd) > 0); /* GTT mapping available */
> +		close(fd);
> +	}
> +
>  	igt_subtest("bo-write-verify-none")
>  		igt_assert(run_test(0, bo_write_verify, I915_TILING_NONE, 80) == 0);
>  
> diff --git a/tests/i915/gem_gtt_cpu_tlb.c b/tests/i915/gem_gtt_cpu_tlb.c
> index cf3c543d..02682a0d 100644
> --- a/tests/i915/gem_gtt_cpu_tlb.c
> +++ b/tests/i915/gem_gtt_cpu_tlb.c
> @@ -79,6 +79,7 @@ igt_simple_main
>  	igt_skip_on_simulation();
>  
>  	fd = drm_open_driver(DRIVER_INTEL);
> +	gem_require_mmap_gtt(fd);
>  
>  	handle = gem_create(fd, OBJ_SIZE);
>  
> diff --git a/tests/i915/gem_gtt_hog.c b/tests/i915/gem_gtt_hog.c
> index ca730649..b2eea679 100644
> --- a/tests/i915/gem_gtt_hog.c
> +++ b/tests/i915/gem_gtt_hog.c
> @@ -161,6 +161,7 @@ igt_simple_main
>  	/* check for an intel gpu before goint nuts. */
>  	int fd = drm_open_driver(DRIVER_INTEL);
>  	igt_require_gem(fd);
> +	gem_require_mmap_gtt(fd);
>  	close(fd);
>  
>  	igt_skip_on_simulation();
> diff --git a/tests/i915/gem_gtt_speed.c b/tests/i915/gem_gtt_speed.c
> index 3d726c4e..f1778370 100644
> --- a/tests/i915/gem_gtt_speed.c
> +++ b/tests/i915/gem_gtt_speed.c
> @@ -116,6 +116,7 @@ int main(int argc, char **argv)
>  	buf = malloc(size);
>  	memset(buf, 0, size);
>  	fd = drm_open_driver(DRIVER_INTEL);
> +	gem_require_mmap_gtt(fd);
>  
>  	handle = gem_create(fd, size);
>  	igt_assert(handle);
> diff --git a/tests/i915/gem_largeobject.c b/tests/i915/gem_largeobject.c
> index 518396fa..a2d47edc 100644
> --- a/tests/i915/gem_largeobject.c
> +++ b/tests/i915/gem_largeobject.c
> @@ -84,6 +84,8 @@ igt_simple_main
>  
>  	fd = drm_open_driver(DRIVER_INTEL);
>  
> +	gem_require_mmap_gtt(fd);
> +
>  	test_large_object(fd);
>  
>  	free(data);
> diff --git a/tests/i915/gem_madvise.c b/tests/i915/gem_madvise.c
> index 729a4d33..f4226a84 100644
> --- a/tests/i915/gem_madvise.c
> +++ b/tests/i915/gem_madvise.c
> @@ -61,6 +61,8 @@ dontneed_before_mmap(void)
>  	uint32_t handle;
>  	char *ptr;
>  
> +	gem_require_mmap_gtt(fd);
> +
>  	handle = gem_create(fd, OBJECT_SIZE);
>  	gem_madvise(fd, handle, I915_MADV_DONTNEED);
>  	ptr = gem_mmap__gtt(fd, handle, OBJECT_SIZE, PROT_READ | PROT_WRITE);
> @@ -89,6 +91,8 @@ dontneed_after_mmap(void)
>  	uint32_t handle;
>  	char *ptr;
>  
> +	gem_require_mmap_gtt(fd);
> +
>  	handle = gem_create(fd, OBJECT_SIZE);
>  	ptr = gem_mmap__gtt(fd, handle, OBJECT_SIZE, PROT_READ | PROT_WRITE);
>  	igt_assert(ptr);
> diff --git a/tests/i915/gem_mmap_gtt.c b/tests/i915/gem_mmap_gtt.c
> index 639de190..de4a5bb5 100644
> --- a/tests/i915/gem_mmap_gtt.c
> +++ b/tests/i915/gem_mmap_gtt.c
> @@ -874,8 +874,10 @@ igt_main
>  	if (igt_run_in_simulation())
>  		OBJECT_SIZE = 1 * 1024 * 1024;
>  
> -	igt_fixture
> +	igt_fixture {
>  		fd = drm_open_driver(DRIVER_INTEL);
> +		gem_require_mmap_gtt(fd);
> +	}
>  
>  	igt_subtest("bad-object") {
>  		uint32_t real_handle = gem_create(fd, 4096);
> diff --git a/tests/i915/gem_mmap_offset_exhaustion.c b/tests/i915/gem_mmap_offset_exhaustion.c
> index 8c8e3fa2..86464231 100644
> --- a/tests/i915/gem_mmap_offset_exhaustion.c
> +++ b/tests/i915/gem_mmap_offset_exhaustion.c
> @@ -82,6 +82,8 @@ igt_simple_main
>  
>  	fd = drm_open_driver(DRIVER_INTEL);
>  
> +	gem_require_mmap_gtt(fd);
> +
>  	/* we have 32bit of address space, so try to fit one MB more
>  	 * than that. */
>  	for (i = 0; i < 4096 + 1; i++)
> diff --git a/tests/i915/gem_mmap_wc.c b/tests/i915/gem_mmap_wc.c
> index e3ffc5ad..3c33034c 100644
> --- a/tests/i915/gem_mmap_wc.c
> +++ b/tests/i915/gem_mmap_wc.c
> @@ -334,6 +334,8 @@ test_write_gtt_read_wc(int fd)
>  	uint32_t handle;
>  	uint32_t *src, *dst;
>  
> +	gem_require_mmap_gtt(fd);
> +
>  	handle = gem_create(fd, OBJECT_SIZE);
>  	set_domain(fd, handle);
>  
> diff --git a/tests/i915/gem_persistent_relocs.c b/tests/i915/gem_persistent_relocs.c
> index 452fe686..17266c48 100644
> --- a/tests/i915/gem_persistent_relocs.c
> +++ b/tests/i915/gem_persistent_relocs.c
> @@ -199,6 +199,8 @@ static void do_test(int fd, bool faulting_reloc)
>  	uint32_t test;
>  	int i, repeat;
>  
> +	gem_require_mmap_gtt(fd);
> +
Why you are adding this check here not in main? Here it is somehow hidden, in
main would be more visible.
>  	if (faulting_reloc)
>  		igt_disable_prefault();
>  
> diff --git a/tests/i915/gem_pwrite_pread.c b/tests/i915/gem_pwrite_pread.c
> index f91fc7c4..43b3987a 100644
> --- a/tests/i915/gem_pwrite_pread.c
> +++ b/tests/i915/gem_pwrite_pread.c
> @@ -182,6 +182,8 @@ static void test_as_gtt_mmap(int fd, uint32_t src, uint32_t dst, int len)
>  	int i;
>  	BUILD_EXEC;
>  
> +	gem_require_mmap_gtt(fd);
> +
>  	src_ptr = gem_mmap__gtt(fd, src, OBJECT_SIZE, PROT_WRITE);
>  	dst_ptr = gem_mmap__gtt(fd, dst, OBJECT_SIZE, PROT_READ);
>  
> @@ -309,6 +311,8 @@ int main(int argc, char **argv)
>  		for (count = 1; count <= 1<<17; count <<= 1) {
>  			struct timeval start, end;
>  
> +			gem_require_mmap_gtt(fd);
> +
>  			gettimeofday(&start, NULL);
>  			as_gtt_mmap(fd, src, dst, tmp, object_size, count);
>  			gettimeofday(&end, NULL);
> @@ -387,6 +391,8 @@ int main(int argc, char **argv)
>  		for (count = 1; count <= 1<<17; count <<= 1) {
>  			struct timeval start, end;
>  
> +			gem_require_mmap_gtt(fd);
> +
>  			gettimeofday(&start, NULL);
>  			as_gtt_mmap(fd, src, dst, tmp, object_size, count);
>  			gettimeofday(&end, NULL);
> diff --git a/tests/i915/gem_reloc_vs_gpu.c b/tests/i915/gem_reloc_vs_gpu.c
> index d421e434..e1475a1f 100644
> --- a/tests/i915/gem_reloc_vs_gpu.c
> +++ b/tests/i915/gem_reloc_vs_gpu.c
> @@ -159,17 +159,17 @@ static void reloc_and_emit(int fd, drm_intel_bo *target_bo, bool faulting_reloc)
>  	 */
>  	reloc[0].presumed_offset = -1;
>  
> -	handle_relocs = gem_create(fd, 4096);
> -	gem_write(fd, handle_relocs, 0, reloc, sizeof(reloc));
> -	gtt_relocs = gem_mmap__gtt(fd, handle_relocs, 4096,
> -				   PROT_READ | PROT_WRITE);
> -
>  	exec[1].handle = special_bo->handle;
>  	exec[1].relocation_count = 1;
>  	/* A newly mmap gtt bo will fault on first access. */
> -	if (faulting_reloc)
> +	if (faulting_reloc) {
> +		handle_relocs = gem_create(fd, 4096);
> +		gem_write(fd, handle_relocs, 0, reloc, sizeof(reloc));
> +		gtt_relocs = gem_mmap__gtt(fd, handle_relocs, 4096,
> +						PROT_READ | PROT_WRITE);
> +
>  		exec[1].relocs_ptr = to_user_pointer(gtt_relocs);
> -	else
> +	} else
>  		exec[1].relocs_ptr = to_user_pointer(reloc);
>  
>  	execbuf.buffers_ptr = to_user_pointer(exec);
> @@ -180,7 +180,8 @@ static void reloc_and_emit(int fd, drm_intel_bo *target_bo, bool faulting_reloc)
>  
>  	gem_execbuf(fd, &execbuf);
>  
> -	gem_close(fd, handle_relocs);
> +	if (faulting_reloc)
> +		gem_close(fd, handle_relocs);
>  }
>  
>  static igt_hang_t no_hang(int fd)
> @@ -201,8 +202,10 @@ static void do_test(int fd, bool faulting_reloc,
>  	uint32_t test;
>  	int i;
>  
> -	if (faulting_reloc)
> +	if (faulting_reloc) {
> +		gem_require_mmap_gtt(fd);
>  		igt_disable_prefault();
> +	}
>  
>  	act_size = 2048;
>  	dummy_bo = drm_intel_bo_alloc_tiled(bufmgr, "tiled dummy_bo", act_size, act_size,
> diff --git a/tests/i915/gem_render_copy.c b/tests/i915/gem_render_copy.c
> index 8d62a0f4..5757c547 100644
> --- a/tests/i915/gem_render_copy.c
> +++ b/tests/i915/gem_render_copy.c
> @@ -572,6 +572,8 @@ static void test(data_t *data, uint32_t tiling, uint64_t ccs_modifier)
>  	int opt_dump_aub = igt_aub_dump_enabled();
>  	int num_src = ARRAY_SIZE(src);
>  
> +	gem_require_mmap_gtt(data->drm_fd);
> +
>  	/* no Yf before gen9 */
>  	if (intel_gen(data->devid) < 9)
>  		num_src--;
> diff --git a/tests/i915/gem_set_tiling_vs_gtt.c b/tests/i915/gem_set_tiling_vs_gtt.c
> index 2611ec55..210d5358 100644
> --- a/tests/i915/gem_set_tiling_vs_gtt.c
> +++ b/tests/i915/gem_set_tiling_vs_gtt.c
> @@ -60,6 +60,8 @@ igt_simple_main
>  
>  	fd = drm_open_driver(DRIVER_INTEL);
>  
> +	gem_require_mmap_gtt(fd);
> +
mmap_gtt depends on gen or not? Did we have mmap_gtt on Gen2? There are no silly
questions :)
>  	if (IS_GEN2(intel_get_drm_devid(fd)))
>  		tile_height = 16;
>  	else
> diff --git a/tests/i915/gem_set_tiling_vs_pwrite.c b/tests/i915/gem_set_tiling_vs_pwrite.c
> index f0126b64..d82e20b4 100644
> --- a/tests/i915/gem_set_tiling_vs_pwrite.c
> +++ b/tests/i915/gem_set_tiling_vs_pwrite.c
> @@ -58,6 +58,8 @@ igt_simple_main
>  
>  	fd = drm_open_driver(DRIVER_INTEL);
>  
> +	gem_require_mmap_gtt(fd);
> +
>  	for (i = 0; i < OBJECT_SIZE/4; i++)
>  		data[i] = i;
>  
> diff --git a/tests/i915/gem_shrink.c b/tests/i915/gem_shrink.c
> index f71a1fcb..e97e0981 100644
> --- a/tests/i915/gem_shrink.c
> +++ b/tests/i915/gem_shrink.c
> @@ -396,6 +396,8 @@ igt_main
>  	uint64_t alloc_size = 0;
>  	int num_processes = 0;
>  
> +	bool has_gtt = false;
> +
>  	igt_skip_on_simulation();
>  
>  	igt_fixture {
> @@ -427,6 +429,8 @@ igt_main
>  			engines[nengine++] = engine;
>  		igt_require(nengine);
>  
> +		has_gtt = gem_mmap__has_gtt(fd);
> +
>  		close(fd);
>  	}
>  
> @@ -435,9 +439,13 @@ igt_main
>  
>  	for(const struct test *t = tests; t->name; t++) {
>  		for(const struct mode *m = modes; m->suffix; m++) {
> -			igt_subtest_f("%s%s", t->name, m->suffix)
> -				run_test(num_processes, alloc_size,
> -					 t->func, m->flags);
> +			igt_subtest_f("%s%s", t->name, m->suffix) {
> +					if (t->func == mmap_gtt)
> +						igt_require(has_gtt);
> +
> +					run_test(num_processes, alloc_size,
> +						 t->func, m->flags);
> +			}
>  		}
>  	}
>  }
> diff --git a/tests/i915/gem_storedw_loop.c b/tests/i915/gem_storedw_loop.c
> index b00555e0..d16a1a6b 100644
> --- a/tests/i915/gem_storedw_loop.c
> +++ b/tests/i915/gem_storedw_loop.c
> @@ -49,6 +49,12 @@ static int devid;
>  
>  static unsigned coherent_domain;
>  
> +static bool
> +uses_coherent_gtt(int fd)
> +{
> +	return (!gem_has_llc(fd) || gem_mmap__has_wc(fd));
> +}
> +
>  static void *
>  mmap_coherent(int fd, uint32_t handle, int size)
>  {
> @@ -164,6 +170,9 @@ check_test_requirements(int fd, int ringid)
>  {
>  	gem_require_ring(fd, ringid);
>  	igt_require(gem_can_store_dword(fd, ringid));
> +
> +	if (uses_coherent_gtt(fd))
> +		gem_require_mmap_gtt(fd);
>  }
>  
>  igt_main
> diff --git a/tests/i915/gem_streaming_writes.c b/tests/i915/gem_streaming_writes.c
> index e83d69de..159cb7a6 100644
> --- a/tests/i915/gem_streaming_writes.c
> +++ b/tests/i915/gem_streaming_writes.c
> @@ -48,6 +48,8 @@
>  
>  #define LOCAL_I915_EXEC_HANDLE_LUT (1<<12)
>  
> +#define NEEDS_GTT(mode) (mode == 1)
> +
>  IGT_TEST_DESCRIPTION("Test of streaming writes into active GPU sources");
>  
>  #define SRC 0
> @@ -75,6 +77,9 @@ static void test_streaming(int fd, int mode, int sync)
>  	} *batch;
>  	int i, n;
>  
> +	if (NEEDS_GTT(mode))
> +		gem_require_mmap_gtt(fd);
> +
>  	memset(exec, 0, sizeof(exec));
>  	exec[SRC].handle = gem_create(fd, OBJECT_SIZE);
>  	exec[DST].handle = gem_create(fd, OBJECT_SIZE);
> @@ -245,6 +250,9 @@ static void test_batch(int fd, int mode, int reverse)
>  	uint32_t *base;
>  	uint32_t offset;
>  
> +	if (NEEDS_GTT(mode))
> +		gem_require_mmap_gtt(fd);
> +
>  	memset(exec, 0, sizeof(exec));
>  	exec[DST].handle = gem_create(fd, OBJECT_SIZE);
>  	exec[SRC].handle = gem_create(fd, OBJECT_SIZE);
> @@ -389,14 +397,18 @@ igt_main
>  
>  	igt_subtest("batch-cpu")
>  		test_batch(fd, 0, 0);
> -	igt_subtest("batch-gtt")
> +	igt_subtest("batch-gtt") {
> +		gem_require_mmap_gtt(fd);
>  		test_batch(fd, 1, 0);
> +	}
>  	igt_subtest("batch-wc")
>  		test_batch(fd, 2, 0);
>  	igt_subtest("batch-reverse-cpu")
>  		test_batch(fd, 0, 1);
> -	igt_subtest("batch-reverse-gtt")
> +	igt_subtest("batch-reverse-gtt") {
> +		gem_require_mmap_gtt(fd);
>  		test_batch(fd, 1, 1);
> +	}
>  	igt_subtest("batch-reverse-wc")
>  		test_batch(fd, 2, 1);
>  
> diff --git a/tests/i915/gem_tiled_fence_blits.c b/tests/i915/gem_tiled_fence_blits.c
> index aacd42b7..249456e8 100644
> --- a/tests/i915/gem_tiled_fence_blits.c
> +++ b/tests/i915/gem_tiled_fence_blits.c
> @@ -213,6 +213,7 @@ igt_main
>  	igt_fixture {
>  		fd = drm_open_driver(DRIVER_INTEL);
>  		igt_require_gem(fd);
> +		gem_require_mmap_gtt(fd);
>  	}
>  
>  	igt_subtest("basic")
> diff --git a/tests/i915/gem_tiled_pread_basic.c b/tests/i915/gem_tiled_pread_basic.c
> index 1ac9eccd..b5a4e348 100644
> --- a/tests/i915/gem_tiled_pread_basic.c
> +++ b/tests/i915/gem_tiled_pread_basic.c
> @@ -124,6 +124,7 @@ igt_simple_main
>  	uint32_t devid;
>  
>  	fd = drm_open_driver(DRIVER_INTEL);
> +	gem_require_mmap_gtt(fd);
>  
>  	handle = create_bo(fd);
>  	igt_require(gem_get_tiling(fd, handle, &tiling, &swizzle));
> diff --git a/tests/i915/gem_tiled_pread_pwrite.c b/tests/i915/gem_tiled_pread_pwrite.c
> index 0988a4e8..0c0cde7f 100644
> --- a/tests/i915/gem_tiled_pread_pwrite.c
> +++ b/tests/i915/gem_tiled_pread_pwrite.c
> @@ -111,8 +111,10 @@ igt_simple_main
>  	uint32_t tiling, swizzle;
>  	int count;
>  	int fd;
> -	
> +
>  	fd = drm_open_driver(DRIVER_INTEL);
> +	gem_require_mmap_gtt(fd);
> +
>  	count = SLOW_QUICK(intel_get_total_ram_mb() * 9 / 10, 8) ;
>  
>  	for (int i = 0; i < count/2; i++) {
> diff --git a/tests/i915/gem_tiled_swapping.c b/tests/i915/gem_tiled_swapping.c
> index ddf2a748..29783aba 100644
> --- a/tests/i915/gem_tiled_swapping.c
> +++ b/tests/i915/gem_tiled_swapping.c
> @@ -175,6 +175,8 @@ igt_main
>  
>  		fd = drm_open_driver(DRIVER_INTEL);
>  
> +		gem_require_mmap_gtt(fd);
> +
>  		intel_purge_vm_caches(fd);
>  		check_memory_layout(fd);
>  
> diff --git a/tests/i915/gem_tiled_wb.c b/tests/i915/gem_tiled_wb.c
> index b7f352fc..61aa1675 100644
> --- a/tests/i915/gem_tiled_wb.c
> +++ b/tests/i915/gem_tiled_wb.c
> @@ -140,6 +140,8 @@ igt_simple_main
>  
>  	fd = drm_open_driver(DRIVER_INTEL);
>  
> +	gem_require_mmap_gtt(fd);
> +
>  	handle = create_bo(fd);
>  	get_tiling(fd, handle, &tiling, &swizzle);
>  
> diff --git a/tests/i915/gem_tiled_wc.c b/tests/i915/gem_tiled_wc.c
> index 845ec228..86e9bf46 100644
> --- a/tests/i915/gem_tiled_wc.c
> +++ b/tests/i915/gem_tiled_wc.c
> @@ -113,6 +113,7 @@ igt_simple_main
>  	uint32_t handle;
>  
>  	fd = drm_open_driver(DRIVER_INTEL);
> +	gem_require_mmap_gtt(fd);
>  	gem_require_mmap_wc(fd);
>  
>  	handle = create_bo(fd);
> diff --git a/tests/i915/gem_tiling_max_stride.c b/tests/i915/gem_tiling_max_stride.c
> index a6f97a91..b5dc053d 100644
> --- a/tests/i915/gem_tiling_max_stride.c
> +++ b/tests/i915/gem_tiling_max_stride.c
> @@ -70,8 +70,9 @@ igt_simple_main
>  
>  	fd = drm_open_driver(DRIVER_INTEL);
>  
> -	devid = intel_get_drm_devid(fd);
> +	gem_require_mmap_wc(fd);
>  
> +	devid = intel_get_drm_devid(fd);
>  	if (intel_gen(devid) >= 7)
>  		stride = 256 * 1024;
>  	else if (intel_gen(devid) >= 4)
> diff --git a/tests/i915/gem_userptr_blits.c b/tests/i915/gem_userptr_blits.c
> index 8f8ddf43..9962e539 100644
> --- a/tests/i915/gem_userptr_blits.c
> +++ b/tests/i915/gem_userptr_blits.c
> @@ -554,6 +554,8 @@ static int test_invalid_gtt_mapping(int fd)
>  	uint32_t handle;
>  	char *gtt, *map;
>  
> +	gem_require_mmap_gtt(fd);
> +
>  	/* Anonymous mapping to find a hole */
>  	map = mmap(NULL, sizeof(linear) + 2 * PAGE_SIZE,
>  		   PROT_READ | PROT_WRITE,
> @@ -616,8 +618,10 @@ static int test_invalid_gtt_mapping(int fd)
>  #define PE_BUSY 0x2
>  static void test_process_exit(int fd, int flags)
>  {
> -	if (flags & PE_GTT_MAP)
> +	if (flags & PE_GTT_MAP) {
>  		igt_require(gem_has_llc(fd));
> +		gem_require_mmap_gtt(fd);
> +	}
>  
>  	igt_fork(child, 1) {
>  		uint32_t handle;
> @@ -700,6 +704,8 @@ static int test_map_fixed_invalidate(int fd, uint32_t flags)
>  	uint32_t handle[num_handles];
>  	uint32_t *ptr;
>  
> +	gem_require_mmap_gtt(fd);
> +
>  	ptr = mmap(NULL, ptr_size,
>  		   PROT_READ | PROT_WRITE,
>  		   MAP_SHARED | MAP_ANONYMOUS,
> @@ -944,6 +950,7 @@ static int test_dmabuf(void)
>  	int ret;
>  
>  	fd1 = drm_open_driver(DRIVER_INTEL);
> +	gem_require_mmap_gtt(fd1);
>  
>  	handle = create_userptr_bo(fd1, sizeof(linear));
>  	memset(get_handle_ptr(handle), counter, sizeof(linear));
> @@ -1212,6 +1219,7 @@ static void test_readonly_mmap(int i915)
>  	 */
>  
>  	igt_require(igt_setup_clflush());
> +	gem_require_mmap_gtt(i915);
>  
>  	sz = 16 << 12;
>  	pages = mmap(NULL, sz, PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1, 0);
> diff --git a/tests/i915/i915_pm_rpm.c b/tests/i915/i915_pm_rpm.c
> index 18adaf6b..97b57ca2 100644
> --- a/tests/i915/i915_pm_rpm.c
> +++ b/tests/i915/i915_pm_rpm.c
> @@ -1006,6 +1006,7 @@ static void gem_mmap_subtest(bool gtt_mmap)
>  	handle = gem_create(drm_fd, buf_size);
>  
>  	if (gtt_mmap) {
> +		gem_require_mmap_gtt(drm_fd);
>  		gem_buf = gem_mmap__gtt(drm_fd, handle, buf_size,
>  					PROT_READ | PROT_WRITE);
>  	}
> @@ -1368,6 +1369,8 @@ static void gem_evict_pwrite_subtest(void)
>  	unsigned int num_trash_bos, n;
>  	uint32_t buf;
>  
> +	gem_require_mmap_gtt(drm_fd);
> +
>  	num_trash_bos = gem_mappable_aperture_size(drm_fd) / (1024*1024) + 1;
>  	trash_bos = malloc(num_trash_bos * sizeof(*trash_bos));
>  	igt_assert(trash_bos);
> @@ -1532,6 +1535,7 @@ static void cursor_subtest(bool dpms)
>  
>  	disable_all_screens_and_wait(&ms_data);
>  
> +	gem_require_mmap_gtt(drm_fd);
>  	igt_require(default_mode_params);
>  	crtc_id = default_mode_params->crtc_id;
>  
> @@ -1649,6 +1653,7 @@ static void test_one_plane(bool dpms, uint32_t plane_id,
>  	int32_t crtc_x = 0, crtc_y = 0;
>  	uint64_t tiling;
>  
> +	gem_require_mmap_gtt(drm_fd);
>  	disable_all_screens_and_wait(&ms_data);
>  
>  	crtc_id = default_mode_params->crtc_id;
> @@ -1796,6 +1801,8 @@ static void pm_test_tiling(void)
>  	/* default stride value */
>  	uint32_t stride = 512;
>  
> +	gem_require_mmap_gtt(drm_fd);
> +
>  	/* calculate how many objects we can map */
>  	for (i = 1 << off_bit; i <= gtt_obj_max_size; i <<= 1, max_gem_objs++)
>  		;
> @@ -1850,6 +1857,7 @@ static void pm_test_caching(void)
>  		I915_CACHING_DISPLAY,           /* eDRAM caching */
>  	};
>  
> +	gem_require_mmap_gtt(drm_fd);
>  	disable_all_screens(&ms_data);
>  
>  	handle = gem_create(drm_fd, gtt_obj_max_size);
> @@ -1887,6 +1895,7 @@ static void fences_subtest(bool dpms)
>  
>  	disable_all_screens_and_wait(&ms_data);
>  
> +	igt_require(gem_available_fences(drm_fd));
Is this function from lib/ioctl_wrappers.h? Why you added it here?
Btw - this function has a comment that is valid for pre-gen4/
>  	igt_require(default_mode_params);
>  	params.crtc_id = default_mode_params->crtc_id;
>  	params.connector_id = default_mode_params->connector_id;
> diff --git a/tests/i915/i915_suspend.c b/tests/i915/i915_suspend.c
> index 17c68cc1..09cf5542 100644
> --- a/tests/i915/i915_suspend.c
> +++ b/tests/i915/i915_suspend.c
> @@ -50,6 +50,8 @@ test_fence_restore(int fd, bool tiled2untiled, bool hibernate)
>  	uint32_t *ptr1, *ptr2, *ptr_tiled;
>  	int i;
>  
> +	igt_require(gem_available_fences(fd));
> +
>  	/* We wall the tiled object with untiled canary objects to make sure
>  	 * that we detect tile leaking in both directions. */
>  	handle1 = gem_create(fd, OBJECT_SIZE);
> diff --git a/tests/kms_draw_crc.c b/tests/kms_draw_crc.c
> index ea14db9a..1a2e2d4f 100644
> --- a/tests/kms_draw_crc.c
> +++ b/tests/kms_draw_crc.c
> @@ -329,13 +329,17 @@ igt_main
>  		igt_subtest_f("draw-method-%s-%s-%s",
>  			      format_str(format_idx),
>  			      igt_draw_get_method_name(method),
> -			      tiling_str(tiling_idx))
> +			      tiling_str(tiling_idx)) {
> +			gem_require_mmap_gtt(drm_fd);
>  			draw_method_subtest(method, format_idx,
>  					    tilings[tiling_idx]);
> +		}
>  	} } }
>  
> -	igt_subtest("fill-fb")
> +	igt_subtest("fill-fb") {
> +		gem_require_mmap_gtt(drm_fd);
>  		fill_fb_subtest();
> +	}
>  
>  	igt_fixture
>  		teardown_environment();
> diff --git a/tests/kms_fence_pin_leak.c b/tests/kms_fence_pin_leak.c
> index 62c52b62..ac0f605c 100644
> --- a/tests/kms_fence_pin_leak.c
> +++ b/tests/kms_fence_pin_leak.c
> @@ -202,6 +202,8 @@ igt_simple_main
>  
>  	data.drm_fd = drm_open_driver_master(DRIVER_INTEL);
>  
> +	gem_require_mmap_gtt(data.drm_fd);
> +
>  	data.devid = intel_get_drm_devid(data.drm_fd);
>  
>  	kmstest_set_vt_graphics_mode();
> diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
> index 4d15ce1c..78299438 100644
> --- a/tests/kms_frontbuffer_tracking.c
> +++ b/tests/kms_frontbuffer_tracking.c
> @@ -1758,6 +1758,9 @@ static void check_test_requirements(const struct test_mode *t)
>  
>  	if (opt.only_pipes != PIPE_COUNT)
>  		igt_require(t->pipes == opt.only_pipes);
> +
> +	if (t->method == IGT_DRAW_MMAP_GTT)
> +		gem_require_mmap_gtt(drm.fd);
>  }
>  
>  static void set_crtc_fbs(const struct test_mode *t)
> diff --git a/tests/kms_psr.c b/tests/kms_psr.c
> index 3e16a6bf..66f4fcd8 100644
> --- a/tests/kms_psr.c
> +++ b/tests/kms_psr.c
> @@ -41,6 +41,8 @@ enum operations {
>  	PLANE_ONOFF,
>  };
>  
> +#define needs_gtt(op) if (op == MMAP_GTT) {gem_require_mmap_gtt(data.drm_fd);}
> +
>  static const char *op_str(enum operations op)
>  {
>  	static const char * const name[] = {
> @@ -474,6 +476,7 @@ int main(int argc, char *argv[])
>  			igt_subtest_f("%sprimary_%s",
>  				      append_subtest_name[data.op_psr_mode],
>  				      op_str(op)) {
> +				needs_gtt(op);
>  				data.op = op;
>  				data.test_plane_id = DRM_PLANE_TYPE_PRIMARY;
>  				test_setup(&data);
> @@ -486,6 +489,7 @@ int main(int argc, char *argv[])
>  			igt_subtest_f("%ssprite_%s",
>  				      append_subtest_name[data.op_psr_mode],
>  				      op_str(op)) {
> +				needs_gtt(op);
>  				data.op = op;
>  				data.test_plane_id = DRM_PLANE_TYPE_OVERLAY;
>  				test_setup(&data);
> diff --git a/tests/prime_mmap.c b/tests/prime_mmap.c
> index 06a66cab..33f97b84 100644
> --- a/tests/prime_mmap.c
> +++ b/tests/prime_mmap.c
> @@ -79,6 +79,8 @@ test_correct(void)
>  	char *ptr1, *ptr2;
>  	uint32_t handle;
>  
> +	gem_require_mmap_gtt(fd);
> +
>  	handle = gem_create(fd, BO_SIZE);
>  	fill_bo(handle, BO_SIZE);
>  
> diff --git a/tests/prime_mmap_coherency.c b/tests/prime_mmap_coherency.c
> index 04b15ddd..9c344df9 100644
> --- a/tests/prime_mmap_coherency.c
> +++ b/tests/prime_mmap_coherency.c
> @@ -295,6 +295,7 @@ int main(int argc, char **argv)
>  	 * reproducing boils down to trial and error to hit different scenarios.
>  	 * TODO: We may want to improve tests a bit by picking random subranges. */
>  	igt_subtest("read") {
> +		gem_require_mmap_gtt(fd);
>  		igt_until_timeout(5) {
>  			int stale = test_read_flush();
>  			igt_fail_on_f(stale,
> diff --git a/tests/prime_vgem.c b/tests/prime_vgem.c
> index 60bb951c..0c60d569 100644
> --- a/tests/prime_vgem.c
> +++ b/tests/prime_vgem.c
> @@ -125,6 +125,8 @@ static void test_fence_mmap(int i915, int vgem)
>  	int dmabuf, i;
>  	int master[2], slave[2];
>  
> +	gem_require_mmap_gtt(i915);
> +
>  	igt_assert(pipe(master) == 0);
>  	igt_assert(pipe(slave) == 0);
>  
> @@ -207,6 +209,8 @@ static void test_gtt(int vgem, int i915)
>  	uint32_t *ptr;
>  	int dmabuf, i;
>  
> +	gem_require_mmap_gtt(i915);
> +
>  	scratch.width = 1024;
>  	scratch.height = 1024;
>  	scratch.bpp = 32;
> @@ -282,6 +286,7 @@ static void test_gtt_interleaved(int vgem, int i915)
>  	uint32_t *ptr, *gtt;
>  	int dmabuf, i;
>  
> +	gem_require_mmap_gtt(i915);
>  	igt_require(is_coherent(i915));
>  
>  	scratch.width = 1024;
> -- 
> 2.20.1
>
Almost 1000 lines, huge patch, but I made it here :)
I hope I did not miss anything.
Kasia :)
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[igt-dev] [RFT v4 5/6] Coherency tests that need to be using WC + sync

[Antonio Argenziano]

---
 tests/prime_mmap.c | 36 ++++++++++++++++++++++++++++++++++--
 1 file changed, 34 insertions(+), 2 deletions(-)

diff --git a/tests/prime_mmap.c b/tests/prime_mmap.c
index 33f97b84..f28985da 100644
--- a/tests/prime_mmap.c
+++ b/tests/prime_mmap.c
@@ -73,7 +73,7 @@ fill_bo_cpu(char *ptr)
 }
 
 static void
-test_correct(void)
+test_correct_gtt(void)
 {
 	int dma_buf_fd;
 	char *ptr1, *ptr2;
@@ -103,6 +103,37 @@ test_correct(void)
 	gem_close(fd, handle);
 }
 
+static void
+test_correct_wc(void)
+{
+	int dma_buf_fd;
+	char *ptr1, *ptr2;
+	uint32_t handle;
+
+	gem_require_mmap_wc(fd);
+
+	handle = gem_create(fd, BO_SIZE);
+	fill_bo(handle, BO_SIZE);
+
+	dma_buf_fd = prime_handle_to_fd(fd, handle);
+	igt_assert(errno == 0);
+
+	/* Check correctness vs WC mapping */
+	ptr1 = gem_mmap__wc(fd, handle, 0, BO_SIZE, PROT_READ);
+	ptr2 = mmap(NULL, BO_SIZE, PROT_READ, MAP_SHARED, dma_buf_fd, 0);
+	igt_assert(ptr1 != MAP_FAILED);
+	igt_assert(ptr2 != MAP_FAILED);
+	igt_assert(memcmp(ptr1, ptr2, BO_SIZE) == 0);
+
+	/* Check pattern correctness */
+	igt_assert(memcmp(ptr2, pattern, sizeof(pattern)) == 0);
+
+	munmap(ptr1, BO_SIZE);
+	munmap(ptr2, BO_SIZE);
+	close(dma_buf_fd);
+	gem_close(fd, handle);
+}
+
 static void
 test_map_unmap(void)
 {
@@ -504,7 +535,8 @@ igt_main
 		const char *name;
 		void (*fn)(void);
 	} tests[] = {
-		{ "test_correct", test_correct },
+		{ "test_correct_gtt", test_correct_gtt },
+		{ "test_correct_wc", test_correct_wc },
 		{ "test_map_unmap", test_map_unmap },
 		{ "test_reprime", test_reprime },
 		{ "test_forked", test_forked },
-- 
2.20.1

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Re: [igt-dev] [RFT v4 5/6] Coherency tests that need to be using WC + sync

[Katarzyna Dec]

On Mon, Mar 25, 2019 at 04:20:42PM -0700, Antonio Argenziano wrote:

Commit msg is missing so there is not backstory to this patch :)
> ---
>  tests/prime_mmap.c | 36 ++++++++++++++++++++++++++++++++++--
>  1 file changed, 34 insertions(+), 2 deletions(-)
> 
> diff --git a/tests/prime_mmap.c b/tests/prime_mmap.c
> index 33f97b84..f28985da 100644
> --- a/tests/prime_mmap.c
> +++ b/tests/prime_mmap.c
> @@ -73,7 +73,7 @@ fill_bo_cpu(char *ptr)
>  }
>  
>  static void
> -test_correct(void)
> +test_correct_gtt(void)
>  {
>  	int dma_buf_fd;
>  	char *ptr1, *ptr2;
> @@ -103,6 +103,37 @@ test_correct(void)
>  	gem_close(fd, handle);
>  }
>  
> +static void
> +test_correct_wc(void)
> +{
> +	int dma_buf_fd;
> +	char *ptr1, *ptr2;
> +	uint32_t handle;
> +
> +	gem_require_mmap_wc(fd);
> +
> +	handle = gem_create(fd, BO_SIZE);
> +	fill_bo(handle, BO_SIZE);
> +
> +	dma_buf_fd = prime_handle_to_fd(fd, handle);
> +	igt_assert(errno == 0);
> +
> +	/* Check correctness vs WC mapping */
> +	ptr1 = gem_mmap__wc(fd, handle, 0, BO_SIZE, PROT_READ);
> +	ptr2 = mmap(NULL, BO_SIZE, PROT_READ, MAP_SHARED, dma_buf_fd, 0);
> +	igt_assert(ptr1 != MAP_FAILED);
> +	igt_assert(ptr2 != MAP_FAILED);
> +	igt_assert(memcmp(ptr1, ptr2, BO_SIZE) == 0);
> +
> +	/* Check pattern correctness */
> +	igt_assert(memcmp(ptr2, pattern, sizeof(pattern)) == 0);
> +
> +	munmap(ptr1, BO_SIZE);
> +	munmap(ptr2, BO_SIZE);
> +	close(dma_buf_fd);
> +	gem_close(fd, handle);
> +}
> +
>  static void
>  test_map_unmap(void)
>  {
> @@ -504,7 +535,8 @@ igt_main
>  		const char *name;
>  		void (*fn)(void);
>  	} tests[] = {
> -		{ "test_correct", test_correct },
> +		{ "test_correct_gtt", test_correct_gtt },
> +		{ "test_correct_wc", test_correct_wc },
>  		{ "test_map_unmap", test_map_unmap },
>  		{ "test_reprime", test_reprime },
>  		{ "test_forked", test_forked },
> -- 
> 2.20.1
> 
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
Based on code I do not see any issues, yet.
Kasia :)
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[igt-dev] [RFT v4 6/6] igt/lib: If mappable aperture is missing return 0 size

[Antonio Argenziano]

So far the aperture size has been read directly from the bar,
in this patch we return zero if the mappable aperture is not available
as the value stored in the bar is not accurate. The patch also adds a
'require' when a call to gem_mappable_aperture_size() is made so that
the aperture is guaranteed to exist before checking the size.

Cc: Katarzyna Dec <katarzyna.dec@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Antonio Argenziano <antonio.argenziano@intel.com>
---
 lib/ioctl_wrappers.c       | 26 ++++++++++++++++++--------
 lib/ioctl_wrappers.h       |  1 +
 tests/i915/gem_cpu_reloc.c | 14 ++++++++++----
 tests/prime_mmap.c         |  7 +++++--
 4 files changed, 34 insertions(+), 14 deletions(-)

diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index a66eb4bc..c903d05c 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -1089,6 +1089,22 @@ uint64_t gem_aperture_size(int fd)
 	return aperture_size;
 }
 
+static uint64_t __gem_mappable_aperture_size(int fd)
+{
+	struct pci_device *pci_dev = igt_device_get_pci_device(fd);
+	int bar;
+
+	if (!gem_mmap__has_gtt(fd))
+		return 0; /* Aperture not available */
+
+	if (intel_gen(pci_dev->device_id) < 3)
+		bar = 0;
+	else
+		bar = 2;
+
+	return pci_dev->regions[bar].size;
+}
+
 /**
  * gem_mappable_aperture_size:
  *
@@ -1099,15 +1115,9 @@ uint64_t gem_aperture_size(int fd)
  */
 uint64_t gem_mappable_aperture_size(int fd)
 {
-	struct pci_device *pci_dev = igt_device_get_pci_device(fd);
-	int bar;
-
-	if (intel_gen(pci_dev->device_id) < 3)
-		bar = 0;
-	else
-		bar = 2;
+	gem_require_mmap_gtt(fd);
 
-	return pci_dev->regions[bar].size;
+	return __gem_mappable_aperture_size(fd);
 }
 
 /**
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index ad93daff..b3b0313e 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -38,6 +38,7 @@
 
 #include "i915/gem_context.h"
 #include "i915/gem_scheduler.h"
+#include "i915/gem_mman.h"
 
 /**
  * igt_ioctl:
diff --git a/tests/i915/gem_cpu_reloc.c b/tests/i915/gem_cpu_reloc.c
index 17c2fe11..58fd4470 100644
--- a/tests/i915/gem_cpu_reloc.c
+++ b/tests/i915/gem_cpu_reloc.c
@@ -283,8 +283,11 @@ igt_main
 		run_test(i915, 1);
 
 	igt_subtest("full") {
-		uint64_t aper_size = gem_mappable_aperture_size(i915);
-		unsigned long count = aper_size / 4096 + 1;
+		uint64_t aper_size;
+		unsigned long count;
+
+		aper_size = gem_mappable_aperture_size(i915);
+		count = aper_size / 4096 + 1;
 
 		intel_require_memory(count, 4096, CHECK_RAM);
 
@@ -292,10 +295,13 @@ igt_main
 	}
 
 	igt_subtest("forked") {
-		uint64_t aper_size = gem_mappable_aperture_size(i915);
-		unsigned long count = aper_size / 4096 + 1;
+		uint64_t aper_size;
+		unsigned long count;
 		int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
 
+		aper_size = gem_mappable_aperture_size(i915);
+		count = aper_size / 4096 + 1;
+
 		intel_require_memory(count, 4096, CHECK_RAM);
 
 		igt_fork(child, ncpus)
diff --git a/tests/prime_mmap.c b/tests/prime_mmap.c
index f28985da..c844effc 100644
--- a/tests/prime_mmap.c
+++ b/tests/prime_mmap.c
@@ -480,8 +480,11 @@ test_aperture_limit(void)
 	char *ptr1, *ptr2;
 	uint32_t handle1, handle2;
 	/* Two buffers the sum of which > mappable aperture */
-	uint64_t size1 = (gem_mappable_aperture_size(fd) * 7) / 8;
-	uint64_t size2 = (gem_mappable_aperture_size(fd) * 3) / 8;
+	uint64_t size1;
+	uint64_t size2;
+
+	size1 = (gem_mappable_aperture_size(fd) * 7) / 8;
+	size2 = (gem_mappable_aperture_size(fd) * 3) / 8;
 
 	handle1 = gem_create(fd, size1);
 	fill_bo(handle1, BO_SIZE);
-- 
2.20.1

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Re: [igt-dev] [RFT v4 6/6] igt/lib: If mappable aperture is missing return 0 size

[Katarzyna Dec]

On Mon, Mar 25, 2019 at 04:20:43PM -0700, Antonio Argenziano wrote:
> So far the aperture size has been read directly from the bar,
> in this patch we return zero if the mappable aperture is not available
> as the value stored in the bar is not accurate. The patch also adds a
> 'require' when a call to gem_mappable_aperture_size() is made so that
> the aperture is guaranteed to exist before checking the size.
> 
> Cc: Katarzyna Dec <katarzyna.dec@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Signed-off-by: Antonio Argenziano <antonio.argenziano@intel.com>
> ---
>  lib/ioctl_wrappers.c       | 26 ++++++++++++++++++--------
>  lib/ioctl_wrappers.h       |  1 +
>  tests/i915/gem_cpu_reloc.c | 14 ++++++++++----
>  tests/prime_mmap.c         |  7 +++++--
>  4 files changed, 34 insertions(+), 14 deletions(-)
> 
> diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
> index a66eb4bc..c903d05c 100644
> --- a/lib/ioctl_wrappers.c
> +++ b/lib/ioctl_wrappers.c
> @@ -1089,6 +1089,22 @@ uint64_t gem_aperture_size(int fd)
>  	return aperture_size;
>  }
>  
> +static uint64_t __gem_mappable_aperture_size(int fd)
> +{
> +	struct pci_device *pci_dev = igt_device_get_pci_device(fd);
> +	int bar;
> +
> +	if (!gem_mmap__has_gtt(fd))
> +		return 0; /* Aperture not available */
> +
> +	if (intel_gen(pci_dev->device_id) < 3)
> +		bar = 0;
> +	else
> +		bar = 2;
> +
> +	return pci_dev->regions[bar].size;
> +}
> +
>  /**
>   * gem_mappable_aperture_size:
>   *
> @@ -1099,15 +1115,9 @@ uint64_t gem_aperture_size(int fd)
>   */
>  uint64_t gem_mappable_aperture_size(int fd)
>  {
> -	struct pci_device *pci_dev = igt_device_get_pci_device(fd);
> -	int bar;
> -
> -	if (intel_gen(pci_dev->device_id) < 3)
> -		bar = 0;
> -	else
> -		bar = 2;
> +	gem_require_mmap_gtt(fd);
>  
> -	return pci_dev->regions[bar].size;
> +	return __gem_mappable_aperture_size(fd);
>  }
>  
>  /**
> diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
> index ad93daff..b3b0313e 100644
> --- a/lib/ioctl_wrappers.h
> +++ b/lib/ioctl_wrappers.h
> @@ -38,6 +38,7 @@
>  
>  #include "i915/gem_context.h"
>  #include "i915/gem_scheduler.h"
> +#include "i915/gem_mman.h"
>  
>  /**
>   * igt_ioctl:
> diff --git a/tests/i915/gem_cpu_reloc.c b/tests/i915/gem_cpu_reloc.c
> index 17c2fe11..58fd4470 100644
> --- a/tests/i915/gem_cpu_reloc.c
> +++ b/tests/i915/gem_cpu_reloc.c
> @@ -283,8 +283,11 @@ igt_main
>  		run_test(i915, 1);
>  
>  	igt_subtest("full") {
> -		uint64_t aper_size = gem_mappable_aperture_size(i915);
> -		unsigned long count = aper_size / 4096 + 1;
> +		uint64_t aper_size;
> +		unsigned long count;
> +
> +		aper_size = gem_mappable_aperture_size(i915);
> +		count = aper_size / 4096 + 1;
Is this just a style change? Or I do not see something? Below as well.
It does seem to be reflected in commit msg.
Kasia
>  
>  		intel_require_memory(count, 4096, CHECK_RAM);
>  
> @@ -292,10 +295,13 @@ igt_main
>  	}
>  
>  	igt_subtest("forked") {
> -		uint64_t aper_size = gem_mappable_aperture_size(i915);
> -		unsigned long count = aper_size / 4096 + 1;
> +		uint64_t aper_size;
> +		unsigned long count;
>  		int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
>  
> +		aper_size = gem_mappable_aperture_size(i915);
> +		count = aper_size / 4096 + 1;
> +
>  		intel_require_memory(count, 4096, CHECK_RAM);
>  
>  		igt_fork(child, ncpus)
> diff --git a/tests/prime_mmap.c b/tests/prime_mmap.c
> index f28985da..c844effc 100644
> --- a/tests/prime_mmap.c
> +++ b/tests/prime_mmap.c
> @@ -480,8 +480,11 @@ test_aperture_limit(void)
>  	char *ptr1, *ptr2;
>  	uint32_t handle1, handle2;
>  	/* Two buffers the sum of which > mappable aperture */
> -	uint64_t size1 = (gem_mappable_aperture_size(fd) * 7) / 8;
> -	uint64_t size2 = (gem_mappable_aperture_size(fd) * 3) / 8;
> +	uint64_t size1;
> +	uint64_t size2;
> +
> +	size1 = (gem_mappable_aperture_size(fd) * 7) / 8;
> +	size2 = (gem_mappable_aperture_size(fd) * 3) / 8;
>  
>  	handle1 = gem_create(fd, size1);
>  	fill_bo(handle1, BO_SIZE);
> -- 
> 2.20.1
> 
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[igt-dev] ✗ Fi.CI.BAT: failure for series starting with [RFT,v4,1/6] lib/i915/gem_mman: Remove static variables

[Patchwork]

== Series Details ==

Series: series starting with [RFT,v4,1/6] lib/i915/gem_mman: Remove static variables
URL   : https://patchwork.freedesktop.org/series/58551/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_5813 -> IGTPW_2705
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_2705 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_2705, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/58551/revisions/1/mbox/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_2705:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_mmap_gtt@basic-small-bo-tiledx:
    - fi-hsw-4770:        PASS -> FAIL +1
    - fi-blb-e6850:       PASS -> FAIL +1
    - fi-ilk-650:         PASS -> FAIL +1
    - fi-snb-2520m:       PASS -> FAIL +1

  * igt@gem_mmap_gtt@basic-small-bo-tiledy:
    - fi-bwr-2160:        PASS -> FAIL +1
    - fi-bdw-gvtdvm:      PASS -> FAIL
    - fi-kbl-guc:         PASS -> FAIL
    - fi-cfl-8109u:       PASS -> FAIL
    - fi-byt-clapper:     PASS -> FAIL
    - fi-kbl-r:           PASS -> FAIL
    - fi-skl-6260u:       PASS -> FAIL
    - fi-bxt-j4205:       PASS -> FAIL
    - fi-bsw-kefka:       PASS -> FAIL
    - fi-icl-u3:          PASS -> FAIL
    - fi-skl-6770hq:      PASS -> FAIL
    - fi-snb-2600:        PASS -> FAIL +1
    - fi-cfl-guc:         PASS -> FAIL
    - fi-byt-j1900:       PASS -> FAIL
    - fi-elk-e7500:       PASS -> FAIL +1
    - fi-skl-6700k2:      PASS -> FAIL
    - fi-byt-n2820:       PASS -> FAIL
    - fi-cfl-8700k:       PASS -> FAIL
    - fi-apl-guc:         PASS -> FAIL
    - fi-bdw-5557u:       PASS -> FAIL
    - fi-pnv-d510:        NOTRUN -> FAIL
    - fi-skl-6600u:       NOTRUN -> FAIL
    - fi-skl-guc:         PASS -> FAIL
    - fi-kbl-7500u:       PASS -> FAIL
    - fi-hsw-peppy:       PASS -> FAIL
    - fi-kbl-8809g:       PASS -> FAIL
    - fi-skl-gvtdvm:      PASS -> FAIL
    - fi-kbl-x1275:       PASS -> FAIL
    - fi-bsw-n3050:       PASS -> FAIL
    - fi-ivb-3770:        PASS -> FAIL
    - fi-skl-iommu:       NOTRUN -> FAIL
    - fi-icl-u2:          PASS -> FAIL
    - fi-whl-u:           NOTRUN -> FAIL

  * igt@kms_frontbuffer_tracking@basic:
    - fi-bsw-n3050:       PASS -> CRASH +1
    - fi-bsw-kefka:       PASS -> CRASH +1
    - fi-ivb-3770:        PASS -> CRASH
    - fi-skl-6700k2:      PASS -> CRASH
    - fi-byt-j1900:       PASS -> CRASH
    - fi-hsw-4770:        PASS -> CRASH
    - fi-skl-6600u:       NOTRUN -> CRASH
    - fi-bdw-5557u:       PASS -> CRASH
    - fi-kbl-r:           PASS -> CRASH
    - fi-cfl-8109u:       PASS -> CRASH
    - fi-skl-6260u:       PASS -> CRASH
    - fi-snb-2600:        PASS -> CRASH
    - fi-ilk-650:         PASS -> CRASH
    - fi-skl-6770hq:      PASS -> CRASH
    - fi-byt-n2820:       PASS -> CRASH
    - fi-cfl-guc:         PASS -> CRASH
    - fi-skl-iommu:       NOTRUN -> CRASH
    - fi-snb-2520m:       PASS -> CRASH
    - fi-whl-u:           NOTRUN -> CRASH
    - fi-cfl-8700k:       PASS -> CRASH
    - fi-bdw-gvtdvm:      PASS -> CRASH
    - fi-skl-guc:         PASS -> CRASH
    - fi-kbl-x1275:       PASS -> CRASH
    - fi-byt-clapper:     PASS -> CRASH
    - fi-skl-gvtdvm:      PASS -> CRASH

  
#### Warnings ####

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u3:          FAIL [fdo#103167] -> CRASH
    - fi-icl-u2:          FAIL [fdo#103167] -> CRASH

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_mmap_gtt@basic-small-bo-tiledy:
    - {fi-skl-lmem}:      PASS -> FAIL

  * igt@kms_frontbuffer_tracking@basic:
    - {fi-skl-lmem}:      PASS -> CRASH

  
Known issues
------------

  Here are the changes found in IGTPW_2705 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@userptr:
    - fi-whl-u:           NOTRUN -> SKIP [fdo#109271] +41

  * igt@amdgpu/amd_cs_nop@fork-compute0:
    - fi-blb-e6850:       NOTRUN -> SKIP [fdo#109271] +18

  * igt@gem_exec_basic@readonly-bsd2:
    - fi-pnv-d510:        NOTRUN -> SKIP [fdo#109271] +76

  * igt@gem_mmap_gtt@basic-wc:
    - fi-pnv-d510:        NOTRUN -> FAIL [fdo#107307]
    - fi-kbl-guc:         PASS -> FAIL [fdo#107307]
    - fi-byt-clapper:     PASS -> FAIL [fdo#107307]
    - fi-kbl-x1275:       PASS -> FAIL [fdo#107307]
    - fi-byt-j1900:       PASS -> FAIL [fdo#107307]
    - fi-kbl-r:           PASS -> FAIL [fdo#107307]
    - fi-skl-6260u:       PASS -> FAIL [fdo#107307]
    - fi-byt-n2820:       PASS -> FAIL [fdo#107307]
    - fi-kbl-8809g:       PASS -> FAIL [fdo#107307]
    - fi-skl-gvtdvm:      PASS -> FAIL [fdo#107307]
    - fi-hsw-4770:        PASS -> FAIL [fdo#107307]
    - fi-snb-2600:        PASS -> FAIL [fdo#107307]
    - fi-cfl-guc:         PASS -> FAIL [fdo#107307]
    - fi-whl-u:           NOTRUN -> FAIL [fdo#107307]
    - fi-skl-guc:         PASS -> FAIL [fdo#107307]
    - fi-bsw-n3050:       PASS -> FAIL [fdo#107307]
    - fi-skl-6700k2:      PASS -> FAIL [fdo#107307]
    - fi-ivb-3770:        PASS -> FAIL [fdo#107307]
    - fi-blb-e6850:       PASS -> FAIL [fdo#107307]
    - fi-hsw-peppy:       PASS -> FAIL [fdo#107307]
    - fi-skl-iommu:       NOTRUN -> FAIL [fdo#107307]
    - fi-cfl-8700k:       PASS -> FAIL [fdo#107307]
    - fi-apl-guc:         PASS -> INCOMPLETE [fdo#103927]
    - fi-skl-6600u:       NOTRUN -> FAIL [fdo#107307]
    - fi-kbl-7500u:       PASS -> FAIL [fdo#107307]
    - fi-gdg-551:         PASS -> FAIL [fdo#107307]
    - fi-cfl-8109u:       PASS -> FAIL [fdo#107307]
    - fi-bxt-j4205:       PASS -> INCOMPLETE [fdo#103927]
    - fi-icl-u3:          PASS -> FAIL [fdo#107307]
    - fi-ilk-650:         PASS -> FAIL [fdo#107307]
    - fi-bdw-gvtdvm:      PASS -> FAIL [fdo#107307]
    - fi-icl-u2:          PASS -> FAIL [fdo#107307]
    - fi-elk-e7500:       PASS -> FAIL [fdo#107307]
    - fi-snb-2520m:       PASS -> FAIL [fdo#107307]
    - fi-bsw-kefka:       PASS -> FAIL [fdo#107307]
    - fi-bwr-2160:        PASS -> FAIL [fdo#107307]
    - fi-bdw-5557u:       PASS -> FAIL [fdo#107307]
    - fi-skl-6770hq:      PASS -> FAIL [fdo#107307]

  * igt@kms_busy@basic-flip-c:
    - fi-pnv-d510:        NOTRUN -> SKIP [fdo#109271] / [fdo#109278]

  * igt@kms_chamelium@dp-edid-read:
    - fi-skl-iommu:       NOTRUN -> SKIP [fdo#109271] +45

  * igt@kms_chamelium@vga-edid-read:
    - fi-skl-6600u:       NOTRUN -> SKIP [fdo#109271] +41

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
    - fi-byt-clapper:     PASS -> FAIL [fdo#103191] / [fdo#107362] +1

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-whl-u:           NOTRUN -> FAIL [fdo#103375] +3

  * igt@kms_psr@cursor_plane_move:
    - fi-whl-u:           NOTRUN -> FAIL [fdo#107383] +3

  * igt@prime_vgem@basic-fence-flip:
    - fi-ilk-650:         PASS -> FAIL [fdo#104008]
    - fi-gdg-551:         PASS -> FAIL [fdo#103182]

  
#### Possible fixes ####

  * igt@i915_module_load@reload:
    - fi-blb-e6850:       INCOMPLETE [fdo#107718] -> PASS

  * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
    - fi-byt-clapper:     FAIL [fdo#103191] / [fdo#107362] -> PASS

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104008]: https://bugs.freedesktop.org/show_bug.cgi?id=104008
  [fdo#107307]: https://bugs.freedesktop.org/show_bug.cgi?id=107307
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109593]: https://bugs.freedesktop.org/show_bug.cgi?id=109593


Participating hosts (41 -> 41)
------------------------------

  Additional (5): fi-whl-u fi-skl-iommu fi-pnv-d510 fi-icl-dsi fi-skl-6600u 
  Missing    (5): fi-hsw-4770r fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bdw-samus 


Build changes
-------------

    * IGT: IGT_4903 -> IGTPW_2705

  CI_DRM_5813: 79df6ae8e7d6fc94965a14e1fa04898954d40316 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_2705: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2705/
  IGT_4903: a4dc3d0f9ac6abf2a0ca6a4771255cb5dcb3b07b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools



== Testlist changes ==

+igt@prime_mmap@test_correct_gtt
+igt@prime_mmap@test_correct_wc
-igt@prime_mmap@test_correct

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2705/
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Re: [igt-dev] [RFT v4 1/6] lib/i915/gem_mman: Remove static variables

[Katarzyna Dec]

On Mon, Mar 25, 2019 at 04:20:38PM -0700, Antonio Argenziano wrote:
> Since the IOCTL wrappers implemented in gem_mman should only be called
> once at fixture time there is no need to save the state across multiple
> calls.
> 
> Signed-off-by: Antonio Argenziano <antonio.argenziano@intel.com>
> Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>

RFT in subject of this patchset means you want somebody to test it or CI will do
it?

Kasia :)
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Re: [igt-dev] [RFT v4 1/6] lib/i915/gem_mman: Remove static variables

[Antonio Argenziano]

On 16/04/19 06:27, Katarzyna Dec wrote:
> On Mon, Mar 25, 2019 at 04:20:38PM -0700, Antonio Argenziano wrote:
>> Since the IOCTL wrappers implemented in gem_mman should only be called
>> once at fixture time there is no need to save the state across multiple
>> calls.
>>
>> Signed-off-by: Antonio Argenziano <antonio.argenziano@intel.com>
>> Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
> 
> RFT in subject of this patchset means you want somebody to test it or CI will do
> it?

I think CI is enough, there is a machine called lmem something so I 
assume it has the lmem patches applied :).

Antonio

> 
> Kasia :)
> 
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