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* [PATCH V5 1/4] dt-bindings: fsl: scu: add general interrupt support
@ 2019-03-18  3:09 ` Anson Huang
  0 siblings, 0 replies; 40+ messages in thread
From: Anson Huang @ 2019-03-18  3:09 UTC (permalink / raw)
  To: robh+dt, mark.rutland, shawnguo, s.hauer, kernel, festevam,
	a.zummo, alexandre.belloni, Aisheng Dong, ulf.hansson,
	Daniel Baluta, devicetree, linux-kernel, linux-arm-kernel,
	linux-rtc
  Cc: dl-linux-imx

Add scu general interrupt function support.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
---
Changes since V4:
	- add mu aliase info and example in binding doc.
---
 .../devicetree/bindings/arm/freescale/fsl,scu.txt  | 29 +++++++++++++++++-----
 1 file changed, 23 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
index 72d481c..5d7dbab 100644
--- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
@@ -22,9 +22,11 @@ Required properties:
 -------------------
 - compatible:	should be "fsl,imx-scu".
 - mbox-names:	should include "tx0", "tx1", "tx2", "tx3",
-			       "rx0", "rx1", "rx2", "rx3".
-- mboxes:	List of phandle of 4 MU channels for tx and 4 MU channels
-		for rx. All 8 MU channels must be in the same MU instance.
+			       "rx0", "rx1", "rx2", "rx3";
+		include "gip3" if want to support general MU interrupt.
+- mboxes:	List of phandle of 4 MU channels for tx, 4 MU channels for
+		rx, and 1 optional MU channel for general interrupt.
+		All MU channels must be in the same MU instance.
 		Cross instances are not allowed. The MU instance can only
 		be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need
 		to make sure use the one which is not conflict with other
@@ -34,6 +36,7 @@ Required properties:
 		Channel 1 must be "tx1" or "rx1".
 		Channel 2 must be "tx2" or "rx2".
 		Channel 3 must be "tx3" or "rx3".
+		General interrupt rx channel must be "gip3".
 		e.g.
 		mboxes = <&lsio_mu1 0 0
 			  &lsio_mu1 0 1
@@ -42,10 +45,18 @@ Required properties:
 			  &lsio_mu1 1 0
 			  &lsio_mu1 1 1
 			  &lsio_mu1 1 2
-			  &lsio_mu1 1 3>;
+			  &lsio_mu1 1 3
+			  &lsio_mu1 3 3>;
 		See Documentation/devicetree/bindings/mailbox/fsl,mu.txt
 		for detailed mailbox binding.
 
+Note: Each mu which supports general interrupt should have an alias correctly
+numbered in "aliases" node.
+e.g.
+aliases {
+	mu1 = &lsio_mu1;
+};
+
 i.MX SCU Client Device Node:
 ============================================================
 
@@ -124,6 +135,10 @@ Required properties:
 
 Example (imx8qxp):
 -------------
+aliases {
+	mu1 = &lsio_mu1;
+};
+
 lsio_mu1: mailbox@5d1c0000 {
 	...
 	#mbox-cells = <2>;
@@ -133,7 +148,8 @@ firmware {
 	scu {
 		compatible = "fsl,imx-scu";
 		mbox-names = "tx0", "tx1", "tx2", "tx3",
-			     "rx0", "rx1", "rx2", "rx3";
+			     "rx0", "rx1", "rx2", "rx3",
+			     "gip3";
 		mboxes = <&lsio_mu1 0 0
 			  &lsio_mu1 0 1
 			  &lsio_mu1 0 2
@@ -141,7 +157,8 @@ firmware {
 			  &lsio_mu1 1 0
 			  &lsio_mu1 1 1
 			  &lsio_mu1 1 2
-			  &lsio_mu1 1 3>;
+			  &lsio_mu1 1 3
+			  &lsio_mu1 3 3>;
 
 		clk: clk {
 			compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 40+ messages in thread

end of thread, other threads:[~2019-04-09  3:09 UTC | newest]

Thread overview: 40+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-03-18  3:09 [PATCH V5 1/4] dt-bindings: fsl: scu: add general interrupt support Anson Huang
2019-03-18  3:09 ` Anson Huang
2019-03-18  3:09 ` Anson Huang
2019-03-18  3:09 ` [PATCH V5 2/4] firmware: imx: enable imx scu general irq function Anson Huang
2019-03-18  3:09   ` Anson Huang
2019-03-18  3:09   ` Anson Huang
2019-04-03  8:47   ` Shawn Guo
2019-04-03  8:47     ` Shawn Guo
2019-04-03  8:47     ` Shawn Guo
2019-04-08 10:35   ` Aisheng Dong
2019-04-08 10:35     ` Aisheng Dong
2019-04-08 10:35     ` Aisheng Dong
2019-04-08 13:05     ` Anson Huang
2019-04-08 13:05       ` Anson Huang
2019-04-08 13:05       ` Anson Huang
2019-03-18  3:10 ` [PATCH V5 3/4] arm64: dts: freescale: imx8qxp: enable scu general irq channel Anson Huang
2019-03-18  3:10   ` Anson Huang
2019-03-18  3:10   ` Anson Huang
2019-03-18  3:10 ` [PATCH V5 4/4] rtc: imx-sc: add rtc alarm support Anson Huang
2019-03-18  3:10   ` Anson Huang
2019-03-18  3:10   ` Anson Huang
2019-04-01 13:11   ` Alexandre Belloni
2019-04-01 13:11     ` Alexandre Belloni
2019-04-01 13:11     ` Alexandre Belloni
2019-04-01 15:26     ` Alexandre Belloni
2019-04-01 15:26       ` Alexandre Belloni
2019-04-01 15:26       ` Alexandre Belloni
2019-04-01 15:28   ` Alexandre Belloni
2019-04-01 15:28     ` Alexandre Belloni
2019-04-01 15:28     ` Alexandre Belloni
2019-04-08 11:08   ` Aisheng Dong
2019-04-08 11:08     ` Aisheng Dong
2019-04-08 11:08     ` Aisheng Dong
2019-04-09  1:59     ` Anson Huang
2019-04-09  1:59       ` Anson Huang
2019-04-09  3:08       ` Aisheng Dong
2019-04-09  3:08         ` Aisheng Dong
2019-04-09  3:08         ` Aisheng Dong
2019-04-01  2:38 ` [PATCH V5 1/4] dt-bindings: fsl: scu: add general interrupt support Anson Huang
2019-04-01  2:38   ` Anson Huang

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