From: David Hildenbrand <david@redhat.com> To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Thomas Huth <thuth@redhat.com>, Cornelia Huck <cohuck@redhat.com>, Richard Henderson <rth@twiddle.net>, David Hildenbrand <david@redhat.com> Subject: [Qemu-devel] [PATCH v1 27/41] s390x/tcg: Implement VECTOR ELEMENT ROTATE LEFT LOGICAL Date: Thu, 11 Apr 2019 12:08:22 +0200 [thread overview] Message-ID: <20190411100836.646-28-david@redhat.com> (raw) In-Reply-To: <20190411100836.646-1-david@redhat.com> Take care of properly taking the modulo of the count. We might later want to come back and create a variant of VERLL where the base register is 0, resulting in an immediate. Signed-off-by: David Hildenbrand <david@redhat.com> --- target/s390x/helper.h | 4 +++ target/s390x/insn-data.def | 3 ++ target/s390x/translate_vx.inc.c | 60 +++++++++++++++++++++++++++++++++ target/s390x/vec_int_helper.c | 40 ++++++++++++++++++++++ 4 files changed, 107 insertions(+) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index a306378950..f0efaf9cd5 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -202,6 +202,10 @@ DEF_HELPER_FLAGS_4(gvec_vmlo16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32) DEF_HELPER_FLAGS_4(gvec_vmlo32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32) DEF_HELPER_FLAGS_3(gvec_vpopct8, TCG_CALL_NO_RWG, void, ptr, cptr, i32) DEF_HELPER_FLAGS_3(gvec_vpopct16, TCG_CALL_NO_RWG, void, ptr, cptr, i32) +DEF_HELPER_FLAGS_4(gvec_verllv8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32) +DEF_HELPER_FLAGS_4(gvec_verllv16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32) +DEF_HELPER_FLAGS_4(gvec_verll8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32) +DEF_HELPER_FLAGS_4(gvec_verll16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32) #ifndef CONFIG_USER_ONLY DEF_HELPER_3(servc, i32, env, i64, i64) diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index 0f786d6ab1..e765c15941 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -1146,6 +1146,9 @@ F(0xe76f, VOC, VRR_c, VE, 0, 0, 0, 0, voc, 0, IF_VEC) /* VECTOR POPULATION COUNT */ F(0xe750, VPOPCT, VRR_a, V, 0, 0, 0, 0, vpopct, 0, IF_VEC) +/* VECTOR ELEMENT ROTATE LEFT LOGICAL */ + F(0xe773, VERLLV, VRR_c, V, 0, 0, 0, 0, verllv, 0, IF_VEC) + F(0xe733, VERLL, VRS_a, V, la2, 0, 0, 0, verll, 0, IF_VEC) #ifndef CONFIG_USER_ONLY /* COMPARE AND SWAP AND PURGE */ diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c index df17b8242d..92c14174da 100644 --- a/target/s390x/translate_vx.inc.c +++ b/target/s390x/translate_vx.inc.c @@ -185,6 +185,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr, #define gen_gvec_2(v1, v2, gen) \ tcg_gen_gvec_2(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ 16, 16, gen) +#define gen_gvec_2s(v1, v2, c, gen) \ + tcg_gen_gvec_2s(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ + 16, 16, c, gen) #define gen_gvec_3(v1, v2, v3, gen) \ tcg_gen_gvec_3(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ vec_full_reg_offset(v3), 16, 16, gen) @@ -1843,3 +1846,60 @@ static DisasJumpType op_vpopct(DisasContext *s, DisasOps *o) gen_gvec_2(get_field(s->fields, v1), get_field(s->fields, v2), &g[es]); return DISAS_NEXT; } + +static void gen_rll_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + TCGv_i32 t0 = tcg_temp_new_i32(); + + tcg_gen_andi_i32(t0, b, 31); + tcg_gen_rotl_i32(d, a, t0); + tcg_temp_free_i32(t0); +} + +static void gen_rll_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 t0 = tcg_temp_new_i64(); + + tcg_gen_andi_i64(t0, b, 63); + tcg_gen_rotl_i64(d, a, t0); + tcg_temp_free_i64(t0); +} + +static DisasJumpType op_verllv(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s->fields, m4); + static const GVecGen3 g[4] = { + { .fno = gen_helper_gvec_verllv8, }, + { .fno = gen_helper_gvec_verllv16, }, + { .fni4 = gen_rll_i32, }, + { .fni8 = gen_rll_i64, }, + }; + + if (es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + gen_gvec_3(get_field(s->fields, v1), get_field(s->fields, v2), + get_field(s->fields, v3), &g[es]); + return DISAS_NEXT; +} + +static DisasJumpType op_verll(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s->fields, m4); + static const GVecGen2s g[4] = { + { .fno = gen_helper_gvec_verll8, }, + { .fno = gen_helper_gvec_verll16, }, + { .fni4 = gen_rll_i32, }, + { .fni8 = gen_rll_i64, }, + }; + + if (es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + gen_gvec_2s(get_field(s->fields, v1), get_field(s->fields, v3), o->addr1, + &g[es]); + return DISAS_NEXT; +} diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c index f49d5c2ffb..ed67fa73fb 100644 --- a/target/s390x/vec_int_helper.c +++ b/target/s390x/vec_int_helper.c @@ -540,3 +540,43 @@ void HELPER(gvec_vpopct##BITS)(void *v1, const void *v2, uint32_t desc) \ } DEF_VPOPCT(8) DEF_VPOPCT(16) + +#define DEF_ROTL(BITS) \ +static uint##BITS##_t rotl##BITS(uint##BITS##_t a, uint8_t count) \ +{ \ + count &= BITS - 1; \ + return (a << count) | (a >> (BITS - count)); \ +} +DEF_ROTL(8) +DEF_ROTL(16) + +#define DEF_VERLLV(BITS) \ +void HELPER(gvec_verllv##BITS)(void *v1, const void *v2, const void *v3, \ + uint32_t desc) \ +{ \ + int i; \ + \ + for (i = 0; i < (128 / BITS); i++) { \ + const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \ + const uint##BITS##_t b = s390_vec_read_element##BITS(v3, i); \ + \ + s390_vec_write_element##BITS(v1, i, rotl##BITS(a, b)); \ + } \ +} +DEF_VERLLV(8) +DEF_VERLLV(16) + +#define DEF_VERLL(BITS) \ +void HELPER(gvec_verll##BITS)(void *v1, const void *v2, uint64_t count, \ + uint32_t desc) \ +{ \ + int i; \ + \ + for (i = 0; i < (128 / BITS); i++) { \ + const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \ + \ + s390_vec_write_element##BITS(v1, i, rotl##BITS(a, count)); \ + } \ +} +DEF_VERLL(8) +DEF_VERLL(16) -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: David Hildenbrand <david@redhat.com> To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Cornelia Huck <cohuck@redhat.com>, David Hildenbrand <david@redhat.com>, Thomas Huth <thuth@redhat.com>, Richard Henderson <rth@twiddle.net> Subject: [Qemu-devel] [PATCH v1 27/41] s390x/tcg: Implement VECTOR ELEMENT ROTATE LEFT LOGICAL Date: Thu, 11 Apr 2019 12:08:22 +0200 [thread overview] Message-ID: <20190411100836.646-28-david@redhat.com> (raw) Message-ID: <20190411100822.wWnTToIRGoL0oBj5_ZcDm3yeZZyMsPfZwolWctDznjo@z> (raw) In-Reply-To: <20190411100836.646-1-david@redhat.com> Take care of properly taking the modulo of the count. We might later want to come back and create a variant of VERLL where the base register is 0, resulting in an immediate. Signed-off-by: David Hildenbrand <david@redhat.com> --- target/s390x/helper.h | 4 +++ target/s390x/insn-data.def | 3 ++ target/s390x/translate_vx.inc.c | 60 +++++++++++++++++++++++++++++++++ target/s390x/vec_int_helper.c | 40 ++++++++++++++++++++++ 4 files changed, 107 insertions(+) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index a306378950..f0efaf9cd5 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -202,6 +202,10 @@ DEF_HELPER_FLAGS_4(gvec_vmlo16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32) DEF_HELPER_FLAGS_4(gvec_vmlo32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32) DEF_HELPER_FLAGS_3(gvec_vpopct8, TCG_CALL_NO_RWG, void, ptr, cptr, i32) DEF_HELPER_FLAGS_3(gvec_vpopct16, TCG_CALL_NO_RWG, void, ptr, cptr, i32) +DEF_HELPER_FLAGS_4(gvec_verllv8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32) +DEF_HELPER_FLAGS_4(gvec_verllv16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32) +DEF_HELPER_FLAGS_4(gvec_verll8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32) +DEF_HELPER_FLAGS_4(gvec_verll16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32) #ifndef CONFIG_USER_ONLY DEF_HELPER_3(servc, i32, env, i64, i64) diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index 0f786d6ab1..e765c15941 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -1146,6 +1146,9 @@ F(0xe76f, VOC, VRR_c, VE, 0, 0, 0, 0, voc, 0, IF_VEC) /* VECTOR POPULATION COUNT */ F(0xe750, VPOPCT, VRR_a, V, 0, 0, 0, 0, vpopct, 0, IF_VEC) +/* VECTOR ELEMENT ROTATE LEFT LOGICAL */ + F(0xe773, VERLLV, VRR_c, V, 0, 0, 0, 0, verllv, 0, IF_VEC) + F(0xe733, VERLL, VRS_a, V, la2, 0, 0, 0, verll, 0, IF_VEC) #ifndef CONFIG_USER_ONLY /* COMPARE AND SWAP AND PURGE */ diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c index df17b8242d..92c14174da 100644 --- a/target/s390x/translate_vx.inc.c +++ b/target/s390x/translate_vx.inc.c @@ -185,6 +185,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr, #define gen_gvec_2(v1, v2, gen) \ tcg_gen_gvec_2(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ 16, 16, gen) +#define gen_gvec_2s(v1, v2, c, gen) \ + tcg_gen_gvec_2s(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ + 16, 16, c, gen) #define gen_gvec_3(v1, v2, v3, gen) \ tcg_gen_gvec_3(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \ vec_full_reg_offset(v3), 16, 16, gen) @@ -1843,3 +1846,60 @@ static DisasJumpType op_vpopct(DisasContext *s, DisasOps *o) gen_gvec_2(get_field(s->fields, v1), get_field(s->fields, v2), &g[es]); return DISAS_NEXT; } + +static void gen_rll_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + TCGv_i32 t0 = tcg_temp_new_i32(); + + tcg_gen_andi_i32(t0, b, 31); + tcg_gen_rotl_i32(d, a, t0); + tcg_temp_free_i32(t0); +} + +static void gen_rll_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 t0 = tcg_temp_new_i64(); + + tcg_gen_andi_i64(t0, b, 63); + tcg_gen_rotl_i64(d, a, t0); + tcg_temp_free_i64(t0); +} + +static DisasJumpType op_verllv(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s->fields, m4); + static const GVecGen3 g[4] = { + { .fno = gen_helper_gvec_verllv8, }, + { .fno = gen_helper_gvec_verllv16, }, + { .fni4 = gen_rll_i32, }, + { .fni8 = gen_rll_i64, }, + }; + + if (es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + gen_gvec_3(get_field(s->fields, v1), get_field(s->fields, v2), + get_field(s->fields, v3), &g[es]); + return DISAS_NEXT; +} + +static DisasJumpType op_verll(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s->fields, m4); + static const GVecGen2s g[4] = { + { .fno = gen_helper_gvec_verll8, }, + { .fno = gen_helper_gvec_verll16, }, + { .fni4 = gen_rll_i32, }, + { .fni8 = gen_rll_i64, }, + }; + + if (es > ES_64) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + gen_gvec_2s(get_field(s->fields, v1), get_field(s->fields, v3), o->addr1, + &g[es]); + return DISAS_NEXT; +} diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c index f49d5c2ffb..ed67fa73fb 100644 --- a/target/s390x/vec_int_helper.c +++ b/target/s390x/vec_int_helper.c @@ -540,3 +540,43 @@ void HELPER(gvec_vpopct##BITS)(void *v1, const void *v2, uint32_t desc) \ } DEF_VPOPCT(8) DEF_VPOPCT(16) + +#define DEF_ROTL(BITS) \ +static uint##BITS##_t rotl##BITS(uint##BITS##_t a, uint8_t count) \ +{ \ + count &= BITS - 1; \ + return (a << count) | (a >> (BITS - count)); \ +} +DEF_ROTL(8) +DEF_ROTL(16) + +#define DEF_VERLLV(BITS) \ +void HELPER(gvec_verllv##BITS)(void *v1, const void *v2, const void *v3, \ + uint32_t desc) \ +{ \ + int i; \ + \ + for (i = 0; i < (128 / BITS); i++) { \ + const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \ + const uint##BITS##_t b = s390_vec_read_element##BITS(v3, i); \ + \ + s390_vec_write_element##BITS(v1, i, rotl##BITS(a, b)); \ + } \ +} +DEF_VERLLV(8) +DEF_VERLLV(16) + +#define DEF_VERLL(BITS) \ +void HELPER(gvec_verll##BITS)(void *v1, const void *v2, uint64_t count, \ + uint32_t desc) \ +{ \ + int i; \ + \ + for (i = 0; i < (128 / BITS); i++) { \ + const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \ + \ + s390_vec_write_element##BITS(v1, i, rotl##BITS(a, count)); \ + } \ +} +DEF_VERLL(8) +DEF_VERLL(16) -- 2.20.1
next prev parent reply other threads:[~2019-04-11 10:24 UTC|newest] Thread overview: 152+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-04-11 10:07 [Qemu-devel] [PATCH v1 00/41] s390x/tcg: Vector Instruction Support Part 2 David Hildenbrand 2019-04-11 10:07 ` David Hildenbrand 2019-04-11 10:07 ` [Qemu-devel] [PATCH v1 01/41] tcg: Implement tcg_gen_gvec_3i() David Hildenbrand 2019-04-11 10:07 ` David Hildenbrand 2019-04-11 10:07 ` [Qemu-devel] [PATCH v1 02/41] s390x/tcg: Implement VECTOR ADD David Hildenbrand 2019-04-11 10:07 ` David Hildenbrand 2019-04-12 18:28 ` Richard Henderson 2019-04-12 18:28 ` Richard Henderson 2019-04-11 10:07 ` [Qemu-devel] [PATCH v1 03/41] s390x/tcg: Implement VECTOR ADD COMPUTE CARRY David Hildenbrand 2019-04-11 10:07 ` David Hildenbrand 2019-04-12 21:05 ` Richard Henderson 2019-04-12 21:05 ` Richard Henderson 2019-04-16 8:01 ` David Hildenbrand 2019-04-16 8:01 ` David Hildenbrand 2019-04-16 8:17 ` Richard Henderson 2019-04-16 8:17 ` Richard Henderson 2019-04-16 8:33 ` David Hildenbrand 2019-04-16 8:33 ` David Hildenbrand 2019-04-16 8:43 ` Richard Henderson 2019-04-16 8:43 ` Richard Henderson 2019-04-16 8:46 ` David Hildenbrand 2019-04-16 8:46 ` David Hildenbrand 2019-04-11 10:07 ` [Qemu-devel] [PATCH v1 04/41] s390x/tcg: Implement VECTOR ADD WITH CARRY David Hildenbrand 2019-04-11 10:07 ` David Hildenbrand 2019-04-12 21:36 ` Richard Henderson 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 05/41] s390x/tcg: Implement VECTOR ADD WITH CARRY COMPUTE CARRY David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-12 21:58 ` Richard Henderson 2019-04-16 8:40 ` David Hildenbrand 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 06/41] s390x/tcg: Implement VECTOR AND (WITH COMPLEMENT) David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-12 21:59 ` Richard Henderson 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 07/41] s390x/tcg: Implement VECTOR AVERAGE David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-12 22:34 ` Richard Henderson 2019-04-16 8:52 ` David Hildenbrand 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 08/41] s390x/tcg: Implement VECTOR AVERAGE LOGICAL David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-12 22:35 ` Richard Henderson 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 09/41] s390x/tcg: Implement VECTOR CHECKSUM David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-12 23:01 ` Richard Henderson 2019-04-16 8:58 ` David Hildenbrand 2019-04-16 9:08 ` Richard Henderson 2019-04-16 9:13 ` David Hildenbrand 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 10/41] s390x/tcg: Implement VECTOR ELEMENT COMPARE * David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-12 23:14 ` Richard Henderson 2019-04-16 9:05 ` David Hildenbrand 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 11/41] s390x/tcg: Implement VECTOR " David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-12 23:17 ` Richard Henderson 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 12/41] s390x/tcg: Implement VECTOR COUNT LEADING ZEROS David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-12 23:21 ` Richard Henderson 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 13/41] s390x/tcg: Implement VECTOR COUNT TRAILING ZEROS David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-12 23:23 ` Richard Henderson 2019-04-16 9:07 ` David Hildenbrand 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 14/41] s390x/tcg: Implement VECTOR EXCLUSIVE OR David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-12 23:23 ` Richard Henderson 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 15/41] s390x/tcg: Implement VECTOR GALOIS FIELD MULTIPLY SUM (AND ACCUMULATE) David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-12 23:44 ` Richard Henderson 2019-04-16 9:10 ` David Hildenbrand 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 16/41] s390x/tcg: Implement VECTOR LOAD COMPLEMENT David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-12 23:47 ` Richard Henderson 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 17/41] s390x/tcg: Implement VECTOR LOAD POSITIVE David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-12 23:50 ` Richard Henderson 2019-04-16 9:16 ` David Hildenbrand 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 18/41] s390x/tcg: Implement VECTOR (MAXIMUM|MINIMUM) (LOGICAL) David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-12 23:51 ` Richard Henderson 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 19/41] s390x/tcg: Implement VECTOR MULTIPLY AND ADD * David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-13 0:01 ` Richard Henderson 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 20/41] s390x/tcg: Implement VECTOR MULTIPLY * David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-13 0:04 ` Richard Henderson 2019-04-16 9:23 ` David Hildenbrand 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 21/41] s390x/tcg: Implement VECTOR NAND David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-13 0:05 ` Richard Henderson 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 22/41] s390x/tcg: Implement VECTOR NOR David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-13 0:05 ` Richard Henderson 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 23/41] s390x/tcg: Implement VECTOR NOT EXCLUSIVE OR David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-13 0:06 ` Richard Henderson 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 24/41] s390x/tcg: Implement VECTOR OR David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-13 0:06 ` Richard Henderson 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 25/41] s390x/tcg: Implement VECTOR OR WITH COMPLEMENT David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-13 0:07 ` Richard Henderson 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 26/41] s390x/tcg: Implement VECTOR POPULATION COUNT David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-13 0:08 ` Richard Henderson 2019-04-11 10:08 ` David Hildenbrand [this message] 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 27/41] s390x/tcg: Implement VECTOR ELEMENT ROTATE LEFT LOGICAL David Hildenbrand 2019-04-13 0:15 ` Richard Henderson 2019-04-16 9:27 ` David Hildenbrand 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 28/41] s390x/tcg: Implement VECTOR ELEMENT ROTATE AND INSERT UNDER MASK David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-13 0:29 ` Richard Henderson 2019-04-16 9:35 ` David Hildenbrand 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 29/41] s390x/tcg: Implement VECTOR ELEMENT SHIFT David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-13 0:31 ` Richard Henderson 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 30/41] s390x/tcg: Implement VECTOR SHIFT LEFT (BY BYTE) David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-13 0:36 ` Richard Henderson 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 31/41] s390x/tcg: Implement VECTOR SHIFT LEFT DOUBLE BY BYTE David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-13 0:54 ` Richard Henderson 2019-04-16 9:45 ` David Hildenbrand 2019-04-16 15:21 ` Richard Henderson 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 32/41] s390x/tcg: Implement VECTOR SHIFT RIGHT ARITHMETIC David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-13 5:48 ` Richard Henderson 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 33/41] s390x/tcg: Implement VECTOR SHIFT RIGHT LOGICAL * David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-13 5:48 ` Richard Henderson 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 34/41] s390x/tcg: Implement VECTOR SUBTRACT David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-13 5:49 ` Richard Henderson 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 35/41] s390x/tcg: Implement VECTOR SUBTRACT COMPUTE BORROW INDICATION David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-13 5:51 ` Richard Henderson 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 36/41] s390x/tcg: Implement VECTOR SUBTRACT WITH " David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-13 5:52 ` Richard Henderson 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 37/41] s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW COMPUTE " David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-13 6:11 ` Richard Henderson 2019-04-16 18:26 ` David Hildenbrand 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 38/41] s390x/tcg: Implement VECTOR SUM ACROSS DOUBLEWORD David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-13 6:15 ` Richard Henderson 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 39/41] s390x/tcg: Implement VECTOR SUM ACROSS QUADWORD David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-13 6:17 ` Richard Henderson 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 40/41] s390x/tcg: Implement VECTOR SUM ACROSS WORD David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-13 6:19 ` Richard Henderson 2019-04-11 10:08 ` [Qemu-devel] [PATCH v1 41/41] s390x/tcg: Implement VECTOR TEST UNDER MASK David Hildenbrand 2019-04-11 10:08 ` David Hildenbrand 2019-04-13 6:28 ` Richard Henderson 2019-04-16 18:20 ` David Hildenbrand
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