* [PATCH v3 0/3] Allow accessing CSR using CSR number @ 2019-04-15 9:37 ` Anup Patel 0 siblings, 0 replies; 20+ messages in thread From: Anup Patel @ 2019-04-15 9:37 UTC (permalink / raw) To: Palmer Dabbelt, Albert Ou Cc: Atish Patra, Paul Walmsley, Christoph Hellwig, linux-riscv, linux-kernel, Anup Patel This patch series adds support to access CSR using both CSR name and CSR numbers. Also, we should prefer accessing CSRs using their CSR numbers because: 1. It compiles fine with older toolchains. 2. We can use latest CSR names in #define macro names of CSR numbers as-per RISC-V spec. (e.g. sptbr => CSR_SATP, sbadaddr => CSR_STVAL, etc.) 3. We can access newly added CSRs even if toolchain does not recognize newly addes CSRs by name. (e.g. BSSTATUS, BSIE, SSIP, etc.) The patchset can be found in riscv_csr_number_v3 branch of https//github.com/avpatel/linux.git Changes since v2: - Dropped PATCH1 which added asm/encoding.h - Added new PATCH1 which beautifies asm/csr.h by using tabs to align macro values Changes since v1: - Squash PATCH2 into cpatch3 - Added new PATCH2 to add interrupt related SCAUSE defines in asm/encoding.h Anup Patel (3): RISC-V: Use tabs to align macro values in asm/csr.h RISC-V: Add interrupt related SCAUSE defines in asm/csr.h RISC-V: Access CSRs using CSR numbers arch/riscv/include/asm/csr.h | 127 +++++++++++++++++---------- arch/riscv/include/asm/irqflags.h | 10 +-- arch/riscv/include/asm/mmu_context.h | 7 +- arch/riscv/kernel/entry.S | 22 ++--- arch/riscv/kernel/head.S | 12 +-- arch/riscv/kernel/irq.c | 23 +---- arch/riscv/kernel/perf_event.c | 4 +- arch/riscv/kernel/smp.c | 2 +- arch/riscv/kernel/traps.c | 6 +- arch/riscv/mm/fault.c | 6 +- 10 files changed, 115 insertions(+), 104 deletions(-) -- 2.17.1 ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 0/3] Allow accessing CSR using CSR number @ 2019-04-15 9:37 ` Anup Patel 0 siblings, 0 replies; 20+ messages in thread From: Anup Patel @ 2019-04-15 9:37 UTC (permalink / raw) To: Palmer Dabbelt, Albert Ou Cc: Anup Patel, linux-kernel, Christoph Hellwig, Atish Patra, Paul Walmsley, linux-riscv This patch series adds support to access CSR using both CSR name and CSR numbers. Also, we should prefer accessing CSRs using their CSR numbers because: 1. It compiles fine with older toolchains. 2. We can use latest CSR names in #define macro names of CSR numbers as-per RISC-V spec. (e.g. sptbr => CSR_SATP, sbadaddr => CSR_STVAL, etc.) 3. We can access newly added CSRs even if toolchain does not recognize newly addes CSRs by name. (e.g. BSSTATUS, BSIE, SSIP, etc.) The patchset can be found in riscv_csr_number_v3 branch of https//github.com/avpatel/linux.git Changes since v2: - Dropped PATCH1 which added asm/encoding.h - Added new PATCH1 which beautifies asm/csr.h by using tabs to align macro values Changes since v1: - Squash PATCH2 into cpatch3 - Added new PATCH2 to add interrupt related SCAUSE defines in asm/encoding.h Anup Patel (3): RISC-V: Use tabs to align macro values in asm/csr.h RISC-V: Add interrupt related SCAUSE defines in asm/csr.h RISC-V: Access CSRs using CSR numbers arch/riscv/include/asm/csr.h | 127 +++++++++++++++++---------- arch/riscv/include/asm/irqflags.h | 10 +-- arch/riscv/include/asm/mmu_context.h | 7 +- arch/riscv/kernel/entry.S | 22 ++--- arch/riscv/kernel/head.S | 12 +-- arch/riscv/kernel/irq.c | 23 +---- arch/riscv/kernel/perf_event.c | 4 +- arch/riscv/kernel/smp.c | 2 +- arch/riscv/kernel/traps.c | 6 +- arch/riscv/mm/fault.c | 6 +- 10 files changed, 115 insertions(+), 104 deletions(-) -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 1/3] RISC-V: Use tabs to align macro values in asm/csr.h 2019-04-15 9:37 ` Anup Patel @ 2019-04-15 9:37 ` Anup Patel -1 siblings, 0 replies; 20+ messages in thread From: Anup Patel @ 2019-04-15 9:37 UTC (permalink / raw) To: Palmer Dabbelt, Albert Ou Cc: Atish Patra, Paul Walmsley, Christoph Hellwig, linux-riscv, linux-kernel, Anup Patel The spacing between macro name and value is not consistent in asm/csr.h. This patch beautifies asm/csr.h by using tabs to align macro values instead of spaces. Signed-off-by: Anup Patel <anup.patel@wdc.com> --- arch/riscv/include/asm/csr.h | 76 ++++++++++++++++++------------------ 1 file changed, 38 insertions(+), 38 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 28a0d1cb374c..2ae54a7386f1 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -17,54 +17,54 @@ #include <linux/const.h> /* Status register flags */ -#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ -#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ -#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ -#define SR_SUM _AC(0x00040000, UL) /* Supervisor may access User Memory */ - -#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ -#define SR_FS_OFF _AC(0x00000000, UL) -#define SR_FS_INITIAL _AC(0x00002000, UL) -#define SR_FS_CLEAN _AC(0x00004000, UL) -#define SR_FS_DIRTY _AC(0x00006000, UL) - -#define SR_XS _AC(0x00018000, UL) /* Extension Status */ -#define SR_XS_OFF _AC(0x00000000, UL) -#define SR_XS_INITIAL _AC(0x00008000, UL) -#define SR_XS_CLEAN _AC(0x00010000, UL) -#define SR_XS_DIRTY _AC(0x00018000, UL) +#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ +#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ +#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ +#define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ + +#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ +#define SR_FS_OFF _AC(0x00000000, UL) +#define SR_FS_INITIAL _AC(0x00002000, UL) +#define SR_FS_CLEAN _AC(0x00004000, UL) +#define SR_FS_DIRTY _AC(0x00006000, UL) + +#define SR_XS _AC(0x00018000, UL) /* Extension Status */ +#define SR_XS_OFF _AC(0x00000000, UL) +#define SR_XS_INITIAL _AC(0x00008000, UL) +#define SR_XS_CLEAN _AC(0x00010000, UL) +#define SR_XS_DIRTY _AC(0x00018000, UL) #ifndef CONFIG_64BIT -#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ +#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ #else -#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ +#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ #endif /* SATP flags */ -#if __riscv_xlen == 32 -#define SATP_PPN _AC(0x003FFFFF, UL) -#define SATP_MODE_32 _AC(0x80000000, UL) -#define SATP_MODE SATP_MODE_32 +#ifndef CONFIG_64BIT +#define SATP_PPN _AC(0x003FFFFF, UL) +#define SATP_MODE_32 _AC(0x80000000, UL) +#define SATP_MODE SATP_MODE_32 #else -#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) -#define SATP_MODE_39 _AC(0x8000000000000000, UL) -#define SATP_MODE SATP_MODE_39 +#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) +#define SATP_MODE_39 _AC(0x8000000000000000, UL) +#define SATP_MODE SATP_MODE_39 #endif /* Interrupt Enable and Interrupt Pending flags */ -#define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */ -#define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */ -#define SIE_SEIE _AC(0x00000200, UL) /* External Interrupt Enable */ - -#define EXC_INST_MISALIGNED 0 -#define EXC_INST_ACCESS 1 -#define EXC_BREAKPOINT 3 -#define EXC_LOAD_ACCESS 5 -#define EXC_STORE_ACCESS 7 -#define EXC_SYSCALL 8 -#define EXC_INST_PAGE_FAULT 12 -#define EXC_LOAD_PAGE_FAULT 13 -#define EXC_STORE_PAGE_FAULT 15 +#define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */ +#define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */ +#define SIE_SEIE _AC(0x00000200, UL) /* External Interrupt Enable */ + +#define EXC_INST_MISALIGNED 0 +#define EXC_INST_ACCESS 1 +#define EXC_BREAKPOINT 3 +#define EXC_LOAD_ACCESS 5 +#define EXC_STORE_ACCESS 7 +#define EXC_SYSCALL 8 +#define EXC_INST_PAGE_FAULT 12 +#define EXC_LOAD_PAGE_FAULT 13 +#define EXC_STORE_PAGE_FAULT 15 #ifndef __ASSEMBLY__ -- 2.17.1 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v3 1/3] RISC-V: Use tabs to align macro values in asm/csr.h @ 2019-04-15 9:37 ` Anup Patel 0 siblings, 0 replies; 20+ messages in thread From: Anup Patel @ 2019-04-15 9:37 UTC (permalink / raw) To: Palmer Dabbelt, Albert Ou Cc: Anup Patel, linux-kernel, Christoph Hellwig, Atish Patra, Paul Walmsley, linux-riscv The spacing between macro name and value is not consistent in asm/csr.h. This patch beautifies asm/csr.h by using tabs to align macro values instead of spaces. Signed-off-by: Anup Patel <anup.patel@wdc.com> --- arch/riscv/include/asm/csr.h | 76 ++++++++++++++++++------------------ 1 file changed, 38 insertions(+), 38 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 28a0d1cb374c..2ae54a7386f1 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -17,54 +17,54 @@ #include <linux/const.h> /* Status register flags */ -#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ -#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ -#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ -#define SR_SUM _AC(0x00040000, UL) /* Supervisor may access User Memory */ - -#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ -#define SR_FS_OFF _AC(0x00000000, UL) -#define SR_FS_INITIAL _AC(0x00002000, UL) -#define SR_FS_CLEAN _AC(0x00004000, UL) -#define SR_FS_DIRTY _AC(0x00006000, UL) - -#define SR_XS _AC(0x00018000, UL) /* Extension Status */ -#define SR_XS_OFF _AC(0x00000000, UL) -#define SR_XS_INITIAL _AC(0x00008000, UL) -#define SR_XS_CLEAN _AC(0x00010000, UL) -#define SR_XS_DIRTY _AC(0x00018000, UL) +#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ +#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ +#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ +#define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ + +#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ +#define SR_FS_OFF _AC(0x00000000, UL) +#define SR_FS_INITIAL _AC(0x00002000, UL) +#define SR_FS_CLEAN _AC(0x00004000, UL) +#define SR_FS_DIRTY _AC(0x00006000, UL) + +#define SR_XS _AC(0x00018000, UL) /* Extension Status */ +#define SR_XS_OFF _AC(0x00000000, UL) +#define SR_XS_INITIAL _AC(0x00008000, UL) +#define SR_XS_CLEAN _AC(0x00010000, UL) +#define SR_XS_DIRTY _AC(0x00018000, UL) #ifndef CONFIG_64BIT -#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ +#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ #else -#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ +#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ #endif /* SATP flags */ -#if __riscv_xlen == 32 -#define SATP_PPN _AC(0x003FFFFF, UL) -#define SATP_MODE_32 _AC(0x80000000, UL) -#define SATP_MODE SATP_MODE_32 +#ifndef CONFIG_64BIT +#define SATP_PPN _AC(0x003FFFFF, UL) +#define SATP_MODE_32 _AC(0x80000000, UL) +#define SATP_MODE SATP_MODE_32 #else -#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) -#define SATP_MODE_39 _AC(0x8000000000000000, UL) -#define SATP_MODE SATP_MODE_39 +#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) +#define SATP_MODE_39 _AC(0x8000000000000000, UL) +#define SATP_MODE SATP_MODE_39 #endif /* Interrupt Enable and Interrupt Pending flags */ -#define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */ -#define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */ -#define SIE_SEIE _AC(0x00000200, UL) /* External Interrupt Enable */ - -#define EXC_INST_MISALIGNED 0 -#define EXC_INST_ACCESS 1 -#define EXC_BREAKPOINT 3 -#define EXC_LOAD_ACCESS 5 -#define EXC_STORE_ACCESS 7 -#define EXC_SYSCALL 8 -#define EXC_INST_PAGE_FAULT 12 -#define EXC_LOAD_PAGE_FAULT 13 -#define EXC_STORE_PAGE_FAULT 15 +#define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */ +#define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */ +#define SIE_SEIE _AC(0x00000200, UL) /* External Interrupt Enable */ + +#define EXC_INST_MISALIGNED 0 +#define EXC_INST_ACCESS 1 +#define EXC_BREAKPOINT 3 +#define EXC_LOAD_ACCESS 5 +#define EXC_STORE_ACCESS 7 +#define EXC_SYSCALL 8 +#define EXC_INST_PAGE_FAULT 12 +#define EXC_LOAD_PAGE_FAULT 13 +#define EXC_STORE_PAGE_FAULT 15 #ifndef __ASSEMBLY__ -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v3 1/3] RISC-V: Use tabs to align macro values in asm/csr.h 2019-04-15 9:37 ` Anup Patel @ 2019-04-24 6:27 ` Christoph Hellwig -1 siblings, 0 replies; 20+ messages in thread From: Christoph Hellwig @ 2019-04-24 6:27 UTC (permalink / raw) To: Anup Patel Cc: Palmer Dabbelt, Albert Ou, linux-kernel, Christoph Hellwig, Atish Patra, Paul Walmsley, linux-riscv On Mon, Apr 15, 2019 at 09:37:17AM +0000, Anup Patel wrote: > The spacing between macro name and value is not consistent in > asm/csr.h. This patch beautifies asm/csr.h by using tabs to align > macro values instead of spaces. > > Signed-off-by: Anup Patel <anup.patel@wdc.com> Looks good, Reviewed-by: Christoph Hellwig <hch@lst.de> ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 1/3] RISC-V: Use tabs to align macro values in asm/csr.h @ 2019-04-24 6:27 ` Christoph Hellwig 0 siblings, 0 replies; 20+ messages in thread From: Christoph Hellwig @ 2019-04-24 6:27 UTC (permalink / raw) To: Anup Patel Cc: Albert Ou, Palmer Dabbelt, linux-kernel, Christoph Hellwig, Atish Patra, Paul Walmsley, linux-riscv On Mon, Apr 15, 2019 at 09:37:17AM +0000, Anup Patel wrote: > The spacing between macro name and value is not consistent in > asm/csr.h. This patch beautifies asm/csr.h by using tabs to align > macro values instead of spaces. > > Signed-off-by: Anup Patel <anup.patel@wdc.com> Looks good, Reviewed-by: Christoph Hellwig <hch@lst.de> _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 2/3] RISC-V: Add interrupt related SCAUSE defines in asm/csr.h 2019-04-15 9:37 ` Anup Patel @ 2019-04-15 9:37 ` Anup Patel -1 siblings, 0 replies; 20+ messages in thread From: Anup Patel @ 2019-04-15 9:37 UTC (permalink / raw) To: Palmer Dabbelt, Albert Ou Cc: Atish Patra, Paul Walmsley, Christoph Hellwig, linux-riscv, linux-kernel, Anup Patel This patch adds SCAUSE interrupt flag and SCAUSE interrupt related defines to asm/csr.h. We also use these defines in kernel/irq.c and express SIE/SIP flags in-terms of SCAUSE interrupt causes. Signed-off-by: Anup Patel <anup.patel@wdc.com> --- arch/riscv/include/asm/csr.h | 25 +++++++++++++++++++++---- arch/riscv/kernel/irq.c | 23 ++++------------------- 2 files changed, 25 insertions(+), 23 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 2ae54a7386f1..ab40a936cb2d 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -51,10 +51,22 @@ #define SATP_MODE SATP_MODE_39 #endif -/* Interrupt Enable and Interrupt Pending flags */ -#define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */ -#define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */ -#define SIE_SEIE _AC(0x00000200, UL) /* External Interrupt Enable */ +/* SCAUSE */ +#ifdef CONFIG_64BIT +#define SCAUSE_IRQ_FLAG _AC(0x8000000000000000, UL) +#else +#define SCAUSE_IRQ_FLAG _AC(0x80000000, UL) +#endif + +#define IRQ_U_SOFT 0 +#define IRQ_S_SOFT 1 +#define IRQ_M_SOFT 3 +#define IRQ_U_TIMER 4 +#define IRQ_S_TIMER 5 +#define IRQ_M_TIMER 7 +#define IRQ_U_EXT 8 +#define IRQ_S_EXT 9 +#define IRQ_M_EXT 11 #define EXC_INST_MISALIGNED 0 #define EXC_INST_ACCESS 1 @@ -66,6 +78,11 @@ #define EXC_LOAD_PAGE_FAULT 13 #define EXC_STORE_PAGE_FAULT 15 +/* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */ +#define SIE_SSIE (_AC(0x1, UL) << IRQ_S_SOFT) +#define SIE_STIE (_AC(0x1, UL) << IRQ_S_TIMER) +#define SIE_SEIE (_AC(0x1, UL) << IRQ_S_EXT) + #ifndef __ASSEMBLY__ #define csr_swap(csr, val) \ diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c index 48e6b7db83a1..68e5025b5a58 100644 --- a/arch/riscv/kernel/irq.c +++ b/arch/riscv/kernel/irq.c @@ -11,21 +11,6 @@ #include <linux/seq_file.h> #include <asm/smp.h> -/* - * Possible interrupt causes: - */ -#define INTERRUPT_CAUSE_SOFTWARE 1 -#define INTERRUPT_CAUSE_TIMER 5 -#define INTERRUPT_CAUSE_EXTERNAL 9 - -/* - * The high order bit of the trap cause register is always set for - * interrupts, which allows us to differentiate them from exceptions - * quickly. The INTERRUPT_CAUSE_* macros don't contain that bit, so we - * need to mask it off. - */ -#define INTERRUPT_CAUSE_FLAG (1UL << (__riscv_xlen - 1)) - int arch_show_interrupts(struct seq_file *p, int prec) { show_ipi_stats(p, prec); @@ -37,12 +22,12 @@ asmlinkage void __irq_entry do_IRQ(struct pt_regs *regs) struct pt_regs *old_regs = set_irq_regs(regs); irq_enter(); - switch (regs->scause & ~INTERRUPT_CAUSE_FLAG) { - case INTERRUPT_CAUSE_TIMER: + switch (regs->scause & ~SCAUSE_IRQ_FLAG) { + case IRQ_S_TIMER: riscv_timer_interrupt(); break; #ifdef CONFIG_SMP - case INTERRUPT_CAUSE_SOFTWARE: + case IRQ_S_SOFT: /* * We only use software interrupts to pass IPIs, so if a non-SMP * system gets one, then we don't know what to do. @@ -50,7 +35,7 @@ asmlinkage void __irq_entry do_IRQ(struct pt_regs *regs) riscv_software_interrupt(); break; #endif - case INTERRUPT_CAUSE_EXTERNAL: + case IRQ_S_EXT: handle_arch_irq(regs); break; default: -- 2.17.1 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v3 2/3] RISC-V: Add interrupt related SCAUSE defines in asm/csr.h @ 2019-04-15 9:37 ` Anup Patel 0 siblings, 0 replies; 20+ messages in thread From: Anup Patel @ 2019-04-15 9:37 UTC (permalink / raw) To: Palmer Dabbelt, Albert Ou Cc: Anup Patel, linux-kernel, Christoph Hellwig, Atish Patra, Paul Walmsley, linux-riscv This patch adds SCAUSE interrupt flag and SCAUSE interrupt related defines to asm/csr.h. We also use these defines in kernel/irq.c and express SIE/SIP flags in-terms of SCAUSE interrupt causes. Signed-off-by: Anup Patel <anup.patel@wdc.com> --- arch/riscv/include/asm/csr.h | 25 +++++++++++++++++++++---- arch/riscv/kernel/irq.c | 23 ++++------------------- 2 files changed, 25 insertions(+), 23 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 2ae54a7386f1..ab40a936cb2d 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -51,10 +51,22 @@ #define SATP_MODE SATP_MODE_39 #endif -/* Interrupt Enable and Interrupt Pending flags */ -#define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */ -#define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */ -#define SIE_SEIE _AC(0x00000200, UL) /* External Interrupt Enable */ +/* SCAUSE */ +#ifdef CONFIG_64BIT +#define SCAUSE_IRQ_FLAG _AC(0x8000000000000000, UL) +#else +#define SCAUSE_IRQ_FLAG _AC(0x80000000, UL) +#endif + +#define IRQ_U_SOFT 0 +#define IRQ_S_SOFT 1 +#define IRQ_M_SOFT 3 +#define IRQ_U_TIMER 4 +#define IRQ_S_TIMER 5 +#define IRQ_M_TIMER 7 +#define IRQ_U_EXT 8 +#define IRQ_S_EXT 9 +#define IRQ_M_EXT 11 #define EXC_INST_MISALIGNED 0 #define EXC_INST_ACCESS 1 @@ -66,6 +78,11 @@ #define EXC_LOAD_PAGE_FAULT 13 #define EXC_STORE_PAGE_FAULT 15 +/* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */ +#define SIE_SSIE (_AC(0x1, UL) << IRQ_S_SOFT) +#define SIE_STIE (_AC(0x1, UL) << IRQ_S_TIMER) +#define SIE_SEIE (_AC(0x1, UL) << IRQ_S_EXT) + #ifndef __ASSEMBLY__ #define csr_swap(csr, val) \ diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c index 48e6b7db83a1..68e5025b5a58 100644 --- a/arch/riscv/kernel/irq.c +++ b/arch/riscv/kernel/irq.c @@ -11,21 +11,6 @@ #include <linux/seq_file.h> #include <asm/smp.h> -/* - * Possible interrupt causes: - */ -#define INTERRUPT_CAUSE_SOFTWARE 1 -#define INTERRUPT_CAUSE_TIMER 5 -#define INTERRUPT_CAUSE_EXTERNAL 9 - -/* - * The high order bit of the trap cause register is always set for - * interrupts, which allows us to differentiate them from exceptions - * quickly. The INTERRUPT_CAUSE_* macros don't contain that bit, so we - * need to mask it off. - */ -#define INTERRUPT_CAUSE_FLAG (1UL << (__riscv_xlen - 1)) - int arch_show_interrupts(struct seq_file *p, int prec) { show_ipi_stats(p, prec); @@ -37,12 +22,12 @@ asmlinkage void __irq_entry do_IRQ(struct pt_regs *regs) struct pt_regs *old_regs = set_irq_regs(regs); irq_enter(); - switch (regs->scause & ~INTERRUPT_CAUSE_FLAG) { - case INTERRUPT_CAUSE_TIMER: + switch (regs->scause & ~SCAUSE_IRQ_FLAG) { + case IRQ_S_TIMER: riscv_timer_interrupt(); break; #ifdef CONFIG_SMP - case INTERRUPT_CAUSE_SOFTWARE: + case IRQ_S_SOFT: /* * We only use software interrupts to pass IPIs, so if a non-SMP * system gets one, then we don't know what to do. @@ -50,7 +35,7 @@ asmlinkage void __irq_entry do_IRQ(struct pt_regs *regs) riscv_software_interrupt(); break; #endif - case INTERRUPT_CAUSE_EXTERNAL: + case IRQ_S_EXT: handle_arch_irq(regs); break; default: -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v3 2/3] RISC-V: Add interrupt related SCAUSE defines in asm/csr.h 2019-04-15 9:37 ` Anup Patel @ 2019-04-24 6:29 ` Christoph Hellwig -1 siblings, 0 replies; 20+ messages in thread From: Christoph Hellwig @ 2019-04-24 6:29 UTC (permalink / raw) To: Anup Patel Cc: Palmer Dabbelt, Albert Ou, linux-kernel, Christoph Hellwig, Atish Patra, Paul Walmsley, linux-riscv On Mon, Apr 15, 2019 at 09:37:23AM +0000, Anup Patel wrote: > This patch adds SCAUSE interrupt flag and SCAUSE interrupt related > defines to asm/csr.h. We also use these defines in kernel/irq.c and > express SIE/SIP flags in-terms of SCAUSE interrupt causes. I'm not a fan of this. For one this pollutes csr.h with bits not really needed by most users, and it makes adding the M-mode nommu port which has to use the M-mode causes much harder: http://git.infradead.org/users/hch/misc.git/commitdiff/1221f5c32345ebe7ea2c1cd6e8a01ad4b422aaba ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 2/3] RISC-V: Add interrupt related SCAUSE defines in asm/csr.h @ 2019-04-24 6:29 ` Christoph Hellwig 0 siblings, 0 replies; 20+ messages in thread From: Christoph Hellwig @ 2019-04-24 6:29 UTC (permalink / raw) To: Anup Patel Cc: Albert Ou, Palmer Dabbelt, linux-kernel, Christoph Hellwig, Atish Patra, Paul Walmsley, linux-riscv On Mon, Apr 15, 2019 at 09:37:23AM +0000, Anup Patel wrote: > This patch adds SCAUSE interrupt flag and SCAUSE interrupt related > defines to asm/csr.h. We also use these defines in kernel/irq.c and > express SIE/SIP flags in-terms of SCAUSE interrupt causes. I'm not a fan of this. For one this pollutes csr.h with bits not really needed by most users, and it makes adding the M-mode nommu port which has to use the M-mode causes much harder: http://git.infradead.org/users/hch/misc.git/commitdiff/1221f5c32345ebe7ea2c1cd6e8a01ad4b422aaba _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 2/3] RISC-V: Add interrupt related SCAUSE defines in asm/csr.h 2019-04-24 6:29 ` Christoph Hellwig @ 2019-04-24 6:45 ` Anup Patel -1 siblings, 0 replies; 20+ messages in thread From: Anup Patel @ 2019-04-24 6:45 UTC (permalink / raw) To: Christoph Hellwig Cc: Anup Patel, Palmer Dabbelt, Albert Ou, linux-kernel, Atish Patra, Paul Walmsley, linux-riscv On Wed, Apr 24, 2019 at 11:59 AM Christoph Hellwig <hch@infradead.org> wrote: > > On Mon, Apr 15, 2019 at 09:37:23AM +0000, Anup Patel wrote: > > This patch adds SCAUSE interrupt flag and SCAUSE interrupt related > > defines to asm/csr.h. We also use these defines in kernel/irq.c and > > express SIE/SIP flags in-terms of SCAUSE interrupt causes. > > I'm not a fan of this. For one this pollutes csr.h with bits not really > needed by most users, and it makes adding the M-mode nommu port which has > to use the M-mode causes much harder: It's not polluting asm/csr.h because when we get interrupt numer in lower bits of SCAUSE CSR. These defines certainly belong to asm/csr.h because they represent possible exception causes when we get interrupt. We need these defines for programming HIDELEG CSR in KVM kernel module so it will be used at multiple places. > > http://git.infradead.org/users/hch/misc.git/commitdiff/1221f5c32345ebe7ea2c1cd6e8a01ad4b422aaba You can certainly use these defines in your nommu commit by using "#ifdef CONFIG_M_MODE" in switch case of do_IRQ(). Regards, Anup ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 2/3] RISC-V: Add interrupt related SCAUSE defines in asm/csr.h @ 2019-04-24 6:45 ` Anup Patel 0 siblings, 0 replies; 20+ messages in thread From: Anup Patel @ 2019-04-24 6:45 UTC (permalink / raw) To: Christoph Hellwig Cc: Palmer Dabbelt, Anup Patel, linux-kernel, Atish Patra, Albert Ou, Paul Walmsley, linux-riscv On Wed, Apr 24, 2019 at 11:59 AM Christoph Hellwig <hch@infradead.org> wrote: > > On Mon, Apr 15, 2019 at 09:37:23AM +0000, Anup Patel wrote: > > This patch adds SCAUSE interrupt flag and SCAUSE interrupt related > > defines to asm/csr.h. We also use these defines in kernel/irq.c and > > express SIE/SIP flags in-terms of SCAUSE interrupt causes. > > I'm not a fan of this. For one this pollutes csr.h with bits not really > needed by most users, and it makes adding the M-mode nommu port which has > to use the M-mode causes much harder: It's not polluting asm/csr.h because when we get interrupt numer in lower bits of SCAUSE CSR. These defines certainly belong to asm/csr.h because they represent possible exception causes when we get interrupt. We need these defines for programming HIDELEG CSR in KVM kernel module so it will be used at multiple places. > > http://git.infradead.org/users/hch/misc.git/commitdiff/1221f5c32345ebe7ea2c1cd6e8a01ad4b422aaba You can certainly use these defines in your nommu commit by using "#ifdef CONFIG_M_MODE" in switch case of do_IRQ(). Regards, Anup _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 2/3] RISC-V: Add interrupt related SCAUSE defines in asm/csr.h 2019-04-24 6:45 ` Anup Patel @ 2019-04-24 15:01 ` Christoph Hellwig -1 siblings, 0 replies; 20+ messages in thread From: Christoph Hellwig @ 2019-04-24 15:01 UTC (permalink / raw) To: Anup Patel Cc: Christoph Hellwig, Palmer Dabbelt, Anup Patel, linux-kernel, Atish Patra, Albert Ou, Paul Walmsley, linux-riscv On Wed, Apr 24, 2019 at 12:15:45PM +0530, Anup Patel wrote: > We need these defines for programming HIDELEG CSR in KVM kernel module > so it will be used at multiple places. > > > > > http://git.infradead.org/users/hch/misc.git/commitdiff/1221f5c32345ebe7ea2c1cd6e8a01ad4b422aaba > > You can certainly use these defines in your nommu commit by using > "#ifdef CONFIG_M_MODE" in switch case of do_IRQ(). Or just keep them in the current format even when you move them, as that allows everything to work with a single ifdef at their point of declaration.. ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 2/3] RISC-V: Add interrupt related SCAUSE defines in asm/csr.h @ 2019-04-24 15:01 ` Christoph Hellwig 0 siblings, 0 replies; 20+ messages in thread From: Christoph Hellwig @ 2019-04-24 15:01 UTC (permalink / raw) To: Anup Patel Cc: Palmer Dabbelt, Anup Patel, linux-kernel, Christoph Hellwig, Atish Patra, Albert Ou, Paul Walmsley, linux-riscv On Wed, Apr 24, 2019 at 12:15:45PM +0530, Anup Patel wrote: > We need these defines for programming HIDELEG CSR in KVM kernel module > so it will be used at multiple places. > > > > > http://git.infradead.org/users/hch/misc.git/commitdiff/1221f5c32345ebe7ea2c1cd6e8a01ad4b422aaba > > You can certainly use these defines in your nommu commit by using > "#ifdef CONFIG_M_MODE" in switch case of do_IRQ(). Or just keep them in the current format even when you move them, as that allows everything to work with a single ifdef at their point of declaration.. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 2/3] RISC-V: Add interrupt related SCAUSE defines in asm/csr.h 2019-04-24 15:01 ` Christoph Hellwig @ 2019-04-25 5:04 ` Anup Patel -1 siblings, 0 replies; 20+ messages in thread From: Anup Patel @ 2019-04-25 5:04 UTC (permalink / raw) To: Christoph Hellwig Cc: Palmer Dabbelt, Anup Patel, linux-kernel, Atish Patra, Albert Ou, Paul Walmsley, linux-riscv On Wed, Apr 24, 2019 at 8:31 PM Christoph Hellwig <hch@infradead.org> wrote: > > On Wed, Apr 24, 2019 at 12:15:45PM +0530, Anup Patel wrote: > > We need these defines for programming HIDELEG CSR in KVM kernel module > > so it will be used at multiple places. > > > > > > > > http://git.infradead.org/users/hch/misc.git/commitdiff/1221f5c32345ebe7ea2c1cd6e8a01ad4b422aaba > > > > You can certainly use these defines in your nommu commit by using > > "#ifdef CONFIG_M_MODE" in switch case of do_IRQ(). > > Or just keep them in the current format even when you move them, as > that allows everything to work with a single ifdef at their point > of declaration.. Sure, will do. I will send v4 soon. Regards, Anup ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 2/3] RISC-V: Add interrupt related SCAUSE defines in asm/csr.h @ 2019-04-25 5:04 ` Anup Patel 0 siblings, 0 replies; 20+ messages in thread From: Anup Patel @ 2019-04-25 5:04 UTC (permalink / raw) To: Christoph Hellwig Cc: Palmer Dabbelt, Anup Patel, linux-kernel, Atish Patra, Albert Ou, Paul Walmsley, linux-riscv On Wed, Apr 24, 2019 at 8:31 PM Christoph Hellwig <hch@infradead.org> wrote: > > On Wed, Apr 24, 2019 at 12:15:45PM +0530, Anup Patel wrote: > > We need these defines for programming HIDELEG CSR in KVM kernel module > > so it will be used at multiple places. > > > > > > > > http://git.infradead.org/users/hch/misc.git/commitdiff/1221f5c32345ebe7ea2c1cd6e8a01ad4b422aaba > > > > You can certainly use these defines in your nommu commit by using > > "#ifdef CONFIG_M_MODE" in switch case of do_IRQ(). > > Or just keep them in the current format even when you move them, as > that allows everything to work with a single ifdef at their point > of declaration.. Sure, will do. I will send v4 soon. Regards, Anup _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 3/3] RISC-V: Access CSRs using CSR numbers 2019-04-15 9:37 ` Anup Patel @ 2019-04-15 9:37 ` Anup Patel -1 siblings, 0 replies; 20+ messages in thread From: Anup Patel @ 2019-04-15 9:37 UTC (permalink / raw) To: Palmer Dabbelt, Albert Ou Cc: Atish Patra, Paul Walmsley, Christoph Hellwig, linux-riscv, linux-kernel, Anup Patel We should prefer accessing CSRs using their CSR numbers because: 1. It compiles fine with older toolchains. 2. We can use latest CSR names in #define macro names of CSR numbers as-per RISC-V spec. 3. We can access newly added CSRs even if toolchain does not recognize newly addes CSRs by name. Signed-off-by: Anup Patel <anup.patel@wdc.com> --- arch/riscv/include/asm/csr.h | 32 ++++++++++++++++++++++------ arch/riscv/include/asm/irqflags.h | 10 ++++----- arch/riscv/include/asm/mmu_context.h | 7 +----- arch/riscv/kernel/entry.S | 22 +++++++++---------- arch/riscv/kernel/head.S | 12 +++++------ arch/riscv/kernel/perf_event.c | 4 ++-- arch/riscv/kernel/smp.c | 2 +- arch/riscv/kernel/traps.c | 6 +++--- arch/riscv/mm/fault.c | 6 +----- 9 files changed, 55 insertions(+), 46 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index ab40a936cb2d..bd0c9ff0ea78 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -14,6 +14,7 @@ #ifndef _ASM_RISCV_CSR_H #define _ASM_RISCV_CSR_H +#include <asm/asm.h> #include <linux/const.h> /* Status register flags */ @@ -83,12 +84,29 @@ #define SIE_STIE (_AC(0x1, UL) << IRQ_S_TIMER) #define SIE_SEIE (_AC(0x1, UL) << IRQ_S_EXT) +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 +#define CSR_SATP 0x180 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 + #ifndef __ASSEMBLY__ #define csr_swap(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrrw %0, " #csr ", %1" \ + __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\ : "=r" (__v) : "rK" (__v) \ : "memory"); \ __v; \ @@ -97,7 +115,7 @@ #define csr_read(csr) \ ({ \ register unsigned long __v; \ - __asm__ __volatile__ ("csrr %0, " #csr \ + __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \ : "=r" (__v) : \ : "memory"); \ __v; \ @@ -106,7 +124,7 @@ #define csr_write(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrw " #csr ", %0" \ + __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \ : : "rK" (__v) \ : "memory"); \ }) @@ -114,7 +132,7 @@ #define csr_read_set(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrrs %0, " #csr ", %1" \ + __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\ : "=r" (__v) : "rK" (__v) \ : "memory"); \ __v; \ @@ -123,7 +141,7 @@ #define csr_set(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrs " #csr ", %0" \ + __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \ : : "rK" (__v) \ : "memory"); \ }) @@ -131,7 +149,7 @@ #define csr_read_clear(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrrc %0, " #csr ", %1" \ + __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\ : "=r" (__v) : "rK" (__v) \ : "memory"); \ __v; \ @@ -140,7 +158,7 @@ #define csr_clear(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrc " #csr ", %0" \ + __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \ : : "rK" (__v) \ : "memory"); \ }) diff --git a/arch/riscv/include/asm/irqflags.h b/arch/riscv/include/asm/irqflags.h index 07a3c6d5706f..1a69b3bcd371 100644 --- a/arch/riscv/include/asm/irqflags.h +++ b/arch/riscv/include/asm/irqflags.h @@ -21,25 +21,25 @@ /* read interrupt enabled status */ static inline unsigned long arch_local_save_flags(void) { - return csr_read(sstatus); + return csr_read(CSR_SSTATUS); } /* unconditionally enable interrupts */ static inline void arch_local_irq_enable(void) { - csr_set(sstatus, SR_SIE); + csr_set(CSR_SSTATUS, SR_SIE); } /* unconditionally disable interrupts */ static inline void arch_local_irq_disable(void) { - csr_clear(sstatus, SR_SIE); + csr_clear(CSR_SSTATUS, SR_SIE); } /* get status and disable interrupts */ static inline unsigned long arch_local_irq_save(void) { - return csr_read_clear(sstatus, SR_SIE); + return csr_read_clear(CSR_SSTATUS, SR_SIE); } /* test flags */ @@ -57,7 +57,7 @@ static inline int arch_irqs_disabled(void) /* set interrupt enabled status */ static inline void arch_local_irq_restore(unsigned long flags) { - csr_set(sstatus, flags & SR_SIE); + csr_set(CSR_SSTATUS, flags & SR_SIE); } #endif /* _ASM_RISCV_IRQFLAGS_H */ diff --git a/arch/riscv/include/asm/mmu_context.h b/arch/riscv/include/asm/mmu_context.h index 336d60ec5698..98c76c821367 100644 --- a/arch/riscv/include/asm/mmu_context.h +++ b/arch/riscv/include/asm/mmu_context.h @@ -83,12 +83,7 @@ static inline void switch_mm(struct mm_struct *prev, cpumask_clear_cpu(cpu, mm_cpumask(prev)); cpumask_set_cpu(cpu, mm_cpumask(next)); - /* - * Use the old spbtr name instead of using the current satp - * name to support binutils 2.29 which doesn't know about the - * privileged ISA 1.10 yet. - */ - csr_write(sptbr, virt_to_pfn(next->pgd) | SATP_MODE); + csr_write(CSR_SATP, virt_to_pfn(next->pgd) | SATP_MODE); local_flush_tlb_all(); flush_icache_deferred(next); diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index fd9b57c8b4ce..1c1ecc238cfa 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -37,11 +37,11 @@ * the kernel thread pointer. If we came from the kernel, sscratch * will contain 0, and we should continue on the current TP. */ - csrrw tp, sscratch, tp + csrrw tp, CSR_SSCRATCH, tp bnez tp, _save_context _restore_kernel_tpsp: - csrr tp, sscratch + csrr tp, CSR_SSCRATCH REG_S sp, TASK_TI_KERNEL_SP(tp) _save_context: REG_S sp, TASK_TI_USER_SP(tp) @@ -87,11 +87,11 @@ _save_context: li t0, SR_SUM | SR_FS REG_L s0, TASK_TI_USER_SP(tp) - csrrc s1, sstatus, t0 - csrr s2, sepc - csrr s3, sbadaddr - csrr s4, scause - csrr s5, sscratch + csrrc s1, CSR_SSTATUS, t0 + csrr s2, CSR_SEPC + csrr s3, CSR_STVAL + csrr s4, CSR_SCAUSE + csrr s5, CSR_SSCRATCH REG_S s0, PT_SP(sp) REG_S s1, PT_SSTATUS(sp) REG_S s2, PT_SEPC(sp) @@ -107,8 +107,8 @@ _save_context: .macro RESTORE_ALL REG_L a0, PT_SSTATUS(sp) REG_L a2, PT_SEPC(sp) - csrw sstatus, a0 - csrw sepc, a2 + csrw CSR_SSTATUS, a0 + csrw CSR_SEPC, a2 REG_L x1, PT_RA(sp) REG_L x3, PT_GP(sp) @@ -155,7 +155,7 @@ ENTRY(handle_exception) * Set sscratch register to 0, so that if a recursive exception * occurs, the exception vector knows it came from the kernel */ - csrw sscratch, x0 + csrw CSR_SSCRATCH, x0 /* Load the global pointer */ .option push @@ -248,7 +248,7 @@ resume_userspace: * Save TP into sscratch, so we can find the kernel data structures * again. */ - csrw sscratch, tp + csrw CSR_SSCRATCH, tp restore_all: RESTORE_ALL diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index fe884cd69abd..041492636b45 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -23,7 +23,7 @@ __INIT ENTRY(_start) /* Mask all interrupts */ - csrw sie, zero + csrw CSR_SIE, zero /* Load the global pointer */ .option push @@ -89,7 +89,7 @@ relocate: /* Point stvec to virtual address of intruction after satp write */ la a0, 1f add a0, a0, a1 - csrw stvec, a0 + csrw CSR_STVEC, a0 /* Compute satp for kernel page tables, but don't load it yet */ la a2, swapper_pg_dir @@ -105,12 +105,12 @@ relocate: srl a0, a0, PAGE_SHIFT or a0, a0, a1 sfence.vma - csrw sptbr, a0 + csrw CSR_SATP, a0 .align 2 1: /* Set trap vector to spin forever to help debug */ la a0, .Lsecondary_park - csrw stvec, a0 + csrw CSR_STVEC, a0 /* Reload the global pointer */ .option push @@ -119,7 +119,7 @@ relocate: .option pop /* Switch to kernel page tables */ - csrw sptbr, a2 + csrw CSR_SATP, a2 ret @@ -130,7 +130,7 @@ relocate: /* Set trap vector to spin forever to help debug */ la a3, .Lsecondary_park - csrw stvec, a3 + csrw CSR_STVEC, a3 slli a3, a0, LGREG la a1, __cpu_up_stack_pointer diff --git a/arch/riscv/kernel/perf_event.c b/arch/riscv/kernel/perf_event.c index 667ee70defea..91626d9ae5f2 100644 --- a/arch/riscv/kernel/perf_event.c +++ b/arch/riscv/kernel/perf_event.c @@ -185,10 +185,10 @@ static inline u64 read_counter(int idx) switch (idx) { case RISCV_PMU_CYCLE: - val = csr_read(cycle); + val = csr_read(CSR_CYCLE); break; case RISCV_PMU_INSTRET: - val = csr_read(instret); + val = csr_read(CSR_INSTRET); break; default: WARN_ON_ONCE(idx < 0 || idx > RISCV_MAX_COUNTERS); diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index 0c41d07ec281..f244c63d29e4 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -89,7 +89,7 @@ void riscv_software_interrupt(void) unsigned long *stats = ipi_data[smp_processor_id()].stats; /* Clear pending IPI */ - csr_clear(sip, SIE_SSIE); + csr_clear(CSR_SIP, SIE_SSIE); while (true) { unsigned long ops; diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 24a9333dda2c..1b407a9db3fc 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -159,9 +159,9 @@ void __init trap_init(void) * Set sup0 scratch register to 0, indicating to exception vector * that we are presently executing in the kernel */ - csr_write(sscratch, 0); + csr_write(CSR_SSCRATCH, 0); /* Set the exception vector address */ - csr_write(stvec, &handle_exception); + csr_write(CSR_STVEC, &handle_exception); /* Enable all interrupts */ - csr_write(sie, -1); + csr_write(CSR_SIE, -1); } diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c index 88401d5125bc..26293bc053a8 100644 --- a/arch/riscv/mm/fault.c +++ b/arch/riscv/mm/fault.c @@ -239,13 +239,9 @@ asmlinkage void do_page_fault(struct pt_regs *regs) * Do _not_ use "tsk->active_mm->pgd" here. * We might be inside an interrupt in the middle * of a task switch. - * - * Note: Use the old spbtr name instead of using the current - * satp name to support binutils 2.29 which doesn't know about - * the privileged ISA 1.10 yet. */ index = pgd_index(addr); - pgd = (pgd_t *)pfn_to_virt(csr_read(sptbr)) + index; + pgd = (pgd_t *)pfn_to_virt(csr_read(CSR_SATP)) + index; pgd_k = init_mm.pgd + index; if (!pgd_present(*pgd_k)) -- 2.17.1 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v3 3/3] RISC-V: Access CSRs using CSR numbers @ 2019-04-15 9:37 ` Anup Patel 0 siblings, 0 replies; 20+ messages in thread From: Anup Patel @ 2019-04-15 9:37 UTC (permalink / raw) To: Palmer Dabbelt, Albert Ou Cc: Anup Patel, linux-kernel, Christoph Hellwig, Atish Patra, Paul Walmsley, linux-riscv We should prefer accessing CSRs using their CSR numbers because: 1. It compiles fine with older toolchains. 2. We can use latest CSR names in #define macro names of CSR numbers as-per RISC-V spec. 3. We can access newly added CSRs even if toolchain does not recognize newly addes CSRs by name. Signed-off-by: Anup Patel <anup.patel@wdc.com> --- arch/riscv/include/asm/csr.h | 32 ++++++++++++++++++++++------ arch/riscv/include/asm/irqflags.h | 10 ++++----- arch/riscv/include/asm/mmu_context.h | 7 +----- arch/riscv/kernel/entry.S | 22 +++++++++---------- arch/riscv/kernel/head.S | 12 +++++------ arch/riscv/kernel/perf_event.c | 4 ++-- arch/riscv/kernel/smp.c | 2 +- arch/riscv/kernel/traps.c | 6 +++--- arch/riscv/mm/fault.c | 6 +----- 9 files changed, 55 insertions(+), 46 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index ab40a936cb2d..bd0c9ff0ea78 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -14,6 +14,7 @@ #ifndef _ASM_RISCV_CSR_H #define _ASM_RISCV_CSR_H +#include <asm/asm.h> #include <linux/const.h> /* Status register flags */ @@ -83,12 +84,29 @@ #define SIE_STIE (_AC(0x1, UL) << IRQ_S_TIMER) #define SIE_SEIE (_AC(0x1, UL) << IRQ_S_EXT) +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 +#define CSR_SATP 0x180 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 + #ifndef __ASSEMBLY__ #define csr_swap(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrrw %0, " #csr ", %1" \ + __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\ : "=r" (__v) : "rK" (__v) \ : "memory"); \ __v; \ @@ -97,7 +115,7 @@ #define csr_read(csr) \ ({ \ register unsigned long __v; \ - __asm__ __volatile__ ("csrr %0, " #csr \ + __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \ : "=r" (__v) : \ : "memory"); \ __v; \ @@ -106,7 +124,7 @@ #define csr_write(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrw " #csr ", %0" \ + __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \ : : "rK" (__v) \ : "memory"); \ }) @@ -114,7 +132,7 @@ #define csr_read_set(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrrs %0, " #csr ", %1" \ + __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\ : "=r" (__v) : "rK" (__v) \ : "memory"); \ __v; \ @@ -123,7 +141,7 @@ #define csr_set(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrs " #csr ", %0" \ + __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \ : : "rK" (__v) \ : "memory"); \ }) @@ -131,7 +149,7 @@ #define csr_read_clear(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrrc %0, " #csr ", %1" \ + __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\ : "=r" (__v) : "rK" (__v) \ : "memory"); \ __v; \ @@ -140,7 +158,7 @@ #define csr_clear(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrc " #csr ", %0" \ + __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \ : : "rK" (__v) \ : "memory"); \ }) diff --git a/arch/riscv/include/asm/irqflags.h b/arch/riscv/include/asm/irqflags.h index 07a3c6d5706f..1a69b3bcd371 100644 --- a/arch/riscv/include/asm/irqflags.h +++ b/arch/riscv/include/asm/irqflags.h @@ -21,25 +21,25 @@ /* read interrupt enabled status */ static inline unsigned long arch_local_save_flags(void) { - return csr_read(sstatus); + return csr_read(CSR_SSTATUS); } /* unconditionally enable interrupts */ static inline void arch_local_irq_enable(void) { - csr_set(sstatus, SR_SIE); + csr_set(CSR_SSTATUS, SR_SIE); } /* unconditionally disable interrupts */ static inline void arch_local_irq_disable(void) { - csr_clear(sstatus, SR_SIE); + csr_clear(CSR_SSTATUS, SR_SIE); } /* get status and disable interrupts */ static inline unsigned long arch_local_irq_save(void) { - return csr_read_clear(sstatus, SR_SIE); + return csr_read_clear(CSR_SSTATUS, SR_SIE); } /* test flags */ @@ -57,7 +57,7 @@ static inline int arch_irqs_disabled(void) /* set interrupt enabled status */ static inline void arch_local_irq_restore(unsigned long flags) { - csr_set(sstatus, flags & SR_SIE); + csr_set(CSR_SSTATUS, flags & SR_SIE); } #endif /* _ASM_RISCV_IRQFLAGS_H */ diff --git a/arch/riscv/include/asm/mmu_context.h b/arch/riscv/include/asm/mmu_context.h index 336d60ec5698..98c76c821367 100644 --- a/arch/riscv/include/asm/mmu_context.h +++ b/arch/riscv/include/asm/mmu_context.h @@ -83,12 +83,7 @@ static inline void switch_mm(struct mm_struct *prev, cpumask_clear_cpu(cpu, mm_cpumask(prev)); cpumask_set_cpu(cpu, mm_cpumask(next)); - /* - * Use the old spbtr name instead of using the current satp - * name to support binutils 2.29 which doesn't know about the - * privileged ISA 1.10 yet. - */ - csr_write(sptbr, virt_to_pfn(next->pgd) | SATP_MODE); + csr_write(CSR_SATP, virt_to_pfn(next->pgd) | SATP_MODE); local_flush_tlb_all(); flush_icache_deferred(next); diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index fd9b57c8b4ce..1c1ecc238cfa 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -37,11 +37,11 @@ * the kernel thread pointer. If we came from the kernel, sscratch * will contain 0, and we should continue on the current TP. */ - csrrw tp, sscratch, tp + csrrw tp, CSR_SSCRATCH, tp bnez tp, _save_context _restore_kernel_tpsp: - csrr tp, sscratch + csrr tp, CSR_SSCRATCH REG_S sp, TASK_TI_KERNEL_SP(tp) _save_context: REG_S sp, TASK_TI_USER_SP(tp) @@ -87,11 +87,11 @@ _save_context: li t0, SR_SUM | SR_FS REG_L s0, TASK_TI_USER_SP(tp) - csrrc s1, sstatus, t0 - csrr s2, sepc - csrr s3, sbadaddr - csrr s4, scause - csrr s5, sscratch + csrrc s1, CSR_SSTATUS, t0 + csrr s2, CSR_SEPC + csrr s3, CSR_STVAL + csrr s4, CSR_SCAUSE + csrr s5, CSR_SSCRATCH REG_S s0, PT_SP(sp) REG_S s1, PT_SSTATUS(sp) REG_S s2, PT_SEPC(sp) @@ -107,8 +107,8 @@ _save_context: .macro RESTORE_ALL REG_L a0, PT_SSTATUS(sp) REG_L a2, PT_SEPC(sp) - csrw sstatus, a0 - csrw sepc, a2 + csrw CSR_SSTATUS, a0 + csrw CSR_SEPC, a2 REG_L x1, PT_RA(sp) REG_L x3, PT_GP(sp) @@ -155,7 +155,7 @@ ENTRY(handle_exception) * Set sscratch register to 0, so that if a recursive exception * occurs, the exception vector knows it came from the kernel */ - csrw sscratch, x0 + csrw CSR_SSCRATCH, x0 /* Load the global pointer */ .option push @@ -248,7 +248,7 @@ resume_userspace: * Save TP into sscratch, so we can find the kernel data structures * again. */ - csrw sscratch, tp + csrw CSR_SSCRATCH, tp restore_all: RESTORE_ALL diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index fe884cd69abd..041492636b45 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -23,7 +23,7 @@ __INIT ENTRY(_start) /* Mask all interrupts */ - csrw sie, zero + csrw CSR_SIE, zero /* Load the global pointer */ .option push @@ -89,7 +89,7 @@ relocate: /* Point stvec to virtual address of intruction after satp write */ la a0, 1f add a0, a0, a1 - csrw stvec, a0 + csrw CSR_STVEC, a0 /* Compute satp for kernel page tables, but don't load it yet */ la a2, swapper_pg_dir @@ -105,12 +105,12 @@ relocate: srl a0, a0, PAGE_SHIFT or a0, a0, a1 sfence.vma - csrw sptbr, a0 + csrw CSR_SATP, a0 .align 2 1: /* Set trap vector to spin forever to help debug */ la a0, .Lsecondary_park - csrw stvec, a0 + csrw CSR_STVEC, a0 /* Reload the global pointer */ .option push @@ -119,7 +119,7 @@ relocate: .option pop /* Switch to kernel page tables */ - csrw sptbr, a2 + csrw CSR_SATP, a2 ret @@ -130,7 +130,7 @@ relocate: /* Set trap vector to spin forever to help debug */ la a3, .Lsecondary_park - csrw stvec, a3 + csrw CSR_STVEC, a3 slli a3, a0, LGREG la a1, __cpu_up_stack_pointer diff --git a/arch/riscv/kernel/perf_event.c b/arch/riscv/kernel/perf_event.c index 667ee70defea..91626d9ae5f2 100644 --- a/arch/riscv/kernel/perf_event.c +++ b/arch/riscv/kernel/perf_event.c @@ -185,10 +185,10 @@ static inline u64 read_counter(int idx) switch (idx) { case RISCV_PMU_CYCLE: - val = csr_read(cycle); + val = csr_read(CSR_CYCLE); break; case RISCV_PMU_INSTRET: - val = csr_read(instret); + val = csr_read(CSR_INSTRET); break; default: WARN_ON_ONCE(idx < 0 || idx > RISCV_MAX_COUNTERS); diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index 0c41d07ec281..f244c63d29e4 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -89,7 +89,7 @@ void riscv_software_interrupt(void) unsigned long *stats = ipi_data[smp_processor_id()].stats; /* Clear pending IPI */ - csr_clear(sip, SIE_SSIE); + csr_clear(CSR_SIP, SIE_SSIE); while (true) { unsigned long ops; diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 24a9333dda2c..1b407a9db3fc 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -159,9 +159,9 @@ void __init trap_init(void) * Set sup0 scratch register to 0, indicating to exception vector * that we are presently executing in the kernel */ - csr_write(sscratch, 0); + csr_write(CSR_SSCRATCH, 0); /* Set the exception vector address */ - csr_write(stvec, &handle_exception); + csr_write(CSR_STVEC, &handle_exception); /* Enable all interrupts */ - csr_write(sie, -1); + csr_write(CSR_SIE, -1); } diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c index 88401d5125bc..26293bc053a8 100644 --- a/arch/riscv/mm/fault.c +++ b/arch/riscv/mm/fault.c @@ -239,13 +239,9 @@ asmlinkage void do_page_fault(struct pt_regs *regs) * Do _not_ use "tsk->active_mm->pgd" here. * We might be inside an interrupt in the middle * of a task switch. - * - * Note: Use the old spbtr name instead of using the current - * satp name to support binutils 2.29 which doesn't know about - * the privileged ISA 1.10 yet. */ index = pgd_index(addr); - pgd = (pgd_t *)pfn_to_virt(csr_read(sptbr)) + index; + pgd = (pgd_t *)pfn_to_virt(csr_read(CSR_SATP)) + index; pgd_k = init_mm.pgd + index; if (!pgd_present(*pgd_k)) -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v3 3/3] RISC-V: Access CSRs using CSR numbers 2019-04-15 9:37 ` Anup Patel @ 2019-04-24 6:30 ` Christoph Hellwig -1 siblings, 0 replies; 20+ messages in thread From: Christoph Hellwig @ 2019-04-24 6:30 UTC (permalink / raw) To: Anup Patel Cc: Palmer Dabbelt, Albert Ou, linux-kernel, Christoph Hellwig, Atish Patra, Paul Walmsley, linux-riscv On Mon, Apr 15, 2019 at 09:37:27AM +0000, Anup Patel wrote: > We should prefer accessing CSRs using their CSR numbers because: > 1. It compiles fine with older toolchains. > 2. We can use latest CSR names in #define macro names of CSR numbers > as-per RISC-V spec. > 3. We can access newly added CSRs even if toolchain does not recognize > newly addes CSRs by name. > > Signed-off-by: Anup Patel <anup.patel@wdc.com> Looks fine: Reviewed-by: Christoph Hellwig <hch@lst.de> ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 3/3] RISC-V: Access CSRs using CSR numbers @ 2019-04-24 6:30 ` Christoph Hellwig 0 siblings, 0 replies; 20+ messages in thread From: Christoph Hellwig @ 2019-04-24 6:30 UTC (permalink / raw) To: Anup Patel Cc: Albert Ou, Palmer Dabbelt, linux-kernel, Christoph Hellwig, Atish Patra, Paul Walmsley, linux-riscv On Mon, Apr 15, 2019 at 09:37:27AM +0000, Anup Patel wrote: > We should prefer accessing CSRs using their CSR numbers because: > 1. It compiles fine with older toolchains. > 2. We can use latest CSR names in #define macro names of CSR numbers > as-per RISC-V spec. > 3. We can access newly added CSRs even if toolchain does not recognize > newly addes CSRs by name. > > Signed-off-by: Anup Patel <anup.patel@wdc.com> Looks fine: Reviewed-by: Christoph Hellwig <hch@lst.de> _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2019-04-25 5:04 UTC | newest] Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-04-15 9:37 [PATCH v3 0/3] Allow accessing CSR using CSR number Anup Patel 2019-04-15 9:37 ` Anup Patel 2019-04-15 9:37 ` [PATCH v3 1/3] RISC-V: Use tabs to align macro values in asm/csr.h Anup Patel 2019-04-15 9:37 ` Anup Patel 2019-04-24 6:27 ` Christoph Hellwig 2019-04-24 6:27 ` Christoph Hellwig 2019-04-15 9:37 ` [PATCH v3 2/3] RISC-V: Add interrupt related SCAUSE defines " Anup Patel 2019-04-15 9:37 ` Anup Patel 2019-04-24 6:29 ` Christoph Hellwig 2019-04-24 6:29 ` Christoph Hellwig 2019-04-24 6:45 ` Anup Patel 2019-04-24 6:45 ` Anup Patel 2019-04-24 15:01 ` Christoph Hellwig 2019-04-24 15:01 ` Christoph Hellwig 2019-04-25 5:04 ` Anup Patel 2019-04-25 5:04 ` Anup Patel 2019-04-15 9:37 ` [PATCH v3 3/3] RISC-V: Access CSRs using CSR numbers Anup Patel 2019-04-15 9:37 ` Anup Patel 2019-04-24 6:30 ` Christoph Hellwig 2019-04-24 6:30 ` Christoph Hellwig
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