* [PATCH] drm/i915/icl: Fix MG_DP_MODE() register programming @ 2019-04-19 7:10 Imre Deak 2019-04-19 7:27 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork ` (4 more replies) 0 siblings, 5 replies; 10+ messages in thread From: Imre Deak @ 2019-04-19 7:10 UTC (permalink / raw) To: intel-gfx; +Cc: Lucas De Marchi Fix the order of lane, port parameters passed to the register macro. Note that this was already partly fixed by commit 37fc7845df7b6 ("drm/i915: Call MG_DP_MODE() macro with the right parameters order") Fixes: 58106b7d816e1 ("drm/i915: Make MG PHY macros semantically consistent") Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Aditya Swarup <aditya.swarup@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/intel_ddi.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 24f9106efcc6..f181c26f62fd 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2905,21 +2905,20 @@ static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port) struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); enum port port = dig_port->base.port; enum tc_port tc_port = intel_port_to_tc(dev_priv, port); - i915_reg_t mg_regs[2] = { MG_DP_MODE(0, port), MG_DP_MODE(1, port) }; u32 val; - int i; + int ln; if (tc_port == PORT_TC_NONE) return; - for (i = 0; i < ARRAY_SIZE(mg_regs); i++) { - val = I915_READ(mg_regs[i]); + for (ln = 0; ln < 2; ln++) { + val = I915_READ(MG_DP_MODE(ln, port)); val |= MG_DP_MODE_CFG_TR2PWR_GATING | MG_DP_MODE_CFG_TRPWR_GATING | MG_DP_MODE_CFG_CLNPWR_GATING | MG_DP_MODE_CFG_DIGPWR_GATING | MG_DP_MODE_CFG_GAONPWR_GATING; - I915_WRITE(mg_regs[i], val); + I915_WRITE(MG_DP_MODE(ln, port), val); } val = I915_READ(MG_MISC_SUS0(tc_port)); @@ -2938,21 +2937,20 @@ static void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port) struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); enum port port = dig_port->base.port; enum tc_port tc_port = intel_port_to_tc(dev_priv, port); - i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) }; u32 val; - int i; + int ln; if (tc_port == PORT_TC_NONE) return; - for (i = 0; i < ARRAY_SIZE(mg_regs); i++) { - val = I915_READ(mg_regs[i]); + for (ln = 0; ln < 2; ln++) { + val = I915_READ(MG_DP_MODE(ln, port)); val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING | MG_DP_MODE_CFG_TRPWR_GATING | MG_DP_MODE_CFG_CLNPWR_GATING | MG_DP_MODE_CFG_DIGPWR_GATING | MG_DP_MODE_CFG_GAONPWR_GATING); - I915_WRITE(mg_regs[i], val); + I915_WRITE(MG_DP_MODE(ln, port), val); } val = I915_READ(MG_MISC_SUS0(tc_port)); -- 2.13.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 10+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: Fix MG_DP_MODE() register programming 2019-04-19 7:10 [PATCH] drm/i915/icl: Fix MG_DP_MODE() register programming Imre Deak @ 2019-04-19 7:27 ` Patchwork 2019-04-19 7:46 ` ✓ Fi.CI.BAT: success " Patchwork ` (3 subsequent siblings) 4 siblings, 0 replies; 10+ messages in thread From: Patchwork @ 2019-04-19 7:27 UTC (permalink / raw) To: Imre Deak; +Cc: intel-gfx == Series Details == Series: drm/i915/icl: Fix MG_DP_MODE() register programming URL : https://patchwork.freedesktop.org/series/59744/ State : warning == Summary == $ dim checkpatch origin/drm-tip d26cc79d0b12 drm/i915/icl: Fix MG_DP_MODE() register programming -:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #12: 37fc7845df7b6 ("drm/i915: Call MG_DP_MODE() macro with the right parameters order") -:12: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 37fc7845df7b ("drm/i915: Call MG_DP_MODE() macro with the right parameters order")' #12: 37fc7845df7b6 ("drm/i915: Call MG_DP_MODE() macro with the right parameters order") total: 1 errors, 1 warnings, 0 checks, 50 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/icl: Fix MG_DP_MODE() register programming 2019-04-19 7:10 [PATCH] drm/i915/icl: Fix MG_DP_MODE() register programming Imre Deak 2019-04-19 7:27 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork @ 2019-04-19 7:46 ` Patchwork 2019-04-19 8:55 ` ✓ Fi.CI.IGT: " Patchwork ` (2 subsequent siblings) 4 siblings, 0 replies; 10+ messages in thread From: Patchwork @ 2019-04-19 7:46 UTC (permalink / raw) To: Imre Deak; +Cc: intel-gfx == Series Details == Series: drm/i915/icl: Fix MG_DP_MODE() register programming URL : https://patchwork.freedesktop.org/series/59744/ State : success == Summary == CI Bug Log - changes from CI_DRM_5954 -> Patchwork_12840 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/59744/revisions/1/mbox/ Known issues ------------ Here are the changes found in Patchwork_12840 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@amdgpu/amd_cs_nop@fork-gfx0: - fi-icl-u2: NOTRUN -> SKIP [fdo#109315] +17 * igt@gem_exec_basic@readonly-bsd1: - fi-icl-u2: NOTRUN -> SKIP [fdo#109276] +3 * igt@gem_exec_parse@basic-allowed: - fi-icl-u2: NOTRUN -> SKIP [fdo#109289] +1 * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718] * igt@i915_selftest@live_contexts: - fi-skl-gvtdvm: PASS -> DMESG-FAIL [fdo#110235 ] * igt@i915_selftest@live_execlists: - fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720] * igt@kms_chamelium@dp-edid-read: - fi-icl-u2: NOTRUN -> SKIP [fdo#109316] +2 * igt@kms_chamelium@vga-hpd-fast: - fi-icl-u2: NOTRUN -> SKIP [fdo#109309] +1 * igt@kms_force_connector_basic@force-edid: - fi-glk-dsi: NOTRUN -> SKIP [fdo#109271] +26 * igt@kms_force_connector_basic@force-load-detect: - fi-bxt-j4205: NOTRUN -> SKIP [fdo#109271] +47 * igt@kms_force_connector_basic@prune-stale-modes: - fi-icl-u2: NOTRUN -> SKIP [fdo#109285] +3 * igt@kms_frontbuffer_tracking@basic: - fi-glk-dsi: NOTRUN -> FAIL [fdo#103167] * igt@runner@aborted: - fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720] #### Possible fixes #### * igt@gem_exec_basic@readonly-bsd: - fi-icl-u2: INCOMPLETE [fdo#107713] -> PASS * igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size: - fi-glk-dsi: INCOMPLETE [fdo#103359] / [k.org#198133] -> PASS * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-byt-clapper: FAIL [fdo#103191] -> PASS +1 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#109316]: https://bugs.freedesktop.org/show_bug.cgi?id=109316 [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720 [fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (48 -> 43) ------------------------------ Additional (1): fi-bxt-j4205 Missing (6): fi-ilk-m540 fi-bsw-cyan fi-ctg-p8600 fi-kbl-x1275 fi-icl-y fi-bdw-samus Build changes ------------- * Linux: CI_DRM_5954 -> Patchwork_12840 CI_DRM_5954: a77e0dc060fcd1a2a09412067097685c5101589c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4957: a765aa108105804c19096554447ad0cb71f64fc3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12840: d26cc79d0b12c09f18764d40b5a496230ad7fc4d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == d26cc79d0b12 drm/i915/icl: Fix MG_DP_MODE() register programming == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12840/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/icl: Fix MG_DP_MODE() register programming 2019-04-19 7:10 [PATCH] drm/i915/icl: Fix MG_DP_MODE() register programming Imre Deak 2019-04-19 7:27 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork 2019-04-19 7:46 ` ✓ Fi.CI.BAT: success " Patchwork @ 2019-04-19 8:55 ` Patchwork 2019-04-23 8:13 ` Imre Deak 2019-04-19 16:02 ` [PATCH] " Souza, Jose 2019-04-22 16:15 ` Lucas De Marchi 4 siblings, 1 reply; 10+ messages in thread From: Patchwork @ 2019-04-19 8:55 UTC (permalink / raw) To: Imre Deak; +Cc: intel-gfx == Series Details == Series: drm/i915/icl: Fix MG_DP_MODE() register programming URL : https://patchwork.freedesktop.org/series/59744/ State : success == Summary == CI Bug Log - changes from CI_DRM_5954_full -> Patchwork_12840_full ==================================================== Summary ------- **SUCCESS** No regressions found. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_12840_full: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt@audio@hdmi-integrity-after-suspend}: - shard-glk: TIMEOUT -> FAIL Known issues ------------ Here are the changes found in Patchwork_12840_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_isolation@rcs0-s3: - shard-apl: PASS -> DMESG-WARN [fdo#108566] +3 * igt@i915_pm_rpm@gem-execbuf-stress: - shard-skl: PASS -> INCOMPLETE [fdo#107803] / [fdo#107807] * igt@i915_pm_rpm@system-suspend: - shard-kbl: PASS -> INCOMPLETE [fdo#103665] / [fdo#107807] * igt@kms_busy@basic-flip-e: - shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1 * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-f: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2 * igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic: - shard-glk: PASS -> FAIL [fdo#104873] * igt@kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: PASS -> SKIP [fdo#109349] * igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled: - shard-skl: NOTRUN -> FAIL [fdo#103184] * igt@kms_fbcon_fbt@fbc-suspend: - shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773] +1 * igt@kms_force_connector_basic@prune-stale-modes: - shard-apl: NOTRUN -> SKIP [fdo#109271] +19 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite: - shard-iclb: PASS -> FAIL [fdo#103167] +3 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render: - shard-snb: NOTRUN -> SKIP [fdo#109271] +117 * igt@kms_lease@atomic_implicit_crtc: - shard-snb: NOTRUN -> FAIL [fdo#110279] * igt@kms_lease@setcrtc_implicit_plane: - shard-snb: NOTRUN -> FAIL [fdo#110281] * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-e: - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +10 * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping: - shard-glk: PASS -> SKIP [fdo#109271] * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: - shard-apl: NOTRUN -> FAIL [fdo#108145] * igt@kms_plane_alpha_blend@pipe-b-alpha-basic: - shard-skl: NOTRUN -> FAIL [fdo#108145] +2 * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-iclb: PASS -> FAIL [fdo#103166] * igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format: - shard-glk: PASS -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: PASS -> SKIP [fdo#109441] +2 * igt@kms_vrr@flip-suspend: - shard-skl: NOTRUN -> SKIP [fdo#109271] +40 * igt@perf_pmu@rc6: - shard-kbl: PASS -> SKIP [fdo#109271] #### Possible fixes #### * igt@gem_softpin@noreloc-s3: - shard-apl: DMESG-WARN [fdo#108566] -> PASS +2 * igt@kms_cursor_crc@cursor-64x64-suspend: - shard-kbl: DMESG-WARN [fdo#108566] -> PASS * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: - shard-iclb: FAIL [fdo#103167] -> PASS +5 * igt@kms_plane@pixel-format-pipe-c-planes: - shard-glk: SKIP [fdo#109271] -> PASS * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: FAIL [fdo#108145] -> PASS * igt@kms_plane_scaling@pipe-c-scaler-with-rotation: - shard-glk: SKIP [fdo#109271] / [fdo#109278] -> PASS +1 * igt@kms_rotation_crc@multiplane-rotation-cropping-bottom: - shard-kbl: DMESG-FAIL [fdo#105763] -> PASS * igt@kms_sysfs_edid_timing: - shard-iclb: FAIL [fdo#100047] -> PASS {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047 [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184 [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665 [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108 [fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873 [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763 [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773 [fdo#107803]: https://bugs.freedesktop.org/show_bug.cgi?id=107803 [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110279]: https://bugs.freedesktop.org/show_bug.cgi?id=110279 [fdo#110281]: https://bugs.freedesktop.org/show_bug.cgi?id=110281 Participating hosts (10 -> 9) ------------------------------ Missing (1): shard-hsw Build changes ------------- * Linux: CI_DRM_5954 -> Patchwork_12840 CI_DRM_5954: a77e0dc060fcd1a2a09412067097685c5101589c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4957: a765aa108105804c19096554447ad0cb71f64fc3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12840: d26cc79d0b12c09f18764d40b5a496230ad7fc4d @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12840/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: ✓ Fi.CI.IGT: success for drm/i915/icl: Fix MG_DP_MODE() register programming 2019-04-19 8:55 ` ✓ Fi.CI.IGT: " Patchwork @ 2019-04-23 8:13 ` Imre Deak 0 siblings, 0 replies; 10+ messages in thread From: Imre Deak @ 2019-04-23 8:13 UTC (permalink / raw) To: intel-gfx, José Roberto de Souza, Lucas De Marchi On Fri, Apr 19, 2019 at 08:55:02AM +0000, Patchwork wrote: > == Series Details == > > Series: drm/i915/icl: Fix MG_DP_MODE() register programming > URL : https://patchwork.freedesktop.org/series/59744/ > State : success Thanks for the reviews, pushed to -dinq adding the not to the commit message about simplifying things. > > == Summary == > > CI Bug Log - changes from CI_DRM_5954_full -> Patchwork_12840_full > ==================================================== > > Summary > ------- > > **SUCCESS** > > No regressions found. > > > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in Patchwork_12840_full: > > ### IGT changes ### > > #### Suppressed #### > > The following results come from untrusted machines, tests, or statuses. > They do not affect the overall result. > > * {igt@audio@hdmi-integrity-after-suspend}: > - shard-glk: TIMEOUT -> FAIL > > > Known issues > ------------ > > Here are the changes found in Patchwork_12840_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt@gem_ctx_isolation@rcs0-s3: > - shard-apl: PASS -> DMESG-WARN [fdo#108566] +3 > > * igt@i915_pm_rpm@gem-execbuf-stress: > - shard-skl: PASS -> INCOMPLETE [fdo#107803] / [fdo#107807] > > * igt@i915_pm_rpm@system-suspend: > - shard-kbl: PASS -> INCOMPLETE [fdo#103665] / [fdo#107807] > > * igt@kms_busy@basic-flip-e: > - shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1 > > * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-f: > - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2 > > * igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic: > - shard-glk: PASS -> FAIL [fdo#104873] > > * igt@kms_dp_dsc@basic-dsc-enable-edp: > - shard-iclb: PASS -> SKIP [fdo#109349] > > * igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled: > - shard-skl: NOTRUN -> FAIL [fdo#103184] > > * igt@kms_fbcon_fbt@fbc-suspend: > - shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773] +1 > > * igt@kms_force_connector_basic@prune-stale-modes: > - shard-apl: NOTRUN -> SKIP [fdo#109271] +19 > > * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite: > - shard-iclb: PASS -> FAIL [fdo#103167] +3 > > * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render: > - shard-snb: NOTRUN -> SKIP [fdo#109271] +117 > > * igt@kms_lease@atomic_implicit_crtc: > - shard-snb: NOTRUN -> FAIL [fdo#110279] > > * igt@kms_lease@setcrtc_implicit_plane: > - shard-snb: NOTRUN -> FAIL [fdo#110281] > > * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-e: > - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +10 > > * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping: > - shard-glk: PASS -> SKIP [fdo#109271] > > * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: > - shard-apl: NOTRUN -> FAIL [fdo#108145] > > * igt@kms_plane_alpha_blend@pipe-b-alpha-basic: > - shard-skl: NOTRUN -> FAIL [fdo#108145] +2 > > * igt@kms_plane_lowres@pipe-a-tiling-x: > - shard-iclb: PASS -> FAIL [fdo#103166] > > * igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format: > - shard-glk: PASS -> SKIP [fdo#109271] / [fdo#109278] > > * igt@kms_psr@psr2_cursor_mmap_cpu: > - shard-iclb: PASS -> SKIP [fdo#109441] +2 > > * igt@kms_vrr@flip-suspend: > - shard-skl: NOTRUN -> SKIP [fdo#109271] +40 > > * igt@perf_pmu@rc6: > - shard-kbl: PASS -> SKIP [fdo#109271] > > > #### Possible fixes #### > > * igt@gem_softpin@noreloc-s3: > - shard-apl: DMESG-WARN [fdo#108566] -> PASS +2 > > * igt@kms_cursor_crc@cursor-64x64-suspend: > - shard-kbl: DMESG-WARN [fdo#108566] -> PASS > > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: > - shard-iclb: FAIL [fdo#103167] -> PASS +5 > > * igt@kms_plane@pixel-format-pipe-c-planes: > - shard-glk: SKIP [fdo#109271] -> PASS > > * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: > - shard-skl: FAIL [fdo#108145] -> PASS > > * igt@kms_plane_scaling@pipe-c-scaler-with-rotation: > - shard-glk: SKIP [fdo#109271] / [fdo#109278] -> PASS +1 > > * igt@kms_rotation_crc@multiplane-rotation-cropping-bottom: > - shard-kbl: DMESG-FAIL [fdo#105763] -> PASS > > * igt@kms_sysfs_edid_timing: > - shard-iclb: FAIL [fdo#100047] -> PASS > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047 > [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166 > [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 > [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184 > [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665 > [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108 > [fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873 > [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763 > [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773 > [fdo#107803]: https://bugs.freedesktop.org/show_bug.cgi?id=107803 > [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807 > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566 > [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 > [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 > [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349 > [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 > [fdo#110279]: https://bugs.freedesktop.org/show_bug.cgi?id=110279 > [fdo#110281]: https://bugs.freedesktop.org/show_bug.cgi?id=110281 > > > Participating hosts (10 -> 9) > ------------------------------ > > Missing (1): shard-hsw > > > Build changes > ------------- > > * Linux: CI_DRM_5954 -> Patchwork_12840 > > CI_DRM_5954: a77e0dc060fcd1a2a09412067097685c5101589c @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_4957: a765aa108105804c19096554447ad0cb71f64fc3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_12840: d26cc79d0b12c09f18764d40b5a496230ad7fc4d @ git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12840/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] drm/i915/icl: Fix MG_DP_MODE() register programming 2019-04-19 7:10 [PATCH] drm/i915/icl: Fix MG_DP_MODE() register programming Imre Deak ` (2 preceding siblings ...) 2019-04-19 8:55 ` ✓ Fi.CI.IGT: " Patchwork @ 2019-04-19 16:02 ` Souza, Jose 2019-04-19 16:04 ` Imre Deak 2019-04-22 16:15 ` Lucas De Marchi 4 siblings, 1 reply; 10+ messages in thread From: Souza, Jose @ 2019-04-19 16:02 UTC (permalink / raw) To: intel-gfx, Deak, Imre; +Cc: De Marchi, Lucas [-- Attachment #1.1: Type: text/plain, Size: 3016 bytes --] On Fri, 2019-04-19 at 10:10 +0300, Imre Deak wrote: > Fix the order of lane, port parameters passed to the register macro. > > Note that this was already partly fixed by commit > 37fc7845df7b6 ("drm/i915: Call MG_DP_MODE() macro with the right > parameters order") > > Fixes: 58106b7d816e1 ("drm/i915: Make MG PHY macros semantically > consistent") > Cc: José Roberto de Souza <jose.souza@intel.com> > Cc: Lucas De Marchi <lucas.demarchi@intel.com> > Cc: Aditya Swarup <aditya.swarup@intel.com> > Signed-off-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/intel_ddi.c | 18 ++++++++---------- > 1 file changed, 8 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c > b/drivers/gpu/drm/i915/intel_ddi.c > index 24f9106efcc6..f181c26f62fd 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -2905,21 +2905,20 @@ static void > icl_enable_phy_clock_gating(struct intel_digital_port *dig_port) > struct drm_i915_private *dev_priv = to_i915(dig_port- > >base.base.dev); > enum port port = dig_port->base.port; > enum tc_port tc_port = intel_port_to_tc(dev_priv, port); > - i915_reg_t mg_regs[2] = { MG_DP_MODE(0, port), MG_DP_MODE(1, > port) }; > u32 val; > - int i; > + int ln; > > if (tc_port == PORT_TC_NONE) > return; > > - for (i = 0; i < ARRAY_SIZE(mg_regs); i++) { > - val = I915_READ(mg_regs[i]); > + for (ln = 0; ln < 2; ln++) { > + val = I915_READ(MG_DP_MODE(ln, port)); > val |= MG_DP_MODE_CFG_TR2PWR_GATING | > MG_DP_MODE_CFG_TRPWR_GATING | > MG_DP_MODE_CFG_CLNPWR_GATING | > MG_DP_MODE_CFG_DIGPWR_GATING | > MG_DP_MODE_CFG_GAONPWR_GATING; > - I915_WRITE(mg_regs[i], val); > + I915_WRITE(MG_DP_MODE(ln, port), val); > } > > val = I915_READ(MG_MISC_SUS0(tc_port)); > @@ -2938,21 +2937,20 @@ static void > icl_disable_phy_clock_gating(struct intel_digital_port *dig_port) > struct drm_i915_private *dev_priv = to_i915(dig_port- > >base.base.dev); > enum port port = dig_port->base.port; > enum tc_port tc_port = intel_port_to_tc(dev_priv, port); > - i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, > 1) }; I would split this fix from the change dropping mg_regs or at least tell that while you were fixing it you changed the way it reads each MG_DP_MODE line. > u32 val; > - int i; > + int ln; > > if (tc_port == PORT_TC_NONE) > return; > > - for (i = 0; i < ARRAY_SIZE(mg_regs); i++) { > - val = I915_READ(mg_regs[i]); > + for (ln = 0; ln < 2; ln++) { > + val = I915_READ(MG_DP_MODE(ln, port)); > val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING | > MG_DP_MODE_CFG_TRPWR_GATING | > MG_DP_MODE_CFG_CLNPWR_GATING | > MG_DP_MODE_CFG_DIGPWR_GATING | > MG_DP_MODE_CFG_GAONPWR_GATING); > - I915_WRITE(mg_regs[i], val); > + I915_WRITE(MG_DP_MODE(ln, port), val); > } > > val = I915_READ(MG_MISC_SUS0(tc_port)); [-- Attachment #1.2: This is a digitally signed message part --] [-- Type: application/pgp-signature, Size: 488 bytes --] [-- Attachment #2: Type: text/plain, Size: 159 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] drm/i915/icl: Fix MG_DP_MODE() register programming 2019-04-19 16:02 ` [PATCH] " Souza, Jose @ 2019-04-19 16:04 ` Imre Deak 2019-04-19 16:29 ` Souza, Jose 0 siblings, 1 reply; 10+ messages in thread From: Imre Deak @ 2019-04-19 16:04 UTC (permalink / raw) To: Souza, Jose; +Cc: intel-gfx, De Marchi, Lucas On Fri, Apr 19, 2019 at 07:02:10PM +0300, Souza, Jose wrote: > On Fri, 2019-04-19 at 10:10 +0300, Imre Deak wrote: > > Fix the order of lane, port parameters passed to the register macro. > > > > Note that this was already partly fixed by commit > > 37fc7845df7b6 ("drm/i915: Call MG_DP_MODE() macro with the right > > parameters order") > > > > Fixes: 58106b7d816e1 ("drm/i915: Make MG PHY macros semantically > > consistent") > > Cc: José Roberto de Souza <jose.souza@intel.com> > > Cc: Lucas De Marchi <lucas.demarchi@intel.com> > > Cc: Aditya Swarup <aditya.swarup@intel.com> > > Signed-off-by: Imre Deak <imre.deak@intel.com> > > --- > > drivers/gpu/drm/i915/intel_ddi.c | 18 ++++++++---------- > > 1 file changed, 8 insertions(+), 10 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c > > b/drivers/gpu/drm/i915/intel_ddi.c > > index 24f9106efcc6..f181c26f62fd 100644 > > --- a/drivers/gpu/drm/i915/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/intel_ddi.c > > @@ -2905,21 +2905,20 @@ static void > > icl_enable_phy_clock_gating(struct intel_digital_port *dig_port) > > struct drm_i915_private *dev_priv = to_i915(dig_port- > > >base.base.dev); > > enum port port = dig_port->base.port; > > enum tc_port tc_port = intel_port_to_tc(dev_priv, port); > > - i915_reg_t mg_regs[2] = { MG_DP_MODE(0, port), MG_DP_MODE(1, > > port) }; > > u32 val; > > - int i; > > + int ln; > > > > if (tc_port == PORT_TC_NONE) > > return; > > > > - for (i = 0; i < ARRAY_SIZE(mg_regs); i++) { > > - val = I915_READ(mg_regs[i]); > > + for (ln = 0; ln < 2; ln++) { > > + val = I915_READ(MG_DP_MODE(ln, port)); > > val |= MG_DP_MODE_CFG_TR2PWR_GATING | > > MG_DP_MODE_CFG_TRPWR_GATING | > > MG_DP_MODE_CFG_CLNPWR_GATING | > > MG_DP_MODE_CFG_DIGPWR_GATING | > > MG_DP_MODE_CFG_GAONPWR_GATING; > > - I915_WRITE(mg_regs[i], val); > > + I915_WRITE(MG_DP_MODE(ln, port), val); > > } > > > > val = I915_READ(MG_MISC_SUS0(tc_port)); > > @@ -2938,21 +2937,20 @@ static void > > icl_disable_phy_clock_gating(struct intel_digital_port *dig_port) > > struct drm_i915_private *dev_priv = to_i915(dig_port- > > >base.base.dev); > > enum port port = dig_port->base.port; > > enum tc_port tc_port = intel_port_to_tc(dev_priv, port); > > - i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, > > 1) }; > > I would split this fix from the change dropping mg_regs or at least > tell that while you were fixing it you changed the way it reads > each MG_DP_MODE line. I don't think it's worth a separate patch, since it's a small change and quite obvious what and how changed. I can add a note to the commit message about making things simpler. > > > > u32 val; > > - int i; > > + int ln; > > > > if (tc_port == PORT_TC_NONE) > > return; > > > > - for (i = 0; i < ARRAY_SIZE(mg_regs); i++) { > > - val = I915_READ(mg_regs[i]); > > + for (ln = 0; ln < 2; ln++) { > > + val = I915_READ(MG_DP_MODE(ln, port)); > > val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING | > > MG_DP_MODE_CFG_TRPWR_GATING | > > MG_DP_MODE_CFG_CLNPWR_GATING | > > MG_DP_MODE_CFG_DIGPWR_GATING | > > MG_DP_MODE_CFG_GAONPWR_GATING); > > - I915_WRITE(mg_regs[i], val); > > + I915_WRITE(MG_DP_MODE(ln, port), val); > > } > > > > val = I915_READ(MG_MISC_SUS0(tc_port)); _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] drm/i915/icl: Fix MG_DP_MODE() register programming 2019-04-19 16:04 ` Imre Deak @ 2019-04-19 16:29 ` Souza, Jose 2019-04-19 17:01 ` Imre Deak 0 siblings, 1 reply; 10+ messages in thread From: Souza, Jose @ 2019-04-19 16:29 UTC (permalink / raw) To: Deak, Imre; +Cc: De Marchi, Lucas, intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 3854 bytes --] On Fri, 2019-04-19 at 19:04 +0300, Imre Deak wrote: > On Fri, Apr 19, 2019 at 07:02:10PM +0300, Souza, Jose wrote: > > On Fri, 2019-04-19 at 10:10 +0300, Imre Deak wrote: > > > Fix the order of lane, port parameters passed to the register > > > macro. > > > > > > Note that this was already partly fixed by commit > > > 37fc7845df7b6 ("drm/i915: Call MG_DP_MODE() macro with the right > > > parameters order") > > > > > > Fixes: 58106b7d816e1 ("drm/i915: Make MG PHY macros semantically > > > consistent") > > > Cc: José Roberto de Souza <jose.souza@intel.com> > > > Cc: Lucas De Marchi <lucas.demarchi@intel.com> > > > Cc: Aditya Swarup <aditya.swarup@intel.com> > > > Signed-off-by: Imre Deak <imre.deak@intel.com> > > > --- > > > drivers/gpu/drm/i915/intel_ddi.c | 18 ++++++++---------- > > > 1 file changed, 8 insertions(+), 10 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c > > > b/drivers/gpu/drm/i915/intel_ddi.c > > > index 24f9106efcc6..f181c26f62fd 100644 > > > --- a/drivers/gpu/drm/i915/intel_ddi.c > > > +++ b/drivers/gpu/drm/i915/intel_ddi.c > > > @@ -2905,21 +2905,20 @@ static void > > > icl_enable_phy_clock_gating(struct intel_digital_port *dig_port) > > > struct drm_i915_private *dev_priv = to_i915(dig_port- > > > > base.base.dev); > > > enum port port = dig_port->base.port; > > > enum tc_port tc_port = intel_port_to_tc(dev_priv, port); > > > - i915_reg_t mg_regs[2] = { MG_DP_MODE(0, port), MG_DP_MODE(1, > > > port) }; > > > u32 val; > > > - int i; > > > + int ln; > > > > > > if (tc_port == PORT_TC_NONE) > > > return; > > > > > > - for (i = 0; i < ARRAY_SIZE(mg_regs); i++) { > > > - val = I915_READ(mg_regs[i]); > > > + for (ln = 0; ln < 2; ln++) { > > > + val = I915_READ(MG_DP_MODE(ln, port)); > > > val |= MG_DP_MODE_CFG_TR2PWR_GATING | > > > MG_DP_MODE_CFG_TRPWR_GATING | > > > MG_DP_MODE_CFG_CLNPWR_GATING | > > > MG_DP_MODE_CFG_DIGPWR_GATING | > > > MG_DP_MODE_CFG_GAONPWR_GATING; > > > - I915_WRITE(mg_regs[i], val); > > > + I915_WRITE(MG_DP_MODE(ln, port), val); > > > } > > > > > > val = I915_READ(MG_MISC_SUS0(tc_port)); > > > @@ -2938,21 +2937,20 @@ static void > > > icl_disable_phy_clock_gating(struct intel_digital_port *dig_port) > > > struct drm_i915_private *dev_priv = to_i915(dig_port- > > > > base.base.dev); > > > enum port port = dig_port->base.port; > > > enum tc_port tc_port = intel_port_to_tc(dev_priv, port); > > > - i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, > > > 1) }; > > > > I would split this fix from the change dropping mg_regs or at least > > tell that while you were fixing it you changed the way it reads > > each MG_DP_MODE line. > > I don't think it's worth a separate patch, since it's a small change > and quite obvious what and how changed. I can add a note to the > commit > message about making things simpler. I suggested split because this will probably be backported so would be nice to be as clean as possible but I'm also okay if you add it to the commit description. > > > > > > u32 val; > > > - int i; > > > + int ln; > > > > > > if (tc_port == PORT_TC_NONE) > > > return; > > > > > > - for (i = 0; i < ARRAY_SIZE(mg_regs); i++) { > > > - val = I915_READ(mg_regs[i]); > > > + for (ln = 0; ln < 2; ln++) { > > > + val = I915_READ(MG_DP_MODE(ln, port)); > > > val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING | > > > MG_DP_MODE_CFG_TRPWR_GATING | > > > MG_DP_MODE_CFG_CLNPWR_GATING | > > > MG_DP_MODE_CFG_DIGPWR_GATING | > > > MG_DP_MODE_CFG_GAONPWR_GATING); > > > - I915_WRITE(mg_regs[i], val); > > > + I915_WRITE(MG_DP_MODE(ln, port), val); > > > } > > > > > > val = I915_READ(MG_MISC_SUS0(tc_port)); > > [-- Attachment #1.2: This is a digitally signed message part --] [-- Type: application/pgp-signature, Size: 488 bytes --] [-- Attachment #2: Type: text/plain, Size: 159 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] drm/i915/icl: Fix MG_DP_MODE() register programming 2019-04-19 16:29 ` Souza, Jose @ 2019-04-19 17:01 ` Imre Deak 0 siblings, 0 replies; 10+ messages in thread From: Imre Deak @ 2019-04-19 17:01 UTC (permalink / raw) To: Souza, Jose; +Cc: De Marchi, Lucas, intel-gfx On Fri, Apr 19, 2019 at 07:29:05PM +0300, Souza, Jose wrote: > On Fri, 2019-04-19 at 19:04 +0300, Imre Deak wrote: > > On Fri, Apr 19, 2019 at 07:02:10PM +0300, Souza, Jose wrote: > > > On Fri, 2019-04-19 at 10:10 +0300, Imre Deak wrote: > > > > Fix the order of lane, port parameters passed to the register > > > > macro. > > > > > > > > Note that this was already partly fixed by commit > > > > 37fc7845df7b6 ("drm/i915: Call MG_DP_MODE() macro with the right > > > > parameters order") > > > > > > > > Fixes: 58106b7d816e1 ("drm/i915: Make MG PHY macros semantically > > > > consistent") > > > > Cc: José Roberto de Souza <jose.souza@intel.com> > > > > Cc: Lucas De Marchi <lucas.demarchi@intel.com> > > > > Cc: Aditya Swarup <aditya.swarup@intel.com> > > > > Signed-off-by: Imre Deak <imre.deak@intel.com> > > > > --- > > > > drivers/gpu/drm/i915/intel_ddi.c | 18 ++++++++---------- > > > > 1 file changed, 8 insertions(+), 10 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c > > > > b/drivers/gpu/drm/i915/intel_ddi.c > > > > index 24f9106efcc6..f181c26f62fd 100644 > > > > --- a/drivers/gpu/drm/i915/intel_ddi.c > > > > +++ b/drivers/gpu/drm/i915/intel_ddi.c > > > > @@ -2905,21 +2905,20 @@ static void > > > > icl_enable_phy_clock_gating(struct intel_digital_port *dig_port) > > > > struct drm_i915_private *dev_priv = to_i915(dig_port- > > > > > base.base.dev); > > > > enum port port = dig_port->base.port; > > > > enum tc_port tc_port = intel_port_to_tc(dev_priv, port); > > > > - i915_reg_t mg_regs[2] = { MG_DP_MODE(0, port), MG_DP_MODE(1, > > > > port) }; > > > > u32 val; > > > > - int i; > > > > + int ln; > > > > > > > > if (tc_port == PORT_TC_NONE) > > > > return; > > > > > > > > - for (i = 0; i < ARRAY_SIZE(mg_regs); i++) { > > > > - val = I915_READ(mg_regs[i]); > > > > + for (ln = 0; ln < 2; ln++) { > > > > + val = I915_READ(MG_DP_MODE(ln, port)); > > > > val |= MG_DP_MODE_CFG_TR2PWR_GATING | > > > > MG_DP_MODE_CFG_TRPWR_GATING | > > > > MG_DP_MODE_CFG_CLNPWR_GATING | > > > > MG_DP_MODE_CFG_DIGPWR_GATING | > > > > MG_DP_MODE_CFG_GAONPWR_GATING; > > > > - I915_WRITE(mg_regs[i], val); > > > > + I915_WRITE(MG_DP_MODE(ln, port), val); > > > > } > > > > > > > > val = I915_READ(MG_MISC_SUS0(tc_port)); > > > > @@ -2938,21 +2937,20 @@ static void > > > > icl_disable_phy_clock_gating(struct intel_digital_port *dig_port) > > > > struct drm_i915_private *dev_priv = to_i915(dig_port- > > > > > base.base.dev); > > > > enum port port = dig_port->base.port; > > > > enum tc_port tc_port = intel_port_to_tc(dev_priv, port); > > > > - i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, > > > > 1) }; > > > > > > I would split this fix from the change dropping mg_regs or at least > > > tell that while you were fixing it you changed the way it reads > > > each MG_DP_MODE line. > > > > I don't think it's worth a separate patch, since it's a small change > > and quite obvious what and how changed. I can add a note to the > > commit > > message about making things simpler. > > I suggested split because this will probably be backported so would be > nice to be as clean as possible but I'm also okay if you add it to the > commit description. No need to backport this, the regressing commit won't make it to 5.1. Even if it had this fix would still go through -fixes since we're still only in -rc5, and so we wouldn't need to backport anything. So this change along with the rest of related macro param shuffling patches won't appear until 5.2. For the future: git fetch stable; git fetch linus-upstream followed by git tag --contains <regressing commit> makes it easy to see if something needs backporting. > > > > > > > > > > u32 val; > > > > - int i; > > > > + int ln; > > > > > > > > if (tc_port == PORT_TC_NONE) > > > > return; > > > > > > > > - for (i = 0; i < ARRAY_SIZE(mg_regs); i++) { > > > > - val = I915_READ(mg_regs[i]); > > > > + for (ln = 0; ln < 2; ln++) { > > > > + val = I915_READ(MG_DP_MODE(ln, port)); > > > > val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING | > > > > MG_DP_MODE_CFG_TRPWR_GATING | > > > > MG_DP_MODE_CFG_CLNPWR_GATING | > > > > MG_DP_MODE_CFG_DIGPWR_GATING | > > > > MG_DP_MODE_CFG_GAONPWR_GATING); > > > > - I915_WRITE(mg_regs[i], val); > > > > + I915_WRITE(MG_DP_MODE(ln, port), val); > > > > } > > > > > > > > val = I915_READ(MG_MISC_SUS0(tc_port)); > > > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] drm/i915/icl: Fix MG_DP_MODE() register programming 2019-04-19 7:10 [PATCH] drm/i915/icl: Fix MG_DP_MODE() register programming Imre Deak ` (3 preceding siblings ...) 2019-04-19 16:02 ` [PATCH] " Souza, Jose @ 2019-04-22 16:15 ` Lucas De Marchi 4 siblings, 0 replies; 10+ messages in thread From: Lucas De Marchi @ 2019-04-22 16:15 UTC (permalink / raw) To: Imre Deak; +Cc: intel-gfx On Fri, Apr 19, 2019 at 10:10:26AM +0300, Imre Deak wrote: >Fix the order of lane, port parameters passed to the register macro. > >Note that this was already partly fixed by commit >37fc7845df7b6 ("drm/i915: Call MG_DP_MODE() macro with the right parameters order") > >Fixes: 58106b7d816e1 ("drm/i915: Make MG PHY macros semantically consistent") >Cc: José Roberto de Souza <jose.souza@intel.com> >Cc: Lucas De Marchi <lucas.demarchi@intel.com> >Cc: Aditya Swarup <aditya.swarup@intel.com> >Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> thanks Lucas De Marchi >--- > drivers/gpu/drm/i915/intel_ddi.c | 18 ++++++++---------- > 1 file changed, 8 insertions(+), 10 deletions(-) > >diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c >index 24f9106efcc6..f181c26f62fd 100644 >--- a/drivers/gpu/drm/i915/intel_ddi.c >+++ b/drivers/gpu/drm/i915/intel_ddi.c >@@ -2905,21 +2905,20 @@ static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port) > struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); > enum port port = dig_port->base.port; > enum tc_port tc_port = intel_port_to_tc(dev_priv, port); >- i915_reg_t mg_regs[2] = { MG_DP_MODE(0, port), MG_DP_MODE(1, port) }; > u32 val; >- int i; >+ int ln; > > if (tc_port == PORT_TC_NONE) > return; > >- for (i = 0; i < ARRAY_SIZE(mg_regs); i++) { >- val = I915_READ(mg_regs[i]); >+ for (ln = 0; ln < 2; ln++) { >+ val = I915_READ(MG_DP_MODE(ln, port)); > val |= MG_DP_MODE_CFG_TR2PWR_GATING | > MG_DP_MODE_CFG_TRPWR_GATING | > MG_DP_MODE_CFG_CLNPWR_GATING | > MG_DP_MODE_CFG_DIGPWR_GATING | > MG_DP_MODE_CFG_GAONPWR_GATING; >- I915_WRITE(mg_regs[i], val); >+ I915_WRITE(MG_DP_MODE(ln, port), val); > } > > val = I915_READ(MG_MISC_SUS0(tc_port)); >@@ -2938,21 +2937,20 @@ static void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port) > struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); > enum port port = dig_port->base.port; > enum tc_port tc_port = intel_port_to_tc(dev_priv, port); >- i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) }; > u32 val; >- int i; >+ int ln; > > if (tc_port == PORT_TC_NONE) > return; > >- for (i = 0; i < ARRAY_SIZE(mg_regs); i++) { >- val = I915_READ(mg_regs[i]); >+ for (ln = 0; ln < 2; ln++) { >+ val = I915_READ(MG_DP_MODE(ln, port)); > val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING | > MG_DP_MODE_CFG_TRPWR_GATING | > MG_DP_MODE_CFG_CLNPWR_GATING | > MG_DP_MODE_CFG_DIGPWR_GATING | > MG_DP_MODE_CFG_GAONPWR_GATING); >- I915_WRITE(mg_regs[i], val); >+ I915_WRITE(MG_DP_MODE(ln, port), val); > } > > val = I915_READ(MG_MISC_SUS0(tc_port)); >-- >2.13.2 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2019-04-23 8:13 UTC | newest] Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-04-19 7:10 [PATCH] drm/i915/icl: Fix MG_DP_MODE() register programming Imre Deak 2019-04-19 7:27 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork 2019-04-19 7:46 ` ✓ Fi.CI.BAT: success " Patchwork 2019-04-19 8:55 ` ✓ Fi.CI.IGT: " Patchwork 2019-04-23 8:13 ` Imre Deak 2019-04-19 16:02 ` [PATCH] " Souza, Jose 2019-04-19 16:04 ` Imre Deak 2019-04-19 16:29 ` Souza, Jose 2019-04-19 17:01 ` Imre Deak 2019-04-22 16:15 ` Lucas De Marchi
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