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From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org
Cc: gkurz@kaod.org, clg@kaod.org, qemu-devel@nongnu.org,
	qemu-ppc@nongnu.org,
	Benjamin Herrenschmidt <benh@kernel.crashing.org>,
	David Gibson <david@gibson.dropbear.id.au>
Subject: [Qemu-devel] [PULL 35/36] ppc/hash32: Rework R and C bit updates
Date: Fri, 26 Apr 2019 16:06:26 +1000	[thread overview]
Message-ID: <20190426060627.18153-36-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <20190426060627.18153-1-david@gibson.dropbear.id.au>

From: Benjamin Herrenschmidt <benh@kernel.crashing.org>

With MT-TCG, we are now running translation in a racy way, thus
we need to mimic hardware when it comes to updating the R and
C bits, by doing byte stores.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20190411080004.8690-5-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
 target/ppc/mmu-hash32.c | 45 ++++++++++++++++++++++++++++-------------
 1 file changed, 31 insertions(+), 14 deletions(-)

diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c
index 3f4dee835e..55cf156a0b 100644
--- a/target/ppc/mmu-hash32.c
+++ b/target/ppc/mmu-hash32.c
@@ -345,6 +345,24 @@ static hwaddr ppc_hash32_pteg_search(PowerPCCPU *cpu, hwaddr pteg_off,
     return -1;
 }
 
+static void ppc_hash32_set_r(PowerPCCPU *cpu, hwaddr pte_offset, uint32_t pte1)
+{
+    target_ulong base = ppc_hash32_hpt_base(cpu);
+    hwaddr offset = pte_offset + 6;
+
+    /* The HW performs a non-atomic byte update */
+    stb_phys(CPU(cpu)->as, base + offset, ((pte1 >> 8) & 0xff) | 0x01);
+}
+
+static void ppc_hash32_set_c(PowerPCCPU *cpu, hwaddr pte_offset, uint64_t pte1)
+{
+    target_ulong base = ppc_hash32_hpt_base(cpu);
+    hwaddr offset = pte_offset + 7;
+
+    /* The HW performs a non-atomic byte update */
+    stb_phys(CPU(cpu)->as, base + offset, (pte1 & 0xff) | 0x80);
+}
+
 static hwaddr ppc_hash32_htab_lookup(PowerPCCPU *cpu,
                                      target_ulong sr, target_ulong eaddr,
                                      ppc_hash_pte32_t *pte)
@@ -403,7 +421,6 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
     hwaddr pte_offset;
     ppc_hash_pte32_t pte;
     int prot;
-    uint32_t new_pte1;
     const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC};
     hwaddr raddr;
 
@@ -519,20 +536,20 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
 
     /* 8. Update PTE referenced and changed bits if necessary */
 
-    new_pte1 = pte.pte1 | HPTE32_R_R; /* set referenced bit */
-    if (rwx == 1) {
-        new_pte1 |= HPTE32_R_C; /* set changed (dirty) bit */
-    } else {
-        /*
-         * Treat the page as read-only for now, so that a later write
-         * will pass through this function again to set the C bit
-         */
-        prot &= ~PAGE_WRITE;
-    }
-
-    if (new_pte1 != pte.pte1) {
-        ppc_hash32_store_hpte1(cpu, pte_offset, new_pte1);
+    if (!(pte.pte1 & HPTE32_R_R)) {
+        ppc_hash32_set_r(cpu, pte_offset, pte.pte1);
     }
+    if (!(pte.pte1 & HPTE32_R_C)) {
+        if (rwx == 1) {
+            ppc_hash32_set_c(cpu, pte_offset, pte.pte1);
+        } else {
+            /*
+             * Treat the page as read-only for now, so that a later write
+             * will pass through this function again to set the C bit
+             */
+            prot &= ~PAGE_WRITE;
+        }
+     }
 
     /* 9. Determine the real address from the PTE */
 
-- 
2.20.1

WARNING: multiple messages have this Message-ID (diff)
From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org
Cc: gkurz@kaod.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org,
	clg@kaod.org, David Gibson <david@gibson.dropbear.id.au>
Subject: [Qemu-devel] [PULL 35/36] ppc/hash32: Rework R and C bit updates
Date: Fri, 26 Apr 2019 16:06:26 +1000	[thread overview]
Message-ID: <20190426060627.18153-36-david@gibson.dropbear.id.au> (raw)
Message-ID: <20190426060626.tbPCU8mWe6ULXbRWxJwZ48HIloP6qGoXZonW29TV08U@z> (raw)
In-Reply-To: <20190426060627.18153-1-david@gibson.dropbear.id.au>

From: Benjamin Herrenschmidt <benh@kernel.crashing.org>

With MT-TCG, we are now running translation in a racy way, thus
we need to mimic hardware when it comes to updating the R and
C bits, by doing byte stores.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20190411080004.8690-5-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
 target/ppc/mmu-hash32.c | 45 ++++++++++++++++++++++++++++-------------
 1 file changed, 31 insertions(+), 14 deletions(-)

diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c
index 3f4dee835e..55cf156a0b 100644
--- a/target/ppc/mmu-hash32.c
+++ b/target/ppc/mmu-hash32.c
@@ -345,6 +345,24 @@ static hwaddr ppc_hash32_pteg_search(PowerPCCPU *cpu, hwaddr pteg_off,
     return -1;
 }
 
+static void ppc_hash32_set_r(PowerPCCPU *cpu, hwaddr pte_offset, uint32_t pte1)
+{
+    target_ulong base = ppc_hash32_hpt_base(cpu);
+    hwaddr offset = pte_offset + 6;
+
+    /* The HW performs a non-atomic byte update */
+    stb_phys(CPU(cpu)->as, base + offset, ((pte1 >> 8) & 0xff) | 0x01);
+}
+
+static void ppc_hash32_set_c(PowerPCCPU *cpu, hwaddr pte_offset, uint64_t pte1)
+{
+    target_ulong base = ppc_hash32_hpt_base(cpu);
+    hwaddr offset = pte_offset + 7;
+
+    /* The HW performs a non-atomic byte update */
+    stb_phys(CPU(cpu)->as, base + offset, (pte1 & 0xff) | 0x80);
+}
+
 static hwaddr ppc_hash32_htab_lookup(PowerPCCPU *cpu,
                                      target_ulong sr, target_ulong eaddr,
                                      ppc_hash_pte32_t *pte)
@@ -403,7 +421,6 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
     hwaddr pte_offset;
     ppc_hash_pte32_t pte;
     int prot;
-    uint32_t new_pte1;
     const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC};
     hwaddr raddr;
 
@@ -519,20 +536,20 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
 
     /* 8. Update PTE referenced and changed bits if necessary */
 
-    new_pte1 = pte.pte1 | HPTE32_R_R; /* set referenced bit */
-    if (rwx == 1) {
-        new_pte1 |= HPTE32_R_C; /* set changed (dirty) bit */
-    } else {
-        /*
-         * Treat the page as read-only for now, so that a later write
-         * will pass through this function again to set the C bit
-         */
-        prot &= ~PAGE_WRITE;
-    }
-
-    if (new_pte1 != pte.pte1) {
-        ppc_hash32_store_hpte1(cpu, pte_offset, new_pte1);
+    if (!(pte.pte1 & HPTE32_R_R)) {
+        ppc_hash32_set_r(cpu, pte_offset, pte.pte1);
     }
+    if (!(pte.pte1 & HPTE32_R_C)) {
+        if (rwx == 1) {
+            ppc_hash32_set_c(cpu, pte_offset, pte.pte1);
+        } else {
+            /*
+             * Treat the page as read-only for now, so that a later write
+             * will pass through this function again to set the C bit
+             */
+            prot &= ~PAGE_WRITE;
+        }
+     }
 
     /* 9. Determine the real address from the PTE */
 
-- 
2.20.1



  parent reply	other threads:[~2019-04-26  6:07 UTC|newest]

Thread overview: 79+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-26  6:05 [Qemu-devel] [PULL 00/36] ppc-for-4.1 queue 20190426 David Gibson
2019-04-26  6:05 ` David Gibson
2019-04-26  6:05 ` [Qemu-devel] [PULL 01/36] spapr: Support NVIDIA V100 GPU with NVLink2 David Gibson
2019-04-26  6:05   ` David Gibson
2019-05-17 17:37   ` Laurent Vivier
2019-05-17 17:58     ` Greg Kurz
2019-05-20  6:06     ` David Gibson
2019-04-26  6:05 ` [Qemu-devel] [PULL 02/36] hw/ppc/prep: Drop useless inclusion of "hw/input/i8042.h" David Gibson
2019-04-26  6:05   ` David Gibson
2019-04-26  6:05 ` [Qemu-devel] [PULL 03/36] spapr/rtas: modify spapr_rtas_register() to remove RTAS handlers David Gibson
2019-04-26  6:05   ` David Gibson
2019-04-26  6:05 ` [Qemu-devel] [PULL 04/36] spapr/irq: remove spapr_ics_create() David Gibson
2019-04-26  6:05   ` David Gibson
2019-04-26  6:05 ` [Qemu-devel] [PULL 05/36] target/ppc: Style fixes for ppc-models.[ch] David Gibson
2019-04-26  6:05   ` David Gibson
2019-04-26  6:05 ` [Qemu-devel] [PULL 06/36] target/ppc: Style fixes for cpu.[ch] David Gibson
2019-04-26  6:05   ` David Gibson
2019-04-26  6:05 ` [Qemu-devel] [PULL 07/36] target/ppc: Style fixes for int_helper.c David Gibson
2019-04-26  6:05   ` David Gibson
2019-04-26  6:05 ` [Qemu-devel] [PULL 08/36] target/ppc: Style fixes for fpu_helper.c David Gibson
2019-04-26  6:05   ` David Gibson
2019-04-26  6:06 ` [Qemu-devel] [PULL 09/36] target/ppc: Style fixes for dfp_helper.c David Gibson
2019-04-26  6:06   ` David Gibson
2019-04-26  6:06 ` [Qemu-devel] [PULL 10/36] target/ppc: Style fixes for excp_helper.c David Gibson
2019-04-26  6:06   ` David Gibson
2019-04-26  6:06 ` [Qemu-devel] [PULL 11/36] target/ppc: Style fixes for gdbstub.c David Gibson
2019-04-26  6:06   ` David Gibson
2019-04-26  6:06 ` [Qemu-devel] [PULL 12/36] target/ppc: Style fixes for helper_regs.h David Gibson
2019-04-26  6:06   ` David Gibson
2019-04-26  6:06 ` [Qemu-devel] [PULL 13/36] target/ppc: Style fixes for kvm_ppc.h and kvm.c David Gibson
2019-04-26  6:06   ` David Gibson
2019-04-26  6:06 ` [Qemu-devel] [PULL 14/36] target/ppc: Style fixes for machine.c David Gibson
2019-04-26  6:06   ` David Gibson
2019-04-26  6:06 ` [Qemu-devel] [PULL 15/36] target/ppc: Style fixes for mem_helper.c David Gibson
2019-04-26  6:06   ` David Gibson
2019-04-26  6:06 ` [Qemu-devel] [PULL 16/36] target/ppc: Style fixes for mfrom_table.inc.c & mfrom_table_gen.c David Gibson
2019-04-26  6:06   ` David Gibson
2019-04-26  6:06 ` [Qemu-devel] [PULL 17/36] target/ppc: Style fixes for misc_helper.c David Gibson
2019-04-26  6:06   ` David Gibson
2019-04-26  6:06 ` [Qemu-devel] [PULL 18/36] target/ppc: Style fixes for mmu-hash32.[ch] David Gibson
2019-04-26  6:06   ` David Gibson
2019-04-26  6:06 ` [Qemu-devel] [PULL 19/36] target/ppc: Style fixes for mmu-hash64.[ch] David Gibson
2019-04-26  6:06   ` David Gibson
2019-04-26  6:06 ` [Qemu-devel] [PULL 20/36] target/ppc: Style fixes for mmu_helper.c David Gibson
2019-04-26  6:06   ` David Gibson
2019-04-26  6:06 ` [Qemu-devel] [PULL 21/36] target/ppc: Style fixes for monitor.c David Gibson
2019-04-26  6:06   ` David Gibson
2019-04-26  6:06 ` [Qemu-devel] [PULL 22/36] target/ppc: Style fixes for translate_init.inc.c David Gibson
2019-04-26  6:06   ` David Gibson
2019-04-26  6:06 ` [Qemu-devel] [PULL 23/36] target/ppc: Style fixes for translate.c David Gibson
2019-04-26  6:06   ` David Gibson
2019-04-26  6:06 ` [Qemu-devel] [PULL 24/36] target/ppc: Style fixes for translate/fp-impl.inc.c David Gibson
2019-04-26  6:06   ` David Gibson
2019-04-26  6:06 ` [Qemu-devel] [PULL 25/36] target/ppc: Style fixes for translate/vsx-impl.inc.c David Gibson
2019-04-26  6:06   ` David Gibson
2019-04-26  6:06 ` [Qemu-devel] [PULL 26/36] target/ppc: Style fixes for translate/vmx-impl.inc.c David Gibson
2019-04-26  6:06   ` David Gibson
2019-04-26  6:06 ` [Qemu-devel] [PULL 27/36] target/ppc: Style fixes for translate/spe-impl.inc.c David Gibson
2019-04-26  6:06   ` David Gibson
2019-04-26  6:06 ` [Qemu-devel] [PULL 28/36] spapr_pci: Get rid of duplicate code for node name creation David Gibson
2019-04-26  6:06   ` David Gibson
2019-04-26  6:06 ` [Qemu-devel] [PULL 29/36] spapr: Drop duplicate PCI swizzle code David Gibson
2019-04-26  6:06   ` David Gibson
2019-04-26  6:06 ` [Qemu-devel] [PULL 30/36] target/ppc/trace-events: Fix trivial typo David Gibson
2019-04-26  6:06   ` David Gibson
2019-04-26  6:06 ` [Qemu-devel] [PULL 31/36] target/ppc/kvm: Convert DPRINTF to traces David Gibson
2019-04-26  6:06   ` David Gibson
2019-04-26  6:06 ` [Qemu-devel] [PULL 32/36] target/ppc: Don't check UPRT in radix mode when in HV real mode David Gibson
2019-04-26  6:06   ` David Gibson
2019-04-26  6:06 ` [Qemu-devel] [PULL 33/36] ppc/spapr: Use proper HPTE accessors for H_READ David Gibson
2019-04-26  6:06   ` David Gibson
2019-04-26  6:06 ` [Qemu-devel] [PULL 34/36] ppc/hash64: Rework R and C bit updates David Gibson
2019-04-26  6:06   ` David Gibson
2019-04-26  6:06 ` David Gibson [this message]
2019-04-26  6:06   ` [Qemu-devel] [PULL 35/36] ppc/hash32: " David Gibson
2019-04-26  6:06 ` [Qemu-devel] [PULL 36/36] target/ppc: improve performance of large BAT invalidations David Gibson
2019-04-26  6:06   ` David Gibson
2019-04-28 10:42 ` [Qemu-devel] [PULL 00/36] ppc-for-4.1 queue 20190426 Peter Maydell
2019-04-28 10:42   ` Peter Maydell

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