[PATCH 0/5] Refactor to expand subslice mask

[PATCH 0/5] Refactor to expand subslice mask

[Stuart Summers]

This patch series contains a few code clean-up patches, followed
by a patch which changes the storage of the subslice mask to better
match the userspace access through the I915_QUERY_TOPOLOGY_INFO
ioctl. The index into the subslice_mask array is then calculated:
  slice * subslice stride + subslice index / 8

v2: fix i915_pm_sseu test failure
v3: no changes to patches in the series, just resending to pick up
    in CI correctly
v4: rebase
v5: fix header test

Stuart Summers (5):
  drm/i915: Use local variable for SSEU info in GETPARAM ioctl
  drm/i915: Add macro for SSEU stride calculation
  drm/i915: Move calculation of subslices per slice to new function
  drm/i915: Move sseu helper functions to intel_sseu.h
  drm/i915: Expand subslice mask

 drivers/gpu/drm/i915/gt/intel_engine_cs.c    |   6 +-
 drivers/gpu/drm/i915/gt/intel_engine_types.h |  32 +++--
 drivers/gpu/drm/i915/gt/intel_hangcheck.c    |   3 +-
 drivers/gpu/drm/i915/gt/intel_sseu.h         |  98 ++++++++++++-
 drivers/gpu/drm/i915/gt/intel_workarounds.c  |   2 +-
 drivers/gpu/drm/i915/i915_debugfs.c          |  45 +++---
 drivers/gpu/drm/i915/i915_drv.c              |  15 +-
 drivers/gpu/drm/i915/i915_gpu_error.c        |   5 +-
 drivers/gpu/drm/i915/i915_query.c            |  15 +-
 drivers/gpu/drm/i915/intel_device_info.c     | 143 +++++++++++--------
 drivers/gpu/drm/i915/intel_device_info.h     |  47 ------
 11 files changed, 247 insertions(+), 164 deletions(-)

-- 
2.21.0.5.gaeb582a983

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[PATCH 1/5] drm/i915: Use local variable for SSEU info in GETPARAM ioctl

[Stuart Summers]

In the GETPARAM ioctl handler, use a local variable to consolidate
usage of SSEU runtime info.

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index aacc8dd6ecfd..b6ce7580d414 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -321,6 +321,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct pci_dev *pdev = dev_priv->drm.pdev;
+	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
 	drm_i915_getparam_t *param = data;
 	int value;
 
@@ -374,12 +375,12 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 		value = i915_cmd_parser_get_version(dev_priv);
 		break;
 	case I915_PARAM_SUBSLICE_TOTAL:
-		value = sseu_subslice_total(&RUNTIME_INFO(dev_priv)->sseu);
+		value = sseu_subslice_total(sseu);
 		if (!value)
 			return -ENODEV;
 		break;
 	case I915_PARAM_EU_TOTAL:
-		value = RUNTIME_INFO(dev_priv)->sseu.eu_total;
+		value = sseu->eu_total;
 		if (!value)
 			return -ENODEV;
 		break;
@@ -396,7 +397,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 		value = HAS_POOLED_EU(dev_priv);
 		break;
 	case I915_PARAM_MIN_EU_IN_POOL:
-		value = RUNTIME_INFO(dev_priv)->sseu.min_eu_in_pool;
+		value = sseu->min_eu_in_pool;
 		break;
 	case I915_PARAM_HUC_STATUS:
 		value = intel_huc_check_status(&dev_priv->huc);
@@ -446,12 +447,12 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 		value = intel_engines_has_context_isolation(dev_priv);
 		break;
 	case I915_PARAM_SLICE_MASK:
-		value = RUNTIME_INFO(dev_priv)->sseu.slice_mask;
+		value = sseu->slice_mask;
 		if (!value)
 			return -ENODEV;
 		break;
 	case I915_PARAM_SUBSLICE_MASK:
-		value = RUNTIME_INFO(dev_priv)->sseu.subslice_mask[0];
+		value = sseu->subslice_mask[0];
 		if (!value)
 			return -ENODEV;
 		break;
-- 
2.21.0.5.gaeb582a983

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Re: [PATCH 1/5] drm/i915: Use local variable for SSEU info in GETPARAM ioctl

[Jani Nikula]

On Mon, 29 Apr 2019, Stuart Summers <stuart.summers@intel.com> wrote:
> In the GETPARAM ioctl handler, use a local variable to consolidate
> usage of SSEU runtime info.
>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.c | 11 ++++++-----
>  1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index aacc8dd6ecfd..b6ce7580d414 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -321,6 +321,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct pci_dev *pdev = dev_priv->drm.pdev;
> +	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;

const?

>  	drm_i915_getparam_t *param = data;
>  	int value;
>  
> @@ -374,12 +375,12 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
>  		value = i915_cmd_parser_get_version(dev_priv);
>  		break;
>  	case I915_PARAM_SUBSLICE_TOTAL:
> -		value = sseu_subslice_total(&RUNTIME_INFO(dev_priv)->sseu);
> +		value = sseu_subslice_total(sseu);
>  		if (!value)
>  			return -ENODEV;
>  		break;
>  	case I915_PARAM_EU_TOTAL:
> -		value = RUNTIME_INFO(dev_priv)->sseu.eu_total;
> +		value = sseu->eu_total;
>  		if (!value)
>  			return -ENODEV;
>  		break;
> @@ -396,7 +397,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
>  		value = HAS_POOLED_EU(dev_priv);
>  		break;
>  	case I915_PARAM_MIN_EU_IN_POOL:
> -		value = RUNTIME_INFO(dev_priv)->sseu.min_eu_in_pool;
> +		value = sseu->min_eu_in_pool;
>  		break;
>  	case I915_PARAM_HUC_STATUS:
>  		value = intel_huc_check_status(&dev_priv->huc);
> @@ -446,12 +447,12 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
>  		value = intel_engines_has_context_isolation(dev_priv);
>  		break;
>  	case I915_PARAM_SLICE_MASK:
> -		value = RUNTIME_INFO(dev_priv)->sseu.slice_mask;
> +		value = sseu->slice_mask;
>  		if (!value)
>  			return -ENODEV;
>  		break;
>  	case I915_PARAM_SUBSLICE_MASK:
> -		value = RUNTIME_INFO(dev_priv)->sseu.subslice_mask[0];
> +		value = sseu->subslice_mask[0];
>  		if (!value)
>  			return -ENODEV;
>  		break;

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [PATCH 1/5] drm/i915: Use local variable for SSEU info in GETPARAM ioctl

[Summers, Stuart]

[-- Attachment #1.1: Type: text/plain, Size: 2743 bytes --]

On Tue, 2019-04-30 at 11:58 +0300, Jani Nikula wrote:
> On Mon, 29 Apr 2019, Stuart Summers <stuart.summers@intel.com> wrote:
> > In the GETPARAM ioctl handler, use a local variable to consolidate
> > usage of SSEU runtime info.
> > 
> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.c | 11 ++++++-----
> >  1 file changed, 6 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > b/drivers/gpu/drm/i915/i915_drv.c
> > index aacc8dd6ecfd..b6ce7580d414 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -321,6 +321,7 @@ static int i915_getparam_ioctl(struct
> > drm_device *dev, void *data,
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(dev);
> >  	struct pci_dev *pdev = dev_priv->drm.pdev;
> > +	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
> 
> const?

Somehow I had missed this email, sorry for the late response. I'll make
this change and post a quick update.

Thanks,
Stuart

> 
> >  	drm_i915_getparam_t *param = data;
> >  	int value;
> >  
> > @@ -374,12 +375,12 @@ static int i915_getparam_ioctl(struct
> > drm_device *dev, void *data,
> >  		value = i915_cmd_parser_get_version(dev_priv);
> >  		break;
> >  	case I915_PARAM_SUBSLICE_TOTAL:
> > -		value = sseu_subslice_total(&RUNTIME_INFO(dev_priv)-
> > >sseu);
> > +		value = sseu_subslice_total(sseu);
> >  		if (!value)
> >  			return -ENODEV;
> >  		break;
> >  	case I915_PARAM_EU_TOTAL:
> > -		value = RUNTIME_INFO(dev_priv)->sseu.eu_total;
> > +		value = sseu->eu_total;
> >  		if (!value)
> >  			return -ENODEV;
> >  		break;
> > @@ -396,7 +397,7 @@ static int i915_getparam_ioctl(struct
> > drm_device *dev, void *data,
> >  		value = HAS_POOLED_EU(dev_priv);
> >  		break;
> >  	case I915_PARAM_MIN_EU_IN_POOL:
> > -		value = RUNTIME_INFO(dev_priv)->sseu.min_eu_in_pool;
> > +		value = sseu->min_eu_in_pool;
> >  		break;
> >  	case I915_PARAM_HUC_STATUS:
> >  		value = intel_huc_check_status(&dev_priv->huc);
> > @@ -446,12 +447,12 @@ static int i915_getparam_ioctl(struct
> > drm_device *dev, void *data,
> >  		value = intel_engines_has_context_isolation(dev_priv);
> >  		break;
> >  	case I915_PARAM_SLICE_MASK:
> > -		value = RUNTIME_INFO(dev_priv)->sseu.slice_mask;
> > +		value = sseu->slice_mask;
> >  		if (!value)
> >  			return -ENODEV;
> >  		break;
> >  	case I915_PARAM_SUBSLICE_MASK:
> > -		value = RUNTIME_INFO(dev_priv)->sseu.subslice_mask[0];
> > +		value = sseu->subslice_mask[0];
> >  		if (!value)
> >  			return -ENODEV;
> >  		break;
> 
> 

[-- Attachment #1.2: smime.p7s --]
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[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

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[PATCH 2/5] drm/i915: Add macro for SSEU stride calculation

[Stuart Summers]

Subslice stride and EU stride are calculated multiple times in
i915_query. Move this calculation to a macro to reduce code duplication.

v2: update headers in intel_sseu.h

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_sseu.h |  2 ++
 drivers/gpu/drm/i915/i915_query.c    | 17 ++++++++---------
 2 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 73bc824094e8..c0b16b248d4c 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -8,11 +8,13 @@
 #define __INTEL_SSEU_H__
 
 #include <linux/types.h>
+#include <linux/kernel.h>
 
 struct drm_i915_private;
 
 #define GEN_MAX_SLICES		(6) /* CNL upper bound */
 #define GEN_MAX_SUBSLICES	(8) /* ICL upper bound */
+#define GEN_SSEU_STRIDE(bits) DIV_ROUND_UP(bits, BITS_PER_BYTE)
 
 struct sseu_dev_info {
 	u8 slice_mask;
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 782183b78f49..7c1708c22811 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -37,6 +37,8 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
 	const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
 	struct drm_i915_query_topology_info topo;
 	u32 slice_length, subslice_length, eu_length, total_length;
+	u8 subslice_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
+	u8 eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
 	int ret;
 
 	if (query_item->flags != 0)
@@ -48,12 +50,10 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
 	BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
 
 	slice_length = sizeof(sseu->slice_mask);
-	subslice_length = sseu->max_slices *
-		DIV_ROUND_UP(sseu->max_subslices, BITS_PER_BYTE);
-	eu_length = sseu->max_slices * sseu->max_subslices *
-		DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE);
-
-	total_length = sizeof(topo) + slice_length + subslice_length + eu_length;
+	subslice_length = sseu->max_slices * subslice_stride;
+	eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
+	total_length = sizeof(topo) + slice_length + subslice_length +
+		       eu_length;
 
 	ret = copy_query_item(&topo, sizeof(topo), total_length,
 			      query_item);
@@ -69,10 +69,9 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
 	topo.max_eus_per_subslice = sseu->max_eus_per_subslice;
 
 	topo.subslice_offset = slice_length;
-	topo.subslice_stride = DIV_ROUND_UP(sseu->max_subslices, BITS_PER_BYTE);
+	topo.subslice_stride = subslice_stride;
 	topo.eu_offset = slice_length + subslice_length;
-	topo.eu_stride =
-		DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE);
+	topo.eu_stride = eu_stride;
 
 	if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr),
 			   &topo, sizeof(topo)))
-- 
2.21.0.5.gaeb582a983

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[PATCH 3/5] drm/i915: Move calculation of subslices per slice to new function

[Stuart Summers]

Add a new function to return the number of subslices per slice to
consolidate code usage.

v2: rebase on changes to move sseu struct to intel_sseu.h

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_sseu.h     | 6 ++++++
 drivers/gpu/drm/i915/i915_debugfs.c      | 2 +-
 drivers/gpu/drm/i915/intel_device_info.c | 4 ++--
 3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index c0b16b248d4c..f5ff6b7a756a 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -63,6 +63,12 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
 	return value;
 }
 
+static inline unsigned int
+sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
+{
+	return hweight8(sseu->subslice_mask[slice]);
+}
+
 u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
 			 const struct intel_sseu *req_sseu);
 
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index ffbf5d920429..0ecf006d26b3 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4184,7 +4184,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
 		   sseu_subslice_total(sseu));
 	for (s = 0; s < fls(sseu->slice_mask); s++) {
 		seq_printf(m, "  %s Slice%i subslices: %u\n", type,
-			   s, hweight8(sseu->subslice_mask[s]));
+			   s, sseu_subslices_per_slice(sseu, s));
 	}
 	seq_printf(m, "  %s EU Total: %u\n", type,
 		   sseu->eu_total);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 6af480b95bc6..559cf0d0628e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -93,7 +93,7 @@ static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
 	drm_printf(p, "subslice total: %u\n", sseu_subslice_total(sseu));
 	for (s = 0; s < sseu->max_slices; s++) {
 		drm_printf(p, "slice%d: %u subslices, mask=%04x\n",
-			   s, hweight8(sseu->subslice_mask[s]),
+			   s, sseu_subslices_per_slice(sseu, s),
 			   sseu->subslice_mask[s]);
 	}
 	drm_printf(p, "EU total: %u\n", sseu->eu_total);
@@ -126,7 +126,7 @@ void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
 
 	for (s = 0; s < sseu->max_slices; s++) {
 		drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n",
-			   s, hweight8(sseu->subslice_mask[s]),
+			   s, sseu_subslices_per_slice(sseu, s),
 			   sseu->subslice_mask[s]);
 
 		for (ss = 0; ss < sseu->max_subslices; ss++) {
-- 
2.21.0.5.gaeb582a983

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[PATCH 4/5] drm/i915: Move sseu helper functions to intel_sseu.h

[Stuart Summers]

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_sseu.h     | 47 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_device_info.h | 47 ------------------------
 2 files changed, 47 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index f5ff6b7a756a..5127b4ff92bf 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -63,12 +63,59 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
 	return value;
 }
 
+static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
+{
+	unsigned int i, total = 0;
+
+	for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
+		total += hweight8(sseu->subslice_mask[i]);
+
+	return total;
+}
+
 static inline unsigned int
 sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
 {
 	return hweight8(sseu->subslice_mask[slice]);
 }
 
+static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
+			      int slice, int subslice)
+{
+	int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
+					   BITS_PER_BYTE);
+	int slice_stride = sseu->max_subslices * subslice_stride;
+
+	return slice * slice_stride + subslice * subslice_stride;
+}
+
+static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
+			       int slice, int subslice)
+{
+	int i, offset = sseu_eu_idx(sseu, slice, subslice);
+	u16 eu_mask = 0;
+
+	for (i = 0;
+	     i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
+		eu_mask |= ((u16) sseu->eu_mask[offset + i]) <<
+			(i * BITS_PER_BYTE);
+	}
+
+	return eu_mask;
+}
+
+static inline void sseu_set_eus(struct sseu_dev_info *sseu,
+				int slice, int subslice, u16 eu_mask)
+{
+	int i, offset = sseu_eu_idx(sseu, slice, subslice);
+
+	for (i = 0;
+	     i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
+		sseu->eu_mask[offset + i] =
+			(eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
+	}
+}
+
 u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
 			 const struct intel_sseu *req_sseu);
 
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 5a2e17d6146b..6412a9c72898 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -218,53 +218,6 @@ struct intel_driver_caps {
 	bool has_logical_contexts:1;
 };
 
-static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
-{
-	unsigned int i, total = 0;
-
-	for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
-		total += hweight8(sseu->subslice_mask[i]);
-
-	return total;
-}
-
-static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
-			      int slice, int subslice)
-{
-	int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
-					   BITS_PER_BYTE);
-	int slice_stride = sseu->max_subslices * subslice_stride;
-
-	return slice * slice_stride + subslice * subslice_stride;
-}
-
-static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
-			       int slice, int subslice)
-{
-	int i, offset = sseu_eu_idx(sseu, slice, subslice);
-	u16 eu_mask = 0;
-
-	for (i = 0;
-	     i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
-		eu_mask |= ((u16) sseu->eu_mask[offset + i]) <<
-			(i * BITS_PER_BYTE);
-	}
-
-	return eu_mask;
-}
-
-static inline void sseu_set_eus(struct sseu_dev_info *sseu,
-				int slice, int subslice, u16 eu_mask)
-{
-	int i, offset = sseu_eu_idx(sseu, slice, subslice);
-
-	for (i = 0;
-	     i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
-		sseu->eu_mask[offset + i] =
-			(eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
-	}
-}
-
 const char *intel_platform_name(enum intel_platform platform);
 
 void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
-- 
2.21.0.5.gaeb582a983

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Re: [PATCH 4/5] drm/i915: Move sseu helper functions to intel_sseu.h

[Jani Nikula]

On Mon, 29 Apr 2019, Stuart Summers <stuart.summers@intel.com> wrote:
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_sseu.h     | 47 ++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_device_info.h | 47 ------------------------
>  2 files changed, 47 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
> index f5ff6b7a756a..5127b4ff92bf 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> @@ -63,12 +63,59 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
>  	return value;
>  }
>  
> +static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
> +{
> +	unsigned int i, total = 0;
> +
> +	for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
> +		total += hweight8(sseu->subslice_mask[i]);
> +
> +	return total;
> +}
> +
>  static inline unsigned int
>  sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
>  {
>  	return hweight8(sseu->subslice_mask[slice]);
>  }
>  
> +static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
> +			      int slice, int subslice)
> +{
> +	int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
> +					   BITS_PER_BYTE);
> +	int slice_stride = sseu->max_subslices * subslice_stride;
> +
> +	return slice * slice_stride + subslice * subslice_stride;
> +}
> +
> +static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
> +			       int slice, int subslice)
> +{
> +	int i, offset = sseu_eu_idx(sseu, slice, subslice);
> +	u16 eu_mask = 0;
> +
> +	for (i = 0;
> +	     i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
> +		eu_mask |= ((u16) sseu->eu_mask[offset + i]) <<
> +			(i * BITS_PER_BYTE);
> +	}
> +
> +	return eu_mask;
> +}
> +
> +static inline void sseu_set_eus(struct sseu_dev_info *sseu,
> +				int slice, int subslice, u16 eu_mask)
> +{
> +	int i, offset = sseu_eu_idx(sseu, slice, subslice);
> +
> +	for (i = 0;
> +	     i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
> +		sseu->eu_mask[offset + i] =
> +			(eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
> +	}
> +}
> +

I'd appreciate follow-up to rename these functions
intel_sseu_*. Functions in intel_foo.[ch] should be named intel_foo_*().

Also, I'm starting to wonder the benefits of the plethora of inline
functions we use. Should we move them to the .c file? It can't be a perf
thing can it?

BR,
Jani.

>  u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
>  			 const struct intel_sseu *req_sseu);
>  
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 5a2e17d6146b..6412a9c72898 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -218,53 +218,6 @@ struct intel_driver_caps {
>  	bool has_logical_contexts:1;
>  };
>  
> -static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
> -{
> -	unsigned int i, total = 0;
> -
> -	for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
> -		total += hweight8(sseu->subslice_mask[i]);
> -
> -	return total;
> -}
> -
> -static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
> -			      int slice, int subslice)
> -{
> -	int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
> -					   BITS_PER_BYTE);
> -	int slice_stride = sseu->max_subslices * subslice_stride;
> -
> -	return slice * slice_stride + subslice * subslice_stride;
> -}
> -
> -static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
> -			       int slice, int subslice)
> -{
> -	int i, offset = sseu_eu_idx(sseu, slice, subslice);
> -	u16 eu_mask = 0;
> -
> -	for (i = 0;
> -	     i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
> -		eu_mask |= ((u16) sseu->eu_mask[offset + i]) <<
> -			(i * BITS_PER_BYTE);
> -	}
> -
> -	return eu_mask;
> -}
> -
> -static inline void sseu_set_eus(struct sseu_dev_info *sseu,
> -				int slice, int subslice, u16 eu_mask)
> -{
> -	int i, offset = sseu_eu_idx(sseu, slice, subslice);
> -
> -	for (i = 0;
> -	     i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
> -		sseu->eu_mask[offset + i] =
> -			(eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
> -	}
> -}
> -
>  const char *intel_platform_name(enum intel_platform platform);
>  
>  void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [PATCH 4/5] drm/i915: Move sseu helper functions to intel_sseu.h

[Summers, Stuart]

[-- Attachment #1.1: Type: text/plain, Size: 5223 bytes --]

On Tue, 2019-04-30 at 12:02 +0300, Jani Nikula wrote:
> On Mon, 29 Apr 2019, Stuart Summers <stuart.summers@intel.com> wrote:
> > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_sseu.h     | 47
> > ++++++++++++++++++++++++
> >  drivers/gpu/drm/i915/intel_device_info.h | 47 --------------------
> > ----
> >  2 files changed, 47 insertions(+), 47 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
> > b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > index f5ff6b7a756a..5127b4ff92bf 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > @@ -63,12 +63,59 @@ intel_sseu_from_device_info(const struct
> > sseu_dev_info *sseu)
> >  	return value;
> >  }
> >  
> > +static inline unsigned int sseu_subslice_total(const struct
> > sseu_dev_info *sseu)
> > +{
> > +	unsigned int i, total = 0;
> > +
> > +	for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
> > +		total += hweight8(sseu->subslice_mask[i]);
> > +
> > +	return total;
> > +}
> > +
> >  static inline unsigned int
> >  sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8
> > slice)
> >  {
> >  	return hweight8(sseu->subslice_mask[slice]);
> >  }
> >  
> > +static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
> > +			      int slice, int subslice)
> > +{
> > +	int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
> > +					   BITS_PER_BYTE);
> > +	int slice_stride = sseu->max_subslices * subslice_stride;
> > +
> > +	return slice * slice_stride + subslice * subslice_stride;
> > +}
> > +
> > +static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
> > +			       int slice, int subslice)
> > +{
> > +	int i, offset = sseu_eu_idx(sseu, slice, subslice);
> > +	u16 eu_mask = 0;
> > +
> > +	for (i = 0;
> > +	     i < DIV_ROUND_UP(sseu->max_eus_per_subslice,
> > BITS_PER_BYTE); i++) {
> > +		eu_mask |= ((u16) sseu->eu_mask[offset + i]) <<
> > +			(i * BITS_PER_BYTE);
> > +	}
> > +
> > +	return eu_mask;
> > +}
> > +
> > +static inline void sseu_set_eus(struct sseu_dev_info *sseu,
> > +				int slice, int subslice, u16 eu_mask)
> > +{
> > +	int i, offset = sseu_eu_idx(sseu, slice, subslice);
> > +
> > +	for (i = 0;
> > +	     i < DIV_ROUND_UP(sseu->max_eus_per_subslice,
> > BITS_PER_BYTE); i++) {an't be 
> > +		sseu->eu_mask[offset + i] =
> > +			(eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
> > +	}
> > +}
> > +
> 
> I'd appreciate follow-up to rename these functions
> intel_sseu_*. Functions in intel_foo.[ch] should be named
> intel_foo_*().

Makes sense.

> 
> Also, I'm starting to wonder the benefits of the plethora of inline
> functions we use. Should we move them to the .c file? It can't be a
> perf
> thing can it?

These are mostly called at driver load time, so no, shouldn't be a
performance issue. I don't have a preference either way, so no problem
moving these as suggested.

Thanks,
Stuart

> 
> BR,
> Jani.
> 
> >  u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
> >  			 const struct intel_sseu *req_sseu);
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> > b/drivers/gpu/drm/i915/intel_device_info.h
> > index 5a2e17d6146b..6412a9c72898 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -218,53 +218,6 @@ struct intel_driver_caps {
> >  	bool has_logical_contexts:1;
> >  };
> >  
> > -static inline unsigned int sseu_subslice_total(const struct
> > sseu_dev_info *sseu)
> > -{
> > -	unsigned int i, total = 0;
> > -
> > -	for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
> > -		total += hweight8(sseu->subslice_mask[i]);
> > -
> > -	return total;
> > -}
> > -
> > -static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
> > -			      int slice, int subslice)
> > -{
> > -	int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
> > -					   BITS_PER_BYTE);
> > -	int slice_stride = sseu->max_subslices * subslice_stride;
> > -
> > -	return slice * slice_stride + subslice * subslice_stride;
> > -}
> > -
> > -static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
> > -			       int slice, int subslice)
> > -{
> > -	int i, offset = sseu_eu_idx(sseu, slice, subslice);
> > -	u16 eu_mask = 0;
> > -
> > -	for (i = 0;
> > -	     i < DIV_ROUND_UP(sseu->max_eus_per_subslice,
> > BITS_PER_BYTE); i++) {
> > -		eu_mask |= ((u16) sseu->eu_mask[offset + i]) <<
> > -			(i * BITS_PER_BYTE);
> > -	}
> > -
> > -	return eu_mask;
> > -}
> > -
> > -static inline void sseu_set_eus(struct sseu_dev_info *sseu,
> > -				int slice, int subslice, u16 eu_mask)
> > -{
> > -	int i, offset = sseu_eu_idx(sseu, slice, subslice);
> > -
> > -	for (i = 0;
> > -	     i < DIV_ROUND_UP(sseu->max_eus_per_subslice,
> > BITS_PER_BYTE); i++) {
> > -		sseu->eu_mask[offset + i] =
> > -			(eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
> > -	}
> > -}
> > -
> >  const char *intel_platform_name(enum intel_platform platform);
> >  
> >  void intel_device_info_subplatform_init(struct drm_i915_private
> > *dev_priv);
> 
> 

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[PATCH 5/5] drm/i915: Expand subslice mask

[Stuart Summers]

Currently, the subslice_mask runtime parameter is stored as an
array of subslices per slice. Expand the subslice mask array to
better match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
  slice * subslice stride + subslice index / 8

v2: fix spacing in set_sseu_info args
    use set_sseu_info to initialize sseu data when building
    device status in debugfs
    rename variables in intel_engine_types.h to avoid checkpatch
    warnings
v3: update headers in intel_sseu.h

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c    |   6 +-
 drivers/gpu/drm/i915/gt/intel_engine_types.h |  32 +++--
 drivers/gpu/drm/i915/gt/intel_hangcheck.c    |   3 +-
 drivers/gpu/drm/i915/gt/intel_sseu.h         |  45 +++++-
 drivers/gpu/drm/i915/gt/intel_workarounds.c  |   2 +-
 drivers/gpu/drm/i915/i915_debugfs.c          |  43 +++---
 drivers/gpu/drm/i915/i915_drv.c              |   6 +-
 drivers/gpu/drm/i915/i915_gpu_error.c        |   5 +-
 drivers/gpu/drm/i915/i915_query.c            |  10 +-
 drivers/gpu/drm/i915/intel_device_info.c     | 139 +++++++++++--------
 10 files changed, 183 insertions(+), 108 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index f7308479d511..8922358ee6c6 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -908,7 +908,7 @@ u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
 	const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
 	u32 mcr_s_ss_select;
 	u32 slice = fls(sseu->slice_mask);
-	u32 subslice = fls(sseu->subslice_mask[slice]);
+	u32 subslice = fls(sseu->subslice_mask[slice * sseu->ss_stride]);
 
 	if (IS_GEN(dev_priv, 10))
 		mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
@@ -984,6 +984,7 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine,
 			       struct intel_instdone *instdone)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
+	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
 	struct intel_uncore *uncore = engine->uncore;
 	u32 mmio_base = engine->mmio_base;
 	int slice;
@@ -1001,7 +1002,8 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine,
 
 		instdone->slice_common =
 			intel_uncore_read(uncore, GEN7_SC_INSTDONE);
-		for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
+		for_each_instdone_slice_subslice(dev_priv, sseu, slice,
+						 subslice) {
 			instdone->sampler[slice][subslice] =
 				read_subslice_reg(dev_priv, slice, subslice,
 						  GEN7_SAMPLER_INSTDONE);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index d972c339309c..fa70528963a4 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -534,20 +534,22 @@ intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine)
 	return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
 }
 
-#define instdone_slice_mask(dev_priv__) \
-	(IS_GEN(dev_priv__, 7) ? \
-	 1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)
-
-#define instdone_subslice_mask(dev_priv__) \
-	(IS_GEN(dev_priv__, 7) ? \
-	 1 : RUNTIME_INFO(dev_priv__)->sseu.subslice_mask[0])
-
-#define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
-	for ((slice__) = 0, (subslice__) = 0; \
-	     (slice__) < I915_MAX_SLICES; \
-	     (subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ? (subslice__) + 1 : 0, \
-	       (slice__) += ((subslice__) == 0)) \
-		for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) && \
-			    (BIT(subslice__) & instdone_subslice_mask(dev_priv__)))
+#define instdone_has_slice(dev_priv___, sseu___, slice___) \
+	((IS_GEN(dev_priv___, 7) ? \
+	  1 : (sseu___)->slice_mask) & \
+	BIT(slice___)) \
+
+#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
+	((IS_GEN(dev_priv__, 7) ? \
+	  1 : (sseu__)->subslice_mask[slice__ * (sseu__)->ss_stride + \
+				      subslice__ / BITS_PER_BYTE]) & \
+	 BIT(subslice__ % BITS_PER_BYTE)) \
+
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+	for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+	     (subslice_) = ((subslice_) + 1) < I915_MAX_SUBSLICES ? (subslice_) + 1 : 0, \
+	       (slice_) += ((subslice_) == 0)) \
+		for_each_if(instdone_has_slice(dev_priv_, sseu_, slice) && \
+			    instdone_has_subslice(dev_priv_, sseu_, slice_, subslice_)) \
 
 #endif /* __INTEL_ENGINE_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_hangcheck.c b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
index e5eaa06fe74d..95dfce65c00c 100644
--- a/drivers/gpu/drm/i915/gt/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
@@ -50,6 +50,7 @@ static bool instdone_unchanged(u32 current_instdone, u32 *old_instdone)
 static bool subunits_stuck(struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
+	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
 	struct intel_instdone instdone;
 	struct intel_instdone *accu_instdone = &engine->hangcheck.instdone;
 	bool stuck;
@@ -71,7 +72,7 @@ static bool subunits_stuck(struct intel_engine_cs *engine)
 	stuck &= instdone_unchanged(instdone.slice_common,
 				    &accu_instdone->slice_common);
 
-	for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
+	for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice) {
 		stuck &= instdone_unchanged(instdone.sampler[slice][subslice],
 					    &accu_instdone->sampler[slice][subslice]);
 		stuck &= instdone_unchanged(instdone.row[slice][subslice],
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 5127b4ff92bf..34b461da6735 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -9,16 +9,18 @@
 
 #include <linux/types.h>
 #include <linux/kernel.h>
+#include <linux/string.h>
 
 struct drm_i915_private;
 
 #define GEN_MAX_SLICES		(6) /* CNL upper bound */
 #define GEN_MAX_SUBSLICES	(8) /* ICL upper bound */
 #define GEN_SSEU_STRIDE(bits) DIV_ROUND_UP(bits, BITS_PER_BYTE)
+#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
 
 struct sseu_dev_info {
 	u8 slice_mask;
-	u8 subslice_mask[GEN_MAX_SLICES];
+	u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
 	u16 eu_total;
 	u8 eu_per_subslice;
 	u8 min_eu_in_pool;
@@ -33,6 +35,9 @@ struct sseu_dev_info {
 	u8 max_subslices;
 	u8 max_eus_per_subslice;
 
+	u8 ss_stride;
+	u8 eu_stride;
+
 	/* We don't have more than 8 eus per subslice at the moment and as we
 	 * store eus enabled using bits, no need to multiply by eus per
 	 * subslice.
@@ -63,6 +68,17 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
 	return value;
 }
 
+static inline void set_sseu_info(struct sseu_dev_info *sseu, u8 max_slices,
+				 u8 max_subslices, u8 max_eus_per_subslice)
+{
+	sseu->max_slices = max_slices;
+	sseu->max_subslices = max_subslices;
+	sseu->max_eus_per_subslice = max_eus_per_subslice;
+
+	sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
+	sseu->eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
+}
+
 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
 {
 	unsigned int i, total = 0;
@@ -76,7 +92,32 @@ static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
 static inline unsigned int
 sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
 {
-	return hweight8(sseu->subslice_mask[slice]);
+	unsigned int i, total = 0;
+
+	for (i = 0; i < sseu->ss_stride; i++)
+		total += hweight8(sseu->subslice_mask[slice * sseu->ss_stride +
+						      i]);
+
+	return total;
+}
+
+static inline void sseu_copy_subslices(const struct sseu_dev_info *sseu,
+				       int slice, u8 *to_mask,
+				       const u8 *from_mask)
+{
+	int offset = slice * sseu->ss_stride;
+
+	memcpy(&to_mask[offset], &from_mask[offset], sseu->ss_stride);
+}
+
+static inline void sseu_set_subslices(struct sseu_dev_info *sseu,
+				      int slice, u32 ss_mask)
+{
+	int i, offset = slice * sseu->ss_stride;
+
+	for (i = 0; i < sseu->ss_stride; i++)
+		sseu->subslice_mask[offset + i] =
+			(ss_mask >> (BITS_PER_BYTE * i)) & 0xff;
 }
 
 static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 5751446a4b0b..51df88873ff5 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -771,7 +771,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
 		u32 slice = fls(sseu->slice_mask);
 		u32 fuse3 =
 			intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3);
-		u8 ss_mask = sseu->subslice_mask[slice];
+		u8 ss_mask = sseu->subslice_mask[slice * sseu->ss_stride];
 
 		u8 enabled_mask = (ss_mask | ss_mask >>
 				   GEN10_L3BANK_PAIR_COUNT) & GEN10_L3BANK_MASK;
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 0ecf006d26b3..4f8d4370912f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1256,6 +1256,7 @@ static void i915_instdone_info(struct drm_i915_private *dev_priv,
 			       struct seq_file *m,
 			       struct intel_instdone *instdone)
 {
+	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
 	int slice;
 	int subslice;
 
@@ -1271,11 +1272,11 @@ static void i915_instdone_info(struct drm_i915_private *dev_priv,
 	if (INTEL_GEN(dev_priv) <= 6)
 		return;
 
-	for_each_instdone_slice_subslice(dev_priv, slice, subslice)
+	for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice)
 		seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
 			   slice, subslice, instdone->sampler[slice][subslice]);
 
-	for_each_instdone_slice_subslice(dev_priv, slice, subslice)
+	for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice)
 		seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
 			   slice, subslice, instdone->row[slice][subslice]);
 }
@@ -4065,7 +4066,9 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
 			continue;
 
 		sseu->slice_mask |= BIT(s);
-		sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
+		sseu_copy_subslices(&info->sseu, s,
+				    sseu->subslice_mask,
+				    info->sseu.subslice_mask);
 
 		for (ss = 0; ss < info->sseu.max_subslices; ss++) {
 			unsigned int eu_cnt;
@@ -4116,18 +4119,22 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
 		sseu->slice_mask |= BIT(s);
 
 		if (IS_GEN9_BC(dev_priv))
-			sseu->subslice_mask[s] =
-				RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s];
+			sseu_copy_subslices(&info->sseu, s,
+					    sseu->subslice_mask,
+					    info->sseu.subslice_mask);
 
 		for (ss = 0; ss < info->sseu.max_subslices; ss++) {
 			unsigned int eu_cnt;
+			u8 ss_idx = s * info->sseu.ss_stride +
+				    ss / BITS_PER_BYTE;
 
 			if (IS_GEN9_LP(dev_priv)) {
 				if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
 					/* skip disabled subslice */
 					continue;
 
-				sseu->subslice_mask[s] |= BIT(ss);
+				sseu->subslice_mask[ss_idx] |=
+					BIT(ss % BITS_PER_BYTE);
 			}
 
 			eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
@@ -4144,25 +4151,24 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
 static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
 					 struct sseu_dev_info *sseu)
 {
+	struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
 	u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
 	int s;
 
 	sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
 
 	if (sseu->slice_mask) {
-		sseu->eu_per_subslice =
-			RUNTIME_INFO(dev_priv)->sseu.eu_per_subslice;
-		for (s = 0; s < fls(sseu->slice_mask); s++) {
-			sseu->subslice_mask[s] =
-				RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s];
-		}
+		sseu->eu_per_subslice = info->sseu.eu_per_subslice;
+		for (s = 0; s < fls(sseu->slice_mask); s++)
+			sseu_copy_subslices(&info->sseu, s,
+					    sseu->subslice_mask,
+					    info->sseu.subslice_mask);
 		sseu->eu_total = sseu->eu_per_subslice *
 				 sseu_subslice_total(sseu);
 
 		/* subtract fused off EU(s) from enabled slice(s) */
 		for (s = 0; s < fls(sseu->slice_mask); s++) {
-			u8 subslice_7eu =
-				RUNTIME_INFO(dev_priv)->sseu.subslice_7eu[s];
+			u8 subslice_7eu = info->sseu.subslice_7eu[s];
 
 			sseu->eu_total -= hweight8(subslice_7eu);
 		}
@@ -4209,6 +4215,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
 static int i915_sseu_status(struct seq_file *m, void *unused)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
+	const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
 	struct sseu_dev_info sseu;
 	intel_wakeref_t wakeref;
 
@@ -4216,14 +4223,12 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
 		return -ENODEV;
 
 	seq_puts(m, "SSEU Device Info\n");
-	i915_print_sseu_info(m, true, &RUNTIME_INFO(dev_priv)->sseu);
+	i915_print_sseu_info(m, true, &info->sseu);
 
 	seq_puts(m, "SSEU Device Status\n");
 	memset(&sseu, 0, sizeof(sseu));
-	sseu.max_slices = RUNTIME_INFO(dev_priv)->sseu.max_slices;
-	sseu.max_subslices = RUNTIME_INFO(dev_priv)->sseu.max_subslices;
-	sseu.max_eus_per_subslice =
-		RUNTIME_INFO(dev_priv)->sseu.max_eus_per_subslice;
+	set_sseu_info(&sseu, info->sseu.max_slices, info->sseu.max_subslices,
+		      info->sseu.max_eus_per_subslice);
 
 	with_intel_runtime_pm(dev_priv, wakeref) {
 		if (IS_CHERRYVIEW(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b6ce7580d414..7a95c262aa14 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -323,7 +323,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 	struct pci_dev *pdev = dev_priv->drm.pdev;
 	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
 	drm_i915_getparam_t *param = data;
-	int value;
+	int value = 0;
 
 	switch (param->param) {
 	case I915_PARAM_IRQ_ACTIVE:
@@ -452,7 +452,9 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 			return -ENODEV;
 		break;
 	case I915_PARAM_SUBSLICE_MASK:
-		value = sseu->subslice_mask[0];
+		/* Only copy bits from the first subslice */
+		memcpy(&value, sseu->subslice_mask,
+		       min(sseu->ss_stride, (u8)sizeof(value)));
 		if (!value)
 			return -ENODEV;
 		break;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index f51ff683dd2e..9da4118ad43a 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -405,6 +405,7 @@ static void print_error_buffers(struct drm_i915_error_state_buf *m,
 static void error_print_instdone(struct drm_i915_error_state_buf *m,
 				 const struct drm_i915_error_engine *ee)
 {
+	struct sseu_dev_info *sseu = &RUNTIME_INFO(m->i915)->sseu;
 	int slice;
 	int subslice;
 
@@ -420,12 +421,12 @@ static void error_print_instdone(struct drm_i915_error_state_buf *m,
 	if (INTEL_GEN(m->i915) <= 6)
 		return;
 
-	for_each_instdone_slice_subslice(m->i915, slice, subslice)
+	for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
 		err_printf(m, "  SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
 			   slice, subslice,
 			   ee->instdone.sampler[slice][subslice]);
 
-	for_each_instdone_slice_subslice(m->i915, slice, subslice)
+	for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
 		err_printf(m, "  ROW_INSTDONE[%d][%d]: 0x%08x\n",
 			   slice, subslice,
 			   ee->instdone.row[slice][subslice]);
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 7c1708c22811..000dcb145ce0 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -37,8 +37,6 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
 	const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
 	struct drm_i915_query_topology_info topo;
 	u32 slice_length, subslice_length, eu_length, total_length;
-	u8 subslice_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
-	u8 eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
 	int ret;
 
 	if (query_item->flags != 0)
@@ -50,8 +48,8 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
 	BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
 
 	slice_length = sizeof(sseu->slice_mask);
-	subslice_length = sseu->max_slices * subslice_stride;
-	eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
+	subslice_length = sseu->max_slices * sseu->ss_stride;
+	eu_length = sseu->max_slices * sseu->max_subslices * sseu->eu_stride;
 	total_length = sizeof(topo) + slice_length + subslice_length +
 		       eu_length;
 
@@ -69,9 +67,9 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
 	topo.max_eus_per_subslice = sseu->max_eus_per_subslice;
 
 	topo.subslice_offset = slice_length;
-	topo.subslice_stride = subslice_stride;
+	topo.subslice_stride = sseu->ss_stride;
 	topo.eu_offset = slice_length + subslice_length;
-	topo.eu_stride = eu_stride;
+	topo.eu_stride = sseu->eu_stride;
 
 	if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr),
 			   &topo, sizeof(topo)))
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 559cf0d0628e..1cc72beb86ee 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -84,17 +84,42 @@ void intel_device_info_dump_flags(const struct intel_device_info *info,
 #undef PRINT_FLAG
 }
 
+#define SS_STR_MAX_SIZE (GEN_MAX_SUBSLICE_STRIDE * 2)
+
+static u8 *
+subslice_per_slice_str(u8 *buf, const struct sseu_dev_info *sseu, u8 slice)
+{
+	int i;
+	u8 ss_offset = slice * sseu->ss_stride;
+
+	GEM_BUG_ON(slice >= sseu->max_slices);
+
+	memset(buf, 0, SS_STR_MAX_SIZE);
+
+	/*
+	 * Print subslice information in reverse order to match
+	 * userspace expectations.
+	 */
+	for (i = 0; i < sseu->ss_stride; i++)
+		sprintf(&buf[i * 2], "%02x",
+			sseu->subslice_mask[ss_offset + sseu->ss_stride -
+					    (i + 1)]);
+
+	return buf;
+}
+
 static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
 {
 	int s;
+	u8 buf[SS_STR_MAX_SIZE];
 
 	drm_printf(p, "slice total: %u, mask=%04x\n",
 		   hweight8(sseu->slice_mask), sseu->slice_mask);
 	drm_printf(p, "subslice total: %u\n", sseu_subslice_total(sseu));
 	for (s = 0; s < sseu->max_slices; s++) {
-		drm_printf(p, "slice%d: %u subslices, mask=%04x\n",
+		drm_printf(p, "slice%d: %u subslices, mask=%s\n",
 			   s, sseu_subslices_per_slice(sseu, s),
-			   sseu->subslice_mask[s]);
+			   subslice_per_slice_str(buf, sseu, s));
 	}
 	drm_printf(p, "EU total: %u\n", sseu->eu_total);
 	drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
@@ -118,6 +143,7 @@ void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
 				     struct drm_printer *p)
 {
 	int s, ss;
+	u8 buf[SS_STR_MAX_SIZE];
 
 	if (sseu->max_slices == 0) {
 		drm_printf(p, "Unavailable\n");
@@ -125,9 +151,9 @@ void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
 	}
 
 	for (s = 0; s < sseu->max_slices; s++) {
-		drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n",
+		drm_printf(p, "slice%d: %u subslice(s) (0x%s):\n",
 			   s, sseu_subslices_per_slice(sseu, s),
-			   sseu->subslice_mask[s]);
+			   subslice_per_slice_str(buf, sseu, s));
 
 		for (ss = 0; ss < sseu->max_subslices; ss++) {
 			u16 enabled_eus = sseu_get_eus(sseu, s, ss);
@@ -156,15 +182,10 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
 	u8 eu_en;
 	int s;
 
-	if (IS_ELKHARTLAKE(dev_priv)) {
-		sseu->max_slices = 1;
-		sseu->max_subslices = 4;
-		sseu->max_eus_per_subslice = 8;
-	} else {
-		sseu->max_slices = 1;
-		sseu->max_subslices = 8;
-		sseu->max_eus_per_subslice = 8;
-	}
+	if (IS_ELKHARTLAKE(dev_priv))
+		set_sseu_info(sseu, 1, 4, 8);
+	else
+		set_sseu_info(sseu, 1, 8, 8);
 
 	s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
 	ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
@@ -177,9 +198,11 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
 			int ss;
 
 			sseu->slice_mask |= BIT(s);
-			sseu->subslice_mask[s] = (ss_en >> ss_idx) & ss_en_mask;
+			sseu->subslice_mask[s * sseu->ss_stride] =
+				(ss_en >> ss_idx) & ss_en_mask;
 			for (ss = 0; ss < sseu->max_subslices; ss++) {
-				if (sseu->subslice_mask[s] & BIT(ss))
+				if (sseu->subslice_mask[s * sseu->ss_stride] &
+				    BIT(ss))
 					sseu_set_eus(sseu, s, ss, eu_en);
 			}
 		}
@@ -201,23 +224,10 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
 	const int eu_mask = 0xff;
 	u32 subslice_mask, eu_en;
 
+	set_sseu_info(sseu, 6, 4, 8);
+
 	sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
 			    GEN10_F2_S_ENA_SHIFT;
-	sseu->max_slices = 6;
-	sseu->max_subslices = 4;
-	sseu->max_eus_per_subslice = 8;
-
-	subslice_mask = (1 << 4) - 1;
-	subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
-			   GEN10_F2_SS_DIS_SHIFT);
-
-	/*
-	 * Slice0 can have up to 3 subslices, but there are only 2 in
-	 * slice1/2.
-	 */
-	sseu->subslice_mask[0] = subslice_mask;
-	for (s = 1; s < sseu->max_slices; s++)
-		sseu->subslice_mask[s] = subslice_mask & 0x3;
 
 	/* Slice0 */
 	eu_en = ~I915_READ(GEN8_EU_DISABLE0);
@@ -242,14 +252,22 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
 	eu_en = ~I915_READ(GEN10_EU_DISABLE3);
 	sseu_set_eus(sseu, 5, 1, eu_en & eu_mask);
 
-	/* Do a second pass where we mark the subslices disabled if all their
-	 * eus are off.
-	 */
+	subslice_mask = (1 << 4) - 1;
+	subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
+			   GEN10_F2_SS_DIS_SHIFT);
+
 	for (s = 0; s < sseu->max_slices; s++) {
 		for (ss = 0; ss < sseu->max_subslices; ss++) {
 			if (sseu_get_eus(sseu, s, ss) == 0)
-				sseu->subslice_mask[s] &= ~BIT(ss);
+				subslice_mask &= ~BIT(ss);
 		}
+
+		/*
+		 * Slice0 can have up to 3 subslices, but there are only 2 in
+		 * slice1/2.
+		 */
+		sseu_set_subslices(sseu, s, s == 0 ? subslice_mask :
+						     subslice_mask & 0x3);
 	}
 
 	sseu->eu_total = compute_eu_total(sseu);
@@ -274,13 +292,12 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
 {
 	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
 	u32 fuse;
+	u8 subslice_mask;
 
 	fuse = I915_READ(CHV_FUSE_GT);
 
 	sseu->slice_mask = BIT(0);
-	sseu->max_slices = 1;
-	sseu->max_subslices = 2;
-	sseu->max_eus_per_subslice = 8;
+	set_sseu_info(sseu, 1, 2, 8);
 
 	if (!(fuse & CHV_FGT_DISABLE_SS0)) {
 		u8 disabled_mask =
@@ -289,7 +306,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
 			(((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
 			  CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
 
-		sseu->subslice_mask[0] |= BIT(0);
+		subslice_mask |= BIT(0);
 		sseu_set_eus(sseu, 0, 0, ~disabled_mask);
 	}
 
@@ -300,10 +317,12 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
 			(((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
 			  CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
 
-		sseu->subslice_mask[0] |= BIT(1);
+		subslice_mask |= BIT(1);
 		sseu_set_eus(sseu, 0, 1, ~disabled_mask);
 	}
 
+	sseu_set_subslices(sseu, 0, subslice_mask);
+
 	sseu->eu_total = compute_eu_total(sseu);
 
 	/*
@@ -335,9 +354,8 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
 	sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
 
 	/* BXT has a single slice and at most 3 subslices. */
-	sseu->max_slices = IS_GEN9_LP(dev_priv) ? 1 : 3;
-	sseu->max_subslices = IS_GEN9_LP(dev_priv) ? 3 : 4;
-	sseu->max_eus_per_subslice = 8;
+	set_sseu_info(sseu, IS_GEN9_LP(dev_priv) ? 1 : 3,
+		      IS_GEN9_LP(dev_priv) ? 3 : 4, 8);
 
 	/*
 	 * The subslice disable field is global, i.e. it applies
@@ -356,14 +374,16 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
 			/* skip disabled slice */
 			continue;
 
-		sseu->subslice_mask[s] = subslice_mask;
+		sseu_set_subslices(sseu, s, subslice_mask);
 
 		eu_disable = I915_READ(GEN9_EU_DISABLE(s));
 		for (ss = 0; ss < sseu->max_subslices; ss++) {
 			int eu_per_ss;
 			u8 eu_disabled_mask;
+			u8 ss_idx = s * sseu->ss_stride + ss / BITS_PER_BYTE;
 
-			if (!(sseu->subslice_mask[s] & BIT(ss)))
+			if (!(sseu->subslice_mask[ss_idx] &
+			      BIT(ss % BITS_PER_BYTE)))
 				/* skip disabled subslice */
 				continue;
 
@@ -435,9 +455,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
 
 	fuse2 = I915_READ(GEN8_FUSE2);
 	sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
-	sseu->max_slices = 3;
-	sseu->max_subslices = 3;
-	sseu->max_eus_per_subslice = 8;
+	set_sseu_info(sseu, 3, 3, 8);
 
 	/*
 	 * The subslice disable field is global, i.e. it applies
@@ -464,18 +482,21 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
 			/* skip disabled slice */
 			continue;
 
-		sseu->subslice_mask[s] = subslice_mask;
+		sseu_set_subslices(sseu, s, subslice_mask);
 
 		for (ss = 0; ss < sseu->max_subslices; ss++) {
 			u8 eu_disabled_mask;
+			u8 ss_idx = s * sseu->ss_stride + ss / BITS_PER_BYTE;
 			u32 n_disabled;
 
-			if (!(sseu->subslice_mask[s] & BIT(ss)))
+			if (!(sseu->subslice_mask[ss_idx] &
+			      BIT(ss % BITS_PER_BYTE)))
 				/* skip disabled subslice */
 				continue;
 
 			eu_disabled_mask =
-				eu_disable[s] >> (ss * sseu->max_eus_per_subslice);
+				eu_disable[s] >>
+					(ss * sseu->max_eus_per_subslice);
 
 			sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
 
@@ -514,6 +535,7 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
 	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
 	u32 fuse1;
 	int s, ss;
+	u32 subslice_mask;
 
 	/*
 	 * There isn't a register to tell us how many slices/subslices. We
@@ -525,22 +547,18 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
 		/* fall through */
 	case 1:
 		sseu->slice_mask = BIT(0);
-		sseu->subslice_mask[0] = BIT(0);
+		subslice_mask = BIT(0);
 		break;
 	case 2:
 		sseu->slice_mask = BIT(0);
-		sseu->subslice_mask[0] = BIT(0) | BIT(1);
+		subslice_mask = BIT(0) | BIT(1);
 		break;
 	case 3:
 		sseu->slice_mask = BIT(0) | BIT(1);
-		sseu->subslice_mask[0] = BIT(0) | BIT(1);
-		sseu->subslice_mask[1] = BIT(0) | BIT(1);
+		subslice_mask = BIT(0) | BIT(1);
 		break;
 	}
 
-	sseu->max_slices = hweight8(sseu->slice_mask);
-	sseu->max_subslices = hweight8(sseu->subslice_mask[0]);
-
 	fuse1 = I915_READ(HSW_PAVP_FUSE1);
 	switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) {
 	default:
@@ -557,9 +575,14 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
 		sseu->eu_per_subslice = 6;
 		break;
 	}
-	sseu->max_eus_per_subslice = sseu->eu_per_subslice;
+
+	set_sseu_info(sseu, hweight8(sseu->slice_mask),
+		      hweight8(subslice_mask),
+		      sseu->eu_per_subslice);
 
 	for (s = 0; s < sseu->max_slices; s++) {
+		sseu_set_subslices(sseu, s, subslice_mask);
+
 		for (ss = 0; ss < sseu->max_subslices; ss++) {
 			sseu_set_eus(sseu, s, ss,
 				     (1UL << sseu->eu_per_subslice) - 1);
-- 
2.21.0.5.gaeb582a983

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 5/5] drm/i915: Expand subslice mask

[Jani Nikula]

On Mon, 29 Apr 2019, Stuart Summers <stuart.summers@intel.com> wrote:
> Currently, the subslice_mask runtime parameter is stored as an
> array of subslices per slice. Expand the subslice mask array to
> better match what is presented to userspace through the
> I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
> then calculated:
>   slice * subslice stride + subslice index / 8
>
> v2: fix spacing in set_sseu_info args
>     use set_sseu_info to initialize sseu data when building
>     device status in debugfs
>     rename variables in intel_engine_types.h to avoid checkpatch
>     warnings
> v3: update headers in intel_sseu.h
>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_engine_cs.c    |   6 +-
>  drivers/gpu/drm/i915/gt/intel_engine_types.h |  32 +++--
>  drivers/gpu/drm/i915/gt/intel_hangcheck.c    |   3 +-
>  drivers/gpu/drm/i915/gt/intel_sseu.h         |  45 +++++-
>  drivers/gpu/drm/i915/gt/intel_workarounds.c  |   2 +-
>  drivers/gpu/drm/i915/i915_debugfs.c          |  43 +++---
>  drivers/gpu/drm/i915/i915_drv.c              |   6 +-
>  drivers/gpu/drm/i915/i915_gpu_error.c        |   5 +-
>  drivers/gpu/drm/i915/i915_query.c            |  10 +-
>  drivers/gpu/drm/i915/intel_device_info.c     | 139 +++++++++++--------
>  10 files changed, 183 insertions(+), 108 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index f7308479d511..8922358ee6c6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -908,7 +908,7 @@ u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
>  	const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
>  	u32 mcr_s_ss_select;
>  	u32 slice = fls(sseu->slice_mask);
> -	u32 subslice = fls(sseu->subslice_mask[slice]);
> +	u32 subslice = fls(sseu->subslice_mask[slice * sseu->ss_stride]);
>  
>  	if (IS_GEN(dev_priv, 10))
>  		mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
> @@ -984,6 +984,7 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine,
>  			       struct intel_instdone *instdone)
>  {
>  	struct drm_i915_private *dev_priv = engine->i915;
> +	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;

const?

>  	struct intel_uncore *uncore = engine->uncore;
>  	u32 mmio_base = engine->mmio_base;
>  	int slice;
> @@ -1001,7 +1002,8 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine,
>  
>  		instdone->slice_common =
>  			intel_uncore_read(uncore, GEN7_SC_INSTDONE);
> -		for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
> +		for_each_instdone_slice_subslice(dev_priv, sseu, slice,
> +						 subslice) {
>  			instdone->sampler[slice][subslice] =
>  				read_subslice_reg(dev_priv, slice, subslice,
>  						  GEN7_SAMPLER_INSTDONE);
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index d972c339309c..fa70528963a4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -534,20 +534,22 @@ intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine)
>  	return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
>  }
>  
> -#define instdone_slice_mask(dev_priv__) \
> -	(IS_GEN(dev_priv__, 7) ? \
> -	 1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)
> -
> -#define instdone_subslice_mask(dev_priv__) \
> -	(IS_GEN(dev_priv__, 7) ? \
> -	 1 : RUNTIME_INFO(dev_priv__)->sseu.subslice_mask[0])
> -
> -#define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
> -	for ((slice__) = 0, (subslice__) = 0; \
> -	     (slice__) < I915_MAX_SLICES; \
> -	     (subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ? (subslice__) + 1 : 0, \
> -	       (slice__) += ((subslice__) == 0)) \
> -		for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) && \
> -			    (BIT(subslice__) & instdone_subslice_mask(dev_priv__)))
> +#define instdone_has_slice(dev_priv___, sseu___, slice___) \
> +	((IS_GEN(dev_priv___, 7) ? \
> +	  1 : (sseu___)->slice_mask) & \
> +	BIT(slice___)) \
> +
> +#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
> +	((IS_GEN(dev_priv__, 7) ? \
> +	  1 : (sseu__)->subslice_mask[slice__ * (sseu__)->ss_stride + \
> +				      subslice__ / BITS_PER_BYTE]) & \
> +	 BIT(subslice__ % BITS_PER_BYTE)) \
> +
> +#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
> +	for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
> +	     (subslice_) = ((subslice_) + 1) < I915_MAX_SUBSLICES ? (subslice_) + 1 : 0, \
> +	       (slice_) += ((subslice_) == 0)) \
> +		for_each_if(instdone_has_slice(dev_priv_, sseu_, slice) && \
> +			    instdone_has_subslice(dev_priv_, sseu_, slice_, subslice_)) \
>  
>  #endif /* __INTEL_ENGINE_TYPES_H__ */
> diff --git a/drivers/gpu/drm/i915/gt/intel_hangcheck.c b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
> index e5eaa06fe74d..95dfce65c00c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_hangcheck.c
> +++ b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
> @@ -50,6 +50,7 @@ static bool instdone_unchanged(u32 current_instdone, u32 *old_instdone)
>  static bool subunits_stuck(struct intel_engine_cs *engine)
>  {
>  	struct drm_i915_private *dev_priv = engine->i915;
> +	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;

const?

>  	struct intel_instdone instdone;
>  	struct intel_instdone *accu_instdone = &engine->hangcheck.instdone;
>  	bool stuck;
> @@ -71,7 +72,7 @@ static bool subunits_stuck(struct intel_engine_cs *engine)
>  	stuck &= instdone_unchanged(instdone.slice_common,
>  				    &accu_instdone->slice_common);
>  
> -	for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
> +	for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice) {
>  		stuck &= instdone_unchanged(instdone.sampler[slice][subslice],
>  					    &accu_instdone->sampler[slice][subslice]);
>  		stuck &= instdone_unchanged(instdone.row[slice][subslice],
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
> index 5127b4ff92bf..34b461da6735 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> @@ -9,16 +9,18 @@
>  
>  #include <linux/types.h>
>  #include <linux/kernel.h>
> +#include <linux/string.h>
>  
>  struct drm_i915_private;
>  
>  #define GEN_MAX_SLICES		(6) /* CNL upper bound */
>  #define GEN_MAX_SUBSLICES	(8) /* ICL upper bound */
>  #define GEN_SSEU_STRIDE(bits) DIV_ROUND_UP(bits, BITS_PER_BYTE)
> +#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
>  
>  struct sseu_dev_info {
>  	u8 slice_mask;
> -	u8 subslice_mask[GEN_MAX_SLICES];
> +	u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
>  	u16 eu_total;
>  	u8 eu_per_subslice;
>  	u8 min_eu_in_pool;
> @@ -33,6 +35,9 @@ struct sseu_dev_info {
>  	u8 max_subslices;
>  	u8 max_eus_per_subslice;
>  
> +	u8 ss_stride;
> +	u8 eu_stride;
> +
>  	/* We don't have more than 8 eus per subslice at the moment and as we
>  	 * store eus enabled using bits, no need to multiply by eus per
>  	 * subslice.
> @@ -63,6 +68,17 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
>  	return value;
>  }
>  
> +static inline void set_sseu_info(struct sseu_dev_info *sseu, u8 max_slices,
> +				 u8 max_subslices, u8 max_eus_per_subslice)
> +{
> +	sseu->max_slices = max_slices;
> +	sseu->max_subslices = max_subslices;
> +	sseu->max_eus_per_subslice = max_eus_per_subslice;
> +
> +	sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
> +	sseu->eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
> +}
> +
>  static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
>  {
>  	unsigned int i, total = 0;
> @@ -76,7 +92,32 @@ static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
>  static inline unsigned int
>  sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
>  {
> -	return hweight8(sseu->subslice_mask[slice]);
> +	unsigned int i, total = 0;
> +
> +	for (i = 0; i < sseu->ss_stride; i++)
> +		total += hweight8(sseu->subslice_mask[slice * sseu->ss_stride +
> +						      i]);
> +
> +	return total;
> +}
> +
> +static inline void sseu_copy_subslices(const struct sseu_dev_info *sseu,
> +				       int slice, u8 *to_mask,
> +				       const u8 *from_mask)
> +{
> +	int offset = slice * sseu->ss_stride;
> +
> +	memcpy(&to_mask[offset], &from_mask[offset], sseu->ss_stride);
> +}
> +
> +static inline void sseu_set_subslices(struct sseu_dev_info *sseu,
> +				      int slice, u32 ss_mask)
> +{
> +	int i, offset = slice * sseu->ss_stride;
> +
> +	for (i = 0; i < sseu->ss_stride; i++)
> +		sseu->subslice_mask[offset + i] =
> +			(ss_mask >> (BITS_PER_BYTE * i)) & 0xff;
>  }
>  
>  static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 5751446a4b0b..51df88873ff5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -771,7 +771,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
>  		u32 slice = fls(sseu->slice_mask);
>  		u32 fuse3 =
>  			intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3);
> -		u8 ss_mask = sseu->subslice_mask[slice];
> +		u8 ss_mask = sseu->subslice_mask[slice * sseu->ss_stride];
>  
>  		u8 enabled_mask = (ss_mask | ss_mask >>
>  				   GEN10_L3BANK_PAIR_COUNT) & GEN10_L3BANK_MASK;
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 0ecf006d26b3..4f8d4370912f 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1256,6 +1256,7 @@ static void i915_instdone_info(struct drm_i915_private *dev_priv,
>  			       struct seq_file *m,
>  			       struct intel_instdone *instdone)
>  {
> +	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
>  	int slice;
>  	int subslice;
>  
> @@ -1271,11 +1272,11 @@ static void i915_instdone_info(struct drm_i915_private *dev_priv,
>  	if (INTEL_GEN(dev_priv) <= 6)
>  		return;
>  
> -	for_each_instdone_slice_subslice(dev_priv, slice, subslice)
> +	for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice)
>  		seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
>  			   slice, subslice, instdone->sampler[slice][subslice]);
>  
> -	for_each_instdone_slice_subslice(dev_priv, slice, subslice)
> +	for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice)
>  		seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
>  			   slice, subslice, instdone->row[slice][subslice]);
>  }
> @@ -4065,7 +4066,9 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
>  			continue;
>  
>  		sseu->slice_mask |= BIT(s);
> -		sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
> +		sseu_copy_subslices(&info->sseu, s,
> +				    sseu->subslice_mask,
> +				    info->sseu.subslice_mask);
>  
>  		for (ss = 0; ss < info->sseu.max_subslices; ss++) {
>  			unsigned int eu_cnt;
> @@ -4116,18 +4119,22 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
>  		sseu->slice_mask |= BIT(s);
>  
>  		if (IS_GEN9_BC(dev_priv))
> -			sseu->subslice_mask[s] =
> -				RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s];
> +			sseu_copy_subslices(&info->sseu, s,
> +					    sseu->subslice_mask,
> +					    info->sseu.subslice_mask);
>  
>  		for (ss = 0; ss < info->sseu.max_subslices; ss++) {
>  			unsigned int eu_cnt;
> +			u8 ss_idx = s * info->sseu.ss_stride +
> +				    ss / BITS_PER_BYTE;
>  
>  			if (IS_GEN9_LP(dev_priv)) {
>  				if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
>  					/* skip disabled subslice */
>  					continue;
>  
> -				sseu->subslice_mask[s] |= BIT(ss);
> +				sseu->subslice_mask[ss_idx] |=
> +					BIT(ss % BITS_PER_BYTE);
>  			}
>  
>  			eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
> @@ -4144,25 +4151,24 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
>  static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
>  					 struct sseu_dev_info *sseu)
>  {
> +	struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
>  	u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
>  	int s;
>  
>  	sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
>  
>  	if (sseu->slice_mask) {
> -		sseu->eu_per_subslice =
> -			RUNTIME_INFO(dev_priv)->sseu.eu_per_subslice;
> -		for (s = 0; s < fls(sseu->slice_mask); s++) {
> -			sseu->subslice_mask[s] =
> -				RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s];
> -		}
> +		sseu->eu_per_subslice = info->sseu.eu_per_subslice;
> +		for (s = 0; s < fls(sseu->slice_mask); s++)
> +			sseu_copy_subslices(&info->sseu, s,
> +					    sseu->subslice_mask,
> +					    info->sseu.subslice_mask);
>  		sseu->eu_total = sseu->eu_per_subslice *
>  				 sseu_subslice_total(sseu);
>  
>  		/* subtract fused off EU(s) from enabled slice(s) */
>  		for (s = 0; s < fls(sseu->slice_mask); s++) {
> -			u8 subslice_7eu =
> -				RUNTIME_INFO(dev_priv)->sseu.subslice_7eu[s];
> +			u8 subslice_7eu = info->sseu.subslice_7eu[s];
>  
>  			sseu->eu_total -= hweight8(subslice_7eu);
>  		}
> @@ -4209,6 +4215,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
>  static int i915_sseu_status(struct seq_file *m, void *unused)
>  {
>  	struct drm_i915_private *dev_priv = node_to_i915(m->private);
> +	const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
>  	struct sseu_dev_info sseu;
>  	intel_wakeref_t wakeref;
>  
> @@ -4216,14 +4223,12 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
>  		return -ENODEV;
>  
>  	seq_puts(m, "SSEU Device Info\n");
> -	i915_print_sseu_info(m, true, &RUNTIME_INFO(dev_priv)->sseu);
> +	i915_print_sseu_info(m, true, &info->sseu);
>  
>  	seq_puts(m, "SSEU Device Status\n");
>  	memset(&sseu, 0, sizeof(sseu));
> -	sseu.max_slices = RUNTIME_INFO(dev_priv)->sseu.max_slices;
> -	sseu.max_subslices = RUNTIME_INFO(dev_priv)->sseu.max_subslices;
> -	sseu.max_eus_per_subslice =
> -		RUNTIME_INFO(dev_priv)->sseu.max_eus_per_subslice;
> +	set_sseu_info(&sseu, info->sseu.max_slices, info->sseu.max_subslices,
> +		      info->sseu.max_eus_per_subslice);
>  
>  	with_intel_runtime_pm(dev_priv, wakeref) {
>  		if (IS_CHERRYVIEW(dev_priv))
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index b6ce7580d414..7a95c262aa14 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -323,7 +323,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
>  	struct pci_dev *pdev = dev_priv->drm.pdev;
>  	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
>  	drm_i915_getparam_t *param = data;
> -	int value;
> +	int value = 0;
>  
>  	switch (param->param) {
>  	case I915_PARAM_IRQ_ACTIVE:
> @@ -452,7 +452,9 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
>  			return -ENODEV;
>  		break;
>  	case I915_PARAM_SUBSLICE_MASK:
> -		value = sseu->subslice_mask[0];
> +		/* Only copy bits from the first subslice */
> +		memcpy(&value, sseu->subslice_mask,
> +		       min(sseu->ss_stride, (u8)sizeof(value)));
>  		if (!value)
>  			return -ENODEV;
>  		break;
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index f51ff683dd2e..9da4118ad43a 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -405,6 +405,7 @@ static void print_error_buffers(struct drm_i915_error_state_buf *m,
>  static void error_print_instdone(struct drm_i915_error_state_buf *m,
>  				 const struct drm_i915_error_engine *ee)
>  {
> +	struct sseu_dev_info *sseu = &RUNTIME_INFO(m->i915)->sseu;
>  	int slice;
>  	int subslice;
>  
> @@ -420,12 +421,12 @@ static void error_print_instdone(struct drm_i915_error_state_buf *m,
>  	if (INTEL_GEN(m->i915) <= 6)
>  		return;
>  
> -	for_each_instdone_slice_subslice(m->i915, slice, subslice)
> +	for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
>  		err_printf(m, "  SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
>  			   slice, subslice,
>  			   ee->instdone.sampler[slice][subslice]);
>  
> -	for_each_instdone_slice_subslice(m->i915, slice, subslice)
> +	for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
>  		err_printf(m, "  ROW_INSTDONE[%d][%d]: 0x%08x\n",
>  			   slice, subslice,
>  			   ee->instdone.row[slice][subslice]);
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> index 7c1708c22811..000dcb145ce0 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -37,8 +37,6 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
>  	const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
>  	struct drm_i915_query_topology_info topo;
>  	u32 slice_length, subslice_length, eu_length, total_length;
> -	u8 subslice_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
> -	u8 eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
>  	int ret;
>  
>  	if (query_item->flags != 0)
> @@ -50,8 +48,8 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
>  	BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
>  
>  	slice_length = sizeof(sseu->slice_mask);
> -	subslice_length = sseu->max_slices * subslice_stride;
> -	eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
> +	subslice_length = sseu->max_slices * sseu->ss_stride;
> +	eu_length = sseu->max_slices * sseu->max_subslices * sseu->eu_stride;
>  	total_length = sizeof(topo) + slice_length + subslice_length +
>  		       eu_length;
>  
> @@ -69,9 +67,9 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
>  	topo.max_eus_per_subslice = sseu->max_eus_per_subslice;
>  
>  	topo.subslice_offset = slice_length;
> -	topo.subslice_stride = subslice_stride;
> +	topo.subslice_stride = sseu->ss_stride;
>  	topo.eu_offset = slice_length + subslice_length;
> -	topo.eu_stride = eu_stride;
> +	topo.eu_stride = sseu->eu_stride;
>  
>  	if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr),
>  			   &topo, sizeof(topo)))
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 559cf0d0628e..1cc72beb86ee 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -84,17 +84,42 @@ void intel_device_info_dump_flags(const struct intel_device_info *info,
>  #undef PRINT_FLAG
>  }
>  
> +#define SS_STR_MAX_SIZE (GEN_MAX_SUBSLICE_STRIDE * 2)
> +
> +static u8 *
> +subslice_per_slice_str(u8 *buf, const struct sseu_dev_info *sseu, u8 slice)
> +{
> +	int i;
> +	u8 ss_offset = slice * sseu->ss_stride;
> +
> +	GEM_BUG_ON(slice >= sseu->max_slices);
> +
> +	memset(buf, 0, SS_STR_MAX_SIZE);
> +
> +	/*
> +	 * Print subslice information in reverse order to match
> +	 * userspace expectations.
> +	 */
> +	for (i = 0; i < sseu->ss_stride; i++)
> +		sprintf(&buf[i * 2], "%02x",
> +			sseu->subslice_mask[ss_offset + sseu->ss_stride -
> +					    (i + 1)]);
> +
> +	return buf;
> +}
> +
>  static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
>  {
>  	int s;
> +	u8 buf[SS_STR_MAX_SIZE];
>  
>  	drm_printf(p, "slice total: %u, mask=%04x\n",
>  		   hweight8(sseu->slice_mask), sseu->slice_mask);
>  	drm_printf(p, "subslice total: %u\n", sseu_subslice_total(sseu));
>  	for (s = 0; s < sseu->max_slices; s++) {
> -		drm_printf(p, "slice%d: %u subslices, mask=%04x\n",
> +		drm_printf(p, "slice%d: %u subslices, mask=%s\n",
>  			   s, sseu_subslices_per_slice(sseu, s),
> -			   sseu->subslice_mask[s]);
> +			   subslice_per_slice_str(buf, sseu, s));
>  	}
>  	drm_printf(p, "EU total: %u\n", sseu->eu_total);
>  	drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
> @@ -118,6 +143,7 @@ void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
>  				     struct drm_printer *p)
>  {
>  	int s, ss;
> +	u8 buf[SS_STR_MAX_SIZE];
>  
>  	if (sseu->max_slices == 0) {
>  		drm_printf(p, "Unavailable\n");
> @@ -125,9 +151,9 @@ void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
>  	}
>  
>  	for (s = 0; s < sseu->max_slices; s++) {
> -		drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n",
> +		drm_printf(p, "slice%d: %u subslice(s) (0x%s):\n",
>  			   s, sseu_subslices_per_slice(sseu, s),
> -			   sseu->subslice_mask[s]);
> +			   subslice_per_slice_str(buf, sseu, s));
>  
>  		for (ss = 0; ss < sseu->max_subslices; ss++) {
>  			u16 enabled_eus = sseu_get_eus(sseu, s, ss);
> @@ -156,15 +182,10 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
>  	u8 eu_en;
>  	int s;
>  
> -	if (IS_ELKHARTLAKE(dev_priv)) {
> -		sseu->max_slices = 1;
> -		sseu->max_subslices = 4;
> -		sseu->max_eus_per_subslice = 8;
> -	} else {
> -		sseu->max_slices = 1;
> -		sseu->max_subslices = 8;
> -		sseu->max_eus_per_subslice = 8;
> -	}
> +	if (IS_ELKHARTLAKE(dev_priv))
> +		set_sseu_info(sseu, 1, 4, 8);
> +	else
> +		set_sseu_info(sseu, 1, 8, 8);
>  
>  	s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
>  	ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
> @@ -177,9 +198,11 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
>  			int ss;
>  
>  			sseu->slice_mask |= BIT(s);
> -			sseu->subslice_mask[s] = (ss_en >> ss_idx) & ss_en_mask;
> +			sseu->subslice_mask[s * sseu->ss_stride] =
> +				(ss_en >> ss_idx) & ss_en_mask;
>  			for (ss = 0; ss < sseu->max_subslices; ss++) {
> -				if (sseu->subslice_mask[s] & BIT(ss))
> +				if (sseu->subslice_mask[s * sseu->ss_stride] &
> +				    BIT(ss))
>  					sseu_set_eus(sseu, s, ss, eu_en);
>  			}
>  		}
> @@ -201,23 +224,10 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
>  	const int eu_mask = 0xff;
>  	u32 subslice_mask, eu_en;
>  
> +	set_sseu_info(sseu, 6, 4, 8);
> +
>  	sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
>  			    GEN10_F2_S_ENA_SHIFT;
> -	sseu->max_slices = 6;
> -	sseu->max_subslices = 4;
> -	sseu->max_eus_per_subslice = 8;
> -
> -	subslice_mask = (1 << 4) - 1;
> -	subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
> -			   GEN10_F2_SS_DIS_SHIFT);
> -
> -	/*
> -	 * Slice0 can have up to 3 subslices, but there are only 2 in
> -	 * slice1/2.
> -	 */
> -	sseu->subslice_mask[0] = subslice_mask;
> -	for (s = 1; s < sseu->max_slices; s++)
> -		sseu->subslice_mask[s] = subslice_mask & 0x3;
>  
>  	/* Slice0 */
>  	eu_en = ~I915_READ(GEN8_EU_DISABLE0);
> @@ -242,14 +252,22 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
>  	eu_en = ~I915_READ(GEN10_EU_DISABLE3);
>  	sseu_set_eus(sseu, 5, 1, eu_en & eu_mask);
>  
> -	/* Do a second pass where we mark the subslices disabled if all their
> -	 * eus are off.
> -	 */
> +	subslice_mask = (1 << 4) - 1;
> +	subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
> +			   GEN10_F2_SS_DIS_SHIFT);
> +
>  	for (s = 0; s < sseu->max_slices; s++) {
>  		for (ss = 0; ss < sseu->max_subslices; ss++) {
>  			if (sseu_get_eus(sseu, s, ss) == 0)
> -				sseu->subslice_mask[s] &= ~BIT(ss);
> +				subslice_mask &= ~BIT(ss);
>  		}
> +
> +		/*
> +		 * Slice0 can have up to 3 subslices, but there are only 2 in
> +		 * slice1/2.
> +		 */
> +		sseu_set_subslices(sseu, s, s == 0 ? subslice_mask :
> +						     subslice_mask & 0x3);
>  	}
>  
>  	sseu->eu_total = compute_eu_total(sseu);
> @@ -274,13 +292,12 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
>  {
>  	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
>  	u32 fuse;
> +	u8 subslice_mask;
>  
>  	fuse = I915_READ(CHV_FUSE_GT);
>  
>  	sseu->slice_mask = BIT(0);
> -	sseu->max_slices = 1;
> -	sseu->max_subslices = 2;
> -	sseu->max_eus_per_subslice = 8;
> +	set_sseu_info(sseu, 1, 2, 8);
>  
>  	if (!(fuse & CHV_FGT_DISABLE_SS0)) {
>  		u8 disabled_mask =
> @@ -289,7 +306,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
>  			(((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
>  			  CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
>  
> -		sseu->subslice_mask[0] |= BIT(0);
> +		subslice_mask |= BIT(0);
>  		sseu_set_eus(sseu, 0, 0, ~disabled_mask);
>  	}
>  
> @@ -300,10 +317,12 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
>  			(((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
>  			  CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
>  
> -		sseu->subslice_mask[0] |= BIT(1);
> +		subslice_mask |= BIT(1);
>  		sseu_set_eus(sseu, 0, 1, ~disabled_mask);
>  	}
>  
> +	sseu_set_subslices(sseu, 0, subslice_mask);
> +
>  	sseu->eu_total = compute_eu_total(sseu);
>  
>  	/*
> @@ -335,9 +354,8 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
>  	sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
>  
>  	/* BXT has a single slice and at most 3 subslices. */
> -	sseu->max_slices = IS_GEN9_LP(dev_priv) ? 1 : 3;
> -	sseu->max_subslices = IS_GEN9_LP(dev_priv) ? 3 : 4;
> -	sseu->max_eus_per_subslice = 8;
> +	set_sseu_info(sseu, IS_GEN9_LP(dev_priv) ? 1 : 3,
> +		      IS_GEN9_LP(dev_priv) ? 3 : 4, 8);
>  
>  	/*
>  	 * The subslice disable field is global, i.e. it applies
> @@ -356,14 +374,16 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
>  			/* skip disabled slice */
>  			continue;
>  
> -		sseu->subslice_mask[s] = subslice_mask;
> +		sseu_set_subslices(sseu, s, subslice_mask);
>  
>  		eu_disable = I915_READ(GEN9_EU_DISABLE(s));
>  		for (ss = 0; ss < sseu->max_subslices; ss++) {
>  			int eu_per_ss;
>  			u8 eu_disabled_mask;
> +			u8 ss_idx = s * sseu->ss_stride + ss / BITS_PER_BYTE;
>  
> -			if (!(sseu->subslice_mask[s] & BIT(ss)))
> +			if (!(sseu->subslice_mask[ss_idx] &
> +			      BIT(ss % BITS_PER_BYTE)))
>  				/* skip disabled subslice */
>  				continue;
>  
> @@ -435,9 +455,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
>  
>  	fuse2 = I915_READ(GEN8_FUSE2);
>  	sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
> -	sseu->max_slices = 3;
> -	sseu->max_subslices = 3;
> -	sseu->max_eus_per_subslice = 8;
> +	set_sseu_info(sseu, 3, 3, 8);
>  
>  	/*
>  	 * The subslice disable field is global, i.e. it applies
> @@ -464,18 +482,21 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
>  			/* skip disabled slice */
>  			continue;
>  
> -		sseu->subslice_mask[s] = subslice_mask;
> +		sseu_set_subslices(sseu, s, subslice_mask);
>  
>  		for (ss = 0; ss < sseu->max_subslices; ss++) {
>  			u8 eu_disabled_mask;
> +			u8 ss_idx = s * sseu->ss_stride + ss / BITS_PER_BYTE;
>  			u32 n_disabled;
>  
> -			if (!(sseu->subslice_mask[s] & BIT(ss)))
> +			if (!(sseu->subslice_mask[ss_idx] &
> +			      BIT(ss % BITS_PER_BYTE)))
>  				/* skip disabled subslice */
>  				continue;
>  
>  			eu_disabled_mask =
> -				eu_disable[s] >> (ss * sseu->max_eus_per_subslice);
> +				eu_disable[s] >>
> +					(ss * sseu->max_eus_per_subslice);
>  
>  			sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
>  
> @@ -514,6 +535,7 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
>  	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
>  	u32 fuse1;
>  	int s, ss;
> +	u32 subslice_mask;
>  
>  	/*
>  	 * There isn't a register to tell us how many slices/subslices. We
> @@ -525,22 +547,18 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
>  		/* fall through */
>  	case 1:
>  		sseu->slice_mask = BIT(0);
> -		sseu->subslice_mask[0] = BIT(0);
> +		subslice_mask = BIT(0);
>  		break;
>  	case 2:
>  		sseu->slice_mask = BIT(0);
> -		sseu->subslice_mask[0] = BIT(0) | BIT(1);
> +		subslice_mask = BIT(0) | BIT(1);
>  		break;
>  	case 3:
>  		sseu->slice_mask = BIT(0) | BIT(1);
> -		sseu->subslice_mask[0] = BIT(0) | BIT(1);
> -		sseu->subslice_mask[1] = BIT(0) | BIT(1);
> +		subslice_mask = BIT(0) | BIT(1);
>  		break;
>  	}
>  
> -	sseu->max_slices = hweight8(sseu->slice_mask);
> -	sseu->max_subslices = hweight8(sseu->subslice_mask[0]);
> -
>  	fuse1 = I915_READ(HSW_PAVP_FUSE1);
>  	switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) {
>  	default:
> @@ -557,9 +575,14 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
>  		sseu->eu_per_subslice = 6;
>  		break;
>  	}
> -	sseu->max_eus_per_subslice = sseu->eu_per_subslice;
> +
> +	set_sseu_info(sseu, hweight8(sseu->slice_mask),
> +		      hweight8(subslice_mask),
> +		      sseu->eu_per_subslice);
>  
>  	for (s = 0; s < sseu->max_slices; s++) {
> +		sseu_set_subslices(sseu, s, subslice_mask);
> +
>  		for (ss = 0; ss < sseu->max_subslices; ss++) {
>  			sseu_set_eus(sseu, s, ss,
>  				     (1UL << sseu->eu_per_subslice) - 1);

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 5/5] drm/i915: Expand subslice mask

[Summers, Stuart]

[-- Attachment #1.1: Type: text/plain, Size: 31838 bytes --]

On Tue, 2019-04-30 at 12:03 +0300, Jani Nikula wrote:
> On Mon, 29 Apr 2019, Stuart Summers <stuart.summers@intel.com> wrote:
> > Currently, the subslice_mask runtime parameter is stored as an
> > array of subslices per slice. Expand the subslice mask array to
> > better match what is presented to userspace through the
> > I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
> > then calculated:
> >   slice * subslice stride + subslice index / 8
> > 
> > v2: fix spacing in set_sseu_info args
> >     use set_sseu_info to initialize sseu data when building
> >     device status in debugfs
> >     rename variables in intel_engine_types.h to avoid checkpatch
> >     warnings
> > v3: update headers in intel_sseu.h
> > 
> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_engine_cs.c    |   6 +-
> >  drivers/gpu/drm/i915/gt/intel_engine_types.h |  32 +++--
> >  drivers/gpu/drm/i915/gt/intel_hangcheck.c    |   3 +-
> >  drivers/gpu/drm/i915/gt/intel_sseu.h         |  45 +++++-
> >  drivers/gpu/drm/i915/gt/intel_workarounds.c  |   2 +-
> >  drivers/gpu/drm/i915/i915_debugfs.c          |  43 +++---
> >  drivers/gpu/drm/i915/i915_drv.c              |   6 +-
> >  drivers/gpu/drm/i915/i915_gpu_error.c        |   5 +-
> >  drivers/gpu/drm/i915/i915_query.c            |  10 +-
> >  drivers/gpu/drm/i915/intel_device_info.c     | 139 +++++++++++--
> > ------
> >  10 files changed, 183 insertions(+), 108 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > index f7308479d511..8922358ee6c6 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > @@ -908,7 +908,7 @@ u32 intel_calculate_mcr_s_ss_select(struct
> > drm_i915_private *dev_priv)
> >  	const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)-
> > >sseu;
> >  	u32 mcr_s_ss_select;
> >  	u32 slice = fls(sseu->slice_mask);
> > -	u32 subslice = fls(sseu->subslice_mask[slice]);
> > +	u32 subslice = fls(sseu->subslice_mask[slice * sseu-
> > >ss_stride]);
> >  
> >  	if (IS_GEN(dev_priv, 10))
> >  		mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
> > @@ -984,6 +984,7 @@ void intel_engine_get_instdone(struct
> > intel_engine_cs *engine,
> >  			       struct intel_instdone *instdone)
> >  {
> >  	struct drm_i915_private *dev_priv = engine->i915;
> > +	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
> 
> const?
> 
> >  	struct intel_uncore *uncore = engine->uncore;
> >  	u32 mmio_base = engine->mmio_base;
> >  	int slice;
> > @@ -1001,7 +1002,8 @@ void intel_engine_get_instdone(struct
> > intel_engine_cs *engine,
> >  
> >  		instdone->slice_common =
> >  			intel_uncore_read(uncore, GEN7_SC_INSTDONE);
> > -		for_each_instdone_slice_subslice(dev_priv, slice,
> > subslice) {
> > +		for_each_instdone_slice_subslice(dev_priv, sseu, slice,
> > +						 subslice) {
> >  			instdone->sampler[slice][subslice] =
> >  				read_subslice_reg(dev_priv, slice,
> > subslice,
> >  						  GEN7_SAMPLER_INSTDONE
> > );
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > index d972c339309c..fa70528963a4 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > @@ -534,20 +534,22 @@ intel_engine_needs_breadcrumb_tasklet(const
> > struct intel_engine_cs *engine)
> >  	return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
> >  }
> >  
> > -#define instdone_slice_mask(dev_priv__) \
> > -	(IS_GEN(dev_priv__, 7) ? \
> > -	 1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)
> > -
> > -#define instdone_subslice_mask(dev_priv__) \
> > -	(IS_GEN(dev_priv__, 7) ? \
> > -	 1 : RUNTIME_INFO(dev_priv__)->sseu.subslice_mask[0])
> > -
> > -#define for_each_instdone_slice_subslice(dev_priv__, slice__,
> > subslice__) \
> > -	for ((slice__) = 0, (subslice__) = 0; \
> > -	     (slice__) < I915_MAX_SLICES; \
> > -	     (subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ?
> > (subslice__) + 1 : 0, \
> > -	       (slice__) += ((subslice__) == 0)) \
> > -		for_each_if((BIT(slice__) &
> > instdone_slice_mask(dev_priv__)) && \
> > -			    (BIT(subslice__) &
> > instdone_subslice_mask(dev_priv__)))
> > +#define instdone_has_slice(dev_priv___, sseu___, slice___) \
> > +	((IS_GEN(dev_priv___, 7) ? \
> > +	  1 : (sseu___)->slice_mask) & \
> > +	BIT(slice___)) \
> > +
> > +#define instdone_has_subslice(dev_priv__, sseu__, slice__,
> > subslice__) \
> > +	((IS_GEN(dev_priv__, 7) ? \
> > +	  1 : (sseu__)->subslice_mask[slice__ * (sseu__)->ss_stride + \
> > +				      subslice__ / BITS_PER_BYTE]) & \
> > +	 BIT(subslice__ % BITS_PER_BYTE)) \
> > +
> > +#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_,
> > subslice_) \
> > +	for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES;
> > \
> > +	     (subslice_) = ((subslice_) + 1) < I915_MAX_SUBSLICES ?
> > (subslice_) + 1 : 0, \
> > +	       (slice_) += ((subslice_) == 0)) \
> > +		for_each_if(instdone_has_slice(dev_priv_, sseu_, slice)
> > && \
> > +			    instdone_has_subslice(dev_priv_, sseu_,
> > slice_, subslice_)) \
> >  
> >  #endif /* __INTEL_ENGINE_TYPES_H__ */
> > diff --git a/drivers/gpu/drm/i915/gt/intel_hangcheck.c
> > b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
> > index e5eaa06fe74d..95dfce65c00c 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_hangcheck.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
> > @@ -50,6 +50,7 @@ static bool instdone_unchanged(u32
> > current_instdone, u32 *old_instdone)
> >  static bool subunits_stuck(struct intel_engine_cs *engine)
> >  {
> >  	struct drm_i915_private *dev_priv = engine->i915;
> > +	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
> 
> const?

Sure. I'll make these two changes in the next revision. Thanks for the
look!

-Stuart

> 
> >  	struct intel_instdone instdone;
> >  	struct intel_instdone *accu_instdone = &engine-
> > >hangcheck.instdone;
> >  	bool stuck;
> > @@ -71,7 +72,7 @@ static bool subunits_stuck(struct intel_engine_cs
> > *engine)
> >  	stuck &= instdone_unchanged(instdone.slice_common,
> >  				    &accu_instdone->slice_common);
> >  
> > -	for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
> > +	for_each_instdone_slice_subslice(dev_priv, sseu, slice,
> > subslice) {
> >  		stuck &=
> > instdone_unchanged(instdone.sampler[slice][subslice],
> >  					    &accu_instdone-
> > >sampler[slice][subslice]);
> >  		stuck &=
> > instdone_unchanged(instdone.row[slice][subslice],
> > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
> > b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > index 5127b4ff92bf..34b461da6735 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > @@ -9,16 +9,18 @@
> >  
> >  #include <linux/types.h>
> >  #include <linux/kernel.h>
> > +#include <linux/string.h>
> >  
> >  struct drm_i915_private;
> >  
> >  #define GEN_MAX_SLICES		(6) /* CNL upper bound */
> >  #define GEN_MAX_SUBSLICES	(8) /* ICL upper bound */
> >  #define GEN_SSEU_STRIDE(bits) DIV_ROUND_UP(bits, BITS_PER_BYTE)
> > +#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
> >  
> >  struct sseu_dev_info {
> >  	u8 slice_mask;
> > -	u8 subslice_mask[GEN_MAX_SLICES];
> > +	u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
> >  	u16 eu_total;
> >  	u8 eu_per_subslice;
> >  	u8 min_eu_in_pool;
> > @@ -33,6 +35,9 @@ struct sseu_dev_info {
> >  	u8 max_subslices;
> >  	u8 max_eus_per_subslice;
> >  
> > +	u8 ss_stride;
> > +	u8 eu_stride;
> > +
> >  	/* We don't have more than 8 eus per subslice at the moment and
> > as we
> >  	 * store eus enabled using bits, no need to multiply by eus per
> >  	 * subslice.
> > @@ -63,6 +68,17 @@ intel_sseu_from_device_info(const struct
> > sseu_dev_info *sseu)
> >  	return value;
> >  }
> >  
> > +static inline void set_sseu_info(struct sseu_dev_info *sseu, u8
> > max_slices,
> > +				 u8 max_subslices, u8
> > max_eus_per_subslice)
> > +{
> > +	sseu->max_slices = max_slices;
> > +	sseu->max_subslices = max_subslices;
> > +	sseu->max_eus_per_subslice = max_eus_per_subslice;
> > +
> > +	sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
> > +	sseu->eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
> > +}
> > +
> >  static inline unsigned int sseu_subslice_total(const struct
> > sseu_dev_info *sseu)
> >  {
> >  	unsigned int i, total = 0;
> > @@ -76,7 +92,32 @@ static inline unsigned int
> > sseu_subslice_total(const struct sseu_dev_info *sseu)
> >  static inline unsigned int
> >  sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8
> > slice)
> >  {
> > -	return hweight8(sseu->subslice_mask[slice]);
> > +	unsigned int i, total = 0;
> > +
> > +	for (i = 0; i < sseu->ss_stride; i++)
> > +		total += hweight8(sseu->subslice_mask[slice * sseu-
> > >ss_stride +
> > +						      i]);
> > +
> > +	return total;
> > +}
> > +
> > +static inline void sseu_copy_subslices(const struct sseu_dev_info
> > *sseu,
> > +				       int slice, u8 *to_mask,
> > +				       const u8 *from_mask)
> > +{
> > +	int offset = slice * sseu->ss_stride;
> > +
> > +	memcpy(&to_mask[offset], &from_mask[offset], sseu->ss_stride);
> > +}
> > +
> > +static inline void sseu_set_subslices(struct sseu_dev_info *sseu,
> > +				      int slice, u32 ss_mask)
> > +{
> > +	int i, offset = slice * sseu->ss_stride;
> > +
> > +	for (i = 0; i < sseu->ss_stride; i++)
> > +		sseu->subslice_mask[offset + i] =
> > +			(ss_mask >> (BITS_PER_BYTE * i)) & 0xff;
> >  }
> >  
> >  static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 5751446a4b0b..51df88873ff5 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -771,7 +771,7 @@ wa_init_mcr(struct drm_i915_private *i915,
> > struct i915_wa_list *wal)
> >  		u32 slice = fls(sseu->slice_mask);
> >  		u32 fuse3 =
> >  			intel_uncore_read(&i915->uncore,
> > GEN10_MIRROR_FUSE3);
> > -		u8 ss_mask = sseu->subslice_mask[slice];
> > +		u8 ss_mask = sseu->subslice_mask[slice * sseu-
> > >ss_stride];
> >  
> >  		u8 enabled_mask = (ss_mask | ss_mask >>
> >  				   GEN10_L3BANK_PAIR_COUNT) &
> > GEN10_L3BANK_MASK;
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 0ecf006d26b3..4f8d4370912f 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -1256,6 +1256,7 @@ static void i915_instdone_info(struct
> > drm_i915_private *dev_priv,
> >  			       struct seq_file *m,
> >  			       struct intel_instdone *instdone)
> >  {
> > +	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
> >  	int slice;
> >  	int subslice;
> >  
> > @@ -1271,11 +1272,11 @@ static void i915_instdone_info(struct
> > drm_i915_private *dev_priv,
> >  	if (INTEL_GEN(dev_priv) <= 6)
> >  		return;
> >  
> > -	for_each_instdone_slice_subslice(dev_priv, slice, subslice)
> > +	for_each_instdone_slice_subslice(dev_priv, sseu, slice,
> > subslice)
> >  		seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
> >  			   slice, subslice, instdone-
> > >sampler[slice][subslice]);
> >  
> > -	for_each_instdone_slice_subslice(dev_priv, slice, subslice)
> > +	for_each_instdone_slice_subslice(dev_priv, sseu, slice,
> > subslice)
> >  		seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
> >  			   slice, subslice, instdone-
> > >row[slice][subslice]);
> >  }
> > @@ -4065,7 +4066,9 @@ static void gen10_sseu_device_status(struct
> > drm_i915_private *dev_priv,
> >  			continue;
> >  
> >  		sseu->slice_mask |= BIT(s);
> > -		sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
> > +		sseu_copy_subslices(&info->sseu, s,
> > +				    sseu->subslice_mask,
> > +				    info->sseu.subslice_mask);
> >  
> >  		for (ss = 0; ss < info->sseu.max_subslices; ss++) {
> >  			unsigned int eu_cnt;
> > @@ -4116,18 +4119,22 @@ static void gen9_sseu_device_status(struct
> > drm_i915_private *dev_priv,
> >  		sseu->slice_mask |= BIT(s);
> >  
> >  		if (IS_GEN9_BC(dev_priv))
> > -			sseu->subslice_mask[s] =
> > -				RUNTIME_INFO(dev_priv)-
> > >sseu.subslice_mask[s];
> > +			sseu_copy_subslices(&info->sseu, s,
> > +					    sseu->subslice_mask,
> > +					    info->sseu.subslice_mask);
> >  
> >  		for (ss = 0; ss < info->sseu.max_subslices; ss++) {
> >  			unsigned int eu_cnt;
> > +			u8 ss_idx = s * info->sseu.ss_stride +
> > +				    ss / BITS_PER_BYTE;
> >  
> >  			if (IS_GEN9_LP(dev_priv)) {
> >  				if (!(s_reg[s] &
> > (GEN9_PGCTL_SS_ACK(ss))))
> >  					/* skip disabled subslice */
> >  					continue;
> >  
> > -				sseu->subslice_mask[s] |= BIT(ss);
> > +				sseu->subslice_mask[ss_idx] |=
> > +					BIT(ss % BITS_PER_BYTE);
> >  			}
> >  
> >  			eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
> > @@ -4144,25 +4151,24 @@ static void gen9_sseu_device_status(struct
> > drm_i915_private *dev_priv,
> >  static void broadwell_sseu_device_status(struct drm_i915_private
> > *dev_priv,
> >  					 struct sseu_dev_info *sseu)
> >  {
> > +	struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
> >  	u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
> >  	int s;
> >  
> >  	sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
> >  
> >  	if (sseu->slice_mask) {
> > -		sseu->eu_per_subslice =
> > -			RUNTIME_INFO(dev_priv)->sseu.eu_per_subslice;
> > -		for (s = 0; s < fls(sseu->slice_mask); s++) {
> > -			sseu->subslice_mask[s] =
> > -				RUNTIME_INFO(dev_priv)-
> > >sseu.subslice_mask[s];
> > -		}
> > +		sseu->eu_per_subslice = info->sseu.eu_per_subslice;
> > +		for (s = 0; s < fls(sseu->slice_mask); s++)
> > +			sseu_copy_subslices(&info->sseu, s,
> > +					    sseu->subslice_mask,
> > +					    info->sseu.subslice_mask);
> >  		sseu->eu_total = sseu->eu_per_subslice *
> >  				 sseu_subslice_total(sseu);
> >  
> >  		/* subtract fused off EU(s) from enabled slice(s) */
> >  		for (s = 0; s < fls(sseu->slice_mask); s++) {
> > -			u8 subslice_7eu =
> > -				RUNTIME_INFO(dev_priv)-
> > >sseu.subslice_7eu[s];
> > +			u8 subslice_7eu = info->sseu.subslice_7eu[s];
> >  
> >  			sseu->eu_total -= hweight8(subslice_7eu);
> >  		}
> > @@ -4209,6 +4215,7 @@ static void i915_print_sseu_info(struct
> > seq_file *m, bool is_available_info,
> >  static int i915_sseu_status(struct seq_file *m, void *unused)
> >  {
> >  	struct drm_i915_private *dev_priv = node_to_i915(m->private);
> > +	const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
> >  	struct sseu_dev_info sseu;
> >  	intel_wakeref_t wakeref;
> >  
> > @@ -4216,14 +4223,12 @@ static int i915_sseu_status(struct seq_file
> > *m, void *unused)
> >  		return -ENODEV;
> >  
> >  	seq_puts(m, "SSEU Device Info\n");
> > -	i915_print_sseu_info(m, true, &RUNTIME_INFO(dev_priv)->sseu);
> > +	i915_print_sseu_info(m, true, &info->sseu);
> >  
> >  	seq_puts(m, "SSEU Device Status\n");
> >  	memset(&sseu, 0, sizeof(sseu));
> > -	sseu.max_slices = RUNTIME_INFO(dev_priv)->sseu.max_slices;
> > -	sseu.max_subslices = RUNTIME_INFO(dev_priv)-
> > >sseu.max_subslices;
> > -	sseu.max_eus_per_subslice =
> > -		RUNTIME_INFO(dev_priv)->sseu.max_eus_per_subslice;
> > +	set_sseu_info(&sseu, info->sseu.max_slices, info-
> > >sseu.max_subslices,
> > +		      info->sseu.max_eus_per_subslice);
> >  
> >  	with_intel_runtime_pm(dev_priv, wakeref) {
> >  		if (IS_CHERRYVIEW(dev_priv))
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > b/drivers/gpu/drm/i915/i915_drv.c
> > index b6ce7580d414..7a95c262aa14 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -323,7 +323,7 @@ static int i915_getparam_ioctl(struct
> > drm_device *dev, void *data,
> >  	struct pci_dev *pdev = dev_priv->drm.pdev;
> >  	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
> >  	drm_i915_getparam_t *param = data;
> > -	int value;
> > +	int value = 0;
> >  
> >  	switch (param->param) {
> >  	case I915_PARAM_IRQ_ACTIVE:
> > @@ -452,7 +452,9 @@ static int i915_getparam_ioctl(struct
> > drm_device *dev, void *data,
> >  			return -ENODEV;
> >  		break;
> >  	case I915_PARAM_SUBSLICE_MASK:
> > -		value = sseu->subslice_mask[0];
> > +		/* Only copy bits from the first subslice */
> > +		memcpy(&value, sseu->subslice_mask,
> > +		       min(sseu->ss_stride, (u8)sizeof(value)));
> >  		if (!value)
> >  			return -ENODEV;
> >  		break;
> > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
> > b/drivers/gpu/drm/i915/i915_gpu_error.c
> > index f51ff683dd2e..9da4118ad43a 100644
> > --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> > @@ -405,6 +405,7 @@ static void print_error_buffers(struct
> > drm_i915_error_state_buf *m,
> >  static void error_print_instdone(struct drm_i915_error_state_buf
> > *m,
> >  				 const struct drm_i915_error_engine
> > *ee)
> >  {
> > +	struct sseu_dev_info *sseu = &RUNTIME_INFO(m->i915)->sseu;
> >  	int slice;
> >  	int subslice;
> >  
> > @@ -420,12 +421,12 @@ static void error_print_instdone(struct
> > drm_i915_error_state_buf *m,
> >  	if (INTEL_GEN(m->i915) <= 6)
> >  		return;
> >  
> > -	for_each_instdone_slice_subslice(m->i915, slice, subslice)
> > +	for_each_instdone_slice_subslice(m->i915, sseu, slice,
> > subslice)
> >  		err_printf(m, "  SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
> >  			   slice, subslice,
> >  			   ee->instdone.sampler[slice][subslice]);
> >  
> > -	for_each_instdone_slice_subslice(m->i915, slice, subslice)
> > +	for_each_instdone_slice_subslice(m->i915, sseu, slice,
> > subslice)
> >  		err_printf(m, "  ROW_INSTDONE[%d][%d]: 0x%08x\n",
> >  			   slice, subslice,
> >  			   ee->instdone.row[slice][subslice]);
> > diff --git a/drivers/gpu/drm/i915/i915_query.c
> > b/drivers/gpu/drm/i915/i915_query.c
> > index 7c1708c22811..000dcb145ce0 100644
> > --- a/drivers/gpu/drm/i915/i915_query.c
> > +++ b/drivers/gpu/drm/i915/i915_query.c
> > @@ -37,8 +37,6 @@ static int query_topology_info(struct
> > drm_i915_private *dev_priv,
> >  	const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)-
> > >sseu;
> >  	struct drm_i915_query_topology_info topo;
> >  	u32 slice_length, subslice_length, eu_length, total_length;
> > -	u8 subslice_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
> > -	u8 eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
> >  	int ret;
> >  
> >  	if (query_item->flags != 0)
> > @@ -50,8 +48,8 @@ static int query_topology_info(struct
> > drm_i915_private *dev_priv,
> >  	BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
> >  
> >  	slice_length = sizeof(sseu->slice_mask);
> > -	subslice_length = sseu->max_slices * subslice_stride;
> > -	eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
> > +	subslice_length = sseu->max_slices * sseu->ss_stride;
> > +	eu_length = sseu->max_slices * sseu->max_subslices * sseu-
> > >eu_stride;
> >  	total_length = sizeof(topo) + slice_length + subslice_length +
> >  		       eu_length;
> >  
> > @@ -69,9 +67,9 @@ static int query_topology_info(struct
> > drm_i915_private *dev_priv,
> >  	topo.max_eus_per_subslice = sseu->max_eus_per_subslice;
> >  
> >  	topo.subslice_offset = slice_length;
> > -	topo.subslice_stride = subslice_stride;
> > +	topo.subslice_stride = sseu->ss_stride;
> >  	topo.eu_offset = slice_length + subslice_length;
> > -	topo.eu_stride = eu_stride;
> > +	topo.eu_stride = sseu->eu_stride;
> >  
> >  	if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr),
> >  			   &topo, sizeof(topo)))
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > b/drivers/gpu/drm/i915/intel_device_info.c
> > index 559cf0d0628e..1cc72beb86ee 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > @@ -84,17 +84,42 @@ void intel_device_info_dump_flags(const struct
> > intel_device_info *info,
> >  #undef PRINT_FLAG
> >  }
> >  
> > +#define SS_STR_MAX_SIZE (GEN_MAX_SUBSLICE_STRIDE * 2)
> > +
> > +static u8 *
> > +subslice_per_slice_str(u8 *buf, const struct sseu_dev_info *sseu,
> > u8 slice)
> > +{
> > +	int i;
> > +	u8 ss_offset = slice * sseu->ss_stride;
> > +
> > +	GEM_BUG_ON(slice >= sseu->max_slices);
> > +
> > +	memset(buf, 0, SS_STR_MAX_SIZE);
> > +
> > +	/*
> > +	 * Print subslice information in reverse order to match
> > +	 * userspace expectations.
> > +	 */
> > +	for (i = 0; i < sseu->ss_stride; i++)
> > +		sprintf(&buf[i * 2], "%02x",
> > +			sseu->subslice_mask[ss_offset + sseu->ss_stride 
> > -
> > +					    (i + 1)]);
> > +
> > +	return buf;
> > +}
> > +
> >  static void sseu_dump(const struct sseu_dev_info *sseu, struct
> > drm_printer *p)
> >  {
> >  	int s;
> > +	u8 buf[SS_STR_MAX_SIZE];
> >  
> >  	drm_printf(p, "slice total: %u, mask=%04x\n",
> >  		   hweight8(sseu->slice_mask), sseu->slice_mask);
> >  	drm_printf(p, "subslice total: %u\n",
> > sseu_subslice_total(sseu));
> >  	for (s = 0; s < sseu->max_slices; s++) {
> > -		drm_printf(p, "slice%d: %u subslices, mask=%04x\n",
> > +		drm_printf(p, "slice%d: %u subslices, mask=%s\n",
> >  			   s, sseu_subslices_per_slice(sseu, s),
> > -			   sseu->subslice_mask[s]);
> > +			   subslice_per_slice_str(buf, sseu, s));
> >  	}
> >  	drm_printf(p, "EU total: %u\n", sseu->eu_total);
> >  	drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
> > @@ -118,6 +143,7 @@ void intel_device_info_dump_topology(const
> > struct sseu_dev_info *sseu,
> >  				     struct drm_printer *p)
> >  {
> >  	int s, ss;
> > +	u8 buf[SS_STR_MAX_SIZE];
> >  
> >  	if (sseu->max_slices == 0) {
> >  		drm_printf(p, "Unavailable\n");
> > @@ -125,9 +151,9 @@ void intel_device_info_dump_topology(const
> > struct sseu_dev_info *sseu,
> >  	}
> >  
> >  	for (s = 0; s < sseu->max_slices; s++) {
> > -		drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n",
> > +		drm_printf(p, "slice%d: %u subslice(s) (0x%s):\n",
> >  			   s, sseu_subslices_per_slice(sseu, s),
> > -			   sseu->subslice_mask[s]);
> > +			   subslice_per_slice_str(buf, sseu, s));
> >  
> >  		for (ss = 0; ss < sseu->max_subslices; ss++) {
> >  			u16 enabled_eus = sseu_get_eus(sseu, s, ss);
> > @@ -156,15 +182,10 @@ static void gen11_sseu_info_init(struct
> > drm_i915_private *dev_priv)
> >  	u8 eu_en;
> >  	int s;
> >  
> > -	if (IS_ELKHARTLAKE(dev_priv)) {
> > -		sseu->max_slices = 1;
> > -		sseu->max_subslices = 4;
> > -		sseu->max_eus_per_subslice = 8;
> > -	} else {
> > -		sseu->max_slices = 1;
> > -		sseu->max_subslices = 8;
> > -		sseu->max_eus_per_subslice = 8;
> > -	}
> > +	if (IS_ELKHARTLAKE(dev_priv))
> > +		set_sseu_info(sseu, 1, 4, 8);
> > +	else
> > +		set_sseu_info(sseu, 1, 8, 8);
> >  
> >  	s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
> >  	ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
> > @@ -177,9 +198,11 @@ static void gen11_sseu_info_init(struct
> > drm_i915_private *dev_priv)
> >  			int ss;
> >  
> >  			sseu->slice_mask |= BIT(s);
> > -			sseu->subslice_mask[s] = (ss_en >> ss_idx) &
> > ss_en_mask;
> > +			sseu->subslice_mask[s * sseu->ss_stride] =
> > +				(ss_en >> ss_idx) & ss_en_mask;
> >  			for (ss = 0; ss < sseu->max_subslices; ss++) {
> > -				if (sseu->subslice_mask[s] & BIT(ss))
> > +				if (sseu->subslice_mask[s * sseu-
> > >ss_stride] &
> > +				    BIT(ss))
> >  					sseu_set_eus(sseu, s, ss,
> > eu_en);
> >  			}
> >  		}
> > @@ -201,23 +224,10 @@ static void gen10_sseu_info_init(struct
> > drm_i915_private *dev_priv)
> >  	const int eu_mask = 0xff;
> >  	u32 subslice_mask, eu_en;
> >  
> > +	set_sseu_info(sseu, 6, 4, 8);
> > +
> >  	sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
> >  			    GEN10_F2_S_ENA_SHIFT;
> > -	sseu->max_slices = 6;
> > -	sseu->max_subslices = 4;
> > -	sseu->max_eus_per_subslice = 8;
> > -
> > -	subslice_mask = (1 << 4) - 1;
> > -	subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
> > -			   GEN10_F2_SS_DIS_SHIFT);
> > -
> > -	/*
> > -	 * Slice0 can have up to 3 subslices, but there are only 2 in
> > -	 * slice1/2.
> > -	 */
> > -	sseu->subslice_mask[0] = subslice_mask;
> > -	for (s = 1; s < sseu->max_slices; s++)
> > -		sseu->subslice_mask[s] = subslice_mask & 0x3;
> >  
> >  	/* Slice0 */
> >  	eu_en = ~I915_READ(GEN8_EU_DISABLE0);
> > @@ -242,14 +252,22 @@ static void gen10_sseu_info_init(struct
> > drm_i915_private *dev_priv)
> >  	eu_en = ~I915_READ(GEN10_EU_DISABLE3);
> >  	sseu_set_eus(sseu, 5, 1, eu_en & eu_mask);
> >  
> > -	/* Do a second pass where we mark the subslices disabled if all
> > their
> > -	 * eus are off.
> > -	 */
> > +	subslice_mask = (1 << 4) - 1;
> > +	subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
> > +			   GEN10_F2_SS_DIS_SHIFT);
> > +
> >  	for (s = 0; s < sseu->max_slices; s++) {
> >  		for (ss = 0; ss < sseu->max_subslices; ss++) {
> >  			if (sseu_get_eus(sseu, s, ss) == 0)
> > -				sseu->subslice_mask[s] &= ~BIT(ss);
> > +				subslice_mask &= ~BIT(ss);
> >  		}
> > +
> > +		/*
> > +		 * Slice0 can have up to 3 subslices, but there are
> > only 2 in
> > +		 * slice1/2.
> > +		 */
> > +		sseu_set_subslices(sseu, s, s == 0 ? subslice_mask :
> > +						     subslice_mask &
> > 0x3);
> >  	}
> >  
> >  	sseu->eu_total = compute_eu_total(sseu);
> > @@ -274,13 +292,12 @@ static void cherryview_sseu_info_init(struct
> > drm_i915_private *dev_priv)
> >  {
> >  	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
> >  	u32 fuse;
> > +	u8 subslice_mask;
> >  
> >  	fuse = I915_READ(CHV_FUSE_GT);
> >  
> >  	sseu->slice_mask = BIT(0);
> > -	sseu->max_slices = 1;
> > -	sseu->max_subslices = 2;
> > -	sseu->max_eus_per_subslice = 8;
> > +	set_sseu_info(sseu, 1, 2, 8);
> >  
> >  	if (!(fuse & CHV_FGT_DISABLE_SS0)) {
> >  		u8 disabled_mask =
> > @@ -289,7 +306,7 @@ static void cherryview_sseu_info_init(struct
> > drm_i915_private *dev_priv)
> >  			(((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
> >  			  CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
> >  
> > -		sseu->subslice_mask[0] |= BIT(0);
> > +		subslice_mask |= BIT(0);
> >  		sseu_set_eus(sseu, 0, 0, ~disabled_mask);
> >  	}
> >  
> > @@ -300,10 +317,12 @@ static void cherryview_sseu_info_init(struct
> > drm_i915_private *dev_priv)
> >  			(((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
> >  			  CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
> >  
> > -		sseu->subslice_mask[0] |= BIT(1);
> > +		subslice_mask |= BIT(1);
> >  		sseu_set_eus(sseu, 0, 1, ~disabled_mask);
> >  	}
> >  
> > +	sseu_set_subslices(sseu, 0, subslice_mask);
> > +
> >  	sseu->eu_total = compute_eu_total(sseu);
> >  
> >  	/*
> > @@ -335,9 +354,8 @@ static void gen9_sseu_info_init(struct
> > drm_i915_private *dev_priv)
> >  	sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >>
> > GEN8_F2_S_ENA_SHIFT;
> >  
> >  	/* BXT has a single slice and at most 3 subslices. */
> > -	sseu->max_slices = IS_GEN9_LP(dev_priv) ? 1 : 3;
> > -	sseu->max_subslices = IS_GEN9_LP(dev_priv) ? 3 : 4;
> > -	sseu->max_eus_per_subslice = 8;
> > +	set_sseu_info(sseu, IS_GEN9_LP(dev_priv) ? 1 : 3,
> > +		      IS_GEN9_LP(dev_priv) ? 3 : 4, 8);
> >  
> >  	/*
> >  	 * The subslice disable field is global, i.e. it applies
> > @@ -356,14 +374,16 @@ static void gen9_sseu_info_init(struct
> > drm_i915_private *dev_priv)
> >  			/* skip disabled slice */
> >  			continue;
> >  
> > -		sseu->subslice_mask[s] = subslice_mask;
> > +		sseu_set_subslices(sseu, s, subslice_mask);
> >  
> >  		eu_disable = I915_READ(GEN9_EU_DISABLE(s));
> >  		for (ss = 0; ss < sseu->max_subslices; ss++) {
> >  			int eu_per_ss;
> >  			u8 eu_disabled_mask;
> > +			u8 ss_idx = s * sseu->ss_stride + ss /
> > BITS_PER_BYTE;
> >  
> > -			if (!(sseu->subslice_mask[s] & BIT(ss)))
> > +			if (!(sseu->subslice_mask[ss_idx] &
> > +			      BIT(ss % BITS_PER_BYTE)))
> >  				/* skip disabled subslice */
> >  				continue;
> >  
> > @@ -435,9 +455,7 @@ static void broadwell_sseu_info_init(struct
> > drm_i915_private *dev_priv)
> >  
> >  	fuse2 = I915_READ(GEN8_FUSE2);
> >  	sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >>
> > GEN8_F2_S_ENA_SHIFT;
> > -	sseu->max_slices = 3;
> > -	sseu->max_subslices = 3;
> > -	sseu->max_eus_per_subslice = 8;
> > +	set_sseu_info(sseu, 3, 3, 8);
> >  
> >  	/*
> >  	 * The subslice disable field is global, i.e. it applies
> > @@ -464,18 +482,21 @@ static void broadwell_sseu_info_init(struct
> > drm_i915_private *dev_priv)
> >  			/* skip disabled slice */
> >  			continue;
> >  
> > -		sseu->subslice_mask[s] = subslice_mask;
> > +		sseu_set_subslices(sseu, s, subslice_mask);
> >  
> >  		for (ss = 0; ss < sseu->max_subslices; ss++) {
> >  			u8 eu_disabled_mask;
> > +			u8 ss_idx = s * sseu->ss_stride + ss /
> > BITS_PER_BYTE;
> >  			u32 n_disabled;
> >  
> > -			if (!(sseu->subslice_mask[s] & BIT(ss)))
> > +			if (!(sseu->subslice_mask[ss_idx] &
> > +			      BIT(ss % BITS_PER_BYTE)))
> >  				/* skip disabled subslice */
> >  				continue;
> >  
> >  			eu_disabled_mask =
> > -				eu_disable[s] >> (ss * sseu-
> > >max_eus_per_subslice);
> > +				eu_disable[s] >>
> > +					(ss * sseu-
> > >max_eus_per_subslice);
> >  
> >  			sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
> >  
> > @@ -514,6 +535,7 @@ static void haswell_sseu_info_init(struct
> > drm_i915_private *dev_priv)
> >  	struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
> >  	u32 fuse1;
> >  	int s, ss;
> > +	u32 subslice_mask;
> >  
> >  	/*
> >  	 * There isn't a register to tell us how many slices/subslices.
> > We
> > @@ -525,22 +547,18 @@ static void haswell_sseu_info_init(struct
> > drm_i915_private *dev_priv)
> >  		/* fall through */
> >  	case 1:
> >  		sseu->slice_mask = BIT(0);
> > -		sseu->subslice_mask[0] = BIT(0);
> > +		subslice_mask = BIT(0);
> >  		break;
> >  	case 2:
> >  		sseu->slice_mask = BIT(0);
> > -		sseu->subslice_mask[0] = BIT(0) | BIT(1);
> > +		subslice_mask = BIT(0) | BIT(1);
> >  		break;
> >  	case 3:
> >  		sseu->slice_mask = BIT(0) | BIT(1);
> > -		sseu->subslice_mask[0] = BIT(0) | BIT(1);
> > -		sseu->subslice_mask[1] = BIT(0) | BIT(1);
> > +		subslice_mask = BIT(0) | BIT(1);
> >  		break;
> >  	}
> >  
> > -	sseu->max_slices = hweight8(sseu->slice_mask);
> > -	sseu->max_subslices = hweight8(sseu->subslice_mask[0]);
> > -
> >  	fuse1 = I915_READ(HSW_PAVP_FUSE1);
> >  	switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) {
> >  	default:
> > @@ -557,9 +575,14 @@ static void haswell_sseu_info_init(struct
> > drm_i915_private *dev_priv)
> >  		sseu->eu_per_subslice = 6;
> >  		break;
> >  	}
> > -	sseu->max_eus_per_subslice = sseu->eu_per_subslice;
> > +
> > +	set_sseu_info(sseu, hweight8(sseu->slice_mask),
> > +		      hweight8(subslice_mask),
> > +		      sseu->eu_per_subslice);
> >  
> >  	for (s = 0; s < sseu->max_slices; s++) {
> > +		sseu_set_subslices(sseu, s, subslice_mask);
> > +
> >  		for (ss = 0; ss < sseu->max_subslices; ss++) {
> >  			sseu_set_eus(sseu, s, ss,
> >  				     (1UL << sseu->eu_per_subslice) -
> > 1);
> 
> 

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✗ Fi.CI.CHECKPATCH: warning for Refactor to expand subslice mask (rev4)

[Patchwork]

== Series Details ==

Series: Refactor to expand subslice mask (rev4)
URL   : https://patchwork.freedesktop.org/series/59742/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
0cad53dc6dba drm/i915: Use local variable for SSEU info in GETPARAM ioctl
da46929baac9 drm/i915: Add macro for SSEU stride calculation
723f76e4f3b1 drm/i915: Move calculation of subslices per slice to new function
4302585e7be1 drm/i915: Move sseu helper functions to intel_sseu.h
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

-:50: CHECK:SPACING: No space is necessary after a cast
#50: FILE: drivers/gpu/drm/i915/gt/intel_sseu.h:100:
+		eu_mask |= ((u16) sseu->eu_mask[offset + i]) <<

total: 0 errors, 1 warnings, 1 checks, 112 lines checked
ca2160abb603 drm/i915: Expand subslice mask
-:82: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'sseu__' - possible side-effects?
#82: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:542:
+#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
+	((IS_GEN(dev_priv__, 7) ? \
+	  1 : (sseu__)->subslice_mask[slice__ * (sseu__)->ss_stride + \
+				      subslice__ / BITS_PER_BYTE]) & \
+	 BIT(subslice__ % BITS_PER_BYTE)) \
+

-:82: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'slice__' may be better as '(slice__)' to avoid precedence issues
#82: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:542:
+#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
+	((IS_GEN(dev_priv__, 7) ? \
+	  1 : (sseu__)->subslice_mask[slice__ * (sseu__)->ss_stride + \
+				      subslice__ / BITS_PER_BYTE]) & \
+	 BIT(subslice__ % BITS_PER_BYTE)) \
+

-:82: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'subslice__' - possible side-effects?
#82: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:542:
+#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
+	((IS_GEN(dev_priv__, 7) ? \
+	  1 : (sseu__)->subslice_mask[slice__ * (sseu__)->ss_stride + \
+				      subslice__ / BITS_PER_BYTE]) & \
+	 BIT(subslice__ % BITS_PER_BYTE)) \
+

-:82: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'subslice__' may be better as '(subslice__)' to avoid precedence issues
#82: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:542:
+#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
+	((IS_GEN(dev_priv__, 7) ? \
+	  1 : (sseu__)->subslice_mask[slice__ * (sseu__)->ss_stride + \
+				      subslice__ / BITS_PER_BYTE]) & \
+	 BIT(subslice__ % BITS_PER_BYTE)) \
+

-:88: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv_' - possible side-effects?
#88: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:548:
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+	for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+	     (subslice_) = ((subslice_) + 1) < I915_MAX_SUBSLICES ? (subslice_) + 1 : 0, \
+	       (slice_) += ((subslice_) == 0)) \
+		for_each_if(instdone_has_slice(dev_priv_, sseu_, slice) && \
+			    instdone_has_subslice(dev_priv_, sseu_, slice_, subslice_)) \
 

-:88: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'sseu_' - possible side-effects?
#88: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:548:
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+	for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+	     (subslice_) = ((subslice_) + 1) < I915_MAX_SUBSLICES ? (subslice_) + 1 : 0, \
+	       (slice_) += ((subslice_) == 0)) \
+		for_each_if(instdone_has_slice(dev_priv_, sseu_, slice) && \
+			    instdone_has_subslice(dev_priv_, sseu_, slice_, subslice_)) \
 

-:88: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'slice_' - possible side-effects?
#88: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:548:
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+	for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+	     (subslice_) = ((subslice_) + 1) < I915_MAX_SUBSLICES ? (subslice_) + 1 : 0, \
+	       (slice_) += ((subslice_) == 0)) \
+		for_each_if(instdone_has_slice(dev_priv_, sseu_, slice) && \
+			    instdone_has_subslice(dev_priv_, sseu_, slice_, subslice_)) \
 

-:88: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'subslice_' - possible side-effects?
#88: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:548:
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+	for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+	     (subslice_) = ((subslice_) + 1) < I915_MAX_SUBSLICES ? (subslice_) + 1 : 0, \
+	       (slice_) += ((subslice_) == 0)) \
+		for_each_if(instdone_has_slice(dev_priv_, sseu_, slice) && \
+			    instdone_has_subslice(dev_priv_, sseu_, slice_, subslice_)) \
 

total: 0 errors, 0 warnings, 8 checks, 632 lines checked

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✗ Fi.CI.SPARSE: warning for Refactor to expand subslice mask (rev4)

[Patchwork]

== Series Details ==

Series: Refactor to expand subslice mask (rev4)
URL   : https://patchwork.freedesktop.org/series/59742/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Use local variable for SSEU info in GETPARAM ioctl
Okay!

Commit: drm/i915: Add macro for SSEU stride calculation
Okay!

Commit: drm/i915: Move calculation of subslices per slice to new function
Okay!

Commit: drm/i915: Move sseu helper functions to intel_sseu.h
Okay!

Commit: drm/i915: Expand subslice mask
+drivers/gpu/drm/i915/i915_drv.c:457:24: warning: expression using sizeof(void)

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✓ Fi.CI.BAT: success for Refactor to expand subslice mask (rev4)

[Patchwork]

== Series Details ==

Series: Refactor to expand subslice mask (rev4)
URL   : https://patchwork.freedesktop.org/series/59742/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6012 -> Patchwork_12898
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/59742/revisions/4/mbox/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_12898:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_chamelium@dp-hpd-fast:
    - {fi-cml-u2}:        [FAIL][1] ([fdo#108767]) -> [SKIP][2] +8 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/fi-cml-u2/igt@kms_chamelium@dp-hpd-fast.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/fi-cml-u2/igt@kms_chamelium@dp-hpd-fast.html

  
Known issues
------------

  Here are the changes found in Patchwork_12898 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6600u:       [PASS][3] -> [INCOMPLETE][4] ([fdo#107807])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/fi-skl-6600u/igt@i915_pm_rpm@module-reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/fi-skl-6600u/igt@i915_pm_rpm@module-reload.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-kbl-7500u:       [PASS][5] -> [DMESG-WARN][6] ([fdo#103841])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u3:          [PASS][7] -> [FAIL][8] ([fdo#103167])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html

  
#### Possible fixes ####

  * igt@amdgpu/amd_basic@userptr:
    - fi-kbl-8809g:       [DMESG-WARN][9] ([fdo#108965]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/fi-kbl-8809g/igt@amdgpu/amd_basic@userptr.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/fi-kbl-8809g/igt@amdgpu/amd_basic@userptr.html

  * igt@gem_exec_basic@basic-blt:
    - {fi-icl-u2}:        [INCOMPLETE][11] ([fdo#107713] / [fdo#110246]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/fi-icl-u2/igt@gem_exec_basic@basic-blt.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/fi-icl-u2/igt@gem_exec_basic@basic-blt.html

  * igt@gem_exec_fence@basic-busy-default:
    - fi-icl-y:           [INCOMPLETE][13] ([fdo#107713]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/fi-icl-y/igt@gem_exec_fence@basic-busy-default.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/fi-icl-y/igt@gem_exec_fence@basic-busy-default.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-byt-clapper:     [FAIL][15] ([fdo#103191]) -> [PASS][16] +1 similar issue
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/fi-byt-clapper/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/fi-byt-clapper/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103841]: https://bugs.freedesktop.org/show_bug.cgi?id=103841
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
  [fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
  [fdo#110246]: https://bugs.freedesktop.org/show_bug.cgi?id=110246


Participating hosts (52 -> 47)
------------------------------

  Missing    (5): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_6012 -> Patchwork_12898

  CI_DRM_6012: e4882f199157e3fb73d1791352931096f6ecfcfd @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4968: caed251990f35bfe45368f803980071a73e36315 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12898: ca2160abb603cf022aded003b29f4cc4c1d91a3b @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

ca2160abb603 drm/i915: Expand subslice mask
4302585e7be1 drm/i915: Move sseu helper functions to intel_sseu.h
723f76e4f3b1 drm/i915: Move calculation of subslices per slice to new function
da46929baac9 drm/i915: Add macro for SSEU stride calculation
0cad53dc6dba drm/i915: Use local variable for SSEU info in GETPARAM ioctl

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/
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✗ Fi.CI.IGT: failure for Refactor to expand subslice mask (rev4)

[Patchwork]

== Series Details ==

Series: Refactor to expand subslice mask (rev4)
URL   : https://patchwork.freedesktop.org/series/59742/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_6012_full -> Patchwork_12898_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_12898_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_12898_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_12898_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_ctx_switch@basic-all-heavy:
    - shard-skl:          NOTRUN -> [INCOMPLETE][1] +2 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/shard-skl1/igt@gem_ctx_switch@basic-all-heavy.html

  * igt@gem_fence_thrash@bo-write-verify-threaded-y:
    - shard-skl:          [PASS][2] -> [INCOMPLETE][3] +11 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-skl9/igt@gem_fence_thrash@bo-write-verify-threaded-y.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/shard-skl6/igt@gem_fence_thrash@bo-write-verify-threaded-y.html

  
#### Warnings ####

  * igt@kms_atomic_transition@6x-modeset-transitions-nonblocking-fencing:
    - shard-skl:          [SKIP][4] ([fdo#109271] / [fdo#109278]) -> [INCOMPLETE][5]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-skl4/igt@kms_atomic_transition@6x-modeset-transitions-nonblocking-fencing.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/shard-skl6/igt@kms_atomic_transition@6x-modeset-transitions-nonblocking-fencing.html

  
Known issues
------------

  Here are the changes found in Patchwork_12898_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_mocs_settings@mocs-isolation-vebox:
    - shard-apl:          [PASS][6] -> [INCOMPLETE][7] ([fdo#103927])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-apl8/igt@gem_mocs_settings@mocs-isolation-vebox.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/shard-apl5/igt@gem_mocs_settings@mocs-isolation-vebox.html

  * igt@gem_workarounds@suspend-resume:
    - shard-apl:          [PASS][8] -> [DMESG-WARN][9] ([fdo#108566]) +2 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-apl7/igt@gem_workarounds@suspend-resume.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/shard-apl3/igt@gem_workarounds@suspend-resume.html

  * igt@i915_pm_rpm@pm-tiling:
    - shard-skl:          [PASS][10] -> [INCOMPLETE][11] ([fdo#107807])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-skl10/igt@i915_pm_rpm@pm-tiling.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/shard-skl2/igt@i915_pm_rpm@pm-tiling.html

  * igt@kms_cursor_crc@cursor-64x21-offscreen:
    - shard-skl:          [PASS][12] -> [FAIL][13] ([fdo#103232])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-skl2/igt@kms_cursor_crc@cursor-64x21-offscreen.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/shard-skl10/igt@kms_cursor_crc@cursor-64x21-offscreen.html

  * igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
    - shard-glk:          [PASS][14] -> [FAIL][15] ([fdo#106509] / [fdo#107409])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-glk1/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/shard-glk1/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@pipe-c-single-move:
    - shard-hsw:          [PASS][16] -> [INCOMPLETE][17] ([fdo#103540]) +4 similar issues
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-hsw7/igt@kms_cursor_legacy@pipe-c-single-move.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/shard-hsw2/igt@kms_cursor_legacy@pipe-c-single-move.html

  * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled:
    - shard-skl:          [PASS][18] -> [FAIL][19] ([fdo#103184] / [fdo#103232])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-skl8/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/shard-skl5/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-glk:          [PASS][20] -> [INCOMPLETE][21] ([fdo#103359] / [k.org#198133]) +4 similar issues
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-glk5/igt@kms_flip@flip-vs-suspend-interruptible.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/shard-glk6/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-stridechange:
    - shard-iclb:         [PASS][22] -> [FAIL][23] ([fdo#103167]) +6 similar issues
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-stridechange.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-stridechange.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [PASS][24] -> [FAIL][25] ([fdo#108145] / [fdo#110403])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_plane_lowres@pipe-a-tiling-y:
    - shard-iclb:         [PASS][26] -> [FAIL][27] ([fdo#103166])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-iclb5/igt@kms_plane_lowres@pipe-a-tiling-y.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-y.html

  * igt@kms_psr@psr2_cursor_mmap_cpu:
    - shard-iclb:         [PASS][28] -> [SKIP][29] ([fdo#109441]) +2 similar issues
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/shard-iclb5/igt@kms_psr@psr2_cursor_mmap_cpu.html

  * igt@kms_sysfs_edid_timing:
    - shard-iclb:         [PASS][30] -> [FAIL][31] ([fdo#100047])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-iclb6/igt@kms_sysfs_edid_timing.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/shard-iclb3/igt@kms_sysfs_edid_timing.html

  * igt@perf_pmu@rc6:
    - shard-kbl:          [PASS][32] -> [SKIP][33] ([fdo#109271])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-kbl3/igt@perf_pmu@rc6.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/shard-kbl5/igt@perf_pmu@rc6.html

  
#### Possible fixes ####

  * igt@i915_suspend@debugfs-reader:
    - shard-apl:          [DMESG-WARN][34] ([fdo#108566]) -> [PASS][35] +6 similar issues
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-apl3/igt@i915_suspend@debugfs-reader.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/shard-apl6/igt@i915_suspend@debugfs-reader.html

  * igt@kms_cursor_crc@cursor-64x64-suspend:
    - shard-skl:          [INCOMPLETE][36] ([fdo#104108]) -> [PASS][37]
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-skl3/igt@kms_cursor_crc@cursor-64x64-suspend.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/shard-skl10/igt@kms_cursor_crc@cursor-64x64-suspend.html

  * igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
    - shard-glk:          [FAIL][38] ([fdo#106509] / [fdo#107409]) -> [PASS][39]
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-glk2/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/shard-glk4/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_dp_dsc@basic-dsc-enable-edp:
    - shard-iclb:         [SKIP][40] ([fdo#109349]) -> [PASS][41]
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-iclb4/igt@kms_dp_dsc@basic-dsc-enable-edp.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html

  * igt@kms_flip@modeset-vs-vblank-race:
    - shard-glk:          [FAIL][42] ([fdo#103060]) -> [PASS][43]
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-glk8/igt@kms_flip@modeset-vs-vblank-race.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/shard-glk4/igt@kms_flip@modeset-vs-vblank-race.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render:
    - shard-iclb:         [FAIL][44] ([fdo#103167]) -> [PASS][45] +3 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-suspend:
    - shard-iclb:         [INCOMPLETE][46] ([fdo#106978] / [fdo#107713]) -> [PASS][47]
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html

  * igt@kms_plane@pixel-format-pipe-c-planes:
    - shard-glk:          [SKIP][48] ([fdo#109271]) -> [PASS][49]
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-glk4/igt@kms_plane@pixel-format-pipe-c-planes.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/shard-glk9/igt@kms_plane@pixel-format-pipe-c-planes.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          [FAIL][50] ([fdo#108145]) -> [PASS][51]
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_plane_scaling@pipe-b-scaler-with-rotation:
    - shard-glk:          [SKIP][52] ([fdo#109271] / [fdo#109278]) -> [PASS][53]
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-glk1/igt@kms_plane_scaling@pipe-b-scaler-with-rotation.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/shard-glk9/igt@kms_plane_scaling@pipe-b-scaler-with-rotation.html

  * igt@kms_setmode@basic:
    - shard-apl:          [FAIL][54] ([fdo#99912]) -> [PASS][55]
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-apl5/igt@kms_setmode@basic.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/shard-apl4/igt@kms_setmode@basic.html

  * igt@tools_test@tools_test:
    - shard-iclb:         [SKIP][56] ([fdo#109352]) -> [PASS][57]
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-iclb8/igt@tools_test@tools_test.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/shard-iclb8/igt@tools_test@tools_test.html

  
#### Warnings ####

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-skl:          [FAIL][58] ([fdo#105363]) -> [FAIL][59] ([fdo#102887])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6012/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
  [fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
  [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#106509]: https://bugs.freedesktop.org/show_bug.cgi?id=106509
  [fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
  [fdo#107409]: https://bugs.freedesktop.org/show_bug.cgi?id=107409
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
  [fdo#109352]: https://bugs.freedesktop.org/show_bug.cgi?id=109352
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#110519]: https://bugs.freedesktop.org/show_bug.cgi?id=110519
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_6012 -> Patchwork_12898

  CI_DRM_6012: e4882f199157e3fb73d1791352931096f6ecfcfd @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4968: caed251990f35bfe45368f803980071a73e36315 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12898: ca2160abb603cf022aded003b29f4cc4c1d91a3b @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12898/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 0/5] Refactor to expand subslice mask

[Stuart Summers]

This patch series contains a few code clean-up patches, followed
by a patch which changes the storage of the subslice mask to better
match the userspace access through the I915_QUERY_TOPOLOGY_INFO
ioctl. The index into the subslice_mask array is then calculated:
  slice * subslice stride + subslice index / 8

v2: fix i915_pm_sseu test failure
v3: no changes to patches in the series, just resending to pick up
    in CI correctly
v4: rebase
v5: fix header test
v6: address review comments from Jari
    address minor checkpatch warning in existing code
    use eu_stride for EU div-by-8
v7: another rebase
v8: address review comments from Tvrtko and Daniele
v9: address review comments from Daniele

Stuart Summers (5):
  drm/i915: Use local variable for SSEU info in GETPARAM ioctl
  drm/i915: Add macro for SSEU stride calculation
  drm/i915: Move calculation of subslices per slice to new function
  drm/i915: Refactor sseu helper functions
  drm/i915: Expand subslice mask

 drivers/gpu/drm/i915/gt/intel_engine_cs.c    |  24 ++-
 drivers/gpu/drm/i915/gt/intel_engine_types.h |  30 ++--
 drivers/gpu/drm/i915/gt/intel_hangcheck.c    |   3 +-
 drivers/gpu/drm/i915/gt/intel_sseu.c         |  62 +++++++
 drivers/gpu/drm/i915/gt/intel_sseu.h         |  36 +++-
 drivers/gpu/drm/i915/gt/intel_workarounds.c  |   2 +-
 drivers/gpu/drm/i915/i915_debugfs.c          |  46 ++---
 drivers/gpu/drm/i915/i915_drv.c              |  15 +-
 drivers/gpu/drm/i915/i915_gpu_error.c        |   5 +-
 drivers/gpu/drm/i915/i915_query.c            |  15 +-
 drivers/gpu/drm/i915/intel_device_info.c     | 176 +++++++++++--------
 drivers/gpu/drm/i915/intel_device_info.h     |  47 -----
 12 files changed, 281 insertions(+), 180 deletions(-)

-- 
2.21.0.5.gaeb582a983

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 0/5] Refactor to expand subslice mask

[Stuart Summers]

This patch series contains a few code clean-up patches, followed
by a patch which changes the storage of the subslice mask to better
match the userspace access through the I915_QUERY_TOPOLOGY_INFO
ioctl. The index into the subslice_mask array is then calculated:
  slice * subslice stride + subslice index / 8

v2: fix i915_pm_sseu test failure
v3: no changes to patches in the series, just resending to pick up
    in CI correctly
v4: rebase
v5: fix header test
v6: address review comments from Jari
    address minor checkpatch warning in existing code
    use eu_stride for EU div-by-8
v7: another rebase
v8: address review comments from Tvrtko and Daniele

Stuart Summers (5):
  drm/i915: Use local variable for SSEU info in GETPARAM ioctl
  drm/i915: Add macro for SSEU stride calculation
  drm/i915: Move calculation of subslices per slice to new function
  drm/i915: Refactor sseu helper functions
  drm/i915: Expand subslice mask

 drivers/gpu/drm/i915/gt/intel_engine_cs.c    |  24 +-
 drivers/gpu/drm/i915/gt/intel_engine_types.h |  30 +--
 drivers/gpu/drm/i915/gt/intel_hangcheck.c    |   3 +-
 drivers/gpu/drm/i915/gt/intel_sseu.c         |  58 +++++
 drivers/gpu/drm/i915/gt/intel_sseu.h         |  36 ++-
 drivers/gpu/drm/i915/gt/intel_workarounds.c  |   2 +-
 drivers/gpu/drm/i915/i915_debugfs.c          |  46 ++--
 drivers/gpu/drm/i915/i915_drv.c              |  15 +-
 drivers/gpu/drm/i915/i915_gpu_error.c        |   5 +-
 drivers/gpu/drm/i915/i915_query.c            |  15 +-
 drivers/gpu/drm/i915/intel_device_info.c     | 246 ++++++++++++-------
 drivers/gpu/drm/i915/intel_device_info.h     |  47 ----
 12 files changed, 327 insertions(+), 200 deletions(-)

-- 
2.21.0.5.gaeb582a983

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 0/5] Refactor to expand subslice mask

[Stuart Summers]

This patch series contains a few code clean-up patches, followed
by a patch which changes the storage of the subslice mask to better
match the userspace access through the I915_QUERY_TOPOLOGY_INFO
ioctl. The index into the subslice_mask array is then calculated:
  slice * subslice stride + subslice index / 8

v2: fix i915_pm_sseu test failure
v3: no changes to patches in the series, just resending to pick up
    in CI correctly
v4: rebase

Stuart Summers (5):
  drm/i915: Use local variable for SSEU info in GETPARAM ioctl
  drm/i915: Add macro for SSEU stride calculation
  drm/i915: Move calculation of subslices per slice to new function
  drm/i915: Move sseu helper functions to intel_sseu.h
  drm/i915: Expand subslice mask

 drivers/gpu/drm/i915/gt/intel_engine_cs.c    |   6 +-
 drivers/gpu/drm/i915/gt/intel_engine_types.h |  32 +++--
 drivers/gpu/drm/i915/gt/intel_hangcheck.c    |   3 +-
 drivers/gpu/drm/i915/gt/intel_sseu.h         |  96 ++++++++++++-
 drivers/gpu/drm/i915/gt/intel_workarounds.c  |   2 +-
 drivers/gpu/drm/i915/i915_debugfs.c          |  45 +++---
 drivers/gpu/drm/i915/i915_drv.c              |  15 +-
 drivers/gpu/drm/i915/i915_gpu_error.c        |   5 +-
 drivers/gpu/drm/i915/i915_query.c            |  15 +-
 drivers/gpu/drm/i915/intel_device_info.c     | 143 +++++++++++--------
 drivers/gpu/drm/i915/intel_device_info.h     |  47 ------
 11 files changed, 245 insertions(+), 164 deletions(-)

-- 
2.21.0.5.gaeb582a983

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 0/5] Refactor to expand subslice mask

[Stuart Summers]

This patch series contains a few code clean-up patches, followed
by a patch which changes the storage of the subslice mask to better
match the userspace access through the I915_QUERY_TOPOLOGY_INFO
ioctl. The index into the subslice_mask array is then calculated:
  slice * subslice stride + subslice index / 8

v2: fix i915_pm_sseu test failure
v3: no changes to patches in the series, just resending to pick up
    in CI correctly

Stuart Summers (5):
  drm/i915: Use local variable for SSEU info in GETPARAM ioctl
  drm/i915: Add macro for SSEU stride calculation
  drm/i915: Move calculation of subslices per slice to new function
  drm/i915: Move sseu helper functions to intel_sseu.h
  drm/i915: Expand subslice mask

 drivers/gpu/drm/i915/i915_debugfs.c       |  45 ++++---
 drivers/gpu/drm/i915/i915_drv.c           |  15 ++-
 drivers/gpu/drm/i915/i915_gpu_error.c     |   5 +-
 drivers/gpu/drm/i915/i915_query.c         |  15 +--
 drivers/gpu/drm/i915/intel_device_info.c  | 143 +++++++++++++---------
 drivers/gpu/drm/i915/intel_device_info.h  |  47 -------
 drivers/gpu/drm/i915/intel_engine_cs.c    |   6 +-
 drivers/gpu/drm/i915/intel_engine_types.h |  32 ++---
 drivers/gpu/drm/i915/intel_hangcheck.c    |   3 +-
 drivers/gpu/drm/i915/intel_sseu.h         |  96 ++++++++++++++-
 drivers/gpu/drm/i915/intel_workarounds.c  |   2 +-
 11 files changed, 245 insertions(+), 164 deletions(-)

-- 
2.21.0.5.gaeb582a983

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 0/4] Refactor to expand subslice mask

[Stuart Summers]

This patch series contains a few code clean-up patches, followed
by a patch which changes the storage of the subslice mask to better
match the userspace access through the I915_QUERY_TOPOLOGY_INFO
ioctl. The index into the subslice_mask array is then calculated:
  slice * subslice stride + subslice index / 8

Stuart Summers (4):
  drm/i915: Use local variable for SSEU info in GETPARAM ioctl
  drm/i915: Add macro for SSEU stride calculation
  drm/i915: Move calculation of subslices per slice to new function
  drm/i915: Expand subslice mask

 drivers/gpu/drm/i915/i915_debugfs.c       |  46 ++++---
 drivers/gpu/drm/i915/i915_drv.c           |  15 ++-
 drivers/gpu/drm/i915/i915_gpu_error.c     |   5 +-
 drivers/gpu/drm/i915/i915_query.c         |  15 +--
 drivers/gpu/drm/i915/intel_device_info.c  | 154 +++++++++++++---------
 drivers/gpu/drm/i915/intel_device_info.h  |  52 ++++++--
 drivers/gpu/drm/i915/intel_engine_cs.c    |   6 +-
 drivers/gpu/drm/i915/intel_engine_types.h |  32 ++---
 drivers/gpu/drm/i915/intel_hangcheck.c    |   3 +-
 drivers/gpu/drm/i915/intel_workarounds.c  |   2 +-
 10 files changed, 203 insertions(+), 127 deletions(-)

-- 
2.21.0.5.gaeb582a983

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 0/5] Refactor to expand subslice mask

[Stuart Summers]

This patch series contains a few code clean-up patches, followed
by a patch which changes the storage of the subslice mask to better
match the userspace access through the I915_QUERY_TOPOLOGY_INFO
ioctl. The index into the subslice_mask array is then calculated:
  slice * subslice stride + subslice index / 8

v2: fix i915_pm_sseu test failure

Stuart Summers (5):
  drm/i915: Use local variable for SSEU info in GETPARAM ioctl
  drm/i915: Add macro for SSEU stride calculation
  drm/i915: Move calculation of subslices per slice to new function
  drm/i915: Move sseu helper functions to intel_sseu.h
  drm/i915: Expand subslice mask

 drivers/gpu/drm/i915/i915_debugfs.c       |  45 ++++---
 drivers/gpu/drm/i915/i915_drv.c           |  15 ++-
 drivers/gpu/drm/i915/i915_gpu_error.c     |   5 +-
 drivers/gpu/drm/i915/i915_query.c         |  15 +--
 drivers/gpu/drm/i915/intel_device_info.c  | 143 +++++++++++++---------
 drivers/gpu/drm/i915/intel_device_info.h  |  47 -------
 drivers/gpu/drm/i915/intel_engine_cs.c    |   6 +-
 drivers/gpu/drm/i915/intel_engine_types.h |  32 ++---
 drivers/gpu/drm/i915/intel_hangcheck.c    |   3 +-
 drivers/gpu/drm/i915/intel_sseu.h         |  96 ++++++++++++++-
 drivers/gpu/drm/i915/intel_workarounds.c  |   2 +-
 11 files changed, 245 insertions(+), 164 deletions(-)

-- 
2.21.0.5.gaeb582a983

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx