* [PATCH 0/5] Refactor to expand subslice mask @ 2019-05-03 21:30 Stuart Summers 2019-05-03 21:30 ` [PATCH 1/5] drm/i915: Use local variable for SSEU info in GETPARAM ioctl Stuart Summers ` (8 more replies) 0 siblings, 9 replies; 21+ messages in thread From: Stuart Summers @ 2019-05-03 21:30 UTC (permalink / raw) To: intel-gfx This patch series contains a few code clean-up patches, followed by a patch which changes the storage of the subslice mask to better match the userspace access through the I915_QUERY_TOPOLOGY_INFO ioctl. The index into the subslice_mask array is then calculated: slice * subslice stride + subslice index / 8 v2: fix i915_pm_sseu test failure v3: no changes to patches in the series, just resending to pick up in CI correctly v4: rebase v5: fix header test v6: address review comments from Jari address minor checkpatch warning in existing code use eu_stride for EU div-by-8 v7: another rebase v8: address review comments from Tvrtko and Daniele Stuart Summers (5): drm/i915: Use local variable for SSEU info in GETPARAM ioctl drm/i915: Add macro for SSEU stride calculation drm/i915: Move calculation of subslices per slice to new function drm/i915: Refactor sseu helper functions drm/i915: Expand subslice mask drivers/gpu/drm/i915/gt/intel_engine_cs.c | 24 +- drivers/gpu/drm/i915/gt/intel_engine_types.h | 30 +-- drivers/gpu/drm/i915/gt/intel_hangcheck.c | 3 +- drivers/gpu/drm/i915/gt/intel_sseu.c | 58 +++++ drivers/gpu/drm/i915/gt/intel_sseu.h | 36 ++- drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- drivers/gpu/drm/i915/i915_debugfs.c | 46 ++-- drivers/gpu/drm/i915/i915_drv.c | 15 +- drivers/gpu/drm/i915/i915_gpu_error.c | 5 +- drivers/gpu/drm/i915/i915_query.c | 15 +- drivers/gpu/drm/i915/intel_device_info.c | 246 ++++++++++++------- drivers/gpu/drm/i915/intel_device_info.h | 47 ---- 12 files changed, 327 insertions(+), 200 deletions(-) -- 2.21.0.5.gaeb582a983 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 1/5] drm/i915: Use local variable for SSEU info in GETPARAM ioctl 2019-05-03 21:30 [PATCH 0/5] Refactor to expand subslice mask Stuart Summers @ 2019-05-03 21:30 ` Stuart Summers 2019-05-03 21:30 ` [PATCH 2/5] drm/i915: Add macro for SSEU stride calculation Stuart Summers ` (7 subsequent siblings) 8 siblings, 0 replies; 21+ messages in thread From: Stuart Summers @ 2019-05-03 21:30 UTC (permalink / raw) To: intel-gfx In the GETPARAM ioctl handler, use a local variable to consolidate usage of SSEU runtime info. v2: add const to sseu_dev_info variable Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Stuart Summers <stuart.summers@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 5ed864752c7b..dcc872f9c676 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -328,6 +328,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data, { struct drm_i915_private *dev_priv = to_i915(dev); struct pci_dev *pdev = dev_priv->drm.pdev; + const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; drm_i915_getparam_t *param = data; int value; @@ -381,12 +382,12 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data, value = i915_cmd_parser_get_version(dev_priv); break; case I915_PARAM_SUBSLICE_TOTAL: - value = sseu_subslice_total(&RUNTIME_INFO(dev_priv)->sseu); + value = sseu_subslice_total(sseu); if (!value) return -ENODEV; break; case I915_PARAM_EU_TOTAL: - value = RUNTIME_INFO(dev_priv)->sseu.eu_total; + value = sseu->eu_total; if (!value) return -ENODEV; break; @@ -403,7 +404,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data, value = HAS_POOLED_EU(dev_priv); break; case I915_PARAM_MIN_EU_IN_POOL: - value = RUNTIME_INFO(dev_priv)->sseu.min_eu_in_pool; + value = sseu->min_eu_in_pool; break; case I915_PARAM_HUC_STATUS: value = intel_huc_check_status(&dev_priv->huc); @@ -453,12 +454,12 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data, value = intel_engines_has_context_isolation(dev_priv); break; case I915_PARAM_SLICE_MASK: - value = RUNTIME_INFO(dev_priv)->sseu.slice_mask; + value = sseu->slice_mask; if (!value) return -ENODEV; break; case I915_PARAM_SUBSLICE_MASK: - value = RUNTIME_INFO(dev_priv)->sseu.subslice_mask[0]; + value = sseu->subslice_mask[0]; if (!value) return -ENODEV; break; -- 2.21.0.5.gaeb582a983 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 2/5] drm/i915: Add macro for SSEU stride calculation 2019-05-03 21:30 [PATCH 0/5] Refactor to expand subslice mask Stuart Summers 2019-05-03 21:30 ` [PATCH 1/5] drm/i915: Use local variable for SSEU info in GETPARAM ioctl Stuart Summers @ 2019-05-03 21:30 ` Stuart Summers 2019-05-03 21:30 ` [PATCH 3/5] drm/i915: Move calculation of subslices per slice to new function Stuart Summers ` (6 subsequent siblings) 8 siblings, 0 replies; 21+ messages in thread From: Stuart Summers @ 2019-05-03 21:30 UTC (permalink / raw) To: intel-gfx Subslice stride and EU stride are calculated multiple times in i915_query. Move this calculation to a macro to reduce code duplication. v2: update headers in intel_sseu.h v3: use GEN_SSEU_STRIDE for stride calculations in intel_sseu.h apply s/bits/max_entries/ to GEN_SSEU_STRIDE parameter Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Stuart Summers <stuart.summers@intel.com> --- drivers/gpu/drm/i915/gt/intel_sseu.h | 2 ++ drivers/gpu/drm/i915/i915_query.c | 17 ++++++++--------- drivers/gpu/drm/i915/intel_device_info.h | 9 +++------ 3 files changed, 13 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h index 73bc824094e8..d20b7f96907d 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.h +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h @@ -8,11 +8,13 @@ #define __INTEL_SSEU_H__ #include <linux/types.h> +#include <linux/kernel.h> struct drm_i915_private; #define GEN_MAX_SLICES (6) /* CNL upper bound */ #define GEN_MAX_SUBSLICES (8) /* ICL upper bound */ +#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE) struct sseu_dev_info { u8 slice_mask; diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c index 782183b78f49..7c1708c22811 100644 --- a/drivers/gpu/drm/i915/i915_query.c +++ b/drivers/gpu/drm/i915/i915_query.c @@ -37,6 +37,8 @@ static int query_topology_info(struct drm_i915_private *dev_priv, const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; struct drm_i915_query_topology_info topo; u32 slice_length, subslice_length, eu_length, total_length; + u8 subslice_stride = GEN_SSEU_STRIDE(sseu->max_subslices); + u8 eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); int ret; if (query_item->flags != 0) @@ -48,12 +50,10 @@ static int query_topology_info(struct drm_i915_private *dev_priv, BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask)); slice_length = sizeof(sseu->slice_mask); - subslice_length = sseu->max_slices * - DIV_ROUND_UP(sseu->max_subslices, BITS_PER_BYTE); - eu_length = sseu->max_slices * sseu->max_subslices * - DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); - - total_length = sizeof(topo) + slice_length + subslice_length + eu_length; + subslice_length = sseu->max_slices * subslice_stride; + eu_length = sseu->max_slices * sseu->max_subslices * eu_stride; + total_length = sizeof(topo) + slice_length + subslice_length + + eu_length; ret = copy_query_item(&topo, sizeof(topo), total_length, query_item); @@ -69,10 +69,9 @@ static int query_topology_info(struct drm_i915_private *dev_priv, topo.max_eus_per_subslice = sseu->max_eus_per_subslice; topo.subslice_offset = slice_length; - topo.subslice_stride = DIV_ROUND_UP(sseu->max_subslices, BITS_PER_BYTE); + topo.subslice_stride = subslice_stride; topo.eu_offset = slice_length + subslice_length; - topo.eu_stride = - DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); + topo.eu_stride = eu_stride; if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr), &topo, sizeof(topo))) diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 5a2e17d6146b..9d43f7edfd63 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -231,8 +231,7 @@ static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu) static inline int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice, int subslice) { - int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice, - BITS_PER_BYTE); + int subslice_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); int slice_stride = sseu->max_subslices * subslice_stride; return slice * slice_stride + subslice * subslice_stride; @@ -244,8 +243,7 @@ static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu, int i, offset = sseu_eu_idx(sseu, slice, subslice); u16 eu_mask = 0; - for (i = 0; - i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) { + for (i = 0; i < GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); i++) { eu_mask |= ((u16) sseu->eu_mask[offset + i]) << (i * BITS_PER_BYTE); } @@ -258,8 +256,7 @@ static inline void sseu_set_eus(struct sseu_dev_info *sseu, { int i, offset = sseu_eu_idx(sseu, slice, subslice); - for (i = 0; - i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) { + for (i = 0; i < GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); i++) { sseu->eu_mask[offset + i] = (eu_mask >> (BITS_PER_BYTE * i)) & 0xff; } -- 2.21.0.5.gaeb582a983 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 3/5] drm/i915: Move calculation of subslices per slice to new function 2019-05-03 21:30 [PATCH 0/5] Refactor to expand subslice mask Stuart Summers 2019-05-03 21:30 ` [PATCH 1/5] drm/i915: Use local variable for SSEU info in GETPARAM ioctl Stuart Summers 2019-05-03 21:30 ` [PATCH 2/5] drm/i915: Add macro for SSEU stride calculation Stuart Summers @ 2019-05-03 21:30 ` Stuart Summers 2019-05-03 21:30 ` [PATCH 4/5] drm/i915: Refactor sseu helper functions Stuart Summers ` (5 subsequent siblings) 8 siblings, 0 replies; 21+ messages in thread From: Stuart Summers @ 2019-05-03 21:30 UTC (permalink / raw) To: intel-gfx Add a new function to return the number of subslices per slice to consolidate code usage. v2: rebase on changes to move sseu struct to intel_sseu.h v3: add intel_* prefix to sseu_subslices_per_slice Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Stuart Summers <stuart.summers@intel.com> --- drivers/gpu/drm/i915/gt/intel_sseu.h | 6 ++++++ drivers/gpu/drm/i915/i915_debugfs.c | 2 +- drivers/gpu/drm/i915/intel_device_info.c | 4 ++-- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h index d20b7f96907d..9618dff46d83 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.h +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h @@ -63,6 +63,12 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu) return value; } +static inline unsigned int +intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice) +{ + return hweight8(sseu->subslice_mask[slice]); +} + u32 intel_sseu_make_rpcs(struct drm_i915_private *i915, const struct intel_sseu *req_sseu); diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 14cd83e9ea8b..dceb32a16c5c 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -4187,7 +4187,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info, sseu_subslice_total(sseu)); for (s = 0; s < fls(sseu->slice_mask); s++) { seq_printf(m, " %s Slice%i subslices: %u\n", type, - s, hweight8(sseu->subslice_mask[s])); + s, intel_sseu_subslices_per_slice(sseu, s)); } seq_printf(m, " %s EU Total: %u\n", type, sseu->eu_total); diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 6af480b95bc6..9d6b9c45bc5e 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -93,7 +93,7 @@ static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p) drm_printf(p, "subslice total: %u\n", sseu_subslice_total(sseu)); for (s = 0; s < sseu->max_slices; s++) { drm_printf(p, "slice%d: %u subslices, mask=%04x\n", - s, hweight8(sseu->subslice_mask[s]), + s, intel_sseu_subslices_per_slice(sseu, s), sseu->subslice_mask[s]); } drm_printf(p, "EU total: %u\n", sseu->eu_total); @@ -126,7 +126,7 @@ void intel_device_info_dump_topology(const struct sseu_dev_info *sseu, for (s = 0; s < sseu->max_slices; s++) { drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n", - s, hweight8(sseu->subslice_mask[s]), + s, intel_sseu_subslices_per_slice(sseu, s), sseu->subslice_mask[s]); for (ss = 0; ss < sseu->max_subslices; ss++) { -- 2.21.0.5.gaeb582a983 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 4/5] drm/i915: Refactor sseu helper functions 2019-05-03 21:30 [PATCH 0/5] Refactor to expand subslice mask Stuart Summers ` (2 preceding siblings ...) 2019-05-03 21:30 ` [PATCH 3/5] drm/i915: Move calculation of subslices per slice to new function Stuart Summers @ 2019-05-03 21:30 ` Stuart Summers 2019-05-07 18:12 ` Daniele Ceraolo Spurio 2019-05-03 21:30 ` [PATCH 5/5] drm/i915: Expand subslice mask Stuart Summers ` (4 subsequent siblings) 8 siblings, 1 reply; 21+ messages in thread From: Stuart Summers @ 2019-05-03 21:30 UTC (permalink / raw) To: intel-gfx Move functions to intel_sseu.h and remove inline qualifier. Additionally, ensure these are all prefixed with intel_sseu_* to match the convention of other functions in i915. v2: fix spacing from checkpatch warning v3: squash helper function changes into a single patch break 80 character line to fix checkpatch warning move get/set_eus helpers to intel_device_info.c Acked-by: Jani Nikula <jani.nikula@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Stuart Summers <stuart.summers@intel.com> --- drivers/gpu/drm/i915/gt/intel_sseu.c | 17 ++++ drivers/gpu/drm/i915/gt/intel_sseu.h | 10 +-- drivers/gpu/drm/i915/i915_debugfs.c | 4 +- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/intel_device_info.c | 103 ++++++++++++++++------- drivers/gpu/drm/i915/intel_device_info.h | 44 ---------- 6 files changed, 97 insertions(+), 83 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c index 7f448f3bea0b..a0756f006f5f 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.c +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c @@ -8,6 +8,23 @@ #include "intel_lrc_reg.h" #include "intel_sseu.h" +unsigned int +intel_sseu_subslice_total(const struct sseu_dev_info *sseu) +{ + unsigned int i, total = 0; + + for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++) + total += hweight8(sseu->subslice_mask[i]); + + return total; +} + +unsigned int +intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice) +{ + return hweight8(sseu->subslice_mask[slice]); +} + u32 intel_sseu_make_rpcs(struct drm_i915_private *i915, const struct intel_sseu *req_sseu) { diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h index 9618dff46d83..b50d0401a4e2 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.h +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h @@ -63,11 +63,11 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu) return value; } -static inline unsigned int -intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice) -{ - return hweight8(sseu->subslice_mask[slice]); -} +unsigned int +intel_sseu_subslice_total(const struct sseu_dev_info *sseu); + +unsigned int +intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice); u32 intel_sseu_make_rpcs(struct drm_i915_private *i915, const struct intel_sseu *req_sseu); diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index dceb32a16c5c..fce3ccd87f76 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -4160,7 +4160,7 @@ static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv, RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s]; } sseu->eu_total = sseu->eu_per_subslice * - sseu_subslice_total(sseu); + intel_sseu_subslice_total(sseu); /* subtract fused off EU(s) from enabled slice(s) */ for (s = 0; s < fls(sseu->slice_mask); s++) { @@ -4184,7 +4184,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info, seq_printf(m, " %s Slice Total: %u\n", type, hweight8(sseu->slice_mask)); seq_printf(m, " %s Subslice Total: %u\n", type, - sseu_subslice_total(sseu)); + intel_sseu_subslice_total(sseu)); for (s = 0; s < fls(sseu->slice_mask); s++) { seq_printf(m, " %s Slice%i subslices: %u\n", type, s, intel_sseu_subslices_per_slice(sseu, s)); diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index dcc872f9c676..c2ea3f0992b2 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -382,7 +382,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data, value = i915_cmd_parser_get_version(dev_priv); break; case I915_PARAM_SUBSLICE_TOTAL: - value = sseu_subslice_total(sseu); + value = intel_sseu_subslice_total(sseu); if (!value) return -ENODEV; break; diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 9d6b9c45bc5e..689702b28e80 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -90,7 +90,7 @@ static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p) drm_printf(p, "slice total: %u, mask=%04x\n", hweight8(sseu->slice_mask), sseu->slice_mask); - drm_printf(p, "subslice total: %u\n", sseu_subslice_total(sseu)); + drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu)); for (s = 0; s < sseu->max_slices; s++) { drm_printf(p, "slice%d: %u subslices, mask=%04x\n", s, intel_sseu_subslices_per_slice(sseu, s), @@ -114,6 +114,43 @@ void intel_device_info_dump_runtime(const struct intel_runtime_info *info, info->cs_timestamp_frequency_khz); } +static int intel_sseu_eu_idx(const struct sseu_dev_info *sseu, int slice, + int subslice) +{ + int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice, + BITS_PER_BYTE); + int slice_stride = sseu->max_subslices * subslice_stride; + + return slice * slice_stride + subslice * subslice_stride; +} + +static u16 intel_sseu_get_eus(const struct sseu_dev_info *sseu, int slice, + int subslice) +{ + int i, offset = intel_sseu_eu_idx(sseu, slice, subslice); + u16 eu_mask = 0; + + for (i = 0; + i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) { + eu_mask |= ((u16)sseu->eu_mask[offset + i]) << + (i * BITS_PER_BYTE); + } + + return eu_mask; +} + +static void intel_sseu_set_eus(struct sseu_dev_info *sseu, int slice, + int subslice, u16 eu_mask) +{ + int i, offset = intel_sseu_eu_idx(sseu, slice, subslice); + + for (i = 0; + i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) { + sseu->eu_mask[offset + i] = + (eu_mask >> (BITS_PER_BYTE * i)) & 0xff; + } +} + void intel_device_info_dump_topology(const struct sseu_dev_info *sseu, struct drm_printer *p) { @@ -130,7 +167,7 @@ void intel_device_info_dump_topology(const struct sseu_dev_info *sseu, sseu->subslice_mask[s]); for (ss = 0; ss < sseu->max_subslices; ss++) { - u16 enabled_eus = sseu_get_eus(sseu, s, ss); + u16 enabled_eus = intel_sseu_get_eus(sseu, s, ss); drm_printf(p, "\tsubslice%d: %u EUs (0x%hx)\n", ss, hweight16(enabled_eus), enabled_eus); @@ -180,7 +217,7 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv) sseu->subslice_mask[s] = (ss_en >> ss_idx) & ss_en_mask; for (ss = 0; ss < sseu->max_subslices; ss++) { if (sseu->subslice_mask[s] & BIT(ss)) - sseu_set_eus(sseu, s, ss, eu_en); + intel_sseu_set_eus(sseu, s, ss, eu_en); } } } @@ -222,32 +259,32 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv) /* Slice0 */ eu_en = ~I915_READ(GEN8_EU_DISABLE0); for (ss = 0; ss < sseu->max_subslices; ss++) - sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask); + intel_sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask); /* Slice1 */ - sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask); + intel_sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask); eu_en = ~I915_READ(GEN8_EU_DISABLE1); - sseu_set_eus(sseu, 1, 1, eu_en & eu_mask); + intel_sseu_set_eus(sseu, 1, 1, eu_en & eu_mask); /* Slice2 */ - sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask); - sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask); + intel_sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask); + intel_sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask); /* Slice3 */ - sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask); + intel_sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask); eu_en = ~I915_READ(GEN8_EU_DISABLE2); - sseu_set_eus(sseu, 3, 1, eu_en & eu_mask); + intel_sseu_set_eus(sseu, 3, 1, eu_en & eu_mask); /* Slice4 */ - sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask); - sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask); + intel_sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask); + intel_sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask); /* Slice5 */ - sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask); + intel_sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask); eu_en = ~I915_READ(GEN10_EU_DISABLE3); - sseu_set_eus(sseu, 5, 1, eu_en & eu_mask); + intel_sseu_set_eus(sseu, 5, 1, eu_en & eu_mask); /* Do a second pass where we mark the subslices disabled if all their * eus are off. */ for (s = 0; s < sseu->max_slices; s++) { for (ss = 0; ss < sseu->max_subslices; ss++) { - if (sseu_get_eus(sseu, s, ss) == 0) + if (intel_sseu_get_eus(sseu, s, ss) == 0) sseu->subslice_mask[s] &= ~BIT(ss); } } @@ -260,9 +297,10 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv) * EU in any one subslice may be fused off for die * recovery. */ - sseu->eu_per_subslice = sseu_subslice_total(sseu) ? + sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? DIV_ROUND_UP(sseu->eu_total, - sseu_subslice_total(sseu)) : 0; + intel_sseu_subslice_total(sseu)) : + 0; /* No restrictions on Power Gating */ sseu->has_slice_pg = 1; @@ -290,7 +328,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4); sseu->subslice_mask[0] |= BIT(0); - sseu_set_eus(sseu, 0, 0, ~disabled_mask); + intel_sseu_set_eus(sseu, 0, 0, ~disabled_mask); } if (!(fuse & CHV_FGT_DISABLE_SS1)) { @@ -301,7 +339,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4); sseu->subslice_mask[0] |= BIT(1); - sseu_set_eus(sseu, 0, 1, ~disabled_mask); + intel_sseu_set_eus(sseu, 0, 1, ~disabled_mask); } sseu->eu_total = compute_eu_total(sseu); @@ -310,8 +348,9 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) * CHV expected to always have a uniform distribution of EU * across subslices. */ - sseu->eu_per_subslice = sseu_subslice_total(sseu) ? - sseu->eu_total / sseu_subslice_total(sseu) : + sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? + sseu->eu_total / + intel_sseu_subslice_total(sseu) : 0; /* * CHV supports subslice power gating on devices with more than @@ -319,7 +358,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) * more than one EU pair per subslice. */ sseu->has_slice_pg = 0; - sseu->has_subslice_pg = sseu_subslice_total(sseu) > 1; + sseu->has_subslice_pg = intel_sseu_subslice_total(sseu) > 1; sseu->has_eu_pg = (sseu->eu_per_subslice > 2); } @@ -369,7 +408,7 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) eu_disabled_mask = (eu_disable >> (ss * 8)) & eu_mask; - sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); + intel_sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); eu_per_ss = sseu->max_eus_per_subslice - hweight8(eu_disabled_mask); @@ -393,9 +432,10 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) * recovery. BXT is expected to be perfectly uniform in EU * distribution. */ - sseu->eu_per_subslice = sseu_subslice_total(sseu) ? + sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? DIV_ROUND_UP(sseu->eu_total, - sseu_subslice_total(sseu)) : 0; + intel_sseu_subslice_total(sseu)) : + 0; /* * SKL+ supports slice power gating on devices with more than * one slice, and supports EU power gating on devices with @@ -407,7 +447,7 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) sseu->has_slice_pg = !IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1; sseu->has_subslice_pg = - IS_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1; + IS_GEN9_LP(dev_priv) && intel_sseu_subslice_total(sseu) > 1; sseu->has_eu_pg = sseu->eu_per_subslice > 2; if (IS_GEN9_LP(dev_priv)) { @@ -477,7 +517,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv) eu_disabled_mask = eu_disable[s] >> (ss * sseu->max_eus_per_subslice); - sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); + intel_sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); n_disabled = hweight8(eu_disabled_mask); @@ -496,9 +536,10 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv) * subslices with the exception that any one EU in any one subslice may * be fused off for die recovery. */ - sseu->eu_per_subslice = sseu_subslice_total(sseu) ? + sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? DIV_ROUND_UP(sseu->eu_total, - sseu_subslice_total(sseu)) : 0; + intel_sseu_subslice_total(sseu)) : + 0; /* * BDW supports slice power gating on devices with more than @@ -561,8 +602,8 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv) for (s = 0; s < sseu->max_slices; s++) { for (ss = 0; ss < sseu->max_subslices; ss++) { - sseu_set_eus(sseu, s, ss, - (1UL << sseu->eu_per_subslice) - 1); + intel_sseu_set_eus(sseu, s, ss, + (1UL << sseu->eu_per_subslice) - 1); } } diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 9d43f7edfd63..6412a9c72898 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -218,50 +218,6 @@ struct intel_driver_caps { bool has_logical_contexts:1; }; -static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu) -{ - unsigned int i, total = 0; - - for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++) - total += hweight8(sseu->subslice_mask[i]); - - return total; -} - -static inline int sseu_eu_idx(const struct sseu_dev_info *sseu, - int slice, int subslice) -{ - int subslice_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); - int slice_stride = sseu->max_subslices * subslice_stride; - - return slice * slice_stride + subslice * subslice_stride; -} - -static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu, - int slice, int subslice) -{ - int i, offset = sseu_eu_idx(sseu, slice, subslice); - u16 eu_mask = 0; - - for (i = 0; i < GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); i++) { - eu_mask |= ((u16) sseu->eu_mask[offset + i]) << - (i * BITS_PER_BYTE); - } - - return eu_mask; -} - -static inline void sseu_set_eus(struct sseu_dev_info *sseu, - int slice, int subslice, u16 eu_mask) -{ - int i, offset = sseu_eu_idx(sseu, slice, subslice); - - for (i = 0; i < GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); i++) { - sseu->eu_mask[offset + i] = - (eu_mask >> (BITS_PER_BYTE * i)) & 0xff; - } -} - const char *intel_platform_name(enum intel_platform platform); void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv); -- 2.21.0.5.gaeb582a983 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH 4/5] drm/i915: Refactor sseu helper functions 2019-05-03 21:30 ` [PATCH 4/5] drm/i915: Refactor sseu helper functions Stuart Summers @ 2019-05-07 18:12 ` Daniele Ceraolo Spurio 2019-05-07 18:21 ` Summers, Stuart 0 siblings, 1 reply; 21+ messages in thread From: Daniele Ceraolo Spurio @ 2019-05-07 18:12 UTC (permalink / raw) To: Stuart Summers, intel-gfx On 5/3/19 2:30 PM, Stuart Summers wrote: > Move functions to intel_sseu.h and remove inline qualifier. > Additionally, ensure these are all prefixed with intel_sseu_* > to match the convention of other functions in i915. > > v2: fix spacing from checkpatch warning > v3: squash helper function changes into a single patch > break 80 character line to fix checkpatch warning > move get/set_eus helpers to intel_device_info.c > > Acked-by: Jani Nikula <jani.nikula@intel.com> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Signed-off-by: Stuart Summers <stuart.summers@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_sseu.c | 17 ++++ > drivers/gpu/drm/i915/gt/intel_sseu.h | 10 +-- > drivers/gpu/drm/i915/i915_debugfs.c | 4 +- > drivers/gpu/drm/i915/i915_drv.c | 2 +- > drivers/gpu/drm/i915/intel_device_info.c | 103 ++++++++++++++++------- > drivers/gpu/drm/i915/intel_device_info.h | 44 ---------- > 6 files changed, 97 insertions(+), 83 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c > index 7f448f3bea0b..a0756f006f5f 100644 > --- a/drivers/gpu/drm/i915/gt/intel_sseu.c > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c > @@ -8,6 +8,23 @@ > #include "intel_lrc_reg.h" > #include "intel_sseu.h" > > +unsigned int > +intel_sseu_subslice_total(const struct sseu_dev_info *sseu) > +{ > + unsigned int i, total = 0; > + > + for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++) > + total += hweight8(sseu->subslice_mask[i]); > + > + return total; > +} > + > +unsigned int > +intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice) > +{ > + return hweight8(sseu->subslice_mask[slice]); > +} > + > u32 intel_sseu_make_rpcs(struct drm_i915_private *i915, > const struct intel_sseu *req_sseu) > { > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h > index 9618dff46d83..b50d0401a4e2 100644 > --- a/drivers/gpu/drm/i915/gt/intel_sseu.h > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h > @@ -63,11 +63,11 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu) > return value; > } > > -static inline unsigned int > -intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice) > -{ > - return hweight8(sseu->subslice_mask[slice]); > -} > +unsigned int > +intel_sseu_subslice_total(const struct sseu_dev_info *sseu); > + > +unsigned int > +intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice); > > u32 intel_sseu_make_rpcs(struct drm_i915_private *i915, > const struct intel_sseu *req_sseu); > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index dceb32a16c5c..fce3ccd87f76 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -4160,7 +4160,7 @@ static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv, > RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s]; > } > sseu->eu_total = sseu->eu_per_subslice * > - sseu_subslice_total(sseu); > + intel_sseu_subslice_total(sseu); > > /* subtract fused off EU(s) from enabled slice(s) */ > for (s = 0; s < fls(sseu->slice_mask); s++) { > @@ -4184,7 +4184,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info, > seq_printf(m, " %s Slice Total: %u\n", type, > hweight8(sseu->slice_mask)); > seq_printf(m, " %s Subslice Total: %u\n", type, > - sseu_subslice_total(sseu)); > + intel_sseu_subslice_total(sseu)); > for (s = 0; s < fls(sseu->slice_mask); s++) { > seq_printf(m, " %s Slice%i subslices: %u\n", type, > s, intel_sseu_subslices_per_slice(sseu, s)); > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index dcc872f9c676..c2ea3f0992b2 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -382,7 +382,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data, > value = i915_cmd_parser_get_version(dev_priv); > break; > case I915_PARAM_SUBSLICE_TOTAL: > - value = sseu_subslice_total(sseu); > + value = intel_sseu_subslice_total(sseu); > if (!value) > return -ENODEV; > break; > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > index 9d6b9c45bc5e..689702b28e80 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -90,7 +90,7 @@ static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p) > > drm_printf(p, "slice total: %u, mask=%04x\n", > hweight8(sseu->slice_mask), sseu->slice_mask); > - drm_printf(p, "subslice total: %u\n", sseu_subslice_total(sseu)); > + drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu)); > for (s = 0; s < sseu->max_slices; s++) { > drm_printf(p, "slice%d: %u subslices, mask=%04x\n", > s, intel_sseu_subslices_per_slice(sseu, s), > @@ -114,6 +114,43 @@ void intel_device_info_dump_runtime(const struct intel_runtime_info *info, > info->cs_timestamp_frequency_khz); > } > > +static int intel_sseu_eu_idx(const struct sseu_dev_info *sseu, int slice, No need for intel_ prefix for these functions if they're static (which also helps reducing the diff). > + int subslice) > +{ > + int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice, > + BITS_PER_BYTE); This was GEN_SSEU_STRIDE in the deleted code (other occurrences below as well). With these addressed: Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Daniele > + int slice_stride = sseu->max_subslices * subslice_stride; > + > + return slice * slice_stride + subslice * subslice_stride; > +} > + > +static u16 intel_sseu_get_eus(const struct sseu_dev_info *sseu, int slice, > + int subslice) > +{ > + int i, offset = intel_sseu_eu_idx(sseu, slice, subslice); > + u16 eu_mask = 0; > + > + for (i = 0; > + i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) { > + eu_mask |= ((u16)sseu->eu_mask[offset + i]) << > + (i * BITS_PER_BYTE); > + } > + > + return eu_mask; > +} > + > +static void intel_sseu_set_eus(struct sseu_dev_info *sseu, int slice, > + int subslice, u16 eu_mask) > +{ > + int i, offset = intel_sseu_eu_idx(sseu, slice, subslice); > + > + for (i = 0; > + i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) { > + sseu->eu_mask[offset + i] = > + (eu_mask >> (BITS_PER_BYTE * i)) & 0xff; > + } > +} > + > void intel_device_info_dump_topology(const struct sseu_dev_info *sseu, > struct drm_printer *p) > { > @@ -130,7 +167,7 @@ void intel_device_info_dump_topology(const struct sseu_dev_info *sseu, > sseu->subslice_mask[s]); > > for (ss = 0; ss < sseu->max_subslices; ss++) { > - u16 enabled_eus = sseu_get_eus(sseu, s, ss); > + u16 enabled_eus = intel_sseu_get_eus(sseu, s, ss); > > drm_printf(p, "\tsubslice%d: %u EUs (0x%hx)\n", > ss, hweight16(enabled_eus), enabled_eus); > @@ -180,7 +217,7 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv) > sseu->subslice_mask[s] = (ss_en >> ss_idx) & ss_en_mask; > for (ss = 0; ss < sseu->max_subslices; ss++) { > if (sseu->subslice_mask[s] & BIT(ss)) > - sseu_set_eus(sseu, s, ss, eu_en); > + intel_sseu_set_eus(sseu, s, ss, eu_en); > } > } > } > @@ -222,32 +259,32 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv) > /* Slice0 */ > eu_en = ~I915_READ(GEN8_EU_DISABLE0); > for (ss = 0; ss < sseu->max_subslices; ss++) > - sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask); > + intel_sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask); > /* Slice1 */ > - sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask); > + intel_sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask); > eu_en = ~I915_READ(GEN8_EU_DISABLE1); > - sseu_set_eus(sseu, 1, 1, eu_en & eu_mask); > + intel_sseu_set_eus(sseu, 1, 1, eu_en & eu_mask); > /* Slice2 */ > - sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask); > - sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask); > + intel_sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask); > + intel_sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask); > /* Slice3 */ > - sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask); > + intel_sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask); > eu_en = ~I915_READ(GEN8_EU_DISABLE2); > - sseu_set_eus(sseu, 3, 1, eu_en & eu_mask); > + intel_sseu_set_eus(sseu, 3, 1, eu_en & eu_mask); > /* Slice4 */ > - sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask); > - sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask); > + intel_sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask); > + intel_sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask); > /* Slice5 */ > - sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask); > + intel_sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask); > eu_en = ~I915_READ(GEN10_EU_DISABLE3); > - sseu_set_eus(sseu, 5, 1, eu_en & eu_mask); > + intel_sseu_set_eus(sseu, 5, 1, eu_en & eu_mask); > > /* Do a second pass where we mark the subslices disabled if all their > * eus are off. > */ > for (s = 0; s < sseu->max_slices; s++) { > for (ss = 0; ss < sseu->max_subslices; ss++) { > - if (sseu_get_eus(sseu, s, ss) == 0) > + if (intel_sseu_get_eus(sseu, s, ss) == 0) > sseu->subslice_mask[s] &= ~BIT(ss); > } > } > @@ -260,9 +297,10 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv) > * EU in any one subslice may be fused off for die > * recovery. > */ > - sseu->eu_per_subslice = sseu_subslice_total(sseu) ? > + sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? > DIV_ROUND_UP(sseu->eu_total, > - sseu_subslice_total(sseu)) : 0; > + intel_sseu_subslice_total(sseu)) : > + 0; > > /* No restrictions on Power Gating */ > sseu->has_slice_pg = 1; > @@ -290,7 +328,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) > CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4); > > sseu->subslice_mask[0] |= BIT(0); > - sseu_set_eus(sseu, 0, 0, ~disabled_mask); > + intel_sseu_set_eus(sseu, 0, 0, ~disabled_mask); > } > > if (!(fuse & CHV_FGT_DISABLE_SS1)) { > @@ -301,7 +339,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) > CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4); > > sseu->subslice_mask[0] |= BIT(1); > - sseu_set_eus(sseu, 0, 1, ~disabled_mask); > + intel_sseu_set_eus(sseu, 0, 1, ~disabled_mask); > } > > sseu->eu_total = compute_eu_total(sseu); > @@ -310,8 +348,9 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) > * CHV expected to always have a uniform distribution of EU > * across subslices. > */ > - sseu->eu_per_subslice = sseu_subslice_total(sseu) ? > - sseu->eu_total / sseu_subslice_total(sseu) : > + sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? > + sseu->eu_total / > + intel_sseu_subslice_total(sseu) : > 0; > /* > * CHV supports subslice power gating on devices with more than > @@ -319,7 +358,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) > * more than one EU pair per subslice. > */ > sseu->has_slice_pg = 0; > - sseu->has_subslice_pg = sseu_subslice_total(sseu) > 1; > + sseu->has_subslice_pg = intel_sseu_subslice_total(sseu) > 1; > sseu->has_eu_pg = (sseu->eu_per_subslice > 2); > } > > @@ -369,7 +408,7 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) > > eu_disabled_mask = (eu_disable >> (ss * 8)) & eu_mask; > > - sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); > + intel_sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); > > eu_per_ss = sseu->max_eus_per_subslice - > hweight8(eu_disabled_mask); > @@ -393,9 +432,10 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) > * recovery. BXT is expected to be perfectly uniform in EU > * distribution. > */ > - sseu->eu_per_subslice = sseu_subslice_total(sseu) ? > + sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? > DIV_ROUND_UP(sseu->eu_total, > - sseu_subslice_total(sseu)) : 0; > + intel_sseu_subslice_total(sseu)) : > + 0; > /* > * SKL+ supports slice power gating on devices with more than > * one slice, and supports EU power gating on devices with > @@ -407,7 +447,7 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) > sseu->has_slice_pg = > !IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1; > sseu->has_subslice_pg = > - IS_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1; > + IS_GEN9_LP(dev_priv) && intel_sseu_subslice_total(sseu) > 1; > sseu->has_eu_pg = sseu->eu_per_subslice > 2; > > if (IS_GEN9_LP(dev_priv)) { > @@ -477,7 +517,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv) > eu_disabled_mask = > eu_disable[s] >> (ss * sseu->max_eus_per_subslice); > > - sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); > + intel_sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); > > n_disabled = hweight8(eu_disabled_mask); > > @@ -496,9 +536,10 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv) > * subslices with the exception that any one EU in any one subslice may > * be fused off for die recovery. > */ > - sseu->eu_per_subslice = sseu_subslice_total(sseu) ? > + sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? > DIV_ROUND_UP(sseu->eu_total, > - sseu_subslice_total(sseu)) : 0; > + intel_sseu_subslice_total(sseu)) : > + 0; > > /* > * BDW supports slice power gating on devices with more than > @@ -561,8 +602,8 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv) > > for (s = 0; s < sseu->max_slices; s++) { > for (ss = 0; ss < sseu->max_subslices; ss++) { > - sseu_set_eus(sseu, s, ss, > - (1UL << sseu->eu_per_subslice) - 1); > + intel_sseu_set_eus(sseu, s, ss, > + (1UL << sseu->eu_per_subslice) - 1); > } > } > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h > index 9d43f7edfd63..6412a9c72898 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.h > +++ b/drivers/gpu/drm/i915/intel_device_info.h > @@ -218,50 +218,6 @@ struct intel_driver_caps { > bool has_logical_contexts:1; > }; > > -static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu) > -{ > - unsigned int i, total = 0; > - > - for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++) > - total += hweight8(sseu->subslice_mask[i]); > - > - return total; > -} > - > -static inline int sseu_eu_idx(const struct sseu_dev_info *sseu, > - int slice, int subslice) > -{ > - int subslice_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); > - int slice_stride = sseu->max_subslices * subslice_stride; > - > - return slice * slice_stride + subslice * subslice_stride; > -} > - > -static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu, > - int slice, int subslice) > -{ > - int i, offset = sseu_eu_idx(sseu, slice, subslice); > - u16 eu_mask = 0; > - > - for (i = 0; i < GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); i++) { > - eu_mask |= ((u16) sseu->eu_mask[offset + i]) << > - (i * BITS_PER_BYTE); > - } > - > - return eu_mask; > -} > - > -static inline void sseu_set_eus(struct sseu_dev_info *sseu, > - int slice, int subslice, u16 eu_mask) > -{ > - int i, offset = sseu_eu_idx(sseu, slice, subslice); > - > - for (i = 0; i < GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); i++) { > - sseu->eu_mask[offset + i] = > - (eu_mask >> (BITS_PER_BYTE * i)) & 0xff; > - } > -} > - > const char *intel_platform_name(enum intel_platform platform); > > void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv); > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 4/5] drm/i915: Refactor sseu helper functions 2019-05-07 18:12 ` Daniele Ceraolo Spurio @ 2019-05-07 18:21 ` Summers, Stuart 0 siblings, 0 replies; 21+ messages in thread From: Summers, Stuart @ 2019-05-07 18:21 UTC (permalink / raw) To: Ceraolo Spurio, Daniele, intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 17859 bytes --] On Tue, 2019-05-07 at 11:12 -0700, Daniele Ceraolo Spurio wrote: > > On 5/3/19 2:30 PM, Stuart Summers wrote: > > Move functions to intel_sseu.h and remove inline qualifier. > > Additionally, ensure these are all prefixed with intel_sseu_* > > to match the convention of other functions in i915. > > > > v2: fix spacing from checkpatch warning > > v3: squash helper function changes into a single patch > > break 80 character line to fix checkpatch warning > > move get/set_eus helpers to intel_device_info.c > > > > Acked-by: Jani Nikula <jani.nikula@intel.com> > > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > > Signed-off-by: Stuart Summers <stuart.summers@intel.com> > > --- > > drivers/gpu/drm/i915/gt/intel_sseu.c | 17 ++++ > > drivers/gpu/drm/i915/gt/intel_sseu.h | 10 +-- > > drivers/gpu/drm/i915/i915_debugfs.c | 4 +- > > drivers/gpu/drm/i915/i915_drv.c | 2 +- > > drivers/gpu/drm/i915/intel_device_info.c | 103 ++++++++++++++++ > > ------- > > drivers/gpu/drm/i915/intel_device_info.h | 44 ---------- > > 6 files changed, 97 insertions(+), 83 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c > > b/drivers/gpu/drm/i915/gt/intel_sseu.c > > index 7f448f3bea0b..a0756f006f5f 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_sseu.c > > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c > > @@ -8,6 +8,23 @@ > > #include "intel_lrc_reg.h"ther occurrences below a > > #include "intel_sseu.h" > > > > +unsigned int > > +intel_sseu_subslice_total(const struct sseu_dev_info *sseu) > > +{ > > + unsigned int i, total = 0; > > + > > + for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++) > > + total += hweight8(sseu->subslice_mask[i]); > > + > > + return total; > > +} > > + > > +unsigned int > > +intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, > > u8 slice) > > +{ > > + return hweight8(sseu->subslice_mask[slice]); > > +} > > + > > u32 intel_sseu_make_rpcs(struct drm_i915_private *i915, > > const struct intel_sseu *req_sseu) > > { > > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h > > b/drivers/gpu/drm/i915/gt/intel_sseu.h > > index 9618dff46d83..b50d0401a4e2 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_sseu.h > > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h > > @@ -63,11 +63,11 @@ intel_sseu_from_device_info(const struct > > sseu_dev_info *sseu) > > return value; > > } > > > > -static inline unsigned int > > -intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, > > u8 slice) > > -{ > > - return hweight8(sseu->subslice_mask[slice]); > > -} > > +unsigned int > > +intel_sseu_subslice_total(const struct sseu_dev_info *sseu); > > + > > +unsigned int > > +intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, > > u8 slice); > > > > u32 intel_sseu_make_rpcs(struct drm_i915_private *i915, > > const struct intel_sseu *req_sseu); > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c > > b/drivers/gpu/drm/i915/i915_debugfs.c > > index dceb32a16c5c..fce3ccd87f76 100644 > > --- a/drivers/gpu/drm/i915/i915_debugfs.c > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > > @@ -4160,7 +4160,7 @@ static void > > broadwell_sseu_device_status(struct drm_i915_private *dev_priv, > > RUNTIME_INFO(dev_priv)- > > >sseu.subslice_mask[s]; > > } > > sseu->eu_total = sseu->eu_per_subslice * > > - sseu_subslice_total(sseu); > > + intel_sseu_subslice_total(sseu); > > > > /* subtract fused off EU(s) from enabled slice(s) */ > > for (s = 0; s < fls(sseu->slice_mask); s++) { > > @@ -4184,7 +4184,7 @@ static void i915_print_sseu_info(struct > > seq_file *m, bool is_available_info, > > seq_printf(m, " %s Slice Total: %u\n", type, > > hweight8(sseu->slice_mask)); > > seq_printf(m, " %s Subslice Total: %u\n", type, > > - sseu_subslice_total(sseu)); > > + intel_sseu_subslice_total(sseu)); > > for (s = 0; s < fls(sseu->slice_mask); s++) { > > seq_printf(m, " %s Slice%i subslices: %u\n", type, > > s, intel_sseu_subslices_per_slice(sseu, s)); > > diff --git a/drivers/gpu/drm/i915/i915_drv.c > > b/drivers/gpu/drm/i915/i915_drv.c > > index dcc872f9c676..c2ea3f0992b2 100644 > > --- a/drivers/gpu/drm/i915/i915_drv.c > > +++ b/drivers/gpu/drm/i915/i915_drv.c > > @@ -382,7 +382,7 @@ static int i915_getparam_ioctl(struct > > drm_device *dev, void *data, > > value = i915_cmd_parser_get_version(dev_priv); > > break; > > case I915_PARAM_SUBSLICE_TOTAL: > > - value = sseu_subslice_total(sseu); > > + value = intel_sseu_subslice_total(sseu); > > if (!value) > > return -ENODEV; > > break; > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c > > b/drivers/gpu/drm/i915/intel_device_info.c > > index 9d6b9c45bc5e..689702b28e80 100644 > > --- a/drivers/gpu/drm/i915/intel_device_info.c > > +++ b/drivers/gpu/drm/i915/intel_device_info.c > > @@ -90,7 +90,7 @@ static void sseu_dump(const struct sseu_dev_info > > *sseu, struct drm_printer *p) > > > > drm_printf(p, "slice total: %u, mask=%04x\n", > > hweight8(sseu->slice_mask), sseu->slice_mask); > > - drm_printf(p, "subslice total: %u\n", > > sseu_subslice_total(sseu)); > > + drm_printf(p, "subslice total: %u\n", > > intel_sseu_subslice_total(sseu)); > > for (s = 0; s < sseu->max_slices; s++) { > > drm_printf(p, "slice%d: %u subslices, mask=%04x\n", > > s, intel_sseu_subslices_per_slice(sseu, s), > > @@ -114,6 +114,43 @@ void intel_device_info_dump_runtime(const > > struct intel_runtime_info *info, > > info->cs_timestamp_frequency_khz); > > } > > > > +static int intel_sseu_eu_idx(const struct sseu_dev_info *sseu, int > > slice, > > No need for intel_ prefix for these functions if they're static > (which > also helps reducing the diff). > > > + int subslice) > > +{ > > + int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice, > > + BITS_PER_BYTE); > > This was GEN_SSEU_STRIDE in the deleted code (other occurrences below > as > well). > > With these addressed: Nice catch, I obviously missed this case. Will address both of these in the next revision. Thanks for the review! -Stuart > > Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > > Daniele > > > + int slice_stride = sseu->max_subslices * subslice_stride; > > + > > + return slice * slice_stride + subslice * subslice_stride; > > +} > > + > > +static u16 intel_sseu_get_eus(const struct sseu_dev_info *sseu, > > int slice, > > + int subslice) > > +{ > > + int i, offset = intel_sseu_eu_idx(sseu, slice, subslice); > > + u16 eu_mask = 0; > > + > > + for (i = 0; > > + i < DIV_ROUND_UP(sseu->max_eus_per_subslice, > > BITS_PER_BYTE); i++) { > > + eu_mask |= ((u16)sseu->eu_mask[offset + i]) << > > + (i * BITS_PER_BYTE); > > + } > > + > > + return eu_mask; > > +} > > + > > +static void intel_sseu_set_eus(struct sseu_dev_info *sseu, int > > slice, > > + int subslice, u16 eu_mask) > > +{ > > + int i, offset = intel_sseu_eu_idx(sseu, slice, subslice); > > + > > + for (i = 0; > > + i < DIV_ROUND_UP(sseu->max_eus_per_subslice, > > BITS_PER_BYTE); i++) { > > + sseu->eu_mask[offset + i] = > > + (eu_mask >> (BITS_PER_BYTE * i)) & 0xff; > > + } > > +} > > + > > void intel_device_info_dump_topology(const struct sseu_dev_info > > *sseu, > > struct drm_printer *p) > > { > > @@ -130,7 +167,7 @@ void intel_device_info_dump_topology(const > > struct sseu_dev_info *sseu, > > sseu->subslice_mask[s]); > > > > for (ss = 0; ss < sseu->max_subslices; ss++) { > > - u16 enabled_eus = sseu_get_eus(sseu, s, ss); > > + u16 enabled_eus = intel_sseu_get_eus(sseu, s, > > ss); > > > > drm_printf(p, "\tsubslice%d: %u EUs (0x%hx)\n", > > ss, hweight16(enabled_eus), > > enabled_eus); > > @@ -180,7 +217,7 @@ static void gen11_sseu_info_init(struct > > drm_i915_private *dev_priv) > > sseu->subslice_mask[s] = (ss_en >> ss_idx) & > > ss_en_mask; > > for (ss = 0; ss < sseu->max_subslices; ss++) { > > if (sseu->subslice_mask[s] & BIT(ss)) > > - sseu_set_eus(sseu, s, ss, > > eu_en); > > + intel_sseu_set_eus(sseu, s, ss, > > eu_en); > > } > > } > > } > > @@ -222,32 +259,32 @@ static void gen10_sseu_info_init(struct > > drm_i915_private *dev_priv) > > /* Slice0 */ > > eu_en = ~I915_READ(GEN8_EU_DISABLE0); > > for (ss = 0; ss < sseu->max_subslices; ss++) > > - sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & > > eu_mask); > > + intel_sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & > > eu_mask); > > /* Slice1 */ > > - sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask); > > + intel_sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask); > > eu_en = ~I915_READ(GEN8_EU_DISABLE1); > > - sseu_set_eus(sseu, 1, 1, eu_en & eu_mask); > > + intel_sseu_set_eus(sseu, 1, 1, eu_en & eu_mask); > > /* Slice2 */ > > - sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask); > > - sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask); > > + intel_sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask); > > + intel_sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask); > > /* Slice3 */ > > - sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask); > > + intel_sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask); > > eu_en = ~I915_READ(GEN8_EU_DISABLE2); > > - sseu_set_eus(sseu, 3, 1, eu_en & eu_mask); > > + intel_sseu_set_eus(sseu, 3, 1, eu_en & eu_mask); > > /* Slice4 */ > > - sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask); > > - sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask); > > + intel_sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask); > > + intel_sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask); > > /* Slice5 */ > > - sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask); > > + intel_sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask); > > eu_en = ~I915_READ(GEN10_EU_DISABLE3); > > - sseu_set_eus(sseu, 5, 1, eu_en & eu_mask); > > + intel_sseu_set_eus(sseu, 5, 1, eu_en & eu_mask); > > > > /* Do a second pass where we mark the subslices disabled if all > > their > > * eus are off. > > */ > > for (s = 0; s < sseu->max_slices; s++) { > > for (ss = 0; ss < sseu->max_subslices; ss++) { > > - if (sseu_get_eus(sseu, s, ss) == 0) > > + if (intel_sseu_get_eus(sseu, s, ss) == 0) > > sseu->subslice_mask[s] &= ~BIT(ss); > > } > > } > > @@ -260,9 +297,10 @@ static void gen10_sseu_info_init(struct > > drm_i915_private *dev_priv) > > * EU in any one subslice may be fused off for die > > * recovery. > > */ > > - sseu->eu_per_subslice = sseu_subslice_total(sseu) ? > > + sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? > > DIV_ROUND_UP(sseu->eu_total, > > - sseu_subslice_total(sseu)) > > : 0; > > + intel_sseu_subslice_total( > > sseu)) : > > + 0; > > > > /* No restrictions on Power Gating */ > > sseu->has_slice_pg = 1; > > @@ -290,7 +328,7 @@ static void cherryview_sseu_info_init(struct > > drm_i915_private *dev_priv) > > CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4); > > > > sseu->subslice_mask[0] |= BIT(0); > > - sseu_set_eus(sseu, 0, 0, ~disabled_mask); > > + intel_sseu_set_eus(sseu, 0, 0, ~disabled_mask); > > } > > > > if (!(fuse & CHV_FGT_DISABLE_SS1)) { > > @@ -301,7 +339,7 @@ static void cherryview_sseu_info_init(struct > > drm_i915_private *dev_priv) > > CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4); > > > > sseu->subslice_mask[0] |= BIT(1); > > - sseu_set_eus(sseu, 0, 1, ~disabled_mask); > > + intel_sseu_set_eus(sseu, 0, 1, ~disabled_mask); > > } > > > > sseu->eu_total = compute_eu_total(sseu); > > @@ -310,8 +348,9 @@ static void cherryview_sseu_info_init(struct > > drm_i915_private *dev_priv) > > * CHV expected to always have a uniform distribution of EU > > * across subslices. > > */ > > - sseu->eu_per_subslice = sseu_subslice_total(sseu) ? > > - sseu->eu_total / > > sseu_subslice_total(sseu) : > > + sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? > > + sseu->eu_total / > > + intel_sseu_subslice_total(sseu) > > : > > 0; > > /* > > * CHV supports subslice power gating on devices with more than > > @@ -319,7 +358,7 @@ static void cherryview_sseu_info_init(struct > > drm_i915_private *dev_priv) > > * more than one EU pair per subslice. > > */ > > sseu->has_slice_pg = 0; > > - sseu->has_subslice_pg = sseu_subslice_total(sseu) > 1; > > + sseu->has_subslice_pg = intel_sseu_subslice_total(sseu) > 1; > > sseu->has_eu_pg = (sseu->eu_per_subslice > 2); > > } > > > > @@ -369,7 +408,7 @@ static void gen9_sseu_info_init(struct > > drm_i915_private *dev_priv) > > > > eu_disabled_mask = (eu_disable >> (ss * 8)) & > > eu_mask; > > > > - sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); > > + intel_sseu_set_eus(sseu, s, ss, > > ~eu_disabled_mask); > > > > eu_per_ss = sseu->max_eus_per_subslice - > > hweight8(eu_disabled_mask); > > @@ -393,9 +432,10 @@ static void gen9_sseu_info_init(struct > > drm_i915_private *dev_priv) > > * recovery. BXT is expected to be perfectly uniform in EU > > * distribution. > > */ > > - sseu->eu_per_subslice = sseu_subslice_total(sseu) ? > > + sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? > > DIV_ROUND_UP(sseu->eu_total, > > - sseu_subslice_total(sseu)) > > : 0; > > + intel_sseu_subslice_total( > > sseu)) : > > + 0; > > /* > > * SKL+ supports slice power gating on devices with more than > > * one slice, and supports EU power gating on devices with > > @@ -407,7 +447,7 @@ static void gen9_sseu_info_init(struct > > drm_i915_private *dev_priv) > > sseu->has_slice_pg = > > !IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > > > 1; > > sseu->has_subslice_pg = > > - IS_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1; > > + IS_GEN9_LP(dev_priv) && intel_sseu_subslice_total(sseu) > > > 1; > > sseu->has_eu_pg = sseu->eu_per_subslice > 2; > > > > if (IS_GEN9_LP(dev_priv)) { > > @@ -477,7 +517,7 @@ static void broadwell_sseu_info_init(struct > > drm_i915_private *dev_priv) > > eu_disabled_mask = > > eu_disable[s] >> (ss * sseu- > > >max_eus_per_subslice); > > > > - sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); > > + intel_sseu_set_eus(sseu, s, ss, > > ~eu_disabled_mask); > > > > n_disabled = hweight8(eu_disabled_mask); > > > > @@ -496,9 +536,10 @@ static void broadwell_sseu_info_init(struct > > drm_i915_private *dev_priv) > > * subslices with the exception that any one EU in any one > > subslice may > > * be fused off for die recovery. > > */ > > - sseu->eu_per_subslice = sseu_subslice_total(sseu) ? > > + sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? > > DIV_ROUND_UP(sseu->eu_total, > > - sseu_subslice_total(sseu)) > > : 0; > > + intel_sseu_subslice_total( > > sseu)) : > > + 0; > > > > /* > > * BDW supports slice power gating on devices with more than > > @@ -561,8 +602,8 @@ static void haswell_sseu_info_init(struct > > drm_i915_private *dev_priv) > > > > for (s = 0; s < sseu->max_slices; s++) { > > for (ss = 0; ss < sseu->max_subslices; ss++) { > > - sseu_set_eus(sseu, s, ss, > > - (1UL << sseu->eu_per_subslice) - > > 1); > > + intel_sseu_set_eus(sseu, s, ss, > > + (1UL << sseu- > > >eu_per_subslice) - 1); > > } > > } > > > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h > > b/drivers/gpu/drm/i915/intel_device_info.h > > index 9d43f7edfd63..6412a9c72898 100644 > > --- a/drivers/gpu/drm/i915/intel_device_info.h > > +++ b/drivers/gpu/drm/i915/intel_device_info.h > > @@ -218,50 +218,6 @@ struct intel_driver_caps { > > bool has_logical_contexts:1; > > }; > > > > -static inline unsigned int sseu_subslice_total(const struct > > sseu_dev_info *sseu) > > -{ > > - unsigned int i, total = 0; > > - > > - for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++) > > - total += hweight8(sseu->subslice_mask[i]); > > - > > - return total; > > -} > > - > > -static inline int sseu_eu_idx(const struct sseu_dev_info *sseu, > > - int slice, int subslice) > > -{ > > - int subslice_stride = GEN_SSEU_STRIDE(sseu- > > >max_eus_per_subslice); > > - int slice_stride = sseu->max_subslices * subslice_stride; > > - > > - return slice * slice_stride + subslice * subslice_stride; > > -} > > - > > -static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu, > > - int slice, int subslice) > > -{ > > - int i, offset = sseu_eu_idx(sseu, slice, subslice); > > - u16 eu_mask = 0; > > - > > - for (i = 0; i < GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); > > i++) { > > - eu_mask |= ((u16) sseu->eu_mask[offset + i]) << > > - (i * BITS_PER_BYTE); > > - } > > - > > - return eu_mask; > > -} > > - > > -static inline void sseu_set_eus(struct sseu_dev_info *sseu, > > - int slice, int subslice, u16 eu_mask) > > -{ > > - int i, offset = sseu_eu_idx(sseu, slice, subslice); > > - > > - for (i = 0; i < GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); > > i++) { > > - sseu->eu_mask[offset + i] = > > - (eu_mask >> (BITS_PER_BYTE * i)) & 0xff; > > - } > > -} > > - > > const char *intel_platform_name(enum intel_platform platform); > > > > void intel_device_info_subplatform_init(struct drm_i915_private > > *dev_priv); > > [-- Attachment #1.2: smime.p7s --] [-- Type: application/x-pkcs7-signature, Size: 3270 bytes --] [-- Attachment #2: Type: text/plain, Size: 159 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 5/5] drm/i915: Expand subslice mask 2019-05-03 21:30 [PATCH 0/5] Refactor to expand subslice mask Stuart Summers ` (3 preceding siblings ...) 2019-05-03 21:30 ` [PATCH 4/5] drm/i915: Refactor sseu helper functions Stuart Summers @ 2019-05-03 21:30 ` Stuart Summers 2019-05-07 19:00 ` Daniele Ceraolo Spurio 2019-05-03 21:56 ` ✗ Fi.CI.CHECKPATCH: warning for Refactor to expand subslice mask (rev8) Patchwork ` (3 subsequent siblings) 8 siblings, 1 reply; 21+ messages in thread From: Stuart Summers @ 2019-05-03 21:30 UTC (permalink / raw) To: intel-gfx Currently, the subslice_mask runtime parameter is stored as an array of subslices per slice. Expand the subslice mask array to better match what is presented to userspace through the I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is then calculated: slice * subslice stride + subslice index / 8 v2: fix spacing in set_sseu_info args use set_sseu_info to initialize sseu data when building device status in debugfs rename variables in intel_engine_types.h to avoid checkpatch warnings v3: update headers in intel_sseu.h v4: add const to some sseu_dev_info variables use sseu->eu_stride for EU stride calculations v5: address review comments from Tvrtko and Daniele Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by: Stuart Summers <stuart.summers@intel.com> --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 24 ++- drivers/gpu/drm/i915/gt/intel_engine_types.h | 30 ++-- drivers/gpu/drm/i915/gt/intel_hangcheck.c | 3 +- drivers/gpu/drm/i915/gt/intel_sseu.c | 43 ++++- drivers/gpu/drm/i915/gt/intel_sseu.h | 28 +++- drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- drivers/gpu/drm/i915/i915_debugfs.c | 40 ++--- drivers/gpu/drm/i915/i915_drv.c | 6 +- drivers/gpu/drm/i915/i915_gpu_error.c | 5 +- drivers/gpu/drm/i915/i915_query.c | 10 +- drivers/gpu/drm/i915/intel_device_info.c | 155 ++++++++++--------- 11 files changed, 227 insertions(+), 119 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 5907a9613641..290bda5cc82b 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -909,12 +909,30 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type) } } +static inline u32 +intel_sseu_fls_subslice(const struct sseu_dev_info *sseu, u32 slice) +{ + u32 subslice; + int i; + + for (i = sseu->ss_stride - 1; i >= 0; i--) { + subslice = fls(sseu->subslice_mask[slice * sseu->ss_stride + + i]); + if (subslice) { + subslice += i * BITS_PER_BYTE; + break; + } + } + + return subslice; +} + u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv) { const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; u32 mcr_s_ss_select; u32 slice = fls(sseu->slice_mask); - u32 subslice = fls(sseu->subslice_mask[slice]); + u32 subslice = intel_sseu_fls_subslice(sseu, slice); if (IS_GEN(dev_priv, 10)) mcr_s_ss_select = GEN8_MCR_SLICE(slice) | @@ -990,6 +1008,7 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine, struct intel_instdone *instdone) { struct drm_i915_private *dev_priv = engine->i915; + const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; struct intel_uncore *uncore = engine->uncore; u32 mmio_base = engine->mmio_base; int slice; @@ -1007,7 +1026,8 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine, instdone->slice_common = intel_uncore_read(uncore, GEN7_SC_INSTDONE); - for_each_instdone_slice_subslice(dev_priv, slice, subslice) { + for_each_instdone_slice_subslice(dev_priv, sseu, slice, + subslice) { instdone->sampler[slice][subslice] = read_subslice_reg(dev_priv, slice, subslice, GEN7_SAMPLER_INSTDONE); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index c0ab11b12e14..582340b55144 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -535,20 +535,20 @@ intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine) return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET; } -#define instdone_slice_mask(dev_priv__) \ - (IS_GEN(dev_priv__, 7) ? \ - 1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask) - -#define instdone_subslice_mask(dev_priv__) \ - (IS_GEN(dev_priv__, 7) ? \ - 1 : RUNTIME_INFO(dev_priv__)->sseu.subslice_mask[0]) - -#define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \ - for ((slice__) = 0, (subslice__) = 0; \ - (slice__) < I915_MAX_SLICES; \ - (subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ? (subslice__) + 1 : 0, \ - (slice__) += ((subslice__) == 0)) \ - for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) && \ - (BIT(subslice__) & instdone_subslice_mask(dev_priv__))) +#define instdone_has_slice(dev_priv___, sseu___, slice___) \ + ((IS_GEN(dev_priv___, 7) ? 1 : ((sseu___)->slice_mask)) & \ + BIT(slice___)) + +#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \ + (IS_GEN(dev_priv__, 7) ? 1 : \ + intel_sseu_has_subslice(sseu__, slice__, subslice__)) + +#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \ + for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \ + (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \ + (slice_) += ((subslice_) == 0)) \ + for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \ + (instdone_has_subslice(dev_priv_, sseu_, slice_, \ + subslice_))) #endif /* __INTEL_ENGINE_TYPES_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_hangcheck.c b/drivers/gpu/drm/i915/gt/intel_hangcheck.c index 721ab74a382f..10e032c9ab10 100644 --- a/drivers/gpu/drm/i915/gt/intel_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/intel_hangcheck.c @@ -51,6 +51,7 @@ static bool instdone_unchanged(u32 current_instdone, u32 *old_instdone) static bool subunits_stuck(struct intel_engine_cs *engine) { struct drm_i915_private *dev_priv = engine->i915; + const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; struct intel_instdone instdone; struct intel_instdone *accu_instdone = &engine->hangcheck.instdone; bool stuck; @@ -72,7 +73,7 @@ static bool subunits_stuck(struct intel_engine_cs *engine) stuck &= instdone_unchanged(instdone.slice_common, &accu_instdone->slice_common); - for_each_instdone_slice_subslice(dev_priv, slice, subslice) { + for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice) { stuck &= instdone_unchanged(instdone.sampler[slice][subslice], &accu_instdone->sampler[slice][subslice]); stuck &= instdone_unchanged(instdone.row[slice][subslice], diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c index a0756f006f5f..a8b98b0266b7 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.c +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c @@ -8,6 +8,17 @@ #include "intel_lrc_reg.h" #include "intel_sseu.h" +void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices, + u8 max_subslices, u8 max_eus_per_subslice) +{ + sseu->max_slices = max_slices; + sseu->max_subslices = max_subslices; + sseu->max_eus_per_subslice = max_eus_per_subslice; + + sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices); + sseu->eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); +} + unsigned int intel_sseu_subslice_total(const struct sseu_dev_info *sseu) { @@ -19,10 +30,40 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu) return total; } +void intel_sseu_copy_subslices(const struct sseu_dev_info *sseu, int slice, + u8 *to_mask) +{ + int offset = slice * sseu->ss_stride; + + memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride); +} + +u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice) +{ + int i, offset = slice * sseu->ss_stride; + u32 mask; + + for (i = 0; i < sseu->ss_stride; i++) + mask |= (u32)sseu->subslice_mask[offset + i] << + i * BITS_PER_BYTE; + + return mask; +} + +void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice, + u32 ss_mask) +{ + int i, offset = slice * sseu->ss_stride; + + for (i = 0; i < sseu->ss_stride; i++) + sseu->subslice_mask[offset + i] = + (ss_mask >> (BITS_PER_BYTE * i)) & 0xff; +} + unsigned int intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice) { - return hweight8(sseu->subslice_mask[slice]); + return hweight32(intel_sseu_get_subslices(sseu, slice)); } u32 intel_sseu_make_rpcs(struct drm_i915_private *i915, diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h index b50d0401a4e2..3602ae54b937 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.h +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h @@ -9,16 +9,18 @@ #include <linux/types.h> #include <linux/kernel.h> +#include <linux/string.h> struct drm_i915_private; #define GEN_MAX_SLICES (6) /* CNL upper bound */ #define GEN_MAX_SUBSLICES (8) /* ICL upper bound */ #define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE) +#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES) struct sseu_dev_info { u8 slice_mask; - u8 subslice_mask[GEN_MAX_SLICES]; + u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE]; u16 eu_total; u8 eu_per_subslice; u8 min_eu_in_pool; @@ -33,6 +35,9 @@ struct sseu_dev_info { u8 max_subslices; u8 max_eus_per_subslice; + u8 ss_stride; + u8 eu_stride; + /* We don't have more than 8 eus per subslice at the moment and as we * store eus enabled using bits, no need to multiply by eus per * subslice. @@ -63,12 +68,33 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu) return value; } +static inline bool +intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice, + int subslice) +{ + u8 mask = sseu->subslice_mask[slice * sseu->ss_stride + + subslice / BITS_PER_BYTE]; + + return mask & BIT(subslice % BITS_PER_BYTE); +} + +void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices, + u8 max_subslices, u8 max_eus_per_subslice); + unsigned int intel_sseu_subslice_total(const struct sseu_dev_info *sseu); unsigned int intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice); +void intel_sseu_copy_subslices(const struct sseu_dev_info *sseu, int slice, + u8 *to_mask); + +u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice); + +void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice, + u32 ss_mask); + u32 intel_sseu_make_rpcs(struct drm_i915_private *i915, const struct intel_sseu *req_sseu); diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 43e290306551..8437f9d918ec 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -767,7 +767,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) u32 slice = fls(sseu->slice_mask); u32 fuse3 = intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3); - u8 ss_mask = sseu->subslice_mask[slice]; + u32 ss_mask = intel_sseu_get_subslices(sseu, slice); u8 enabled_mask = (ss_mask | ss_mask >> GEN10_L3BANK_PAIR_COUNT) & GEN10_L3BANK_MASK; diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index fce3ccd87f76..22ac2db98dde 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1259,6 +1259,7 @@ static void i915_instdone_info(struct drm_i915_private *dev_priv, struct seq_file *m, struct intel_instdone *instdone) { + struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; int slice; int subslice; @@ -1274,11 +1275,11 @@ static void i915_instdone_info(struct drm_i915_private *dev_priv, if (INTEL_GEN(dev_priv) <= 6) return; - for_each_instdone_slice_subslice(dev_priv, slice, subslice) + for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice) seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n", slice, subslice, instdone->sampler[slice][subslice]); - for_each_instdone_slice_subslice(dev_priv, slice, subslice) + for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice) seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n", slice, subslice, instdone->row[slice][subslice]); } @@ -4068,7 +4069,7 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv, continue; sseu->slice_mask |= BIT(s); - sseu->subslice_mask[s] = info->sseu.subslice_mask[s]; + intel_sseu_copy_subslices(&info->sseu, s, sseu->subslice_mask); for (ss = 0; ss < info->sseu.max_subslices; ss++) { unsigned int eu_cnt; @@ -4119,18 +4120,21 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, sseu->slice_mask |= BIT(s); if (IS_GEN9_BC(dev_priv)) - sseu->subslice_mask[s] = - RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s]; + intel_sseu_copy_subslices(&info->sseu, s, + sseu->subslice_mask); for (ss = 0; ss < info->sseu.max_subslices; ss++) { unsigned int eu_cnt; + u8 ss_idx = s * info->sseu.ss_stride + + ss / BITS_PER_BYTE; if (IS_GEN9_LP(dev_priv)) { if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) /* skip disabled subslice */ continue; - sseu->subslice_mask[s] |= BIT(ss); + sseu->subslice_mask[ss_idx] |= + BIT(ss % BITS_PER_BYTE); } eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & @@ -4147,25 +4151,23 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv, struct sseu_dev_info *sseu) { + struct intel_runtime_info *info = RUNTIME_INFO(dev_priv); u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); int s; sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK; if (sseu->slice_mask) { - sseu->eu_per_subslice = - RUNTIME_INFO(dev_priv)->sseu.eu_per_subslice; - for (s = 0; s < fls(sseu->slice_mask); s++) { - sseu->subslice_mask[s] = - RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s]; - } + sseu->eu_per_subslice = info->sseu.eu_per_subslice; + for (s = 0; s < fls(sseu->slice_mask); s++) + intel_sseu_copy_subslices(&info->sseu, s, + sseu->subslice_mask); sseu->eu_total = sseu->eu_per_subslice * intel_sseu_subslice_total(sseu); /* subtract fused off EU(s) from enabled slice(s) */ for (s = 0; s < fls(sseu->slice_mask); s++) { - u8 subslice_7eu = - RUNTIME_INFO(dev_priv)->sseu.subslice_7eu[s]; + u8 subslice_7eu = info->sseu.subslice_7eu[s]; sseu->eu_total -= hweight8(subslice_7eu); } @@ -4212,6 +4214,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info, static int i915_sseu_status(struct seq_file *m, void *unused) { struct drm_i915_private *dev_priv = node_to_i915(m->private); + const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv); struct sseu_dev_info sseu; intel_wakeref_t wakeref; @@ -4219,14 +4222,13 @@ static int i915_sseu_status(struct seq_file *m, void *unused) return -ENODEV; seq_puts(m, "SSEU Device Info\n"); - i915_print_sseu_info(m, true, &RUNTIME_INFO(dev_priv)->sseu); + i915_print_sseu_info(m, true, &info->sseu); seq_puts(m, "SSEU Device Status\n"); memset(&sseu, 0, sizeof(sseu)); - sseu.max_slices = RUNTIME_INFO(dev_priv)->sseu.max_slices; - sseu.max_subslices = RUNTIME_INFO(dev_priv)->sseu.max_subslices; - sseu.max_eus_per_subslice = - RUNTIME_INFO(dev_priv)->sseu.max_eus_per_subslice; + intel_sseu_set_info(&sseu, info->sseu.max_slices, + info->sseu.max_subslices, + info->sseu.max_eus_per_subslice); with_intel_runtime_pm(dev_priv, wakeref) { if (IS_CHERRYVIEW(dev_priv)) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index c2ea3f0992b2..c3432b5f9d4b 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -330,7 +330,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data, struct pci_dev *pdev = dev_priv->drm.pdev; const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; drm_i915_getparam_t *param = data; - int value; + int value = 0; switch (param->param) { case I915_PARAM_IRQ_ACTIVE: @@ -459,7 +459,9 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data, return -ENODEV; break; case I915_PARAM_SUBSLICE_MASK: - value = sseu->subslice_mask[0]; + /* Only copy bits from the first slice */ + memcpy(&value, sseu->subslice_mask, + min(sseu->ss_stride, (u8)sizeof(value))); if (!value) return -ENODEV; break; diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 4f85cbdddb0d..c760cc5b3388 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -408,6 +408,7 @@ static void print_error_buffers(struct drm_i915_error_state_buf *m, static void error_print_instdone(struct drm_i915_error_state_buf *m, const struct drm_i915_error_engine *ee) { + struct sseu_dev_info *sseu = &RUNTIME_INFO(m->i915)->sseu; int slice; int subslice; @@ -423,12 +424,12 @@ static void error_print_instdone(struct drm_i915_error_state_buf *m, if (INTEL_GEN(m->i915) <= 6) return; - for_each_instdone_slice_subslice(m->i915, slice, subslice) + for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", slice, subslice, ee->instdone.sampler[slice][subslice]); - for_each_instdone_slice_subslice(m->i915, slice, subslice) + for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n", slice, subslice, ee->instdone.row[slice][subslice]); diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c index 7c1708c22811..000dcb145ce0 100644 --- a/drivers/gpu/drm/i915/i915_query.c +++ b/drivers/gpu/drm/i915/i915_query.c @@ -37,8 +37,6 @@ static int query_topology_info(struct drm_i915_private *dev_priv, const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; struct drm_i915_query_topology_info topo; u32 slice_length, subslice_length, eu_length, total_length; - u8 subslice_stride = GEN_SSEU_STRIDE(sseu->max_subslices); - u8 eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); int ret; if (query_item->flags != 0) @@ -50,8 +48,8 @@ static int query_topology_info(struct drm_i915_private *dev_priv, BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask)); slice_length = sizeof(sseu->slice_mask); - subslice_length = sseu->max_slices * subslice_stride; - eu_length = sseu->max_slices * sseu->max_subslices * eu_stride; + subslice_length = sseu->max_slices * sseu->ss_stride; + eu_length = sseu->max_slices * sseu->max_subslices * sseu->eu_stride; total_length = sizeof(topo) + slice_length + subslice_length + eu_length; @@ -69,9 +67,9 @@ static int query_topology_info(struct drm_i915_private *dev_priv, topo.max_eus_per_subslice = sseu->max_eus_per_subslice; topo.subslice_offset = slice_length; - topo.subslice_stride = subslice_stride; + topo.subslice_stride = sseu->ss_stride; topo.eu_offset = slice_length + subslice_length; - topo.eu_stride = eu_stride; + topo.eu_stride = sseu->eu_stride; if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr), &topo, sizeof(topo))) diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 689702b28e80..b72505a192a0 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -84,17 +84,46 @@ void intel_device_info_dump_flags(const struct intel_device_info *info, #undef PRINT_FLAG } +#define SS_STR_MAX_SIZE (GEN_MAX_SUBSLICE_STRIDE * 2 + 1) + +static char * +subslice_per_slice_str(char *buf, u8 size, const struct sseu_dev_info *sseu, + u8 slice) +{ + int i; + u8 ss_offset = slice * sseu->ss_stride; + + GEM_BUG_ON(slice >= sseu->max_slices); + + /* Two ASCII character hex plus null terminator */ + GEM_BUG_ON(size < sseu->ss_stride * 2 + 1); + + memset(buf, 0, size); + + /* + * Print subslice information in reverse order to match + * userspace expectations. + */ + for (i = 0; i < sseu->ss_stride; i++) + sprintf(&buf[i * 2], "%02x", + sseu->subslice_mask[ss_offset + sseu->ss_stride - + (i + 1)]); + + return buf; +} + static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p) { int s; + char buf[SS_STR_MAX_SIZE]; drm_printf(p, "slice total: %u, mask=%04x\n", hweight8(sseu->slice_mask), sseu->slice_mask); drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu)); for (s = 0; s < sseu->max_slices; s++) { - drm_printf(p, "slice%d: %u subslices, mask=%04x\n", + drm_printf(p, "slice%d: %u subslices, mask=%s\n", s, intel_sseu_subslices_per_slice(sseu, s), - sseu->subslice_mask[s]); + subslice_per_slice_str(buf, ARRAY_SIZE(buf), sseu, s)); } drm_printf(p, "EU total: %u\n", sseu->eu_total); drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice); @@ -117,11 +146,9 @@ void intel_device_info_dump_runtime(const struct intel_runtime_info *info, static int intel_sseu_eu_idx(const struct sseu_dev_info *sseu, int slice, int subslice) { - int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice, - BITS_PER_BYTE); - int slice_stride = sseu->max_subslices * subslice_stride; + int slice_stride = sseu->max_subslices * sseu->eu_stride; - return slice * slice_stride + subslice * subslice_stride; + return slice * slice_stride + subslice * sseu->eu_stride; } static u16 intel_sseu_get_eus(const struct sseu_dev_info *sseu, int slice, @@ -130,8 +157,7 @@ static u16 intel_sseu_get_eus(const struct sseu_dev_info *sseu, int slice, int i, offset = intel_sseu_eu_idx(sseu, slice, subslice); u16 eu_mask = 0; - for (i = 0; - i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) { + for (i = 0; i < sseu->eu_stride; i++) { eu_mask |= ((u16)sseu->eu_mask[offset + i]) << (i * BITS_PER_BYTE); } @@ -144,8 +170,7 @@ static void intel_sseu_set_eus(struct sseu_dev_info *sseu, int slice, { int i, offset = intel_sseu_eu_idx(sseu, slice, subslice); - for (i = 0; - i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) { + for (i = 0; i < sseu->eu_stride; i++) { sseu->eu_mask[offset + i] = (eu_mask >> (BITS_PER_BYTE * i)) & 0xff; } @@ -155,6 +180,7 @@ void intel_device_info_dump_topology(const struct sseu_dev_info *sseu, struct drm_printer *p) { int s, ss; + char buf[SS_STR_MAX_SIZE]; if (sseu->max_slices == 0) { drm_printf(p, "Unavailable\n"); @@ -162,9 +188,9 @@ void intel_device_info_dump_topology(const struct sseu_dev_info *sseu, } for (s = 0; s < sseu->max_slices; s++) { - drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n", + drm_printf(p, "slice%d: %u subslice(s) (0x%s):\n", s, intel_sseu_subslices_per_slice(sseu, s), - sseu->subslice_mask[s]); + subslice_per_slice_str(buf, ARRAY_SIZE(buf), sseu, s)); for (ss = 0; ss < sseu->max_subslices; ss++) { u16 enabled_eus = intel_sseu_get_eus(sseu, s, ss); @@ -193,15 +219,10 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv) u8 eu_en; int s; - if (IS_ELKHARTLAKE(dev_priv)) { - sseu->max_slices = 1; - sseu->max_subslices = 4; - sseu->max_eus_per_subslice = 8; - } else { - sseu->max_slices = 1; - sseu->max_subslices = 8; - sseu->max_eus_per_subslice = 8; - } + if (IS_ELKHARTLAKE(dev_priv)) + intel_sseu_set_info(sseu, 1, 4, 8); + else + intel_sseu_set_info(sseu, 1, 8, 8); s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK; ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE); @@ -210,15 +231,15 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv) for (s = 0; s < sseu->max_slices; s++) { if (s_en & BIT(s)) { - int ss_idx = sseu->max_subslices * s; int ss; sseu->slice_mask |= BIT(s); - sseu->subslice_mask[s] = (ss_en >> ss_idx) & ss_en_mask; - for (ss = 0; ss < sseu->max_subslices; ss++) { - if (sseu->subslice_mask[s] & BIT(ss)) + + intel_sseu_set_subslices(sseu, s, ss_en_mask); + + for (ss = 0; ss < sseu->max_subslices; ss++) + if (intel_sseu_has_subslice(sseu, s, ss)) intel_sseu_set_eus(sseu, s, ss, eu_en); - } } } sseu->eu_per_subslice = hweight8(eu_en); @@ -238,23 +259,10 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv) const int eu_mask = 0xff; u32 subslice_mask, eu_en; + intel_sseu_set_info(sseu, 6, 4, 8); + sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >> GEN10_F2_S_ENA_SHIFT; - sseu->max_slices = 6; - sseu->max_subslices = 4; - sseu->max_eus_per_subslice = 8; - - subslice_mask = (1 << 4) - 1; - subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >> - GEN10_F2_SS_DIS_SHIFT); - - /* - * Slice0 can have up to 3 subslices, but there are only 2 in - * slice1/2. - */ - sseu->subslice_mask[0] = subslice_mask; - for (s = 1; s < sseu->max_slices; s++) - sseu->subslice_mask[s] = subslice_mask & 0x3; /* Slice0 */ eu_en = ~I915_READ(GEN8_EU_DISABLE0); @@ -279,14 +287,22 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv) eu_en = ~I915_READ(GEN10_EU_DISABLE3); intel_sseu_set_eus(sseu, 5, 1, eu_en & eu_mask); - /* Do a second pass where we mark the subslices disabled if all their - * eus are off. - */ + subslice_mask = (1 << 4) - 1; + subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >> + GEN10_F2_SS_DIS_SHIFT); + for (s = 0; s < sseu->max_slices; s++) { for (ss = 0; ss < sseu->max_subslices; ss++) { if (intel_sseu_get_eus(sseu, s, ss) == 0) - sseu->subslice_mask[s] &= ~BIT(ss); + subslice_mask &= ~BIT(ss); } + + /* + * Slice0 can have up to 3 subslices, but there are only 2 in + * slice1/2. + */ + intel_sseu_set_subslices(sseu, s, s == 0 ? subslice_mask : + subslice_mask & 0x3); } sseu->eu_total = compute_eu_total(sseu); @@ -312,13 +328,12 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) { struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; u32 fuse; + u8 subslice_mask; fuse = I915_READ(CHV_FUSE_GT); sseu->slice_mask = BIT(0); - sseu->max_slices = 1; - sseu->max_subslices = 2; - sseu->max_eus_per_subslice = 8; + intel_sseu_set_info(sseu, 1, 2, 8); if (!(fuse & CHV_FGT_DISABLE_SS0)) { u8 disabled_mask = @@ -327,7 +342,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >> CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4); - sseu->subslice_mask[0] |= BIT(0); + subslice_mask |= BIT(0); intel_sseu_set_eus(sseu, 0, 0, ~disabled_mask); } @@ -338,10 +353,12 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >> CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4); - sseu->subslice_mask[0] |= BIT(1); + subslice_mask |= BIT(1); intel_sseu_set_eus(sseu, 0, 1, ~disabled_mask); } + intel_sseu_set_subslices(sseu, 0, subslice_mask); + sseu->eu_total = compute_eu_total(sseu); /* @@ -374,9 +391,8 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; /* BXT has a single slice and at most 3 subslices. */ - sseu->max_slices = IS_GEN9_LP(dev_priv) ? 1 : 3; - sseu->max_subslices = IS_GEN9_LP(dev_priv) ? 3 : 4; - sseu->max_eus_per_subslice = 8; + intel_sseu_set_info(sseu, IS_GEN9_LP(dev_priv) ? 1 : 3, + IS_GEN9_LP(dev_priv) ? 3 : 4, 8); /* * The subslice disable field is global, i.e. it applies @@ -395,14 +411,14 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) /* skip disabled slice */ continue; - sseu->subslice_mask[s] = subslice_mask; + intel_sseu_set_subslices(sseu, s, subslice_mask); eu_disable = I915_READ(GEN9_EU_DISABLE(s)); for (ss = 0; ss < sseu->max_subslices; ss++) { int eu_per_ss; u8 eu_disabled_mask; - if (!(sseu->subslice_mask[s] & BIT(ss))) + if (!intel_sseu_has_subslice(sseu, s, ss)) /* skip disabled subslice */ continue; @@ -475,9 +491,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv) fuse2 = I915_READ(GEN8_FUSE2); sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; - sseu->max_slices = 3; - sseu->max_subslices = 3; - sseu->max_eus_per_subslice = 8; + intel_sseu_set_info(sseu, 3, 3, 8); /* * The subslice disable field is global, i.e. it applies @@ -504,18 +518,19 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv) /* skip disabled slice */ continue; - sseu->subslice_mask[s] = subslice_mask; + intel_sseu_set_subslices(sseu, s, subslice_mask); for (ss = 0; ss < sseu->max_subslices; ss++) { u8 eu_disabled_mask; u32 n_disabled; - if (!(sseu->subslice_mask[s] & BIT(ss))) + if (!intel_sseu_has_subslice(sseu, s, ss)) /* skip disabled subslice */ continue; eu_disabled_mask = - eu_disable[s] >> (ss * sseu->max_eus_per_subslice); + eu_disable[s] >> + (ss * sseu->max_eus_per_subslice); intel_sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); @@ -555,6 +570,7 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv) struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; u32 fuse1; int s, ss; + u32 subslice_mask; /* * There isn't a register to tell us how many slices/subslices. We @@ -566,22 +582,18 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv) /* fall through */ case 1: sseu->slice_mask = BIT(0); - sseu->subslice_mask[0] = BIT(0); + subslice_mask = BIT(0); break; case 2: sseu->slice_mask = BIT(0); - sseu->subslice_mask[0] = BIT(0) | BIT(1); + subslice_mask = BIT(0) | BIT(1); break; case 3: sseu->slice_mask = BIT(0) | BIT(1); - sseu->subslice_mask[0] = BIT(0) | BIT(1); - sseu->subslice_mask[1] = BIT(0) | BIT(1); + subslice_mask = BIT(0) | BIT(1); break; } - sseu->max_slices = hweight8(sseu->slice_mask); - sseu->max_subslices = hweight8(sseu->subslice_mask[0]); - fuse1 = I915_READ(HSW_PAVP_FUSE1); switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) { default: @@ -598,9 +610,14 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv) sseu->eu_per_subslice = 6; break; } - sseu->max_eus_per_subslice = sseu->eu_per_subslice; + + intel_sseu_set_info(sseu, hweight8(sseu->slice_mask), + hweight8(subslice_mask), + sseu->eu_per_subslice); for (s = 0; s < sseu->max_slices; s++) { + intel_sseu_set_subslices(sseu, s, subslice_mask); + for (ss = 0; ss < sseu->max_subslices; ss++) { intel_sseu_set_eus(sseu, s, ss, (1UL << sseu->eu_per_subslice) - 1); -- 2.21.0.5.gaeb582a983 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH 5/5] drm/i915: Expand subslice mask 2019-05-03 21:30 ` [PATCH 5/5] drm/i915: Expand subslice mask Stuart Summers @ 2019-05-07 19:00 ` Daniele Ceraolo Spurio 2019-05-07 20:48 ` Summers, Stuart 0 siblings, 1 reply; 21+ messages in thread From: Daniele Ceraolo Spurio @ 2019-05-07 19:00 UTC (permalink / raw) To: Stuart Summers, intel-gfx On 5/3/19 2:30 PM, Stuart Summers wrote: > Currently, the subslice_mask runtime parameter is stored as an > array of subslices per slice. Expand the subslice mask array to > better match what is presented to userspace through the > I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is > then calculated: > slice * subslice stride + subslice index / 8 > > v2: fix spacing in set_sseu_info args > use set_sseu_info to initialize sseu data when building > device status in debugfs > rename variables in intel_engine_types.h to avoid checkpatch > warnings > v3: update headers in intel_sseu.h > v4: add const to some sseu_dev_info variables > use sseu->eu_stride for EU stride calculations > v5: address review comments from Tvrtko and Daniele > > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> > Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> > Signed-off-by: Stuart Summers <stuart.summers@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 24 ++- > drivers/gpu/drm/i915/gt/intel_engine_types.h | 30 ++-- > drivers/gpu/drm/i915/gt/intel_hangcheck.c | 3 +- > drivers/gpu/drm/i915/gt/intel_sseu.c | 43 ++++- > drivers/gpu/drm/i915/gt/intel_sseu.h | 28 +++- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- > drivers/gpu/drm/i915/i915_debugfs.c | 40 ++--- > drivers/gpu/drm/i915/i915_drv.c | 6 +- > drivers/gpu/drm/i915/i915_gpu_error.c | 5 +- > drivers/gpu/drm/i915/i915_query.c | 10 +- > drivers/gpu/drm/i915/intel_device_info.c | 155 ++++++++++--------- > 11 files changed, 227 insertions(+), 119 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index 5907a9613641..290bda5cc82b 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -909,12 +909,30 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type) > } > } > > +static inline u32 > +intel_sseu_fls_subslice(const struct sseu_dev_info *sseu, u32 slice) > +{ > + u32 subslice; > + int i; > + > + for (i = sseu->ss_stride - 1; i >= 0; i--) { > + subslice = fls(sseu->subslice_mask[slice * sseu->ss_stride + > + i]); > + if (subslice) { > + subslice += i * BITS_PER_BYTE; > + break; > + } > + } > + > + return subslice; > +} > + > u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv) > { > const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; > u32 mcr_s_ss_select; > u32 slice = fls(sseu->slice_mask); > - u32 subslice = fls(sseu->subslice_mask[slice]); > + u32 subslice = intel_sseu_fls_subslice(sseu, slice); > > if (IS_GEN(dev_priv, 10)) > mcr_s_ss_select = GEN8_MCR_SLICE(slice) | > @@ -990,6 +1008,7 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine, > struct intel_instdone *instdone) > { > struct drm_i915_private *dev_priv = engine->i915; > + const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; > struct intel_uncore *uncore = engine->uncore; > u32 mmio_base = engine->mmio_base; > int slice; > @@ -1007,7 +1026,8 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine, > > instdone->slice_common = > intel_uncore_read(uncore, GEN7_SC_INSTDONE); > - for_each_instdone_slice_subslice(dev_priv, slice, subslice) { > + for_each_instdone_slice_subslice(dev_priv, sseu, slice, > + subslice) { > instdone->sampler[slice][subslice] = > read_subslice_reg(dev_priv, slice, subslice, > GEN7_SAMPLER_INSTDONE); > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h > index c0ab11b12e14..582340b55144 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h > +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h > @@ -535,20 +535,20 @@ intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine) > return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET; > } > > -#define instdone_slice_mask(dev_priv__) \ > - (IS_GEN(dev_priv__, 7) ? \ > - 1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask) > - > -#define instdone_subslice_mask(dev_priv__) \ > - (IS_GEN(dev_priv__, 7) ? \ > - 1 : RUNTIME_INFO(dev_priv__)->sseu.subslice_mask[0]) > - > -#define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \ > - for ((slice__) = 0, (subslice__) = 0; \ > - (slice__) < I915_MAX_SLICES; \ > - (subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ? (subslice__) + 1 : 0, \ > - (slice__) += ((subslice__) == 0)) \ > - for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) && \ > - (BIT(subslice__) & instdone_subslice_mask(dev_priv__))) > +#define instdone_has_slice(dev_priv___, sseu___, slice___) \ > + ((IS_GEN(dev_priv___, 7) ? 1 : ((sseu___)->slice_mask)) & \ > + BIT(slice___)) > + > +#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \ > + (IS_GEN(dev_priv__, 7) ? 1 : \ This will return true for all ss on gen7, while the original code returned 1 as the subslice mask (i.e. only has ss == 0). > + intel_sseu_has_subslice(sseu__, slice__, subslice__)) > + > +#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \ > + for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \ > + (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \ > + (slice_) += ((subslice_) == 0)) \ > + for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \ > + (instdone_has_subslice(dev_priv_, sseu_, slice_, \ > + subslice_))) > > #endif /* __INTEL_ENGINE_TYPES_H__ */ > diff --git a/drivers/gpu/drm/i915/gt/intel_hangcheck.c b/drivers/gpu/drm/i915/gt/intel_hangcheck.c > index 721ab74a382f..10e032c9ab10 100644 > --- a/drivers/gpu/drm/i915/gt/intel_hangcheck.c > +++ b/drivers/gpu/drm/i915/gt/intel_hangcheck.c > @@ -51,6 +51,7 @@ static bool instdone_unchanged(u32 current_instdone, u32 *old_instdone) > static bool subunits_stuck(struct intel_engine_cs *engine) > { > struct drm_i915_private *dev_priv = engine->i915; > + const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; > struct intel_instdone instdone; > struct intel_instdone *accu_instdone = &engine->hangcheck.instdone; > bool stuck; > @@ -72,7 +73,7 @@ static bool subunits_stuck(struct intel_engine_cs *engine) > stuck &= instdone_unchanged(instdone.slice_common, > &accu_instdone->slice_common); > > - for_each_instdone_slice_subslice(dev_priv, slice, subslice) { > + for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice) { > stuck &= instdone_unchanged(instdone.sampler[slice][subslice], > &accu_instdone->sampler[slice][subslice]); > stuck &= instdone_unchanged(instdone.row[slice][subslice], > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c > index a0756f006f5f..a8b98b0266b7 100644 > --- a/drivers/gpu/drm/i915/gt/intel_sseu.c > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c > @@ -8,6 +8,17 @@ > #include "intel_lrc_reg.h" > #include "intel_sseu.h" > > +void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices, > + u8 max_subslices, u8 max_eus_per_subslice) > +{ > + sseu->max_slices = max_slices; > + sseu->max_subslices = max_subslices; > + sseu->max_eus_per_subslice = max_eus_per_subslice; > + > + sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices); > + sseu->eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); > +} > + > unsigned int > intel_sseu_subslice_total(const struct sseu_dev_info *sseu) > { > @@ -19,10 +30,40 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu) > return total; > } > > +void intel_sseu_copy_subslices(const struct sseu_dev_info *sseu, int slice, > + u8 *to_mask) > +{ > + int offset = slice * sseu->ss_stride; > + > + memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride); > +} > + > +u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice) nitpick: extra space > +{ > + int i, offset = slice * sseu->ss_stride; > + u32 mask; > + GEM_BUG_ON(sseu->ss_stride > size(u32)) to catch the unlikely case we go over and need to update the mask size? > + for (i = 0; i < sseu->ss_stride; i++) > + mask |= (u32)sseu->subslice_mask[offset + i] << > + i * BITS_PER_BYTE; > + > + return mask; > +} > + > +void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice, > + u32 ss_mask) > +{ > + int i, offset = slice * sseu->ss_stride; > + > + for (i = 0; i < sseu->ss_stride; i++) > + sseu->subslice_mask[offset + i] = > + (ss_mask >> (BITS_PER_BYTE * i)) & 0xff; > +} > + > unsigned int > intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice) > { > - return hweight8(sseu->subslice_mask[slice]); > + return hweight32(intel_sseu_get_subslices(sseu, slice)); > } > > u32 intel_sseu_make_rpcs(struct drm_i915_private *i915, <snip> > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -84,17 +84,46 @@ void intel_device_info_dump_flags(const struct intel_device_info *info, > #undef PRINT_FLAG > } > > +#define SS_STR_MAX_SIZE (GEN_MAX_SUBSLICE_STRIDE * 2 + 1) > + > +static char * > +subslice_per_slice_str(char *buf, u8 size, const struct sseu_dev_info *sseu, > + u8 slice) > +{ > + int i; > + u8 ss_offset = slice * sseu->ss_stride; > + > + GEM_BUG_ON(slice >= sseu->max_slices); > + > + /* Two ASCII character hex plus null terminator */ > + GEM_BUG_ON(size < sseu->ss_stride * 2 + 1); > + > + memset(buf, 0, size); > + > + /* > + * Print subslice information in reverse order to match > + * userspace expectations. > + */ > + for (i = 0; i < sseu->ss_stride; i++) > + sprintf(&buf[i * 2], "%02x", > + sseu->subslice_mask[ss_offset + sseu->ss_stride - > + (i + 1)]); > + > + return buf; > +} > + > static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p) > { > int s; > + char buf[SS_STR_MAX_SIZE]; > > drm_printf(p, "slice total: %u, mask=%04x\n", > hweight8(sseu->slice_mask), sseu->slice_mask); > drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu)); > for (s = 0; s < sseu->max_slices; s++) { > - drm_printf(p, "slice%d: %u subslices, mask=%04x\n", > + drm_printf(p, "slice%d: %u subslices, mask=%s\n", > s, intel_sseu_subslices_per_slice(sseu, s), > - sseu->subslice_mask[s]); > + subslice_per_slice_str(buf, ARRAY_SIZE(buf), sseu, s)); Now that we have intel_sseu_get_subslices() can't we just print the return from that instead of using the buffer? > } > drm_printf(p, "EU total: %u\n", sseu->eu_total); > drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice); <snip> > @@ -555,6 +570,7 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv) > struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; > u32 fuse1; > int s, ss; > + u32 subslice_mask; > > /* > * There isn't a register to tell us how many slices/subslices. We > @@ -566,22 +582,18 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv) > /* fall through */ > case 1: > sseu->slice_mask = BIT(0); > - sseu->subslice_mask[0] = BIT(0); > + subslice_mask = BIT(0); > break; > case 2: > sseu->slice_mask = BIT(0); > - sseu->subslice_mask[0] = BIT(0) | BIT(1); > + subslice_mask = BIT(0) | BIT(1); > break; > case 3: > sseu->slice_mask = BIT(0) | BIT(1); > - sseu->subslice_mask[0] = BIT(0) | BIT(1); > - sseu->subslice_mask[1] = BIT(0) | BIT(1); > + subslice_mask = BIT(0) | BIT(1); > break; > } > > - sseu->max_slices = hweight8(sseu->slice_mask); > - sseu->max_subslices = hweight8(sseu->subslice_mask[0]); > - > fuse1 = I915_READ(HSW_PAVP_FUSE1); > switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) { > default: > @@ -598,9 +610,14 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv) > sseu->eu_per_subslice = 6; > break; > } > - sseu->max_eus_per_subslice = sseu->eu_per_subslice; > + > + intel_sseu_set_info(sseu, hweight8(sseu->slice_mask), > + hweight8(subslice_mask), > + sseu->eu_per_subslice); I'd still prefer this to use a local variable so that we always only set sseu->eu_per_subslice from within intel_sseu_set_info. Daniele > > for (s = 0; s < sseu->max_slices; s++) { > + intel_sseu_set_subslices(sseu, s, subslice_mask); > + > for (ss = 0; ss < sseu->max_subslices; ss++) { > intel_sseu_set_eus(sseu, s, ss, > (1UL << sseu->eu_per_subslice) - 1); > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 5/5] drm/i915: Expand subslice mask 2019-05-07 19:00 ` Daniele Ceraolo Spurio @ 2019-05-07 20:48 ` Summers, Stuart 2019-05-07 21:16 ` Daniele Ceraolo Spurio 0 siblings, 1 reply; 21+ messages in thread From: Summers, Stuart @ 2019-05-07 20:48 UTC (permalink / raw) To: Ceraolo Spurio, Daniele, intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 14992 bytes --] On Tue, 2019-05-07 at 12:00 -0700, Daniele Ceraolo Spurio wrote: > > On 5/3/19 2:30 PM, Stuart Summers wrote: > > Currently, the subslice_mask runtime parameter is stored as an > > array of subslices per slice. Expand the subslice mask array to > > better match what is presented to userspace through the > > I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is > > then calculated: > > slice * subslice stride + subslice index / 8 > > > > v2: fix spacing in set_sseu_info args > > use set_sseu_info to initialize sseu data when building > > device status in debugfs > > rename variables in intel_engine_types.h to avoid checkpatch > > warnings > > v3: update headers in intel_sseu.h > > v4: add const to some sseu_dev_info variables > > use sseu->eu_stride for EU stride calculations > > v5: address review comments from Tvrtko and Daniele > > > > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > > Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> > > Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> > > Signed-off-by: Stuart Summers <stuart.summers@intel.com> > > --- > > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 24 ++- > > drivers/gpu/drm/i915/gt/intel_engine_types.h | 30 ++-- > > drivers/gpu/drm/i915/gt/intel_hangcheck.c | 3 +- > > drivers/gpu/drm/i915/gt/intel_sseu.c | 43 ++++- > > drivers/gpu/drm/i915/gt/intel_sseu.h | 28 +++- > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- > > drivers/gpu/drm/i915/i915_debugfs.c | 40 ++--- > > drivers/gpu/drm/i915/i915_drv.c | 6 +- > > drivers/gpu/drm/i915/i915_gpu_error.c | 5 +- > > drivers/gpu/drm/i915/i915_query.c | 10 +- > > drivers/gpu/drm/i915/intel_device_info.c | 155 ++++++++++-- > > ------- > > 11 files changed, 227 insertions(+), 119 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > > index 5907a9613641..290bda5cc82b 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > > @@ -909,12 +909,30 @@ const char *i915_cache_level_str(struct > > drm_i915_private *i915, int type) > > } > > } > > > > +static inline u32 > > +intel_sseu_fls_subslice(const struct sseu_dev_info *sseu, u32 > > slice) > > +{ > > + u32 subslice; > > + int i; > > + > > + for (i = sseu->ss_stride - 1; i >= 0; i--) { > > + subslice = fls(sseu->subslice_mask[slice * sseu- > > >ss_stride + > > + i]); > > + if (subslice) { > > + subslice += i * BITS_PER_BYTE; > > + break; > > + } > > + } > > + > > + return subslice; > > +} > > + > > u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private > > *dev_priv) > > { > > const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)- > > >sseu; > > u32 mcr_s_ss_select; > > u32 slice = fls(sseu->slice_mask); > > - u32 subslice = fls(sseu->subslice_mask[slice]); > > + u32 subslice = intel_sseu_fls_subslice(sseu, slice); > > > > if (IS_GEN(dev_priv, 10)) > > mcr_s_ss_select = GEN8_MCR_SLICE(slice) | > > @@ -990,6 +1008,7 @@ void intel_engine_get_instdone(struct > > intel_engine_cs *engine, > > struct intel_instdone *instdone) > > { > > struct drm_i915_private *dev_priv = engine->i915; > > + const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)- > > >sseu; > > struct intel_uncore *uncore = engine->uncore; > > u32 mmio_base = engine->mmio_base; > > int slice; > > @@ -1007,7 +1026,8 @@ void intel_engine_get_instdone(struct > > intel_engine_cs *engine, > > > > instdone->slice_common = > > intel_uncore_read(uncore, GEN7_SC_INSTDONE); > > - for_each_instdone_slice_subslice(dev_priv, slice, > > subslice) { > > + for_each_instdone_slice_subslice(dev_priv, sseu, slice, > > + subslice) { > > instdone->sampler[slice][subslice] = > > read_subslice_reg(dev_priv, slice, > > subslice, > > GEN7_SAMPLER_INSTDONE > > ); > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h > > b/drivers/gpu/drm/i915/gt/intel_engine_types.h > > index c0ab11b12e14..582340b55144 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h > > @@ -535,20 +535,20 @@ intel_engine_needs_breadcrumb_tasklet(const > > struct intel_engine_cs *engine) > > return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET; > > } > > > > -#define instdone_slice_mask(dev_priv__) \ > > - (IS_GEN(dev_priv__, 7) ? \ > > - 1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask) > > - > > -#define instdone_subslice_mask(dev_priv__) \ > > - (IS_GEN(dev_priv__, 7) ? \ > > - 1 : RUNTIME_INFO(dev_priv__)->sseu.subslice_mask[0]) > > - > > -#define for_each_instdone_slice_subslice(dev_priv__, slice__, > > subslice__) \ > > - for ((slice__) = 0, (subslice__) = 0; \ > > - (slice__) < I915_MAX_SLICES; \ > > - (subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ? > > (subslice__) + 1 : 0, \ > > - (slice__) += ((subslice__) == 0)) \ > > - for_each_if((BIT(slice__) & > > instdone_slice_mask(dev_priv__)) && \ > > - (BIT(subslice__) & > > instdone_subslice_mask(dev_priv__))) > > +#define instdone_has_slice(dev_priv___, sseu___, slice___) \ > > + ((IS_GEN(dev_priv___, 7) ? 1 : ((sseu___)->slice_mask)) & \ > > + BIT(slice___)) > > + > > +#define instdone_has_subslice(dev_priv__, sseu__, slice__, > > subslice__) \ > > + (IS_GEN(dev_priv__, 7) ? 1 : \ > > This will return true for all ss on gen7, while the original code > returned 1 as the subslice mask (i.e. only has ss == 0). True, I'll fix this. > > > + intel_sseu_has_subslice(sseu__, slice__, subslice__)) > > + > > +#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, > > subslice_) \ > > + for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; > > \ > > + (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \ > > + (slice_) += ((subslice_) == 0)) \ > > + for_each_if((instdone_has_slice(dev_priv_, sseu_, > > slice_)) && \ > > + (irnstdone_has_subslice(dev_priv_, sseu_, > > slice_, \ > > + subslice_))) > > > > #endif /* __INTEL_ENGINE_TYPES_H__ */ > > diff --git a/drivers/gpu/drm/i915/gt/intel_hangcheck.c > > b/drivers/gpu/drm/i915/gt/intel_hangcheck.c > > index 721ab74a382f..10e032c9ab10 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_hangcheck.c > > +++ b/drivers/gpu/drm/i915/gt/intel_hangcheck.c > > @@ -51,6 +51,7 @@ static bool instdone_unchanged(u32 > > current_instdone, u32 *old_instdone) > > static bool subunits_stuck(struct intel_engine_cs *engine) > > { > > struct drm_i915_private *dev_priv = engine->i915; > > + const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)- > > >sseu; > > struct intel_instdone instdone; > > struct intel_instdone *accu_instdone = &engine- > > >hangcheck.instdone; > > bool stuck; > > @@ -72,7 +73,7 @@ static bool subunits_stuck(struct intel_engine_cs > > *engine) > > stuck &= instdone_unchanged(instdone.slice_common, > > &accu_instdone->slice_common); > > > > - for_each_instdone_slice_subslice(dev_priv, slice, subslice) { > > + for_each_instdone_slice_subslice(dev_priv, sseu, slice, > > subslice) { > > stuck &= > > instdone_unchanged(instdone.sampler[slice][subslice], > > &accu_instdone- > > >sampler[slice][subslice]); > > stuck &= > > instdone_unchanged(instdone.row[slice][subslice], > > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c > > b/drivers/gpu/drm/i915/gt/intel_sseu.c > > index a0756f006f5f..a8b98b0266b7 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_sseu.c > > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c > > @@ -8,6 +8,17 @@ > > #include "intel_lrc_reg.h" > > #include "intel_sseu.h" > > > > +void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 > > max_slices, > > + u8 max_subslices, u8 max_eus_per_subslice) > > +{ > > + sseu->max_slices = max_slices; > > + sseu->max_subslices = max_subslices; > > + sseu->max_eus_per_subslice = max_eus_per_subslice; > > + > > + sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices); > > + sseu->eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); > > +} > > + > > unsigned int > > intel_sseu_subslice_total(const struct sseu_dev_info *sseu) > > { > > @@ -19,10 +30,40 @@ intel_sseu_subslice_total(const struct > > sseu_dev_info *sseu) > > return total; > > } > > > > +void intel_sseu_copy_subslices(const struct sseu_dev_info *sseu, > > int slice, > > + u8 *to_mask) > > +{ > > + int offset = slice * sseu->ss_stride; > > + > > + memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu- > > >ss_stride); > > +} > > + > > +u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 > > slice) > > nitpick: extra space Ok. > > > +{ > > + int i, offset = slice * sseu->ss_stride; > > + u32 mask; > > + > > GEM_BUG_ON(sseu->ss_stride > size(u32)) to catch the unlikely case we > go > over and need to update the mask size? Makes sense. I'll add this. > > > + for (i = 0; i < sseu->ss_stride; i++) > > + mask |= (u32)sseu->subslice_mask[offset + i] << > > + i * BITS_PER_BYTE; > > + > > + return mask; > > +} > > + > > +void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int > > slice, > > + u32 ss_mask) > > +{ > > + int i, offset = slice * sseu->ss_stride; > > + > > + for (i = 0; i < sseu->ss_stride; i++) > > + sseu->subslice_mask[offset + i] = > > + (ss_mask >> (BITS_PER_BYTE * i)) & 0xff; > > +} > > + > > unsigned int > > intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, > > u8 slice) > > { > > - return hweight8(sseu->subslice_mask[slice]); > > + return hweight32(intel_sseu_get_subslices(sseu, slice)); > > } > > > > u32 intel_sseu_make_rpcs(struct drm_i915_private *i915, > > <snip> > > > --- a/drivers/gpu/drm/i915/intel_device_info.c > > +++ b/drivers/gpu/drm/i915/intel_device_info.c > > @@ -84,17 +84,46 @@ void intel_device_info_dump_flags(const struct > > intel_device_info *info, > > #undef PRINT_FLAG > > } > > > > +#define SS_STR_MAX_SIZE (GEN_MAX_SUBSLICE_STRIDE * 2 + 1) > > + > > +static char * > > +subslice_per_slice_str(char *buf, u8 size, const struct > > sseu_dev_info *sseu, > > + u8 slice) > > +{ > > + int i; > > + u8 ss_offset = slice * sseu->ss_stride; > > + > > + GEM_BUG_ON(slice >= sseu->max_slices); > > + > > + /* Two ASCII character hex plus null terminator */ > > + GEM_BUG_ON(size < sseu->ss_stride * 2 + 1); > > + > > + memset(buf, 0, size); > > + > > + /* > > + * Print subslice information in reverse order to match > > + * userspace expectations. > > + */ > > + for (i = 0; i < sseu->ss_stride; i++) > > + sprintf(&buf[i * 2], "%02x", > > + sseu->subslice_mask[ss_offset + sseu->ss_stride > > - > > + (i + 1)]); > > + > > + return buf; > > +} > > + > > static void sseu_dump(const struct sseu_dev_info *sseu, struct > > drm_printer *p) > > { > > int s; > > + char buf[SS_STR_MAX_SIZE]; > > > > drm_printf(p, "slice total: %u, mask=%04x\n", > > hweight8(sseu->slice_mask), sseu->slice_mask); > > drm_printf(p, "subslice total: %u\n", > > intel_sseu_subslice_total(sseu)); > > for (s = 0; s < sseu->max_slices; s++) { > > - drm_printf(p, "slice%d: %u subslices, mask=%04x\n", > > + drm_printf(p, "slice%d: %u subslices, mask=%s\n", > > s, intel_sseu_subslices_per_slice(sseu, s), > > - sseu->subslice_mask[s]); > > + subslice_per_slice_str(buf, ARRAY_SIZE(buf), > > sseu, s)); > > Now that we have intel_sseu_get_subslices() can't we just print the > return from that instead of using the buffer? I personally would prefer we keep the stringify function as it gives a little more flexibility. Do you have a strong preference to move to a direct printk formatted string? > > > > } > > drm_printf(p, "EU total: %u\n", sseu->eu_total); > > drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice); > > <snip> > > > @@ -555,6 +570,7 @@ static void haswell_sseu_info_init(struct > > drm_i915_private *dev_priv) > > struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; > > u32 fuse1; > > int s, ss; > > + u32 subslice_mask; > > > > /* > > * There isn't a register to tell us how many slices/subslices. > > We > > @@ -566,22 +582,18 @@ static void haswell_sseu_info_init(struct > > drm_i915_private *dev_priv) > > /* fall through */ > > case 1: > > sseu->slice_mask = BIT(0); > > - sseu->subslice_mask[0] = BIT(0); > > + subslice_mask = BIT(0); > > break; > > case 2: > > sseu->slice_mask = BIT(0); > > - sseu->subslice_mask[0] = BIT(0) | BIT(1); > > + subslice_mask = BIT(0) | BIT(1); > > break; > > case 3: > > sseu->slice_mask = BIT(0) | BIT(1); > > - sseu->subslice_mask[0] = BIT(0) | BIT(1); > > - sseu->subslice_mask[1] = BIT(0) | BIT(1); > > + subslice_mask = BIT(0) | BIT(1); > > break; > > } > > > > - sseu->max_slices = hweight8(sseu->slice_mask); > > - sseu->max_subslices = hweight8(sseu->subslice_mask[0]); > > - > > fuse1 = I915_READ(HSW_PAVP_FUSE1); > > switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) { > > default: > > @@ -598,9 +610,14 @@ static void haswell_sseu_info_init(struct > > drm_i915_private *dev_priv) > > sseu->eu_per_subslice = 6; > > break; > > } > > - sseu->max_eus_per_subslice = sseu->eu_per_subslice; > > + > > + intel_sseu_set_info(sseu, hweight8(sseu->slice_mask), > > + hweight8(subslice_mask), > > + sseu->eu_per_subslice); > > I'd still prefer this to use a local variable so that we always only > set > sseu->eu_per_subslice from within intel_sseu_set_info. So the reason I kept this is in intel_sseu_set_info we are really just setting the max_eus_per_subslice, not the eu_per_subslice. Are you saying you'd also like to move the code that sets eu_per_subslice in each generation's handler to local variables and/or just passed directly as an argument to intel_sseu_set_info? I.e. should we use intel_sseu_set_info to set most or all of the members of the intel_sseu structure? Or is it OK to keep the current implementation of only using this to set default maximums per platform? -Stuart > > Daniele > > > > > for (s = 0; s < sseu->max_slices; s++) { > > + intel_sseu_set_subslices(sseu, s, subslice_mask); > > + > > for (ss = 0; ss < sseu->max_subslices; ss++) { > > intel_sseu_set_eus(sseu, s, ss, > > (1UL << sseu- > > >eu_per_subslice) - 1); > > [-- Attachment #1.2: smime.p7s --] [-- Type: application/x-pkcs7-signature, Size: 3270 bytes --] [-- Attachment #2: Type: text/plain, Size: 159 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 5/5] drm/i915: Expand subslice mask 2019-05-07 20:48 ` Summers, Stuart @ 2019-05-07 21:16 ` Daniele Ceraolo Spurio 2019-05-07 21:19 ` Summers, Stuart 0 siblings, 1 reply; 21+ messages in thread From: Daniele Ceraolo Spurio @ 2019-05-07 21:16 UTC (permalink / raw) To: Summers, Stuart, intel-gfx <snip> >> >>> --- a/drivers/gpu/drm/i915/intel_device_info.c >>> +++ b/drivers/gpu/drm/i915/intel_device_info.c >>> @@ -84,17 +84,46 @@ void intel_device_info_dump_flags(const struct >>> intel_device_info *info, >>> #undef PRINT_FLAG >>> } >>> >>> +#define SS_STR_MAX_SIZE (GEN_MAX_SUBSLICE_STRIDE * 2 + 1) >>> + >>> +static char * >>> +subslice_per_slice_str(char *buf, u8 size, const struct >>> sseu_dev_info *sseu, >>> + u8 slice) >>> +{ >>> + int i; >>> + u8 ss_offset = slice * sseu->ss_stride; >>> + >>> + GEM_BUG_ON(slice >= sseu->max_slices); >>> + >>> + /* Two ASCII character hex plus null terminator */ >>> + GEM_BUG_ON(size < sseu->ss_stride * 2 + 1); >>> + >>> + memset(buf, 0, size); >>> + >>> + /* >>> + * Print subslice information in reverse order to match >>> + * userspace expectations. >>> + */ >>> + for (i = 0; i < sseu->ss_stride; i++) >>> + sprintf(&buf[i * 2], "%02x", >>> + sseu->subslice_mask[ss_offset + sseu->ss_stride >>> - >>> + (i + 1)]); >>> + >>> + return buf; >>> +} >>> + >>> static void sseu_dump(const struct sseu_dev_info *sseu, struct >>> drm_printer *p) >>> { >>> int s; >>> + char buf[SS_STR_MAX_SIZE]; >>> >>> drm_printf(p, "slice total: %u, mask=%04x\n", >>> hweight8(sseu->slice_mask), sseu->slice_mask); >>> drm_printf(p, "subslice total: %u\n", >>> intel_sseu_subslice_total(sseu)); >>> for (s = 0; s < sseu->max_slices; s++) { >>> - drm_printf(p, "slice%d: %u subslices, mask=%04x\n", >>> + drm_printf(p, "slice%d: %u subslices, mask=%s\n", >>> s, intel_sseu_subslices_per_slice(sseu, s), >>> - sseu->subslice_mask[s]); >>> + subslice_per_slice_str(buf, ARRAY_SIZE(buf), >>> sseu, s)); >> >> Now that we have intel_sseu_get_subslices() can't we just print the >> return from that instead of using the buffer? > > I personally would prefer we keep the stringify function as it gives a > little more flexibility. Do you have a strong preference to move to a > direct printk formatted string? > I do not, it just seemed like duplication since you're not really using any extra formatting or other flexibility in filling the buffer. This isn't a lot of code, so maybe we can switch to just using the u32 for now and add this back if/when we do require the flexibility? >> >> >>> } >>> drm_printf(p, "EU total: %u\n", sseu->eu_total); >>> drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice); >> >> <snip> >> >>> @@ -555,6 +570,7 @@ static void haswell_sseu_info_init(struct >>> drm_i915_private *dev_priv) >>> struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; >>> u32 fuse1; >>> int s, ss; >>> + u32 subslice_mask; >>> >>> /* >>> * There isn't a register to tell us how many slices/subslices. >>> We >>> @@ -566,22 +582,18 @@ static void haswell_sseu_info_init(struct >>> drm_i915_private *dev_priv) >>> /* fall through */ >>> case 1: >>> sseu->slice_mask = BIT(0); >>> - sseu->subslice_mask[0] = BIT(0); >>> + subslice_mask = BIT(0); >>> break; >>> case 2: >>> sseu->slice_mask = BIT(0); >>> - sseu->subslice_mask[0] = BIT(0) | BIT(1); >>> + subslice_mask = BIT(0) | BIT(1); >>> break; >>> case 3: >>> sseu->slice_mask = BIT(0) | BIT(1); >>> - sseu->subslice_mask[0] = BIT(0) | BIT(1); >>> - sseu->subslice_mask[1] = BIT(0) | BIT(1); >>> + subslice_mask = BIT(0) | BIT(1); >>> break; >>> } >>> >>> - sseu->max_slices = hweight8(sseu->slice_mask); >>> - sseu->max_subslices = hweight8(sseu->subslice_mask[0]); >>> - >>> fuse1 = I915_READ(HSW_PAVP_FUSE1); >>> switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) { >>> default: >>> @@ -598,9 +610,14 @@ static void haswell_sseu_info_init(struct >>> drm_i915_private *dev_priv) >>> sseu->eu_per_subslice = 6; >>> break; >>> } >>> - sseu->max_eus_per_subslice = sseu->eu_per_subslice; >>> + >>> + intel_sseu_set_info(sseu, hweight8(sseu->slice_mask), >>> + hweight8(subslice_mask), >>> + sseu->eu_per_subslice); >> >> I'd still prefer this to use a local variable so that we always only >> set >> sseu->eu_per_subslice from within intel_sseu_set_info. > > So the reason I kept this is in intel_sseu_set_info we are really just > setting the max_eus_per_subslice, not the eu_per_subslice. Are you > saying you'd also like to move the code that sets eu_per_subslice in > each generation's handler to local variables and/or just passed > directly as an argument to intel_sseu_set_info? My bad, I confused eu_per_subslice and max_eus_per_subslice as the same variable. Just ignore this comment :) Daniele > > I.e. should we use intel_sseu_set_info to set most or all of the > members of the intel_sseu structure? Or is it OK to keep the current > implementation of only using this to set default maximums per platform? > > -Stuart > >> >> Daniele >> >>> >>> for (s = 0; s < sseu->max_slices; s++) { >>> + intel_sseu_set_subslices(sseu, s, subslice_mask); >>> + >>> for (ss = 0; ss < sseu->max_subslices; ss++) { >>> intel_sseu_set_eus(sseu, s, ss, >>> (1UL << sseu- >>>> eu_per_subslice) - 1); >>> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 5/5] drm/i915: Expand subslice mask 2019-05-07 21:16 ` Daniele Ceraolo Spurio @ 2019-05-07 21:19 ` Summers, Stuart 0 siblings, 0 replies; 21+ messages in thread From: Summers, Stuart @ 2019-05-07 21:19 UTC (permalink / raw) To: Ceraolo Spurio, Daniele, intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 6274 bytes --] On Tue, 2019-05-07 at 14:16 -0700, Daniele Ceraolo Spurio wrote: > <snip> > > > > > > > > --- a/drivers/gpu/drm/i915/intel_device_info.c > > > > +++ b/drivers/gpu/drm/i915/intel_device_info.c > > > > @@ -84,17 +84,46 @@ void intel_device_info_dump_flags(const > > > > struct > > > > intel_device_info *info, > > > > #undef PRINT_FLAG > > > > } > > > > > > > > +#define SS_STR_MAX_SIZE (GEN_MAX_SUBSLICE_STRIDE * 2 + 1) > > > > + > > > > +static char * > > > > +subslice_per_slice_str(char *buf, u8 size, const struct > > > > sseu_dev_info *sseu, > > > > + u8 slice) > > > > +{ > > > > + int i; > > > > + u8 ss_offset = slice * sseu->ss_stride; > > > > + > > > > + GEM_BUG_ON(slice >= sseu->max_slices); > > > > + > > > > + /* Two ASCII character hex plus null terminator */ > > > > + GEM_BUG_ON(size < sseu->ss_stride * 2 + 1); > > > > + > > > > + memset(buf, 0, size); > > > > + > > > > + /* > > > > + * Print subslice information in reverse order to match > > > > + * userspace expectations. > > > > + */ > > > > + for (i = 0; i < sseu->ss_stride; i++) > > > > + sprintf(&buf[i * 2], "%02x", > > > > + sseu->subslice_mask[ss_offset + sseu- > > > > >ss_stride > > > > - > > > > + (i + 1)]); > > > > + > > > > + return buf; > > > > +} > > > > + > > > > static void sseu_dump(const struct sseu_dev_info *sseu, > > > > struct > > > > drm_printer *p) > > > > { > > > > int s; > > > > + char buf[SS_STR_MAX_SIZE]; > > > > > > > > drm_printf(p, "slice total: %u, mask=%04x\n", > > > > hweight8(sseu->slice_mask), sseu- > > > > >slice_mask); > > > > drm_printf(p, "subslice total: %u\n", > > > > intel_sseu_subslice_total(sseu)); > > > > for (s = 0; s < sseu->max_slices; s++) { > > > > - drm_printf(p, "slice%d: %u subslices, > > > > mask=%04x\n", > > > > + drm_printf(p, "slice%d: %u subslices, > > > > mask=%s\n", > > > > s, > > > > intel_sseu_subslices_per_slice(sseu, s), > > > > - sseu->subslice_mask[s]); > > > > + subslice_per_slice_str(buf, > > > > ARRAY_SIZE(buf), > > > > sseu, s)); > > > > > > Now that we have intel_sseu_get_subslices() can't we just print > > > the > > > return from that instead of using the buffer? > > > > I personally would prefer we keep the stringify function as it > > gives a > > little more flexibility. Do you have a strong preference to move to > > a > > direct printk formatted string? > > > > I do not, it just seemed like duplication since you're not really > using > any extra formatting or other flexibility in filling the buffer. > This > isn't a lot of code, so maybe we can switch to just using the u32 > for > now and add this back if/when we do require the flexibility? Makes sense and thanks for the feedback. I'll revert back to the printk format. > > > > > > > > > > > } > > > > drm_printf(p, "EU total: %u\n", sseu->eu_total); > > > > drm_printf(p, "EU per subslice: %u\n", sseu- > > > > >eu_per_subslice); > > > > > > <snip> > > > > > > > @@ -555,6 +570,7 @@ static void haswell_sseu_info_init(struct > > > > drm_i915_private *dev_priv) > > > > struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)- > > > > >sseu; > > > > u32 fuse1; > > > > int s, ss; > > > > + u32 subslice_mask; > > > > > > > > /* > > > > * There isn't a register to tell us how many > > > > slices/subslices. > > > > We > > > > @@ -566,22 +582,18 @@ static void haswell_sseu_info_init(struct > > > > drm_i915_private *dev_priv) > > > > /* fall through */ > > > > case 1: > > > > sseu->slice_mask = BIT(0); > > > > - sseu->subslice_mask[0] = BIT(0); > > > > + subslice_mask = BIT(0); > > > > break; > > > > case 2: > > > > sseu->slice_mask = BIT(0); > > > > - sseu->subslice_mask[0] = BIT(0) | BIT(1); > > > > + subslice_mask = BIT(0) | BIT(1); > > > > break; > > > > case 3: > > > > sseu->slice_mask = BIT(0) | BIT(1); > > > > - sseu->subslice_mask[0] = BIT(0) | BIT(1); > > > > - sseu->subslice_mask[1] = BIT(0) | BIT(1); > > > > + subslice_mask = BIT(0) | BIT(1); > > > > break; > > > > } > > > > > > > > - sseu->max_slices = hweight8(sseu->slice_mask); > > > > - sseu->max_subslices = hweight8(sseu->subslice_mask[0]); > > > > - > > > > fuse1 = I915_READ(HSW_PAVP_FUSE1); > > > > switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> > > > > HSW_F1_EU_DIS_SHIFT) { > > > > default: > > > > @@ -598,9 +610,14 @@ static void haswell_sseu_info_init(struct > > > > drm_i915_private *dev_priv) > > > > sseu->eu_per_subslice = 6; > > > > break; > > > > } > > > > - sseu->max_eus_per_subslice = sseu->eu_per_subslice; > > > > + > > > > + intel_sseu_set_info(sseu, hweight8(sseu->slice_mask), > > > > + hweight8(subslice_mask), > > > > + sseu->eu_per_subslice); > > > > > > I'd still prefer this to use a local variable so that we always > > > only > > > set > > > sseu->eu_per_subslice from within intel_sseu_set_info. > > > > So the reason I kept this is in intel_sseu_set_info we are really > > just > > setting the max_eus_per_subslice, not the eu_per_subslice. Are you > > saying you'd also like to move the code that sets eu_per_subslice > > in > > each generation's handler to local variables and/or just passed > > directly as an argument to intel_sseu_set_info? > > My bad, I confused eu_per_subslice and max_eus_per_subslice as the > same > variable. Just ignore this comment :) No problem, thanks! -Stuart > > Daniele > > > > > I.e. should we use intel_sseu_set_info to set most or all of the > > members of the intel_sseu structure? Or is it OK to keep the > > current > > implementation of only using this to set default maximums per > > platform? > > > > -Stuart > > > > > > > > Daniele > > > > > > > > > > > for (s = 0; s < sseu->max_slices; s++) { > > > > + intel_sseu_set_subslices(sseu, s, > > > > subslice_mask); > > > > + > > > > for (ss = 0; ss < sseu->max_subslices; ss++) { > > > > intel_sseu_set_eus(sseu, s, ss, > > > > (1UL << sseu- > > > > > eu_per_subslice) - 1); [-- Attachment #1.2: smime.p7s --] [-- Type: application/x-pkcs7-signature, Size: 3270 bytes --] [-- Attachment #2: Type: text/plain, Size: 159 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Refactor to expand subslice mask (rev8) 2019-05-03 21:30 [PATCH 0/5] Refactor to expand subslice mask Stuart Summers ` (4 preceding siblings ...) 2019-05-03 21:30 ` [PATCH 5/5] drm/i915: Expand subslice mask Stuart Summers @ 2019-05-03 21:56 ` Patchwork 2019-05-03 21:59 ` ✗ Fi.CI.SPARSE: " Patchwork ` (2 subsequent siblings) 8 siblings, 0 replies; 21+ messages in thread From: Patchwork @ 2019-05-03 21:56 UTC (permalink / raw) To: Stuart Summers; +Cc: intel-gfx == Series Details == Series: Refactor to expand subslice mask (rev8) URL : https://patchwork.freedesktop.org/series/59742/ State : warning == Summary == $ dim checkpatch origin/drm-tip bde01fefeccf drm/i915: Use local variable for SSEU info in GETPARAM ioctl 5b5850b4867c drm/i915: Add macro for SSEU stride calculation 2d091162979d drm/i915: Move calculation of subslices per slice to new function 9562a29d51ba drm/i915: Refactor sseu helper functions 8236a3377935 drm/i915: Expand subslice mask -:113: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv_' - possible side-effects? #113: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:546: +#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \ + for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \ + (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \ + (slice_) += ((subslice_) == 0)) \ + for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \ + (instdone_has_subslice(dev_priv_, sseu_, slice_, \ + subslice_))) -:113: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'sseu_' - possible side-effects? #113: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:546: +#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \ + for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \ + (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \ + (slice_) += ((subslice_) == 0)) \ + for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \ + (instdone_has_subslice(dev_priv_, sseu_, slice_, \ + subslice_))) -:113: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'slice_' - possible side-effects? #113: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:546: +#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \ + for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \ + (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \ + (slice_) += ((subslice_) == 0)) \ + for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \ + (instdone_has_subslice(dev_priv_, sseu_, slice_, \ + subslice_))) -:113: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'subslice_' - possible side-effects? #113: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:546: +#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \ + for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \ + (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \ + (slice_) += ((subslice_) == 0)) \ + for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \ + (instdone_has_subslice(dev_priv_, sseu_, slice_, \ + subslice_))) total: 0 errors, 0 warnings, 4 checks, 729 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* ✗ Fi.CI.SPARSE: warning for Refactor to expand subslice mask (rev8) 2019-05-03 21:30 [PATCH 0/5] Refactor to expand subslice mask Stuart Summers ` (5 preceding siblings ...) 2019-05-03 21:56 ` ✗ Fi.CI.CHECKPATCH: warning for Refactor to expand subslice mask (rev8) Patchwork @ 2019-05-03 21:59 ` Patchwork 2019-05-03 22:44 ` ✓ Fi.CI.BAT: success " Patchwork 2019-05-04 4:28 ` ✓ Fi.CI.IGT: " Patchwork 8 siblings, 0 replies; 21+ messages in thread From: Patchwork @ 2019-05-03 21:59 UTC (permalink / raw) To: Stuart Summers; +Cc: intel-gfx == Series Details == Series: Refactor to expand subslice mask (rev8) URL : https://patchwork.freedesktop.org/series/59742/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Use local variable for SSEU info in GETPARAM ioctl Okay! Commit: drm/i915: Add macro for SSEU stride calculation Okay! Commit: drm/i915: Move calculation of subslices per slice to new function Okay! Commit: drm/i915: Refactor sseu helper functions Okay! Commit: drm/i915: Expand subslice mask +drivers/gpu/drm/i915/i915_drv.c:464:24: warning: expression using sizeof(void) _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* ✓ Fi.CI.BAT: success for Refactor to expand subslice mask (rev8) 2019-05-03 21:30 [PATCH 0/5] Refactor to expand subslice mask Stuart Summers ` (6 preceding siblings ...) 2019-05-03 21:59 ` ✗ Fi.CI.SPARSE: " Patchwork @ 2019-05-03 22:44 ` Patchwork 2019-05-04 4:28 ` ✓ Fi.CI.IGT: " Patchwork 8 siblings, 0 replies; 21+ messages in thread From: Patchwork @ 2019-05-03 22:44 UTC (permalink / raw) To: Stuart Summers; +Cc: intel-gfx == Series Details == Series: Refactor to expand subslice mask (rev8) URL : https://patchwork.freedesktop.org/series/59742/ State : success == Summary == CI Bug Log - changes from CI_DRM_6043 -> Patchwork_12965 ==================================================== Summary ------- **WARNING** Minor unknown changes coming with Patchwork_12965 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12965, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/ Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_12965: ### IGT changes ### #### Warnings #### * igt@i915_selftest@live_hangcheck: - fi-apl-guc: [INCOMPLETE][1] ([fdo#103927] / [fdo#110581]) -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/fi-apl-guc/igt@i915_selftest@live_hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/fi-apl-guc/igt@i915_selftest@live_hangcheck.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@kms_chamelium@dp-crc-fast: - {fi-cml-u2}: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html Known issues ------------ Here are the changes found in Patchwork_12965 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_selftest@live_hangcheck: - fi-skl-iommu: [PASS][5] -> [INCOMPLETE][6] ([fdo#108602] / [fdo#108744] / [fdo#110581]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-apl-guc: [PASS][7] -> [DMESG-WARN][8] ([fdo#110512]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/fi-apl-guc/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/fi-apl-guc/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html #### Possible fixes #### * igt@gem_exec_suspend@basic-s3: - fi-apl-guc: [DMESG-WARN][9] ([fdo#110512]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/fi-apl-guc/igt@gem_exec_suspend@basic-s3.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/fi-apl-guc/igt@gem_exec_suspend@basic-s3.html * igt@i915_selftest@live_contexts: - fi-skl-gvtdvm: [DMESG-FAIL][11] ([fdo#110235]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602 [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744 [fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 [fdo#110512]: https://bugs.freedesktop.org/show_bug.cgi?id=110512 [fdo#110581]: https://bugs.freedesktop.org/show_bug.cgi?id=110581 Participating hosts (53 -> 43) ------------------------------ Missing (10): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-gdg-551 fi-icl-y fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_6043 -> Patchwork_12965 CI_DRM_6043: b33a03a0d9c2f7376b78c356d4e0e9e55f495f69 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4972: f052e49a43cc9704ea5f240df15dd9d3dfed68ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12965: 8236a337793574e5ba805f69c4ac50598d6c7034 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 8236a3377935 drm/i915: Expand subslice mask 9562a29d51ba drm/i915: Refactor sseu helper functions 2d091162979d drm/i915: Move calculation of subslices per slice to new function 5b5850b4867c drm/i915: Add macro for SSEU stride calculation bde01fefeccf drm/i915: Use local variable for SSEU info in GETPARAM ioctl == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* ✓ Fi.CI.IGT: success for Refactor to expand subslice mask (rev8) 2019-05-03 21:30 [PATCH 0/5] Refactor to expand subslice mask Stuart Summers ` (7 preceding siblings ...) 2019-05-03 22:44 ` ✓ Fi.CI.BAT: success " Patchwork @ 2019-05-04 4:28 ` Patchwork 8 siblings, 0 replies; 21+ messages in thread From: Patchwork @ 2019-05-04 4:28 UTC (permalink / raw) To: Stuart Summers; +Cc: intel-gfx == Series Details == Series: Refactor to expand subslice mask (rev8) URL : https://patchwork.freedesktop.org/series/59742/ State : success == Summary == CI Bug Log - changes from CI_DRM_6043_full -> Patchwork_12965_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_12965_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_isolation@bcs0-s3: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/shard-kbl6/igt@gem_ctx_isolation@bcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/shard-kbl1/igt@gem_ctx_isolation@bcs0-s3.html * igt@gem_softpin@noreloc-s3: - shard-skl: [PASS][3] -> [INCOMPLETE][4] ([fdo#104108] / [fdo#107773] / [fdo#110581]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/shard-skl9/igt@gem_softpin@noreloc-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/shard-skl5/igt@gem_softpin@noreloc-s3.html * igt@i915_pm_rpm@pm-caching: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([fdo#107807] / [fdo#110581]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/shard-skl9/igt@i915_pm_rpm@pm-caching.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/shard-skl6/igt@i915_pm_rpm@pm-caching.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic: - shard-glk: [PASS][7] -> [FAIL][8] ([fdo#104873]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/shard-glk4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/shard-glk4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html * igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled: - shard-skl: [PASS][9] -> [FAIL][10] ([fdo#103184] / [fdo#103232]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/shard-skl5/igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/shard-skl9/igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled.html * igt@kms_flip@2x-flip-vs-suspend-interruptible: - shard-glk: [PASS][11] -> [INCOMPLETE][12] ([fdo#103359] / [fdo#110581] / [k.org#198133]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/shard-glk3/igt@kms_flip@2x-flip-vs-suspend-interruptible.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/shard-glk7/igt@kms_flip@2x-flip-vs-suspend-interruptible.html * igt@kms_flip@2x-plain-flip-fb-recreate: - shard-glk: [PASS][13] -> [FAIL][14] ([fdo#100368]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/shard-glk9/igt@kms_flip@2x-plain-flip-fb-recreate.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/shard-glk9/igt@kms_flip@2x-plain-flip-fb-recreate.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#105363]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/shard-skl8/igt@kms_flip@flip-vs-expired-vblank.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html * igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-cpu: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#103167] / [fdo#110379]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/shard-skl5/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-cpu.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/shard-skl9/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-cpu.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-skl: [PASS][19] -> [INCOMPLETE][20] ([fdo#104108] / [fdo#110581]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/shard-skl6/igt@kms_frontbuffer_tracking@fbc-suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/shard-skl2/igt@kms_frontbuffer_tracking@fbc-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#103167]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#103167]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/shard-skl5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/shard-skl9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-apl: [PASS][25] -> [DMESG-WARN][26] ([fdo#108566]) +5 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/shard-apl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/shard-apl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-iclb: [PASS][27] -> [FAIL][28] ([fdo#103166]) +1 similar issue [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/shard-iclb3/igt@kms_plane_lowres@pipe-a-tiling-x.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/shard-iclb4/igt@kms_plane_lowres@pipe-a-tiling-x.html * igt@kms_psr@no_drrs: - shard-iclb: [PASS][29] -> [FAIL][30] ([fdo#108341]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/shard-iclb5/igt@kms_psr@no_drrs.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/shard-iclb1/igt@kms_psr@no_drrs.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#109441]) +2 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/shard-iclb8/igt@kms_psr@psr2_sprite_plane_move.html * igt@kms_rotation_crc@multiplane-rotation: - shard-kbl: [PASS][33] -> [INCOMPLETE][34] ([fdo#103665] / [fdo#110581]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/shard-kbl2/igt@kms_rotation_crc@multiplane-rotation.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/shard-kbl5/igt@kms_rotation_crc@multiplane-rotation.html #### Possible fixes #### * igt@gem_workarounds@suspend-resume: - shard-apl: [DMESG-WARN][35] ([fdo#108566]) -> [PASS][36] +4 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/shard-apl3/igt@gem_workarounds@suspend-resume.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/shard-apl8/igt@gem_workarounds@suspend-resume.html * igt@i915_pm_rpm@i2c: - shard-iclb: [FAIL][37] ([fdo#104097]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/shard-iclb3/igt@i915_pm_rpm@i2c.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/shard-iclb4/igt@i915_pm_rpm@i2c.html * igt@i915_suspend@debugfs-reader: - shard-kbl: [DMESG-WARN][39] ([fdo#108566]) -> [PASS][40] +1 similar issue [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/shard-kbl1/igt@i915_suspend@debugfs-reader.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/shard-kbl2/igt@i915_suspend@debugfs-reader.html * igt@kms_flip@plain-flip-ts-check-interruptible: - shard-skl: [FAIL][41] ([fdo#100368]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/shard-skl9/igt@kms_flip@plain-flip-ts-check-interruptible.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/shard-skl9/igt@kms_flip@plain-flip-ts-check-interruptible.html * igt@kms_frontbuffer_tracking@fbcpsr-tilingchange: - shard-iclb: [FAIL][43] ([fdo#103167]) -> [PASS][44] +5 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-tilingchange.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-tilingchange.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [FAIL][45] ([fdo#108145]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][47] ([fdo#108145] / [fdo#110403]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt@kms_psr@psr2_primary_mmap_gtt: - shard-iclb: [SKIP][49] ([fdo#109441]) -> [PASS][50] +2 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/shard-iclb4/igt@kms_psr@psr2_primary_mmap_gtt.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html * igt@kms_setmode@basic: - shard-kbl: [FAIL][51] ([fdo#99912]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/shard-kbl6/igt@kms_setmode@basic.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/shard-kbl1/igt@kms_setmode@basic.html #### Warnings #### * igt@gem_eio@reset-stress: - shard-skl: [FAIL][53] -> [FAIL][54] ([fdo#105957]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6043/shard-skl5/igt@gem_eio@reset-stress.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/shard-skl2/igt@gem_eio@reset-stress.html [fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368 [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184 [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232 [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359 [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665 [fdo#104097]: https://bugs.freedesktop.org/show_bug.cgi?id=104097 [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108 [fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873 [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363 [fdo#105957]: https://bugs.freedesktop.org/show_bug.cgi?id=105957 [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773 [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341 [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110379]: https://bugs.freedesktop.org/show_bug.cgi?id=110379 [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403 [fdo#110581]: https://bugs.freedesktop.org/show_bug.cgi?id=110581 [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (10 -> 10) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_6043 -> Patchwork_12965 CI_DRM_6043: b33a03a0d9c2f7376b78c356d4e0e9e55f495f69 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4972: f052e49a43cc9704ea5f240df15dd9d3dfed68ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12965: 8236a337793574e5ba805f69c4ac50598d6c7034 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12965/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 0/5] Refactor to expand subslice mask @ 2019-05-13 20:56 Stuart Summers 0 siblings, 0 replies; 21+ messages in thread From: Stuart Summers @ 2019-05-13 20:56 UTC (permalink / raw) To: intel-gfx This patch series contains a few code clean-up patches, followed by a patch which changes the storage of the subslice mask to better match the userspace access through the I915_QUERY_TOPOLOGY_INFO ioctl. The index into the subslice_mask array is then calculated: slice * subslice stride + subslice index / 8 v2: fix i915_pm_sseu test failure v3: no changes to patches in the series, just resending to pick up in CI correctly v4: rebase v5: fix header test v6: address review comments from Jari address minor checkpatch warning in existing code use eu_stride for EU div-by-8 v7: another rebase v8: address review comments from Tvrtko and Daniele v9: address review comments from Daniele Stuart Summers (5): drm/i915: Use local variable for SSEU info in GETPARAM ioctl drm/i915: Add macro for SSEU stride calculation drm/i915: Move calculation of subslices per slice to new function drm/i915: Refactor sseu helper functions drm/i915: Expand subslice mask drivers/gpu/drm/i915/gt/intel_engine_cs.c | 24 ++- drivers/gpu/drm/i915/gt/intel_engine_types.h | 30 ++-- drivers/gpu/drm/i915/gt/intel_hangcheck.c | 3 +- drivers/gpu/drm/i915/gt/intel_sseu.c | 62 +++++++ drivers/gpu/drm/i915/gt/intel_sseu.h | 36 +++- drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- drivers/gpu/drm/i915/i915_debugfs.c | 46 ++--- drivers/gpu/drm/i915/i915_drv.c | 15 +- drivers/gpu/drm/i915/i915_gpu_error.c | 5 +- drivers/gpu/drm/i915/i915_query.c | 15 +- drivers/gpu/drm/i915/intel_device_info.c | 176 +++++++++++-------- drivers/gpu/drm/i915/intel_device_info.h | 47 ----- 12 files changed, 281 insertions(+), 180 deletions(-) -- 2.21.0.5.gaeb582a983 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 0/5] Refactor to expand subslice mask @ 2019-04-29 15:51 Stuart Summers 0 siblings, 0 replies; 21+ messages in thread From: Stuart Summers @ 2019-04-29 15:51 UTC (permalink / raw) To: intel-gfx This patch series contains a few code clean-up patches, followed by a patch which changes the storage of the subslice mask to better match the userspace access through the I915_QUERY_TOPOLOGY_INFO ioctl. The index into the subslice_mask array is then calculated: slice * subslice stride + subslice index / 8 v2: fix i915_pm_sseu test failure v3: no changes to patches in the series, just resending to pick up in CI correctly v4: rebase v5: fix header test Stuart Summers (5): drm/i915: Use local variable for SSEU info in GETPARAM ioctl drm/i915: Add macro for SSEU stride calculation drm/i915: Move calculation of subslices per slice to new function drm/i915: Move sseu helper functions to intel_sseu.h drm/i915: Expand subslice mask drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 +- drivers/gpu/drm/i915/gt/intel_engine_types.h | 32 +++-- drivers/gpu/drm/i915/gt/intel_hangcheck.c | 3 +- drivers/gpu/drm/i915/gt/intel_sseu.h | 98 ++++++++++++- drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- drivers/gpu/drm/i915/i915_debugfs.c | 45 +++--- drivers/gpu/drm/i915/i915_drv.c | 15 +- drivers/gpu/drm/i915/i915_gpu_error.c | 5 +- drivers/gpu/drm/i915/i915_query.c | 15 +- drivers/gpu/drm/i915/intel_device_info.c | 143 +++++++++++-------- drivers/gpu/drm/i915/intel_device_info.h | 47 ------ 11 files changed, 247 insertions(+), 164 deletions(-) -- 2.21.0.5.gaeb582a983 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 0/5] Refactor to expand subslice mask @ 2019-04-26 20:24 Stuart Summers 0 siblings, 0 replies; 21+ messages in thread From: Stuart Summers @ 2019-04-26 20:24 UTC (permalink / raw) To: intel-gfx This patch series contains a few code clean-up patches, followed by a patch which changes the storage of the subslice mask to better match the userspace access through the I915_QUERY_TOPOLOGY_INFO ioctl. The index into the subslice_mask array is then calculated: slice * subslice stride + subslice index / 8 v2: fix i915_pm_sseu test failure v3: no changes to patches in the series, just resending to pick up in CI correctly v4: rebase Stuart Summers (5): drm/i915: Use local variable for SSEU info in GETPARAM ioctl drm/i915: Add macro for SSEU stride calculation drm/i915: Move calculation of subslices per slice to new function drm/i915: Move sseu helper functions to intel_sseu.h drm/i915: Expand subslice mask drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 +- drivers/gpu/drm/i915/gt/intel_engine_types.h | 32 +++-- drivers/gpu/drm/i915/gt/intel_hangcheck.c | 3 +- drivers/gpu/drm/i915/gt/intel_sseu.h | 96 ++++++++++++- drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- drivers/gpu/drm/i915/i915_debugfs.c | 45 +++--- drivers/gpu/drm/i915/i915_drv.c | 15 +- drivers/gpu/drm/i915/i915_gpu_error.c | 5 +- drivers/gpu/drm/i915/i915_query.c | 15 +- drivers/gpu/drm/i915/intel_device_info.c | 143 +++++++++++-------- drivers/gpu/drm/i915/intel_device_info.h | 47 ------ 11 files changed, 245 insertions(+), 164 deletions(-) -- 2.21.0.5.gaeb582a983 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 0/5] Refactor to expand subslice mask @ 2019-04-25 22:24 Stuart Summers 0 siblings, 0 replies; 21+ messages in thread From: Stuart Summers @ 2019-04-25 22:24 UTC (permalink / raw) To: intel-gfx This patch series contains a few code clean-up patches, followed by a patch which changes the storage of the subslice mask to better match the userspace access through the I915_QUERY_TOPOLOGY_INFO ioctl. The index into the subslice_mask array is then calculated: slice * subslice stride + subslice index / 8 v2: fix i915_pm_sseu test failure v3: no changes to patches in the series, just resending to pick up in CI correctly Stuart Summers (5): drm/i915: Use local variable for SSEU info in GETPARAM ioctl drm/i915: Add macro for SSEU stride calculation drm/i915: Move calculation of subslices per slice to new function drm/i915: Move sseu helper functions to intel_sseu.h drm/i915: Expand subslice mask drivers/gpu/drm/i915/i915_debugfs.c | 45 ++++--- drivers/gpu/drm/i915/i915_drv.c | 15 ++- drivers/gpu/drm/i915/i915_gpu_error.c | 5 +- drivers/gpu/drm/i915/i915_query.c | 15 +-- drivers/gpu/drm/i915/intel_device_info.c | 143 +++++++++++++--------- drivers/gpu/drm/i915/intel_device_info.h | 47 ------- drivers/gpu/drm/i915/intel_engine_cs.c | 6 +- drivers/gpu/drm/i915/intel_engine_types.h | 32 ++--- drivers/gpu/drm/i915/intel_hangcheck.c | 3 +- drivers/gpu/drm/i915/intel_sseu.h | 96 ++++++++++++++- drivers/gpu/drm/i915/intel_workarounds.c | 2 +- 11 files changed, 245 insertions(+), 164 deletions(-) -- 2.21.0.5.gaeb582a983 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 0/4] Refactor to expand subslice mask @ 2019-04-19 0:00 Stuart Summers 2019-04-25 16:28 ` [PATCH 0/5] " Stuart Summers 0 siblings, 1 reply; 21+ messages in thread From: Stuart Summers @ 2019-04-19 0:00 UTC (permalink / raw) To: intel-gfx This patch series contains a few code clean-up patches, followed by a patch which changes the storage of the subslice mask to better match the userspace access through the I915_QUERY_TOPOLOGY_INFO ioctl. The index into the subslice_mask array is then calculated: slice * subslice stride + subslice index / 8 Stuart Summers (4): drm/i915: Use local variable for SSEU info in GETPARAM ioctl drm/i915: Add macro for SSEU stride calculation drm/i915: Move calculation of subslices per slice to new function drm/i915: Expand subslice mask drivers/gpu/drm/i915/i915_debugfs.c | 46 ++++--- drivers/gpu/drm/i915/i915_drv.c | 15 ++- drivers/gpu/drm/i915/i915_gpu_error.c | 5 +- drivers/gpu/drm/i915/i915_query.c | 15 +-- drivers/gpu/drm/i915/intel_device_info.c | 154 +++++++++++++--------- drivers/gpu/drm/i915/intel_device_info.h | 52 ++++++-- drivers/gpu/drm/i915/intel_engine_cs.c | 6 +- drivers/gpu/drm/i915/intel_engine_types.h | 32 ++--- drivers/gpu/drm/i915/intel_hangcheck.c | 3 +- drivers/gpu/drm/i915/intel_workarounds.c | 2 +- 10 files changed, 203 insertions(+), 127 deletions(-) -- 2.21.0.5.gaeb582a983 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 0/5] Refactor to expand subslice mask 2019-04-19 0:00 [PATCH 0/4] " Stuart Summers @ 2019-04-25 16:28 ` Stuart Summers 0 siblings, 0 replies; 21+ messages in thread From: Stuart Summers @ 2019-04-25 16:28 UTC (permalink / raw) To: intel-gfx This patch series contains a few code clean-up patches, followed by a patch which changes the storage of the subslice mask to better match the userspace access through the I915_QUERY_TOPOLOGY_INFO ioctl. The index into the subslice_mask array is then calculated: slice * subslice stride + subslice index / 8 v2: fix i915_pm_sseu test failure Stuart Summers (5): drm/i915: Use local variable for SSEU info in GETPARAM ioctl drm/i915: Add macro for SSEU stride calculation drm/i915: Move calculation of subslices per slice to new function drm/i915: Move sseu helper functions to intel_sseu.h drm/i915: Expand subslice mask drivers/gpu/drm/i915/i915_debugfs.c | 45 ++++--- drivers/gpu/drm/i915/i915_drv.c | 15 ++- drivers/gpu/drm/i915/i915_gpu_error.c | 5 +- drivers/gpu/drm/i915/i915_query.c | 15 +-- drivers/gpu/drm/i915/intel_device_info.c | 143 +++++++++++++--------- drivers/gpu/drm/i915/intel_device_info.h | 47 ------- drivers/gpu/drm/i915/intel_engine_cs.c | 6 +- drivers/gpu/drm/i915/intel_engine_types.h | 32 ++--- drivers/gpu/drm/i915/intel_hangcheck.c | 3 +- drivers/gpu/drm/i915/intel_sseu.h | 96 ++++++++++++++- drivers/gpu/drm/i915/intel_workarounds.c | 2 +- 11 files changed, 245 insertions(+), 164 deletions(-) -- 2.21.0.5.gaeb582a983 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2019-05-13 20:56 UTC | newest] Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-05-03 21:30 [PATCH 0/5] Refactor to expand subslice mask Stuart Summers 2019-05-03 21:30 ` [PATCH 1/5] drm/i915: Use local variable for SSEU info in GETPARAM ioctl Stuart Summers 2019-05-03 21:30 ` [PATCH 2/5] drm/i915: Add macro for SSEU stride calculation Stuart Summers 2019-05-03 21:30 ` [PATCH 3/5] drm/i915: Move calculation of subslices per slice to new function Stuart Summers 2019-05-03 21:30 ` [PATCH 4/5] drm/i915: Refactor sseu helper functions Stuart Summers 2019-05-07 18:12 ` Daniele Ceraolo Spurio 2019-05-07 18:21 ` Summers, Stuart 2019-05-03 21:30 ` [PATCH 5/5] drm/i915: Expand subslice mask Stuart Summers 2019-05-07 19:00 ` Daniele Ceraolo Spurio 2019-05-07 20:48 ` Summers, Stuart 2019-05-07 21:16 ` Daniele Ceraolo Spurio 2019-05-07 21:19 ` Summers, Stuart 2019-05-03 21:56 ` ✗ Fi.CI.CHECKPATCH: warning for Refactor to expand subslice mask (rev8) Patchwork 2019-05-03 21:59 ` ✗ Fi.CI.SPARSE: " Patchwork 2019-05-03 22:44 ` ✓ Fi.CI.BAT: success " Patchwork 2019-05-04 4:28 ` ✓ Fi.CI.IGT: " Patchwork -- strict thread matches above, loose matches on Subject: below -- 2019-05-13 20:56 [PATCH 0/5] Refactor to expand subslice mask Stuart Summers 2019-04-29 15:51 Stuart Summers 2019-04-26 20:24 Stuart Summers 2019-04-25 22:24 Stuart Summers 2019-04-19 0:00 [PATCH 0/4] " Stuart Summers 2019-04-25 16:28 ` [PATCH 0/5] " Stuart Summers
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