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* [v3 1/4] drm/i915: Fix the pipe state timing mismatch warnings
@ 2019-05-02  6:34 Vandita Kulkarni
  2019-05-02  6:34 ` [v3 2/4] drm/i915: Refactor bdw_get_pipemisc_bpp Vandita Kulkarni
                   ` (5 more replies)
  0 siblings, 6 replies; 7+ messages in thread
From: Vandita Kulkarni @ 2019-05-02  6:34 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula, ville.syrjala

Adjust the get transcoder timings for mipi dsi as per the
set timing calculations.

v2: Use the existing intel_get_pipe_timings and do the dsi
    specific adjustments in the encoder get_config hook.(Ville, Jani)

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index c6ecc00..45fe69c 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1194,6 +1194,34 @@ static void gen11_dsi_disable(struct intel_encoder *encoder,
 	gen11_dsi_disable_io_power(encoder);
 }
 
+static void gen11_dsi_get_timings(struct intel_encoder *encoder,
+				  struct intel_crtc_state *pipe_config)
+{
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	struct drm_display_mode *adjusted_mode =
+					&pipe_config->base.adjusted_mode;
+
+	if (intel_dsi->dual_link) {
+		adjusted_mode->crtc_hdisplay *= 2;
+		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
+			adjusted_mode->crtc_hdisplay -=
+						intel_dsi->pixel_overlap;
+		adjusted_mode->crtc_htotal *= 2;
+	}
+	adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
+	adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
+
+	if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
+		if (intel_dsi->dual_link) {
+			adjusted_mode->crtc_hsync_start *= 2;
+			adjusted_mode->crtc_hsync_end *= 2;
+		}
+	}
+	adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
+	adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
+
+}
+
 static void gen11_dsi_get_config(struct intel_encoder *encoder,
 				 struct intel_crtc_state *pipe_config)
 {
@@ -1204,6 +1232,7 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
 	pipe_config->port_clock =
 		cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state);
 	pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
+	gen11_dsi_get_timings(encoder, pipe_config);
 	pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
 }
 
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 7+ messages in thread
end of thread, other threads:[~2019-05-02 13:21 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-05-02  6:34 [v3 1/4] drm/i915: Fix the pipe state timing mismatch warnings Vandita Kulkarni
2019-05-02  6:34 ` [v3 2/4] drm/i915: Refactor bdw_get_pipemisc_bpp Vandita Kulkarni
2019-05-02  6:34 ` [v3 3/4] drm/i915: Fix pipe config mismatch for bpp, output format Vandita Kulkarni
2019-05-02  6:34 ` [v3 4/4] drm/i915: Fix pixel clock and crtc clock config mismatch Vandita Kulkarni
2019-05-02  7:18 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/4] drm/i915: Fix the pipe state timing mismatch warnings Patchwork
2019-05-02  7:35 ` ✓ Fi.CI.BAT: success " Patchwork
2019-05-02 13:21 ` ✓ Fi.CI.IGT: " Patchwork

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