[PATCH 00/10] drm/i915: Add support for asynchronous display power disabling

[PATCH 00/10] drm/i915: Add support for asynchronous display power disabling

[Imre Deak]

This is a preparation for making hotplug useable on ICL TypeC ports. On
ICL we need a stricter control on when either kind of AUX power domain
(TBT-alt or DP-alt) is enabled. That control becomes unfeasible if the
reference can be held for arbitratry periods due to locking
dependencies. OTOH it makes sense to restrict holding the reference only
for the duration when it's actually needed. One result of that would be
the unnecessary on-off-on power togglings when the reference is dropped
and reacquired quickly.

This patchset adds support for dropping display power domain references
asynchronously with a delay to avoid the unecessary power togglings, and
restricts holding the AUX power domain reference to the sequence where
it's required during detection and HPD pulse handling.

Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>

Imre Deak (10):
  drm/i915: Add support for tracking wakerefs w/o power-on guarantee
  drm/i915: Verify power domains state during suspend in all cases
  drm/i915: Add support for asynchronous display power disabling
  drm/i915: Disable power asynchronously during DP AUX transfers
  drm/i915: WARN for eDP encoders in intel_dp_detect_dpcd()
  drm/i915: Remove the unneeded AUX power ref from intel_dp_detect()
  drm/i915: Remove the unneeded AUX power ref from intel_dp_hpd_pulse()
  drm/i915: Replace use of PLLS power domain with DISPLAY_CORE domain
  drm/i915: Avoid taking the PPS lock for non-eDP/VLV/CHV
  drm/i915: Assert that TypeC ports are not used for eDP

 drivers/gpu/drm/i915/i915_drv.h         |   6 +
 drivers/gpu/drm/i915/intel_display.c    |   2 +-
 drivers/gpu/drm/i915/intel_display.h    |   2 +-
 drivers/gpu/drm/i915/intel_dp.c         |  76 ++--
 drivers/gpu/drm/i915/intel_dpll_mgr.c   |  36 +-
 drivers/gpu/drm/i915/intel_psr.c        |   6 +
 drivers/gpu/drm/i915/intel_runtime_pm.c | 443 ++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_runtime_pm.h |   4 +
 8 files changed, 491 insertions(+), 84 deletions(-)

-- 
2.17.1
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[PATCH 01/10] drm/i915: Add support for tracking wakerefs w/o power-on guarantee

[Imre Deak]

It's useful to track runtime PM refs that don't guarantee a device
power-on state to the rest of the driver. One such case is holding a
reference that will be put asynchronously, during which normal users
without their own reference shouldn't access the HW. A follow-up patch
will add support for disabling display power domains asynchronously
which needs this.

For this we can track all references with a separate wakeref_track_count
and references guaranteeing a power-on state with the current
wakeref_count.

Follow-up patches will make use of the API added here, so add a
__used__ attribute quirk to keep git bisect working.

No functional changes.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h         |   1 +
 drivers/gpu/drm/i915/intel_runtime_pm.c | 121 ++++++++++++++++++++----
 2 files changed, 102 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9a634ba57ff9..9fb26634a6be 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1177,6 +1177,7 @@ struct skl_wm_params {
  */
 struct i915_runtime_pm {
 	atomic_t wakeref_count;
+	atomic_t wakeref_track_count;
 	bool suspended;
 	bool irqs_enabled;
 
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 30e7cb9d5801..4a7bfc945322 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -59,6 +59,12 @@
  * present for a given platform.
  */
 
+static void
+assert_raw_rpm_wakelock_held(struct drm_i915_private *i915)
+{
+	WARN_ON(!atomic_read(&i915->runtime_pm.wakeref_track_count));
+}
+
 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
 
 #include <linux/sort.h>
@@ -100,17 +106,18 @@ static void init_intel_runtime_pm_wakeref(struct drm_i915_private *i915)
 	struct i915_runtime_pm *rpm = &i915->runtime_pm;
 
 	spin_lock_init(&rpm->debug.lock);
+	atomic_set(&rpm->wakeref_track_count, 0);
 }
 
 static noinline depot_stack_handle_t
-track_intel_runtime_pm_wakeref(struct drm_i915_private *i915)
+track_intel_runtime_pm_wakeref_raw(struct drm_i915_private *i915)
 {
 	struct i915_runtime_pm *rpm = &i915->runtime_pm;
 	depot_stack_handle_t stack, *stacks;
 	unsigned long flags;
 
-	atomic_inc(&rpm->wakeref_count);
-	assert_rpm_wakelock_held(i915);
+	atomic_inc(&rpm->wakeref_track_count);
+	assert_raw_rpm_wakelock_held(i915);
 
 	if (!HAS_RUNTIME_PM(i915))
 		return -1;
@@ -139,6 +146,15 @@ track_intel_runtime_pm_wakeref(struct drm_i915_private *i915)
 	return stack;
 }
 
+static noinline depot_stack_handle_t
+track_intel_runtime_pm_wakeref(struct drm_i915_private *i915)
+{
+	atomic_inc(&i915->runtime_pm.wakeref_count);
+	assert_rpm_wakelock_held(i915);
+
+	return track_intel_runtime_pm_wakeref_raw(i915);
+}
+
 static void cancel_intel_runtime_pm_wakeref(struct drm_i915_private *i915,
 					    depot_stack_handle_t stack)
 {
@@ -163,7 +179,7 @@ static void cancel_intel_runtime_pm_wakeref(struct drm_i915_private *i915,
 
 	if (WARN(!found,
 		 "Unmatched wakeref (tracking %lu), count %u\n",
-		 rpm->debug.count, atomic_read(&rpm->wakeref_count))) {
+		 rpm->debug.count, atomic_read(&rpm->wakeref_track_count))) {
 		char *buf;
 
 		buf = kmalloc(PAGE_SIZE, GFP_NOWAIT | __GFP_NOWARN);
@@ -235,15 +251,15 @@ __print_intel_runtime_pm_wakeref(struct drm_printer *p,
 }
 
 static noinline void
-untrack_intel_runtime_pm_wakeref(struct drm_i915_private *i915)
+untrack_intel_runtime_pm_wakeref_raw(struct drm_i915_private *i915)
 {
 	struct i915_runtime_pm *rpm = &i915->runtime_pm;
 	struct intel_runtime_pm_debug dbg = {};
 	struct drm_printer p;
 	unsigned long flags;
 
-	assert_rpm_wakelock_held(i915);
-	if (atomic_dec_and_lock_irqsave(&rpm->wakeref_count,
+	assert_raw_rpm_wakelock_held(i915);
+	if (atomic_dec_and_lock_irqsave(&rpm->wakeref_track_count,
 					&rpm->debug.lock,
 					flags)) {
 		dbg = rpm->debug;
@@ -263,6 +279,15 @@ untrack_intel_runtime_pm_wakeref(struct drm_i915_private *i915)
 	kfree(dbg.owners);
 }
 
+static noinline void
+untrack_intel_runtime_pm_wakeref(struct drm_i915_private *i915)
+{
+	untrack_intel_runtime_pm_wakeref_raw(i915);
+
+	assert_rpm_wakelock_held(i915);
+	atomic_dec(&i915->runtime_pm.wakeref_count);
+}
+
 void print_intel_runtime_pm_wakeref(struct drm_i915_private *i915,
 				    struct drm_printer *p)
 {
@@ -308,15 +333,33 @@ static void init_intel_runtime_pm_wakeref(struct drm_i915_private *i915)
 }
 
 static depot_stack_handle_t
-track_intel_runtime_pm_wakeref(struct drm_i915_private *i915)
+track_intel_runtime_pm_wakeref_raw(struct drm_i915_private *i915)
 {
-	atomic_inc(&i915->runtime_pm.wakeref_count);
-	assert_rpm_wakelock_held(i915);
+	atomic_inc(&i915->runtime_pm.wakeref_track_count);
+	assert_raw_rpm_wakelock_held(i915);
+
 	return -1;
 }
 
+static depot_stack_handle_t
+track_intel_runtime_pm_wakeref(struct drm_i915_private *i915)
+{
+	atomic_inc(&i915->runtime_pm.wakeref_count);
+	assert_rpm_wakelock_held(i915);
+
+	return track_intel_runtime_pm_wakeref_raw(i915);
+}
+
+static void untrack_intel_runtime_pm_wakeref_raw(struct drm_i915_private *i915)
+{
+	assert_raw_rpm_wakelock_held(i915);
+	atomic_dec(&i915->runtime_pm.wakeref_track_count);
+}
+
 static void untrack_intel_runtime_pm_wakeref(struct drm_i915_private *i915)
 {
+	untrack_intel_runtime_pm_wakeref_raw(i915);
+
 	assert_rpm_wakelock_held(i915);
 	atomic_dec(&i915->runtime_pm.wakeref_count);
 }
@@ -4347,7 +4390,7 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915)
  *
  * Returns: the wakeref cookie to pass to intel_runtime_pm_put()
  */
-intel_wakeref_t intel_runtime_pm_get(struct drm_i915_private *i915)
+static void __intel_runtime_pm_get(struct drm_i915_private *i915)
 {
 	struct pci_dev *pdev = i915->drm.pdev;
 	struct device *kdev = &pdev->dev;
@@ -4355,6 +4398,19 @@ intel_wakeref_t intel_runtime_pm_get(struct drm_i915_private *i915)
 
 	ret = pm_runtime_get_sync(kdev);
 	WARN_ONCE(ret < 0, "pm_runtime_get_sync() failed: %d\n", ret);
+}
+
+__attribute__((__used__))
+static intel_wakeref_t intel_runtime_pm_get_raw(struct drm_i915_private *i915)
+{
+	__intel_runtime_pm_get(i915);
+
+	return track_intel_runtime_pm_wakeref_raw(i915);
+}
+
+intel_wakeref_t intel_runtime_pm_get(struct drm_i915_private *i915)
+{
+	__intel_runtime_pm_get(i915);
 
 	return track_intel_runtime_pm_wakeref(i915);
 }
@@ -4430,23 +4486,48 @@ intel_wakeref_t intel_runtime_pm_get_noresume(struct drm_i915_private *i915)
  * intel_runtime_pm_get() and might power down the corresponding
  * hardware block right away if this is the last reference.
  */
+static void __intel_runtime_pm_put_unchecked(struct drm_i915_private *i915)
+{
+	struct pci_dev *pdev = i915->drm.pdev;
+	struct device *kdev = &pdev->dev;
+
+	pm_runtime_mark_last_busy(kdev);
+	pm_runtime_put_autosuspend(kdev);
+}
+
+static void intel_runtime_pm_put_unchecked_raw(struct drm_i915_private *i915)
+{
+	untrack_intel_runtime_pm_wakeref_raw(i915);
+	__intel_runtime_pm_put_unchecked(i915);
+}
+
 void intel_runtime_pm_put_unchecked(struct drm_i915_private *i915)
 {
-	struct pci_dev *pdev = i915->drm.pdev;
-	struct device *kdev = &pdev->dev;
-
 	untrack_intel_runtime_pm_wakeref(i915);
-
-	pm_runtime_mark_last_busy(kdev);
-	pm_runtime_put_autosuspend(kdev);
+	__intel_runtime_pm_put_unchecked(i915);
 }
 
 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
+__attribute__((__used__))
+static void intel_runtime_pm_put_raw(struct drm_i915_private *i915,
+				     intel_wakeref_t wref)
+{
+	cancel_intel_runtime_pm_wakeref(i915, wref);
+	intel_runtime_pm_put_unchecked_raw(i915);
+}
+
 void intel_runtime_pm_put(struct drm_i915_private *i915, intel_wakeref_t wref)
 {
 	cancel_intel_runtime_pm_wakeref(i915, wref);
 	intel_runtime_pm_put_unchecked(i915);
 }
+#else
+__attribute__((__used__))
+static void intel_runtime_pm_put_raw(struct drm_i915_private *i915,
+				     intel_wakeref_t wref)
+{
+	intel_runtime_pm_put_unchecked_raw(i915);
+}
 #endif
 
 /**
@@ -4521,12 +4602,12 @@ void intel_runtime_pm_cleanup(struct drm_i915_private *i915)
 	struct i915_runtime_pm *rpm = &i915->runtime_pm;
 	int count;
 
-	count = atomic_fetch_inc(&rpm->wakeref_count); /* balance untrack */
+	count = atomic_fetch_inc(&rpm->wakeref_track_count); /* balance untrack */
 	WARN(count,
-	     "i915->runtime_pm.wakeref_count=%d on cleanup\n",
+	     "i915->runtime_pm.wakeref_track_count=%d on cleanup\n",
 	     count);
 
-	untrack_intel_runtime_pm_wakeref(i915);
+	untrack_intel_runtime_pm_wakeref_raw(i915);
 }
 
 void intel_runtime_pm_init_early(struct drm_i915_private *i915)
-- 
2.17.1

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[PATCH 02/10] drm/i915: Verify power domains state during suspend in all cases

[Imre Deak]

There is no reason why we couldn't verify the power domains state during
suspend in all cases, so do that. I overlooked this when originally
adding the check.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 4a7bfc945322..cc45cbcb43cb 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -4251,10 +4251,10 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
 	 * Even if power well support was disabled we still want to disable
 	 * power wells if power domains must be deinitialized for suspend.
 	 */
-	if (!i915_modparams.disable_power_well) {
+	if (!i915_modparams.disable_power_well)
 		intel_display_power_put_unchecked(i915, POWER_DOMAIN_INIT);
-		intel_power_domains_verify_state(i915);
-	}
+
+	intel_power_domains_verify_state(i915);
 
 	if (INTEL_GEN(i915) >= 11)
 		icl_display_core_uninit(i915);
-- 
2.17.1

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[PATCH 03/10] drm/i915: Add support for asynchronous display power disabling

[Imre Deak]

By disabling a power domain asynchronously we can restrict holding a
reference on that power domain to the actual code sequence that
requires the power to be on for the HW access it's doing, by also
avoiding unneeded on-off-on togglings of the power domain (since the
disabling happens with a delay).

One benefit is potential power saving if the delay is chosen properly.

In the case of the AUX power domain holding the reference on the domain
for the minimal amount of time at defined spots is also a requirement:
on ICL we need a stricter control of when either kind of AUX power
domain (TBT-alt or DP-alt) can be enabled and the locking we need for
that becomes problematic (due to dependencies on other locks) if we
allow the reference to be held for arbitrarily long periods/places in
the code.

I chose the disabling delay to be 100msec for now to avoid the unneeded
toggling (and so not to introduce dmesg spamming) in the DP MST sideband
signaling code. We could optimize this delay later.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h         |   5 +
 drivers/gpu/drm/i915/intel_runtime_pm.c | 316 +++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_runtime_pm.h |   4 +
 3 files changed, 315 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9fb26634a6be..53a6b0da3571 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -839,6 +839,11 @@ struct i915_power_domains {
 
 	struct mutex lock;
 	int domain_use_count[POWER_DOMAIN_NUM];
+
+	struct delayed_work async_put_work;
+	intel_wakeref_t async_put_wakeref;
+	u64 async_put_domains[2];
+
 	struct i915_power_well *power_wells;
 };
 
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index cc45cbcb43cb..bc0693e3614e 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1883,6 +1883,130 @@ static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
 	chv_set_pipe_power_well(dev_priv, power_well, false);
 }
 
+static intel_wakeref_t
+intel_runtime_pm_get_raw(struct drm_i915_private *i915);
+static void
+intel_runtime_pm_put_raw(struct drm_i915_private *i915, intel_wakeref_t wref);
+
+static u64 __async_put_domains_mask(struct i915_power_domains *power_domains)
+{
+	return power_domains->async_put_domains[0] |
+	       power_domains->async_put_domains[1];
+}
+
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
+
+static bool
+assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains)
+{
+	return !WARN_ON(power_domains->async_put_domains[0] &
+			power_domains->async_put_domains[1]);
+}
+
+static bool
+__async_put_domains_state_ok(struct i915_power_domains *power_domains)
+{
+	enum intel_display_power_domain domain;
+	bool err = false;
+
+	err |= !assert_async_put_domain_masks_disjoint(power_domains);
+	err |= WARN_ON(!!power_domains->async_put_wakeref !=
+		       !!__async_put_domains_mask(power_domains));
+
+	for_each_power_domain(domain, __async_put_domains_mask(power_domains))
+		err |= WARN_ON(power_domains->domain_use_count[domain] != 1);
+
+	return !err;
+}
+
+static void print_power_domains(struct i915_power_domains *power_domains,
+				const char *prefix, u64 mask)
+{
+	enum intel_display_power_domain domain;
+
+	DRM_DEBUG_DRIVER("%s (%lu):\n", prefix, hweight64(mask));
+	for_each_power_domain(domain, mask)
+		DRM_DEBUG_DRIVER("%s use_count %d\n",
+				 intel_display_power_domain_str(domain),
+				 power_domains->domain_use_count[domain]);
+}
+
+static void
+print_async_put_domains_state(struct i915_power_domains *power_domains)
+{
+	DRM_DEBUG_DRIVER("async_put_wakeref %u\n",
+			 power_domains->async_put_wakeref);
+
+	print_power_domains(power_domains, "async_put_domains[0]",
+			    power_domains->async_put_domains[0]);
+	print_power_domains(power_domains, "async_put_domains[1]",
+			    power_domains->async_put_domains[1]);
+}
+
+static void
+verify_async_put_domains_state(struct i915_power_domains *power_domains)
+{
+	if (!__async_put_domains_state_ok(power_domains))
+		print_async_put_domains_state(power_domains);
+}
+
+#else
+
+static void
+assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains)
+{
+}
+
+static void
+verify_async_put_domains_state(struct i915_power_domains *power_domains)
+{
+}
+
+#endif /* CONFIG_DRM_I915_DEBUG_RUNTIME_PM */
+
+static u64 async_put_domains_mask(struct i915_power_domains *power_domains)
+{
+	assert_async_put_domain_masks_disjoint(power_domains);
+
+	return __async_put_domains_mask(power_domains);
+}
+
+static void
+async_put_domains_clear_domain(struct i915_power_domains *power_domains,
+			       enum intel_display_power_domain domain)
+{
+	assert_async_put_domain_masks_disjoint(power_domains);
+
+	power_domains->async_put_domains[0] &= ~BIT_ULL(domain);
+	power_domains->async_put_domains[1] &= ~BIT_ULL(domain);
+}
+
+static bool
+intel_display_power_grab_async_put_ref(struct drm_i915_private *dev_priv,
+				       enum intel_display_power_domain domain)
+{
+	struct i915_power_domains *power_domains = &dev_priv->power_domains;
+	bool ret = false;
+
+	if (!(async_put_domains_mask(power_domains) & BIT_ULL(domain)))
+		goto out_verify;
+
+	async_put_domains_clear_domain(power_domains, domain);
+
+	ret = true;
+
+	if (async_put_domains_mask(power_domains))
+		goto out_verify;
+
+	cancel_delayed_work(&power_domains->async_put_work);
+	intel_runtime_pm_put_raw(dev_priv,
+				 fetch_and_zero(&power_domains->async_put_wakeref));
+out_verify:
+	verify_async_put_domains_state(power_domains);
+
+	return ret;
+}
+
 static void
 __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
 				 enum intel_display_power_domain domain)
@@ -1890,6 +2014,9 @@ __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
 	struct i915_power_well *power_well;
 
+	if (intel_display_power_grab_async_put_ref(dev_priv, domain))
+		return;
+
 	for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain))
 		intel_power_well_get(dev_priv, power_well);
 
@@ -1915,9 +2042,7 @@ intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
 	intel_wakeref_t wakeref = intel_runtime_pm_get(dev_priv);
 
 	mutex_lock(&power_domains->lock);
-
 	__intel_display_power_get_domain(dev_priv, domain);
-
 	mutex_unlock(&power_domains->lock);
 
 	return wakeref;
@@ -1966,24 +2091,36 @@ intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
 	return wakeref;
 }
 
-static void __intel_display_power_put(struct drm_i915_private *dev_priv,
-				      enum intel_display_power_domain domain)
+static void
+__intel_display_power_put_domain(struct drm_i915_private *dev_priv,
+				 enum intel_display_power_domain domain)
 {
 	struct i915_power_domains *power_domains;
 	struct i915_power_well *power_well;
+	const char *name = intel_display_power_domain_str(domain);
 
 	power_domains = &dev_priv->power_domains;
 
-	mutex_lock(&power_domains->lock);
-
 	WARN(!power_domains->domain_use_count[domain],
 	     "Use count on domain %s is already zero\n",
-	     intel_display_power_domain_str(domain));
+	     name);
+	WARN(async_put_domains_mask(power_domains) & BIT_ULL(domain),
+	     "Async disabling of domain %s is pending\n",
+	     name);
+
 	power_domains->domain_use_count[domain]--;
 
 	for_each_power_domain_well_reverse(dev_priv, power_well, BIT_ULL(domain))
 		intel_power_well_put(dev_priv, power_well);
+}
 
+static void __intel_display_power_put(struct drm_i915_private *dev_priv,
+				      enum intel_display_power_domain domain)
+{
+	struct i915_power_domains *power_domains = &dev_priv->power_domains;
+
+	mutex_lock(&power_domains->lock);
+	__intel_display_power_put_domain(dev_priv, domain);
 	mutex_unlock(&power_domains->lock);
 }
 
@@ -2003,6 +2140,159 @@ void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
 	intel_runtime_pm_put_unchecked(dev_priv);
 }
 
+static void
+queue_async_put_domains_work(struct i915_power_domains *power_domains,
+			     intel_wakeref_t wakeref)
+{
+	WARN_ON(power_domains->async_put_wakeref);
+	power_domains->async_put_wakeref = wakeref;
+	WARN_ON(!queue_delayed_work(system_unbound_wq,
+				    &power_domains->async_put_work,
+				    msecs_to_jiffies(100)));
+}
+
+static void
+release_async_put_domains(struct i915_power_domains *power_domains, u64 mask)
+{
+	struct drm_i915_private *dev_priv =
+		container_of(power_domains, struct drm_i915_private,
+			     power_domains);
+	enum intel_display_power_domain domain;
+	intel_wakeref_t wakeref;
+
+	/*
+	 * The caller must hold already raw wakeref, upgrade that to a proper
+	 * wakeref to make the state checker happy about the HW access during
+	 * power well disabling.
+	 */
+	assert_raw_rpm_wakelock_held(dev_priv);
+	wakeref = intel_runtime_pm_get(dev_priv);
+
+	for_each_power_domain(domain, mask) {
+		/* Clear before put, so put's sanity check is happy. */
+		async_put_domains_clear_domain(power_domains, domain);
+		__intel_display_power_put_domain(dev_priv, domain);
+	}
+
+	intel_runtime_pm_put(dev_priv, wakeref);
+}
+
+static void
+intel_display_power_put_async_work(struct work_struct *work)
+{
+	struct drm_i915_private *dev_priv =
+		container_of(work, struct drm_i915_private,
+			     power_domains.async_put_work.work);
+	struct i915_power_domains *power_domains = &dev_priv->power_domains;
+	intel_wakeref_t new_work_wakeref = intel_runtime_pm_get_raw(dev_priv);
+	intel_wakeref_t old_work_wakeref = 0;
+
+	mutex_lock(&power_domains->lock);
+
+	/*
+	 * Bail out if all the domain refs pending to be released were grabbed
+	 * by subsequent gets or a flush_work.
+	 */
+	old_work_wakeref = fetch_and_zero(&power_domains->async_put_wakeref);
+	if (!old_work_wakeref)
+		goto out_verify;
+
+	release_async_put_domains(power_domains,
+				  power_domains->async_put_domains[0]);
+
+	/* Requeue the work if more domains were async put meanwhile. */
+	if (power_domains->async_put_domains[1]) {
+		power_domains->async_put_domains[0] =
+			fetch_and_zero(&power_domains->async_put_domains[1]);
+		queue_async_put_domains_work(power_domains,
+					     fetch_and_zero(&new_work_wakeref));
+	}
+
+out_verify:
+	verify_async_put_domains_state(power_domains);
+
+	mutex_unlock(&power_domains->lock);
+
+	if (old_work_wakeref)
+		intel_runtime_pm_put_raw(dev_priv, old_work_wakeref);
+	if (new_work_wakeref)
+		intel_runtime_pm_put_raw(dev_priv, new_work_wakeref);
+}
+
+void intel_display_power_put_async(struct drm_i915_private *dev_priv,
+				   enum intel_display_power_domain domain,
+				   intel_wakeref_t wakeref)
+{
+	struct i915_power_domains *power_domains = &dev_priv->power_domains;
+	intel_wakeref_t work_wakeref = intel_runtime_pm_get_raw(dev_priv);
+
+	mutex_lock(&power_domains->lock);
+
+	if (power_domains->domain_use_count[domain] > 1) {
+		__intel_display_power_put_domain(dev_priv, domain);
+
+		goto out_verify;
+	}
+
+	WARN_ON(power_domains->domain_use_count[domain] != 1);
+
+	/* Let a pending work requeue itself or queue a new one. */
+	if (power_domains->async_put_wakeref) {
+		power_domains->async_put_domains[1] |= BIT_ULL(domain);
+	} else {
+		power_domains->async_put_domains[0] |= BIT_ULL(domain);
+		queue_async_put_domains_work(power_domains,
+					     fetch_and_zero(&work_wakeref));
+	}
+
+out_verify:
+	verify_async_put_domains_state(power_domains);
+
+	mutex_unlock(&power_domains->lock);
+
+	if (work_wakeref)
+		intel_runtime_pm_put_raw(dev_priv, work_wakeref);
+
+	intel_runtime_pm_put(dev_priv, wakeref);
+}
+
+void intel_display_power_flush_work(struct drm_i915_private *dev_priv)
+{
+	struct i915_power_domains *power_domains = &dev_priv->power_domains;
+	intel_wakeref_t work_wakeref;
+
+	mutex_lock(&power_domains->lock);
+
+	work_wakeref = fetch_and_zero(&power_domains->async_put_wakeref);
+	if (!work_wakeref)
+		goto out_verify;
+
+	release_async_put_domains(power_domains,
+				  async_put_domains_mask(power_domains));
+	cancel_delayed_work(&power_domains->async_put_work);
+
+out_verify:
+	verify_async_put_domains_state(power_domains);
+
+	mutex_unlock(&power_domains->lock);
+
+	if (work_wakeref)
+		intel_runtime_pm_put_raw(dev_priv, work_wakeref);
+}
+
+static void
+intel_display_power_flush_work_sync(struct drm_i915_private *dev_priv)
+{
+	struct i915_power_domains *power_domains = &dev_priv->power_domains;
+
+	intel_display_power_flush_work(dev_priv);
+	cancel_delayed_work_sync(&power_domains->async_put_work);
+
+	verify_async_put_domains_state(power_domains);
+
+	WARN_ON(power_domains->async_put_wakeref);
+}
+
 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
 void intel_display_power_put(struct drm_i915_private *dev_priv,
 			     enum intel_display_power_domain domain,
@@ -3491,6 +3781,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
 
 	mutex_init(&power_domains->lock);
 
+	INIT_DELAYED_WORK(&power_domains->async_put_work,
+			  intel_display_power_put_async_work);
+
 	/*
 	 * The enabling order will be from lower to higher indexed wells,
 	 * the disabling order is reversed.
@@ -4168,6 +4461,8 @@ void intel_power_domains_fini_hw(struct drm_i915_private *i915)
 	if (!i915_modparams.disable_power_well)
 		intel_display_power_put_unchecked(i915, POWER_DOMAIN_INIT);
 
+	intel_display_power_flush_work_sync(i915);
+
 	intel_power_domains_verify_state(i915);
 
 	/* Keep the power well enabled, but cancel its rpm wakeref. */
@@ -4243,6 +4538,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
 	if (!(i915->csr.allowed_dc_mask & DC_STATE_EN_DC9) &&
 	    suspend_mode == I915_DRM_SUSPEND_IDLE &&
 	    i915->csr.dmc_payload) {
+		intel_display_power_flush_work(i915);
 		intel_power_domains_verify_state(i915);
 		return;
 	}
@@ -4254,6 +4550,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
 	if (!i915_modparams.disable_power_well)
 		intel_display_power_put_unchecked(i915, POWER_DOMAIN_INIT);
 
+	intel_display_power_flush_work(i915);
 	intel_power_domains_verify_state(i915);
 
 	if (INTEL_GEN(i915) >= 11)
@@ -4332,6 +4629,8 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915)
 
 	mutex_lock(&power_domains->lock);
 
+	verify_async_put_domains_state(power_domains);
+
 	dump_domain_info = false;
 	for_each_power_well(i915, power_well) {
 		enum intel_display_power_domain domain;
@@ -4400,7 +4699,6 @@ static void __intel_runtime_pm_get(struct drm_i915_private *i915)
 	WARN_ONCE(ret < 0, "pm_runtime_get_sync() failed: %d\n", ret);
 }
 
-__attribute__((__used__))
 static intel_wakeref_t intel_runtime_pm_get_raw(struct drm_i915_private *i915)
 {
 	__intel_runtime_pm_get(i915);
@@ -4508,7 +4806,6 @@ void intel_runtime_pm_put_unchecked(struct drm_i915_private *i915)
 }
 
 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
-__attribute__((__used__))
 static void intel_runtime_pm_put_raw(struct drm_i915_private *i915,
 				     intel_wakeref_t wref)
 {
@@ -4522,7 +4819,6 @@ void intel_runtime_pm_put(struct drm_i915_private *i915, intel_wakeref_t wref)
 	intel_runtime_pm_put_unchecked(i915);
 }
 #else
-__attribute__((__used__))
 static void intel_runtime_pm_put_raw(struct drm_i915_private *i915,
 				     intel_wakeref_t wref)
 {
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.h b/drivers/gpu/drm/i915/intel_runtime_pm.h
index 69227756de3e..cabf6f900273 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.h
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.h
@@ -57,6 +57,10 @@ intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
 				   enum intel_display_power_domain domain);
 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
 				       enum intel_display_power_domain domain);
+void intel_display_power_put_async(struct drm_i915_private *dev_priv,
+				   enum intel_display_power_domain domain,
+				   intel_wakeref_t wakeref);
+void intel_display_power_flush_work(struct drm_i915_private *dev_priv);
 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
 void intel_display_power_put(struct drm_i915_private *dev_priv,
 			     enum intel_display_power_domain domain,
-- 
2.17.1

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[PATCH 04/10] drm/i915: Disable power asynchronously during DP AUX transfers

[Imre Deak]

In a follow-up patch we will restrict holding the reference on the AUX
power domain to the AUX transfer function. To avoid the unnecessary
on-off-on power togglings drop the reference asynchronously.

There is no reason we couldn't do this in general and also put the
reference asynchronously in pps_unlock(); but that's a separate change
that can be done as a follow-up.

Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 42a880e0b392..0475601c2f33 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1219,7 +1219,10 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
 			to_i915(intel_dig_port->base.base.dev);
 	i915_reg_t ch_ctl, ch_data[5];
 	u32 aux_clock_divider;
-	intel_wakeref_t wakeref;
+	enum intel_display_power_domain aux_domain =
+		intel_aux_power_domain(intel_dig_port);
+	intel_wakeref_t aux_wakeref;
+	intel_wakeref_t pps_wakeref;
 	int i, ret, recv_bytes;
 	int try, clock = 0;
 	u32 status;
@@ -1229,7 +1232,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
 	for (i = 0; i < ARRAY_SIZE(ch_data); i++)
 		ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
 
-	wakeref = pps_lock(intel_dp);
+	aux_wakeref = intel_display_power_get(dev_priv, aux_domain);
+	pps_wakeref = pps_lock(intel_dp);
 
 	/*
 	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
@@ -1375,7 +1379,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
 	if (vdd)
 		edp_panel_vdd_off(intel_dp, false);
 
-	pps_unlock(intel_dp, wakeref);
+	pps_unlock(intel_dp, pps_wakeref);
+	intel_display_power_put_async(dev_priv, aux_domain, aux_wakeref);
 
 	return ret;
 }
-- 
2.17.1

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[PATCH 05/10] drm/i915: WARN for eDP encoders in intel_dp_detect_dpcd()

[Imre Deak]

We are not calling this function for eDP, so add an early assert about
this for clarity.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 0475601c2f33..1865286eacae 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4842,15 +4842,15 @@ intel_dp_detect_dpcd(struct intel_dp *intel_dp)
 	u8 *dpcd = intel_dp->dpcd;
 	u8 type;
 
+	if (WARN_ON(intel_dp_is_edp(intel_dp)))
+		return connector_status_connected;
+
 	if (lspcon->active)
 		lspcon_resume(lspcon);
 
 	if (!intel_dp_get_dpcd(intel_dp))
 		return connector_status_disconnected;
 
-	if (intel_dp_is_edp(intel_dp))
-		return connector_status_connected;
-
 	/* if there's no downstream port, we're done */
 	if (!drm_dp_is_branch(dpcd))
 		return connector_status_connected;
-- 
2.17.1

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[PATCH 06/10] drm/i915: Remove the unneeded AUX power ref from intel_dp_detect()

[Imre Deak]

We don't need the AUX power for the whole duration of the detect, only
when we're doing AUX transfers. The AUX transfer function takes its own
reference on the AUX power domain already. The two places during detect
which access display core registers (not specific to a
pipe/port/transcoder) only need the power domain that is required for
that access. That power domain is equivalent to the device global power
domain on most platforms (enabled whenever we hold a runtime PM
reference) except on CHV/VLV where it's equivalent to the display power
well.

Add a new power domain that reflects the above, and use this at the two
spots accessing registers. With that we can avoid taking the AUX
reference for the whole duration of the detect function.

Put the domains asynchronously to avoid the unneeded on-off-on toggling.

Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_display.h    |  1 +
 drivers/gpu/drm/i915/intel_dp.c         | 32 +++++++++++++++++--------
 drivers/gpu/drm/i915/intel_runtime_pm.c |  4 ++++
 3 files changed, 27 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index 2220588e86ac..fd62a6f40d22 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -218,6 +218,7 @@ enum aux_ch {
 #define aux_ch_name(a) ((a) + 'A')
 
 enum intel_display_power_domain {
+	POWER_DOMAIN_DISPLAY_CORE,
 	POWER_DOMAIN_PIPE_A,
 	POWER_DOMAIN_PIPE_B,
 	POWER_DOMAIN_PIPE_C,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1865286eacae..fee1f291aba8 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -214,15 +214,21 @@ static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp)
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 	enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
+	intel_wakeref_t wakeref;
 	u32 lane_info;
 
 	if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)
 		return 4;
 
+	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
+
 	lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
 		     DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
 		    DP_LANE_ASSIGNMENT_SHIFT(tc_port);
 
+	intel_display_power_put_async(dev_priv, POWER_DOMAIN_DISPLAY_CORE,
+				      wakeref);
+
 	switch (lane_info) {
 	default:
 		MISSING_CASE(lane_info);
@@ -5292,7 +5298,7 @@ static bool icl_digital_port_connected(struct intel_encoder *encoder)
  *
  * Return %true if port is connected, %false otherwise.
  */
-bool intel_digital_port_connected(struct intel_encoder *encoder)
+static bool __intel_digital_port_connected(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
@@ -5322,6 +5328,20 @@ bool intel_digital_port_connected(struct intel_encoder *encoder)
 	return false;
 }
 
+bool intel_digital_port_connected(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	intel_wakeref_t wakeref;
+	bool res;
+
+	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
+	res = __intel_digital_port_connected(encoder);
+	intel_display_power_put_async(dev_priv, POWER_DOMAIN_DISPLAY_CORE,
+				      wakeref);
+
+	return res;
+}
+
 static struct edid *
 intel_dp_get_edid(struct intel_dp *intel_dp)
 {
@@ -5375,16 +5395,11 @@ intel_dp_detect(struct drm_connector *connector,
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct intel_encoder *encoder = &dig_port->base;
 	enum drm_connector_status status;
-	enum intel_display_power_domain aux_domain =
-		intel_aux_power_domain(dig_port);
-	intel_wakeref_t wakeref;
 
 	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
 		      connector->base.id, connector->name);
 	WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
 
-	wakeref = intel_display_power_get(dev_priv, aux_domain);
-
 	/* Can't disconnect eDP */
 	if (intel_dp_is_edp(intel_dp))
 		status = edp_detect(intel_dp);
@@ -5448,10 +5463,8 @@ intel_dp_detect(struct drm_connector *connector,
 		int ret;
 
 		ret = intel_dp_retrain_link(encoder, ctx);
-		if (ret) {
-			intel_display_power_put(dev_priv, aux_domain, wakeref);
+		if (ret)
 			return ret;
-		}
 	}
 
 	/*
@@ -5473,7 +5486,6 @@ intel_dp_detect(struct drm_connector *connector,
 	if (status != connector_status_connected && !intel_dp->is_mst)
 		intel_dp_unset_edid(intel_dp);
 
-	intel_display_power_put(dev_priv, aux_domain, wakeref);
 	return status;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index bc0693e3614e..31ac5ebb32d6 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -373,6 +373,8 @@ const char *
 intel_display_power_domain_str(enum intel_display_power_domain domain)
 {
 	switch (domain) {
+	case POWER_DOMAIN_DISPLAY_CORE:
+		return "DISPLAY_CORE";
 	case POWER_DOMAIN_PIPE_A:
 		return "PIPE_A";
 	case POWER_DOMAIN_PIPE_B:
@@ -2313,6 +2315,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 	BIT_ULL(POWER_DOMAIN_INIT))
 
 #define VLV_DISPLAY_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) |	\
 	BIT_ULL(POWER_DOMAIN_PIPE_A) |		\
 	BIT_ULL(POWER_DOMAIN_PIPE_B) |		\
 	BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |	\
@@ -2359,6 +2362,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 	BIT_ULL(POWER_DOMAIN_INIT))
 
 #define CHV_DISPLAY_POWER_DOMAINS (		\
+	BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) |	\
 	BIT_ULL(POWER_DOMAIN_PIPE_A) |		\
 	BIT_ULL(POWER_DOMAIN_PIPE_B) |		\
 	BIT_ULL(POWER_DOMAIN_PIPE_C) |		\
-- 
2.17.1

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[PATCH 07/10] drm/i915: Remove the unneeded AUX power ref from intel_dp_hpd_pulse()

[Imre Deak]

The power get/put was added in

commit 1c767b339b3938b19076ffdc9d70aa1e4235a45b
Author: Imre Deak <imre.deak@intel.com>
Date:   Mon Aug 18 14:42:42 2014 +0300

    drm/i915: take display port power domain in DP HPD handle

to account for the HW access in ibx_digital_port_connected(). This
latter call was in turn removed in

commit 7d23e3c37bb3fc6952dc84007ee60cb533fd2d5c
Author: Shubhangi Shrivastava <shubhangi.shrivastava@intel.com>
Date:   Wed Mar 30 18:05:23 2016 +0530

    drm/i915: Cleaning up intel_dp_hpd_pulse

after which we didn't actually need the power reference.

One way we are accessing the HW during HPD pulse handling is via DP AUX
transfers, but the transfer function takes its own reference, so doesn't
need the reference in intel_dp_hpd_pulse().

The other spot is in the PSR code doing register access, for that we can
use the DISPLAY_CORE power domain in a similar way done in the previous
patch.

Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  | 20 ++++----------------
 drivers/gpu/drm/i915/intel_psr.c |  6 ++++++
 2 files changed, 10 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index fee1f291aba8..f56cbda59fb3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -6306,9 +6306,6 @@ enum irqreturn
 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
 {
 	struct intel_dp *intel_dp = &intel_dig_port->dp;
-	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-	enum irqreturn ret = IRQ_NONE;
-	intel_wakeref_t wakeref;
 
 	if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
 		/*
@@ -6331,9 +6328,6 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
 		return IRQ_NONE;
 	}
 
-	wakeref = intel_display_power_get(dev_priv,
-					  intel_aux_power_domain(intel_dig_port));
-
 	if (intel_dp->is_mst) {
 		if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
 			/*
@@ -6345,7 +6339,8 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
 			intel_dp->is_mst = false;
 			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
 							intel_dp->is_mst);
-			goto put_power;
+
+			return IRQ_NONE;
 		}
 	}
 
@@ -6355,17 +6350,10 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
 		handled = intel_dp_short_pulse(intel_dp);
 
 		if (!handled)
-			goto put_power;
+			return IRQ_NONE;
 	}
 
-	ret = IRQ_HANDLED;
-
-put_power:
-	intel_display_power_put(dev_priv,
-				intel_aux_power_domain(intel_dig_port),
-				wakeref);
-
-	return ret;
+	return IRQ_HANDLED;
 }
 
 /* check the VBT to see whether the eDP is on another port */
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 963663ba0edf..856a39c7ee77 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -1251,10 +1251,13 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
 	const u8 errors = DP_PSR_RFB_STORAGE_ERROR |
 			  DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
 			  DP_PSR_LINK_CRC_ERROR;
+	intel_wakeref_t wakeref;
 
 	if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp))
 		return;
 
+	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
+
 	mutex_lock(&psr->lock);
 
 	if (!psr->enabled || psr->dp != intel_dp)
@@ -1294,6 +1297,9 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
 	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val);
 exit:
 	mutex_unlock(&psr->lock);
+
+	intel_display_power_put_async(dev_priv, POWER_DOMAIN_DISPLAY_CORE,
+				      wakeref);
 }
 
 bool intel_psr_enabled(struct intel_dp *intel_dp)
-- 
2.17.1

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[PATCH 08/10] drm/i915: Replace use of PLLS power domain with DISPLAY_CORE domain

[Imre Deak]

There isn't a separate power domain specific to PLLs. When programming
them we require the same power domain to be enabled which is needed when
accessing other display core parts (not specific to any
pipe/port/transcoder). This corresponds to the DISPLAY_CORE domain added
previously in this patchset, so use that instead to save bits in the
power domain mask.

Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c    |  2 +-
 drivers/gpu/drm/i915/intel_display.h    |  1 -
 drivers/gpu/drm/i915/intel_dpll_mgr.c   | 36 ++++++++++++-------------
 drivers/gpu/drm/i915/intel_runtime_pm.c |  2 --
 4 files changed, 19 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index dd65d7c521c1..45c9d3e10c97 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6349,7 +6349,7 @@ static u64 get_crtc_power_domains(struct drm_crtc *crtc,
 		mask |= BIT_ULL(POWER_DOMAIN_AUDIO);
 
 	if (crtc_state->shared_dpll)
-		mask |= BIT_ULL(POWER_DOMAIN_PLLS);
+		mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
 
 	return mask;
 }
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index fd62a6f40d22..e1324c3b2b52 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -249,7 +249,6 @@ enum intel_display_power_domain {
 	POWER_DOMAIN_PORT_OTHER,
 	POWER_DOMAIN_VGA,
 	POWER_DOMAIN_AUDIO,
-	POWER_DOMAIN_PLLS,
 	POWER_DOMAIN_AUX_A,
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_AUX_C,
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index dda5ddb49b34..0d029ffb8ce0 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -350,7 +350,7 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
 	u32 val;
 
 	wakeref = intel_display_power_get_if_enabled(dev_priv,
-						     POWER_DOMAIN_PLLS);
+						     POWER_DOMAIN_DISPLAY_CORE);
 	if (!wakeref)
 		return false;
 
@@ -359,7 +359,7 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
 	hw_state->fp0 = I915_READ(PCH_FP0(id));
 	hw_state->fp1 = I915_READ(PCH_FP1(id));
 
-	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS, wakeref);
+	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
 
 	return val & DPLL_VCO_ENABLE;
 }
@@ -518,14 +518,14 @@ static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
 	u32 val;
 
 	wakeref = intel_display_power_get_if_enabled(dev_priv,
-						     POWER_DOMAIN_PLLS);
+						     POWER_DOMAIN_DISPLAY_CORE);
 	if (!wakeref)
 		return false;
 
 	val = I915_READ(WRPLL_CTL(id));
 	hw_state->wrpll = val;
 
-	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS, wakeref);
+	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
 
 	return val & WRPLL_PLL_ENABLE;
 }
@@ -538,14 +538,14 @@ static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,
 	u32 val;
 
 	wakeref = intel_display_power_get_if_enabled(dev_priv,
-						     POWER_DOMAIN_PLLS);
+						     POWER_DOMAIN_DISPLAY_CORE);
 	if (!wakeref)
 		return false;
 
 	val = I915_READ(SPLL_CTL);
 	hw_state->spll = val;
 
-	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS, wakeref);
+	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
 
 	return val & SPLL_PLL_ENABLE;
 }
@@ -1003,7 +1003,7 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
 	bool ret;
 
 	wakeref = intel_display_power_get_if_enabled(dev_priv,
-						     POWER_DOMAIN_PLLS);
+						     POWER_DOMAIN_DISPLAY_CORE);
 	if (!wakeref)
 		return false;
 
@@ -1024,7 +1024,7 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
 	ret = true;
 
 out:
-	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS, wakeref);
+	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
 
 	return ret;
 }
@@ -1040,7 +1040,7 @@ static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv,
 	bool ret;
 
 	wakeref = intel_display_power_get_if_enabled(dev_priv,
-						     POWER_DOMAIN_PLLS);
+						     POWER_DOMAIN_DISPLAY_CORE);
 	if (!wakeref)
 		return false;
 
@@ -1057,7 +1057,7 @@ static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv,
 	ret = true;
 
 out:
-	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS, wakeref);
+	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
 
 	return ret;
 }
@@ -1601,7 +1601,7 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
 	bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
 
 	wakeref = intel_display_power_get_if_enabled(dev_priv,
-						     POWER_DOMAIN_PLLS);
+						     POWER_DOMAIN_DISPLAY_CORE);
 	if (!wakeref)
 		return false;
 
@@ -1659,7 +1659,7 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
 	ret = true;
 
 out:
-	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS, wakeref);
+	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
 
 	return ret;
 }
@@ -2107,7 +2107,7 @@ static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
 	bool ret;
 
 	wakeref = intel_display_power_get_if_enabled(dev_priv,
-						     POWER_DOMAIN_PLLS);
+						     POWER_DOMAIN_DISPLAY_CORE);
 	if (!wakeref)
 		return false;
 
@@ -2127,7 +2127,7 @@ static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
 	ret = true;
 
 out:
-	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS, wakeref);
+	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
 
 	return ret;
 }
@@ -2882,7 +2882,7 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv,
 	u32 val;
 
 	wakeref = intel_display_power_get_if_enabled(dev_priv,
-						     POWER_DOMAIN_PLLS);
+						     POWER_DOMAIN_DISPLAY_CORE);
 	if (!wakeref)
 		return false;
 
@@ -2929,7 +2929,7 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv,
 
 	ret = true;
 out:
-	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS, wakeref);
+	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
 	return ret;
 }
 
@@ -2944,7 +2944,7 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
 	u32 val;
 
 	wakeref = intel_display_power_get_if_enabled(dev_priv,
-						     POWER_DOMAIN_PLLS);
+						     POWER_DOMAIN_DISPLAY_CORE);
 	if (!wakeref)
 		return false;
 
@@ -2957,7 +2957,7 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
 
 	ret = true;
 out:
-	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS, wakeref);
+	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
 	return ret;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 31ac5ebb32d6..2cbad29ee595 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -435,8 +435,6 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
 		return "VGA";
 	case POWER_DOMAIN_AUDIO:
 		return "AUDIO";
-	case POWER_DOMAIN_PLLS:
-		return "PLLS";
 	case POWER_DOMAIN_AUX_A:
 		return "AUX_A";
 	case POWER_DOMAIN_AUX_B:
-- 
2.17.1

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[PATCH 09/10] drm/i915: Avoid taking the PPS lock for non-eDP/VLV/CHV

[Imre Deak]

On ICL we have to make sure that we enable the AUX power domain in a
controlled way (corresponding to the port's actual TypeC mode). Since
the PPS lock - which takes an AUX power ref - is only needed on
eDP/VLV/CHV avoid taking it in other cases.

Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f56cbda59fb3..1ee9b7ebd801 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -6263,6 +6263,10 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder)
 
 	intel_dp->reset_link_params = true;
 
+	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
+	    !intel_dp_is_edp(intel_dp))
+		return;
+
 	with_pps_lock(intel_dp, wakeref) {
 		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 			intel_dp->active_pipe = vlv_active_pipe(intel_dp);
-- 
2.17.1

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[PATCH 10/10] drm/i915: Assert that TypeC ports are not used for eDP

[Imre Deak]

Add an assert that we don't use TypeC ports for eDP. That may in theory
be possible on TypeC legacy ports, but I'm not sure if that's a
practical scenario, so let's deal with that only if there's a use case.
Adding support for that wouldn't be too difficult, since TypeC mode
switching is not possible on TypeC legacy ports.

Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1ee9b7ebd801..f8b384cb04d6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -7210,10 +7210,16 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 	intel_dp->DP = I915_READ(intel_dp->output_reg);
 	intel_dp->attached_connector = intel_connector;
 
-	if (intel_dp_is_port_edp(dev_priv, port))
+	if (intel_dp_is_port_edp(dev_priv, port)) {
+		/*
+		 * Currently we don't support eDP on TypeC ports, although in
+		 * theory it could work on TypeC legacy ports.
+		 */
+		WARN_ON(intel_port_is_tc(dev_priv, port));
 		type = DRM_MODE_CONNECTOR_eDP;
-	else
+	} else {
 		type = DRM_MODE_CONNECTOR_DisplayPort;
+	}
 
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		intel_dp->active_pipe = vlv_active_pipe(intel_dp);
-- 
2.17.1

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✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add support for asynchronous display power disabling

[Patchwork]

== Series Details ==

Series: drm/i915: Add support for asynchronous display power disabling
URL   : https://patchwork.freedesktop.org/series/60242/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
51d597ed4135 drm/i915: Add support for tracking wakerefs w/o power-on guarantee
105dea8ad0dc drm/i915: Verify power domains state during suspend in all cases
e96c9522db7b drm/i915: Add support for asynchronous display power disabling
5973f78ce699 drm/i915: Disable power asynchronously during DP AUX transfers
46a227a6cb90 drm/i915: WARN for eDP encoders in intel_dp_detect_dpcd()
032d4c40cffe drm/i915: Remove the unneeded AUX power ref from intel_dp_detect()
5ed3bacef970 drm/i915: Remove the unneeded AUX power ref from intel_dp_hpd_pulse()
-:12: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 1c767b339b39 ("drm/i915: take display port power domain in DP HPD handler")'
#12: 
commit 1c767b339b3938b19076ffdc9d70aa1e4235a45b

-:21: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 7d23e3c37bb3 ("drm/i915: Cleaning up intel_dp_hpd_pulse")'
#21: 
commit 7d23e3c37bb3fc6952dc84007ee60cb533fd2d5c

total: 2 errors, 0 warnings, 0 checks, 68 lines checked
e597618a7634 drm/i915: Replace use of PLLS power domain with DISPLAY_CORE domain
08ce0f3433d1 drm/i915: Avoid taking the PPS lock for non-eDP/VLV/CHV
ba990253d5d8 drm/i915: Assert that TypeC ports are not used for eDP

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✗ Fi.CI.SPARSE: warning for drm/i915: Add support for asynchronous display power disabling

[Patchwork]

== Series Details ==

Series: drm/i915: Add support for asynchronous display power disabling
URL   : https://patchwork.freedesktop.org/series/60242/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Add support for tracking wakerefs w/o power-on guarantee
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3448:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3449:16: warning: expression using sizeof(void)

Commit: drm/i915: Verify power domains state during suspend in all cases
Okay!

Commit: drm/i915: Add support for asynchronous display power disabling
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3449:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3454:16: warning: expression using sizeof(void)

Commit: drm/i915: Disable power asynchronously during DP AUX transfers
Okay!

Commit: drm/i915: WARN for eDP encoders in intel_dp_detect_dpcd()
Okay!

Commit: drm/i915: Remove the unneeded AUX power ref from intel_dp_detect()
Okay!

Commit: drm/i915: Remove the unneeded AUX power ref from intel_dp_hpd_pulse()
Okay!

Commit: drm/i915: Replace use of PLLS power domain with DISPLAY_CORE domain
Okay!

Commit: drm/i915: Avoid taking the PPS lock for non-eDP/VLV/CHV
Okay!

Commit: drm/i915: Assert that TypeC ports are not used for eDP
Okay!

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✓ Fi.CI.BAT: success for drm/i915: Add support for asynchronous display power disabling

[Patchwork]

== Series Details ==

Series: drm/i915: Add support for asynchronous display power disabling
URL   : https://patchwork.freedesktop.org/series/60242/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6032 -> Patchwork_12955
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/60242/revisions/1/mbox/

Known issues
------------

  Here are the changes found in Patchwork_12955 that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      [FAIL][1] ([fdo#108511]) -> [PASS][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html

  
  [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511


Participating hosts (49 -> 43)
------------------------------

  Additional (2): fi-bxt-dsi fi-icl-dsi 
  Missing    (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_6032 -> Patchwork_12955

  CI_DRM_6032: 6ad93073ac75c314e859cfe1020b569d0c63ccf5 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4972: f052e49a43cc9704ea5f240df15dd9d3dfed68ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12955: ba990253d5d8234db983bd54d29ed627c9a613c8 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

ba990253d5d8 drm/i915: Assert that TypeC ports are not used for eDP
08ce0f3433d1 drm/i915: Avoid taking the PPS lock for non-eDP/VLV/CHV
e597618a7634 drm/i915: Replace use of PLLS power domain with DISPLAY_CORE domain
5ed3bacef970 drm/i915: Remove the unneeded AUX power ref from intel_dp_hpd_pulse()
032d4c40cffe drm/i915: Remove the unneeded AUX power ref from intel_dp_detect()
46a227a6cb90 drm/i915: WARN for eDP encoders in intel_dp_detect_dpcd()
5973f78ce699 drm/i915: Disable power asynchronously during DP AUX transfers
e96c9522db7b drm/i915: Add support for asynchronous display power disabling
105dea8ad0dc drm/i915: Verify power domains state during suspend in all cases
51d597ed4135 drm/i915: Add support for tracking wakerefs w/o power-on guarantee

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/
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✗ Fi.CI.IGT: failure for drm/i915: Add support for asynchronous display power disabling

[Patchwork]

== Series Details ==

Series: drm/i915: Add support for asynchronous display power disabling
URL   : https://patchwork.freedesktop.org/series/60242/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_6032_full -> Patchwork_12955_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_12955_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_12955_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_12955_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_persistent_relocs@forked-interruptible-thrashing:
    - shard-glk:          [PASS][1] -> [TIMEOUT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-glk6/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-glk7/igt@gem_persistent_relocs@forked-interruptible-thrashing.html

  
Known issues
------------

  Here are the changes found in Patchwork_12955_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@drm-resources-equal:
    - shard-skl:          [PASS][3] -> [INCOMPLETE][4] ([fdo#107807] / [fdo#110581])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-skl10/igt@i915_pm_rpm@drm-resources-equal.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-skl8/igt@i915_pm_rpm@drm-resources-equal.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-iclb:         [PASS][5] -> [DMESG-WARN][6] ([fdo#107724])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-iclb1/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-iclb2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled:
    - shard-skl:          [PASS][7] -> [FAIL][8] ([fdo#103184] / [fdo#103232])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-skl2/igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-skl9/igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled.html

  * igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-cpu:
    - shard-skl:          [PASS][9] -> [FAIL][10] ([fdo#103167] / [fdo#110379])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-skl2/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-cpu.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-skl9/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbc-tilingchange:
    - shard-iclb:         [PASS][11] -> [FAIL][12] ([fdo#103167]) +4 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-tilingchange.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-tilingchange.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt:
    - shard-skl:          [PASS][13] -> [FAIL][14] ([fdo#108040])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-skl2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-skl9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
    - shard-glk:          [PASS][15] -> [SKIP][16] ([fdo#109271])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-glk9/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-glk4/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
    - shard-apl:          [PASS][17] -> [DMESG-WARN][18] ([fdo#108566]) +3 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html

  * igt@kms_plane@plane-position-hole-dpms-pipe-b-planes:
    - shard-snb:          [PASS][19] -> [SKIP][20] ([fdo#109271]) +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-snb2/igt@kms_plane@plane-position-hole-dpms-pipe-b-planes.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-snb2/igt@kms_plane@plane-position-hole-dpms-pipe-b-planes.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [PASS][21] -> [FAIL][22] ([fdo#108145])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_psr@psr2_primary_mmap_cpu:
    - shard-iclb:         [PASS][23] -> [SKIP][24] ([fdo#109441]) +2 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-iclb3/igt@kms_psr@psr2_primary_mmap_cpu.html

  
#### Possible fixes ####

  * igt@gem_workarounds@suspend-resume:
    - shard-apl:          [DMESG-WARN][25] ([fdo#108566]) -> [PASS][26] +6 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-apl7/igt@gem_workarounds@suspend-resume.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-apl4/igt@gem_workarounds@suspend-resume.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - shard-iclb:         [INCOMPLETE][27] ([fdo#107713] / [fdo#108840] / [fdo#110581]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-iclb4/igt@i915_pm_rpm@basic-pci-d3-state.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-iclb7/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_pm_rpm@i2c:
    - shard-iclb:         [DMESG-WARN][29] ([fdo#109982]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-iclb2/igt@i915_pm_rpm@i2c.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-iclb3/igt@i915_pm_rpm@i2c.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt:
    - shard-iclb:         [FAIL][31] ([fdo#103167]) -> [PASS][32] +7 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
    - shard-glk:          [SKIP][33] ([fdo#109271]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-glk4/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-glk9/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [FAIL][35] ([fdo#108145] / [fdo#110403]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_plane_scaling@pipe-a-scaler-with-pixel-format:
    - shard-glk:          [SKIP][37] ([fdo#109271] / [fdo#109278]) -> [PASS][38] +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-glk3/igt@kms_plane_scaling@pipe-a-scaler-with-pixel-format.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-glk9/igt@kms_plane_scaling@pipe-a-scaler-with-pixel-format.html

  * igt@kms_psr@psr2_cursor_mmap_cpu:
    - shard-iclb:         [SKIP][39] ([fdo#109441]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-iclb1/igt@kms_psr@psr2_cursor_mmap_cpu.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html

  * igt@kms_setmode@basic:
    - shard-apl:          [FAIL][41] ([fdo#99912]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-apl8/igt@kms_setmode@basic.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-apl1/igt@kms_setmode@basic.html
    - shard-kbl:          [FAIL][43] ([fdo#99912]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-kbl1/igt@kms_setmode@basic.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-kbl6/igt@kms_setmode@basic.html

  * igt@kms_sysfs_edid_timing:
    - shard-iclb:         [FAIL][45] ([fdo#100047]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-iclb3/igt@kms_sysfs_edid_timing.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-iclb5/igt@kms_sysfs_edid_timing.html

  * igt@tools_test@tools_test:
    - shard-iclb:         [SKIP][47] ([fdo#109352]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-iclb6/igt@tools_test@tools_test.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-iclb1/igt@tools_test@tools_test.html

  
#### Warnings ####

  * igt@kms_atomic_transition@3x-modeset-transitions:
    - shard-snb:          [SKIP][49] ([fdo#109271] / [fdo#109278]) -> [SKIP][50] ([fdo#109271])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-snb2/igt@kms_atomic_transition@3x-modeset-transitions.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-snb2/igt@kms_atomic_transition@3x-modeset-transitions.html

  
  [fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109352]: https://bugs.freedesktop.org/show_bug.cgi?id=109352
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109982]: https://bugs.freedesktop.org/show_bug.cgi?id=109982
  [fdo#110379]: https://bugs.freedesktop.org/show_bug.cgi?id=110379
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#110581]: https://bugs.freedesktop.org/show_bug.cgi?id=110581
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_6032 -> Patchwork_12955

  CI_DRM_6032: 6ad93073ac75c314e859cfe1020b569d0c63ccf5 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4972: f052e49a43cc9704ea5f240df15dd9d3dfed68ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12955: ba990253d5d8234db983bd54d29ed627c9a613c8 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: ✗ Fi.CI.IGT: failure for drm/i915: Add support for asynchronous display power disabling

[Imre Deak]

On Fri, May 03, 2019 at 07:50:26AM +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: Add support for asynchronous display power disabling
> URL   : https://patchwork.freedesktop.org/series/60242/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_6032_full -> Patchwork_12955_full
> ====================================================
> 
> Summary
> -------
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_12955_full absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_12955_full, please notify your bug team to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> Possible new issues
> -------------------
> 
>   Here are the unknown changes that may have been introduced in Patchwork_12955_full:
> 
> ### IGT changes ###
> 
> #### Possible regressions ####
> 
>   * igt@gem_persistent_relocs@forked-interruptible-thrashing:
>     - shard-glk:          [PASS][1] -> [TIMEOUT][2]
>    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-glk6/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
>    [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-glk7/igt@gem_persistent_relocs@forked-interruptible-thrashing.html

Looks like an unrelated issue: on this GLK there are two HDMI displays
connected, so the change shouldn't make any diffence on it. The change
only affects the DP detect and hotplug paths, where we'll do now an
async power domain put.

The machine is still up when the problem happens, the test seems to get
stuck and aborted by the test runner (after ~6mins according to [1]).

[43/82] (762s left) gem_persistent_relocs (forked-interruptible-thrashing)
Starting subtest: forked-interruptible-thrashing
Timeout. Killing the current test with SIGQUIT.
Timeout. Killing the current test with SIGKILL.
Build timed out (after 20 minutes)

Err:	
Starting subtest: forked-interruptible-thrashing
Received signal SIGQUIT.
Stack trace: 
 #0 [fatal_sig_handler+0xd5]
 #1 [killpg+0x40]
 #2 [waitpid+0x12]
 #3 [__waitpid+0x38]
 #4 [igt_wait_helper+0x44]
 #5 [igt_stop_helper+0x52]
 #6 [do_forked_test+0x13e]
 #7 [__real_main317+0x1b4]
 #8 [main+0x44]
 #9 [__libc_start_main+0xe7]
 #10 [_start+0x2a]

[1] https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-glk7/runtimes25.log

> 
>   
> Known issues
> ------------
> 
>   Here are the changes found in Patchwork_12955_full that come from known issues:
> 
> ### IGT changes ###
> 
> #### Issues hit ####
> 
>   * igt@i915_pm_rpm@drm-resources-equal:
>     - shard-skl:          [PASS][3] -> [INCOMPLETE][4] ([fdo#107807] / [fdo#110581])
>    [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-skl10/igt@i915_pm_rpm@drm-resources-equal.html
>    [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-skl8/igt@i915_pm_rpm@drm-resources-equal.html
> 
>   * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
>     - shard-iclb:         [PASS][5] -> [DMESG-WARN][6] ([fdo#107724])
>    [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-iclb1/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
>    [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-iclb2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
> 
>   * igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled:
>     - shard-skl:          [PASS][7] -> [FAIL][8] ([fdo#103184] / [fdo#103232])
>    [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-skl2/igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled.html
>    [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-skl9/igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled.html
> 
>   * igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-cpu:
>     - shard-skl:          [PASS][9] -> [FAIL][10] ([fdo#103167] / [fdo#110379])
>    [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-skl2/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-cpu.html
>    [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-skl9/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-cpu.html
> 
>   * igt@kms_frontbuffer_tracking@fbc-tilingchange:
>     - shard-iclb:         [PASS][11] -> [FAIL][12] ([fdo#103167]) +4 similar issues
>    [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-tilingchange.html
>    [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-tilingchange.html
> 
>   * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt:
>     - shard-skl:          [PASS][13] -> [FAIL][14] ([fdo#108040])
>    [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-skl2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt.html
>    [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-skl9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt.html
> 
>   * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
>     - shard-glk:          [PASS][15] -> [SKIP][16] ([fdo#109271])
>    [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-glk9/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html
>    [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-glk4/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html
> 
>   * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
>     - shard-apl:          [PASS][17] -> [DMESG-WARN][18] ([fdo#108566]) +3 similar issues
>    [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
>    [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
> 
>   * igt@kms_plane@plane-position-hole-dpms-pipe-b-planes:
>     - shard-snb:          [PASS][19] -> [SKIP][20] ([fdo#109271]) +1 similar issue
>    [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-snb2/igt@kms_plane@plane-position-hole-dpms-pipe-b-planes.html
>    [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-snb2/igt@kms_plane@plane-position-hole-dpms-pipe-b-planes.html
> 
>   * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
>     - shard-skl:          [PASS][21] -> [FAIL][22] ([fdo#108145])
>    [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
>    [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
> 
>   * igt@kms_psr@psr2_primary_mmap_cpu:
>     - shard-iclb:         [PASS][23] -> [SKIP][24] ([fdo#109441]) +2 similar issues
>    [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
>    [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-iclb3/igt@kms_psr@psr2_primary_mmap_cpu.html
> 
>   
> #### Possible fixes ####
> 
>   * igt@gem_workarounds@suspend-resume:
>     - shard-apl:          [DMESG-WARN][25] ([fdo#108566]) -> [PASS][26] +6 similar issues
>    [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-apl7/igt@gem_workarounds@suspend-resume.html
>    [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-apl4/igt@gem_workarounds@suspend-resume.html
> 
>   * igt@i915_pm_rpm@basic-pci-d3-state:
>     - shard-iclb:         [INCOMPLETE][27] ([fdo#107713] / [fdo#108840] / [fdo#110581]) -> [PASS][28]
>    [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-iclb4/igt@i915_pm_rpm@basic-pci-d3-state.html
>    [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-iclb7/igt@i915_pm_rpm@basic-pci-d3-state.html
> 
>   * igt@i915_pm_rpm@i2c:
>     - shard-iclb:         [DMESG-WARN][29] ([fdo#109982]) -> [PASS][30]
>    [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-iclb2/igt@i915_pm_rpm@i2c.html
>    [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-iclb3/igt@i915_pm_rpm@i2c.html
> 
>   * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt:
>     - shard-iclb:         [FAIL][31] ([fdo#103167]) -> [PASS][32] +7 similar issues
>    [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
>    [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
> 
>   * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
>     - shard-glk:          [SKIP][33] ([fdo#109271]) -> [PASS][34]
>    [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-glk4/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
>    [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-glk9/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
> 
>   * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
>     - shard-skl:          [FAIL][35] ([fdo#108145] / [fdo#110403]) -> [PASS][36]
>    [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
>    [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
> 
>   * igt@kms_plane_scaling@pipe-a-scaler-with-pixel-format:
>     - shard-glk:          [SKIP][37] ([fdo#109271] / [fdo#109278]) -> [PASS][38] +1 similar issue
>    [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-glk3/igt@kms_plane_scaling@pipe-a-scaler-with-pixel-format.html
>    [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-glk9/igt@kms_plane_scaling@pipe-a-scaler-with-pixel-format.html
> 
>   * igt@kms_psr@psr2_cursor_mmap_cpu:
>     - shard-iclb:         [SKIP][39] ([fdo#109441]) -> [PASS][40]
>    [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-iclb1/igt@kms_psr@psr2_cursor_mmap_cpu.html
>    [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
> 
>   * igt@kms_setmode@basic:
>     - shard-apl:          [FAIL][41] ([fdo#99912]) -> [PASS][42]
>    [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-apl8/igt@kms_setmode@basic.html
>    [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-apl1/igt@kms_setmode@basic.html
>     - shard-kbl:          [FAIL][43] ([fdo#99912]) -> [PASS][44]
>    [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-kbl1/igt@kms_setmode@basic.html
>    [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-kbl6/igt@kms_setmode@basic.html
> 
>   * igt@kms_sysfs_edid_timing:
>     - shard-iclb:         [FAIL][45] ([fdo#100047]) -> [PASS][46]
>    [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-iclb3/igt@kms_sysfs_edid_timing.html
>    [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-iclb5/igt@kms_sysfs_edid_timing.html
> 
>   * igt@tools_test@tools_test:
>     - shard-iclb:         [SKIP][47] ([fdo#109352]) -> [PASS][48]
>    [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-iclb6/igt@tools_test@tools_test.html
>    [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-iclb1/igt@tools_test@tools_test.html
> 
>   
> #### Warnings ####
> 
>   * igt@kms_atomic_transition@3x-modeset-transitions:
>     - shard-snb:          [SKIP][49] ([fdo#109271] / [fdo#109278]) -> [SKIP][50] ([fdo#109271])
>    [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-snb2/igt@kms_atomic_transition@3x-modeset-transitions.html
>    [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-snb2/igt@kms_atomic_transition@3x-modeset-transitions.html
> 
>   
>   [fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
>   [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
>   [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
>   [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
>   [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
>   [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
>   [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
>   [fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
>   [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
>   [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
>   [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
>   [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
>   [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
>   [fdo#109352]: https://bugs.freedesktop.org/show_bug.cgi?id=109352
>   [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
>   [fdo#109982]: https://bugs.freedesktop.org/show_bug.cgi?id=109982
>   [fdo#110379]: https://bugs.freedesktop.org/show_bug.cgi?id=110379
>   [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
>   [fdo#110581]: https://bugs.freedesktop.org/show_bug.cgi?id=110581
>   [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
> 
> 
> Participating hosts (10 -> 10)
> ------------------------------
> 
>   No changes in participating hosts
> 
> 
> Build changes
> -------------
> 
>   * Linux: CI_DRM_6032 -> Patchwork_12955
> 
>   CI_DRM_6032: 6ad93073ac75c314e859cfe1020b569d0c63ccf5 @ git://anongit.freedesktop.org/gfx-ci/linux
>   IGT_4972: f052e49a43cc9704ea5f240df15dd9d3dfed68ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>   Patchwork_12955: ba990253d5d8234db983bd54d29ed627c9a613c8 @ git://anongit.freedesktop.org/gfx-ci/linux
>   piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/
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Re: [PATCH 03/10] drm/i915: Add support for asynchronous display power disabling

[Chris Wilson]

Quoting Imre Deak (2019-05-03 00:26:41)
> By disabling a power domain asynchronously we can restrict holding a
> reference on that power domain to the actual code sequence that
> requires the power to be on for the HW access it's doing, by also
> avoiding unneeded on-off-on togglings of the power domain (since the
> disabling happens with a delay).

That applies to no-delay. Are we not starting from a state where the
code acquires the powerwell for its immediate use, or it takes and holds
it for protracted durations even when the powerwell is not being used?

> One benefit is potential power saving if the delay is chosen properly.

Which is suggesting that some delay is better power saving than
no-delay? It's believable that powering on cost mores more energy than
normal. But do please fill in a few details on how the delay should be
chosen.

> In the case of the AUX power domain holding the reference on the domain
> for the minimal amount of time at defined spots is also a requirement:

Do you mean that there is a minimum duration for which the power well
must be asserted once acquired before being released?

> on ICL we need a stricter control of when either kind of AUX power
> domain (TBT-alt or DP-alt) can be enabled and the locking we need for
> that becomes problematic (due to dependencies on other locks) if we
> allow the reference to be held for arbitrarily long periods/places in
> the code.
> 
> I chose the disabling delay to be 100msec for now to avoid the unneeded
> toggling (and so not to introduce dmesg spamming) in the DP MST sideband
> signaling code. We could optimize this delay later.

Or removing the spam. Are we at a point where the error detection is
good enough to pin-point the lack of a particular powerwell wakeref?
-Chris
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Re: ✗ Fi.CI.IGT: failure for drm/i915: Add support for asynchronous display power disabling

[Chris Wilson]

Quoting Imre Deak (2019-05-03 11:07:55)
> On Fri, May 03, 2019 at 07:50:26AM +0000, Patchwork wrote:
> > == Series Details ==
> > 
> > Series: drm/i915: Add support for asynchronous display power disabling
> > URL   : https://patchwork.freedesktop.org/series/60242/
> > State : failure
> > 
> > == Summary ==
> > 
> > CI Bug Log - changes from CI_DRM_6032_full -> Patchwork_12955_full
> > ====================================================
> > 
> > Summary
> > -------
> > 
> >   **FAILURE**
> > 
> >   Serious unknown changes coming with Patchwork_12955_full absolutely need to be
> >   verified manually.
> >   
> >   If you think the reported changes have nothing to do with the changes
> >   introduced in Patchwork_12955_full, please notify your bug team to allow them
> >   to document this new failure mode, which will reduce false positives in CI.
> > 
> >   
> > 
> > Possible new issues
> > -------------------
> > 
> >   Here are the unknown changes that may have been introduced in Patchwork_12955_full:
> > 
> > ### IGT changes ###
> > 
> > #### Possible regressions ####
> > 
> >   * igt@gem_persistent_relocs@forked-interruptible-thrashing:
> >     - shard-glk:          [PASS][1] -> [TIMEOUT][2]
> >    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-glk6/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
> >    [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-glk7/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
> 
> Looks like an unrelated issue: on this GLK there are two HDMI displays
> connected, so the change shouldn't make any diffence on it. The change
> only affects the DP detect and hotplug paths, where we'll do now an
> async power domain put.

There's no history of glk locking up there, 

> The machine is still up when the problem happens, the test seems to get
> stuck and aborted by the test runner (after ~6mins according to [1]).
> 
> [43/82] (762s left) gem_persistent_relocs (forked-interruptible-thrashing)
> Starting subtest: forked-interruptible-thrashing
> Timeout. Killing the current test with SIGQUIT.
> Timeout. Killing the current test with SIGKILL.

and yet it locked up sufficiently to not respond to a signal, suggesting
an oops (the test takes 3s normally on glk).
-Chris
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Re: [PATCH 03/10] drm/i915: Add support for asynchronous display power disabling

[Imre Deak]

On Fri, May 03, 2019 at 01:16:04PM +0100, Chris Wilson wrote:
> Quoting Imre Deak (2019-05-03 00:26:41)
> > By disabling a power domain asynchronously we can restrict holding a
> > reference on that power domain to the actual code sequence that
> > requires the power to be on for the HW access it's doing, by also
> > avoiding unneeded on-off-on togglings of the power domain (since the
> > disabling happens with a delay).
> 
> That applies to no-delay. Are we not starting from a state where the
> code acquires the powerwell for its immediate use, or it takes and holds
> it for protracted durations even when the powerwell is not being used?

The latter: we hold it for the entire duration of the detect and hotplug
cycles, whereas we would only need it for the actual AUX transfers. By
the end of the patchset we only hold it for the required duration, that
is the AUX transfer, but to do that we would also want - imo - to avoid
the power well on/off ping-pong due to back-to-back AUX transfers.

> > One benefit is potential power saving if the delay is chosen properly.
> 
> Which is suggesting that some delay is better power saving than
> no-delay? It's believable that powering on cost mores more energy than
> normal. But do please fill in a few details on how the delay should be
> chosen.

It's just my assumption that an on-off-on sequence costs more then just
leaving the power well(s) on if the duration is short between the two on
events, I haven't measured this.

In the extreme case we could reduce the delay to 0, but still keep the
disabling asynchronous, which would mean not blocking on the disabling.
I measured the disabling time (with wait_for_us) to be ~1ms in average
on VLV with the worst case being 4ms.

> > In the case of the AUX power domain holding the reference on the domain
> > for the minimal amount of time at defined spots is also a requirement:
> 
> Do you mean that there is a minimum duration for which the power well
> must be asserted once acquired before being released?

I meant that we would need to keep the sequence where we hold the
reference short and a well defined place, like what we would have by
just holding the reference for the actual AUX transfer (achieved by the
end of the patchset). Anything else would make the locking we need for
ICL TypeC ports around this sequence rather problematic, adding for
instance unnecessary lockdep dependencies, which I would really like to
avoid.

> > on ICL we need a stricter control of when either kind of AUX power
> > domain (TBT-alt or DP-alt) can be enabled and the locking we need for
> > that becomes problematic (due to dependencies on other locks) if we
> > allow the reference to be held for arbitrarily long periods/places in
> > the code.
> > 
> > I chose the disabling delay to be 100msec for now to avoid the unneeded
> > toggling (and so not to introduce dmesg spamming) in the DP MST sideband
> > signaling code. We could optimize this delay later.
> 
> Or removing the spam. Are we at a point where the error detection is
> good enough to pin-point the lack of a particular powerwell wakeref?

We don't have a per-powerwell list of registers that we could check
against if that's what you mean. So we only detect if no wakeref is held
(by this or another thread) or an actual unclaimed access if the power
well is really off.

> -Chris
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Re: ✗ Fi.CI.IGT: failure for drm/i915: Add support for asynchronous display power disabling

[Imre Deak]

On Fri, May 03, 2019 at 01:37:53PM +0100, Chris Wilson wrote:
> Quoting Imre Deak (2019-05-03 11:07:55)
> > On Fri, May 03, 2019 at 07:50:26AM +0000, Patchwork wrote:
> > > == Series Details ==
> > > 
> > > Series: drm/i915: Add support for asynchronous display power disabling
> > > URL   : https://patchwork.freedesktop.org/series/60242/
> > > State : failure
> > > 
> > > == Summary ==
> > > 
> > > CI Bug Log - changes from CI_DRM_6032_full -> Patchwork_12955_full
> > > ====================================================
> > > 
> > > Summary
> > > -------
> > > 
> > >   **FAILURE**
> > > 
> > >   Serious unknown changes coming with Patchwork_12955_full absolutely need to be
> > >   verified manually.
> > >   
> > >   If you think the reported changes have nothing to do with the changes
> > >   introduced in Patchwork_12955_full, please notify your bug team to allow them
> > >   to document this new failure mode, which will reduce false positives in CI.
> > > 
> > >   
> > > 
> > > Possible new issues
> > > -------------------
> > > 
> > >   Here are the unknown changes that may have been introduced in Patchwork_12955_full:
> > > 
> > > ### IGT changes ###
> > > 
> > > #### Possible regressions ####
> > > 
> > >   * igt@gem_persistent_relocs@forked-interruptible-thrashing:
> > >     - shard-glk:          [PASS][1] -> [TIMEOUT][2]
> > >    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-glk6/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
> > >    [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-glk7/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
> > 
> > Looks like an unrelated issue: on this GLK there are two HDMI displays
> > connected, so the change shouldn't make any diffence on it. The change
> > only affects the DP detect and hotplug paths, where we'll do now an
> > async power domain put.
> 
> There's no history of glk locking up there, 
> 
> > The machine is still up when the problem happens, the test seems to get
> > stuck and aborted by the test runner (after ~6mins according to [1]).
> > 
> > [43/82] (762s left) gem_persistent_relocs (forked-interruptible-thrashing)
> > Starting subtest: forked-interruptible-thrashing
> > Timeout. Killing the current test with SIGQUIT.
> > Timeout. Killing the current test with SIGKILL.
> 
> and yet it locked up sufficiently to not respond to a signal, suggesting
> an oops (the test takes 3s normally on glk).

No pstore logs either. I also noticed that the run [1] above resulted in
an incomplete, if that's indicative of anything. The same goes for the
previous Patchwork_12954 run.

> -Chris
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Re: ✗ Fi.CI.IGT: failure for drm/i915: Add support for asynchronous display power disabling

[Imre Deak]

On Fri, May 03, 2019 at 04:52:58PM +0300, Imre Deak wrote:
> > > > [...]
> > > >   * igt@gem_persistent_relocs@forked-interruptible-thrashing:
> > > >     - shard-glk:          [PASS][1] -> [TIMEOUT][2]
> > > >    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-glk6/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
> > > >    [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-glk7/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
> > > 
> > > Looks like an unrelated issue: on this GLK there are two HDMI displays
> > > connected, so the change shouldn't make any diffence on it. The change
> > > only affects the DP detect and hotplug paths, where we'll do now an
> > > async power domain put.
> > 
> > There's no history of glk locking up there, 
> > 
> > > The machine is still up when the problem happens, the test seems to get
> > > stuck and aborted by the test runner (after ~6mins according to [1]).
> > > 
> > > [43/82] (762s left) gem_persistent_relocs (forked-interruptible-thrashing)
> > > Starting subtest: forked-interruptible-thrashing
> > > Timeout. Killing the current test with SIGQUIT.
> > > Timeout. Killing the current test with SIGKILL.
> > 
> > and yet it locked up sufficiently to not respond to a signal, suggesting
> > an oops (the test takes 3s normally on glk).
> 
> No pstore logs either. I also noticed that the run [1] above resulted in
> an incomplete, if that's indicative of anything. The same goes for the
> previous Patchwork_12954 run.

Ah, there is actually a pstore log it's just not linked the html page
for some reason, Tomi?

Here it is:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-glk7/pstore25-1556858613_Panic_1.log

--Imre
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Re: ✗ Fi.CI.IGT: failure for drm/i915: Add support for asynchronous display power disabling

[Imre Deak]

On Fri, May 03, 2019 at 04:52:58PM +0300, Imre Deak wrote:
> > > > [...]
> > > >   * igt@gem_persistent_relocs@forked-interruptible-thrashing:
> > > >     - shard-glk:          [PASS][1] -> [TIMEOUT][2]
> > > >    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6032/shard-glk6/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
> > > >    [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12955/shard-glk7/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
> > > 
> > > Looks like an unrelated issue: on this GLK there are two HDMI displays
> > > connected, so the change shouldn't make any diffence on it. The change
> > > only affects the DP detect and hotplug paths, where we'll do now an
> > > async power domain put.
> > 
> > There's no history of glk locking up there, 
> > 
> > > The machine is still up when the problem happens, the test seems to get
> > > stuck and aborted by the test runner (after ~6mins according to [1]).
> > > 
> > > [43/82] (762s left) gem_persistent_relocs (forked-interruptible-thrashing)
> > > Starting subtest: forked-interruptible-thrashing
> > > Timeout. Killing the current test with SIGQUIT.
> > > Timeout. Killing the current test with SIGKILL.
> > 
> > and yet it locked up sufficiently to not respond to a signal, suggesting
> > an oops (the test takes 3s normally on glk).
> 
> No pstore logs either. I also noticed that the run [1] above resulted in
> an incomplete, if that's indicative of anything. The same goes for the
> previous Patchwork_12954 run.

For reference what we discussed on IRC:

There is also a previous Trybot run on SKL that hang in the same test in
a similar way:
https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_4242/shard-skl9/igt%40gem_persistent_relocs%40forked-interruptible-thrashing.html

We're missing stack dumps to better isolate the problem, but based on
the above it's unlikely to be caused by the changes in this patchset.
Chris suggested

cat /proc/*/stack on timeout and ptracing the child from the IGT runner,
adding Petri for that.

I'm trying to repro the problem on SKL/GLK with and without this
patchset, so far I didn't hit the issue.

I opened the following bug to capture the findings:
https://bugs.freedesktop.org/show_bug.cgi?id=110618

and will check out Chris' patchset that may be related/fix the problem:
https://patchwork.freedesktop.org/series/60257/

--Imre
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[PATCH v2 03/10] drm/i915: Add support for asynchronous display power disabling

[Imre Deak]

By disabling a power domain asynchronously we can restrict holding a
reference on that power domain to the actual code sequence that
requires the power to be on for the HW access it's doing, by also
avoiding unneeded on-off-on togglings of the power domain (since the
disabling happens with a delay).

One benefit is potential power saving due to the following two reasons:
1. The fact that we will now be holding the reference only for the
   necessary duration by the end of the patchset. While simply not
   delaying the disabling has the same benefit, it has the problem that
   frequent on-off-on power switching has its own power cost (see the 2.
   point below) and the debug trace for power well on/off events will
   cause a lot of dmesg spam (see details about this further below).
2. Avoiding the power cost of freuqent on-off-on power switching. This
   requires us to find the optimal disabling delay based on the measured
   power cost of on->off and off->on switching of each power well vs.
   the power of keeping the given power well on.

   In this patchset I'm not providing this optimal delay for two
   reasons:
   a) I don't have the means yet to perform the measurement (with high
      enough signal-to-noise ratio, or with the help of an energy
      counter that takes switching into account). I'm currently looking
      for a way to measure this.

   b) Before reducing the disabling delay we need an alternative way for
      debug tracing powerwell on/off events. Simply avoiding/throttling
      the debug messages is not a solution, see further below.

   Note that even in the case where we can't measure any considerable
   power cost of frequent on-off switching of powerwells, it still would
   make sense to do the disabling asynchronously (with 0 delay) to avoid
   blocking on the disabling. On VLV I measured this disabling time
   overhead to be 1ms on average with a worst case of 4ms.

In the case of the AUX power domains on ICL we would also need to keep
the sequence where we hold the power reference short, the way it would
be by the end of this patchset where we hold it only for the actual AUX
transfer. Anything else would make the locking we need for ICL TypeC
ports (whenever we hold a reference on any AUX power domain) rather
problematic, adding for instance unnecessary lockdep dependencies to
the required TypeC port lock.

I chose the disabling delay to be 100msec for now to avoid the unneeded
toggling (and so not to introduce dmesg spamming) in the DP MST sideband
signaling code. We could optimize this delay later, once we have the
means to measure the switching power cost (see above).

Note that simply removing/throttling the debug tracing for power well
on/off events is not a solution. We need to know the exact spots of
these events and cannot rely only on incorrect register accesses caught
(due to not holding a wakeref at the time of access). Incorrect
powerwell enabling/disabling could lead to other problems, for instance
we need to keep certain powerwells enabled for the duration of modesets
and AUX transfers.

v2:
- Clarify the commit log parts about power cost measurement and the
  problem of simply removing/throttling debug tracing. (Chris)

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h         |   5 +
 drivers/gpu/drm/i915/intel_runtime_pm.c | 316 +++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_runtime_pm.h |   4 +
 3 files changed, 315 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a162d57f0b58..8d18d124f496 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -835,6 +835,11 @@ struct i915_power_domains {
 
 	struct mutex lock;
 	int domain_use_count[POWER_DOMAIN_NUM];
+
+	struct delayed_work async_put_work;
+	intel_wakeref_t async_put_wakeref;
+	u64 async_put_domains[2];
+
 	struct i915_power_well *power_wells;
 };
 
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index b4b17cdc6f26..4079b1378f2d 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1884,6 +1884,130 @@ static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
 	chv_set_pipe_power_well(dev_priv, power_well, false);
 }
 
+static intel_wakeref_t
+intel_runtime_pm_get_raw(struct drm_i915_private *i915);
+static void
+intel_runtime_pm_put_raw(struct drm_i915_private *i915, intel_wakeref_t wref);
+
+static u64 __async_put_domains_mask(struct i915_power_domains *power_domains)
+{
+	return power_domains->async_put_domains[0] |
+	       power_domains->async_put_domains[1];
+}
+
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
+
+static bool
+assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains)
+{
+	return !WARN_ON(power_domains->async_put_domains[0] &
+			power_domains->async_put_domains[1]);
+}
+
+static bool
+__async_put_domains_state_ok(struct i915_power_domains *power_domains)
+{
+	enum intel_display_power_domain domain;
+	bool err = false;
+
+	err |= !assert_async_put_domain_masks_disjoint(power_domains);
+	err |= WARN_ON(!!power_domains->async_put_wakeref !=
+		       !!__async_put_domains_mask(power_domains));
+
+	for_each_power_domain(domain, __async_put_domains_mask(power_domains))
+		err |= WARN_ON(power_domains->domain_use_count[domain] != 1);
+
+	return !err;
+}
+
+static void print_power_domains(struct i915_power_domains *power_domains,
+				const char *prefix, u64 mask)
+{
+	enum intel_display_power_domain domain;
+
+	DRM_DEBUG_DRIVER("%s (%lu):\n", prefix, hweight64(mask));
+	for_each_power_domain(domain, mask)
+		DRM_DEBUG_DRIVER("%s use_count %d\n",
+				 intel_display_power_domain_str(domain),
+				 power_domains->domain_use_count[domain]);
+}
+
+static void
+print_async_put_domains_state(struct i915_power_domains *power_domains)
+{
+	DRM_DEBUG_DRIVER("async_put_wakeref %u\n",
+			 power_domains->async_put_wakeref);
+
+	print_power_domains(power_domains, "async_put_domains[0]",
+			    power_domains->async_put_domains[0]);
+	print_power_domains(power_domains, "async_put_domains[1]",
+			    power_domains->async_put_domains[1]);
+}
+
+static void
+verify_async_put_domains_state(struct i915_power_domains *power_domains)
+{
+	if (!__async_put_domains_state_ok(power_domains))
+		print_async_put_domains_state(power_domains);
+}
+
+#else
+
+static void
+assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains)
+{
+}
+
+static void
+verify_async_put_domains_state(struct i915_power_domains *power_domains)
+{
+}
+
+#endif /* CONFIG_DRM_I915_DEBUG_RUNTIME_PM */
+
+static u64 async_put_domains_mask(struct i915_power_domains *power_domains)
+{
+	assert_async_put_domain_masks_disjoint(power_domains);
+
+	return __async_put_domains_mask(power_domains);
+}
+
+static void
+async_put_domains_clear_domain(struct i915_power_domains *power_domains,
+			       enum intel_display_power_domain domain)
+{
+	assert_async_put_domain_masks_disjoint(power_domains);
+
+	power_domains->async_put_domains[0] &= ~BIT_ULL(domain);
+	power_domains->async_put_domains[1] &= ~BIT_ULL(domain);
+}
+
+static bool
+intel_display_power_grab_async_put_ref(struct drm_i915_private *dev_priv,
+				       enum intel_display_power_domain domain)
+{
+	struct i915_power_domains *power_domains = &dev_priv->power_domains;
+	bool ret = false;
+
+	if (!(async_put_domains_mask(power_domains) & BIT_ULL(domain)))
+		goto out_verify;
+
+	async_put_domains_clear_domain(power_domains, domain);
+
+	ret = true;
+
+	if (async_put_domains_mask(power_domains))
+		goto out_verify;
+
+	cancel_delayed_work(&power_domains->async_put_work);
+	intel_runtime_pm_put_raw(dev_priv,
+				 fetch_and_zero(&power_domains->async_put_wakeref));
+out_verify:
+	verify_async_put_domains_state(power_domains);
+
+	return ret;
+}
+
 static void
 __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
 				 enum intel_display_power_domain domain)
@@ -1891,6 +2015,9 @@ __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
 	struct i915_power_well *power_well;
 
+	if (intel_display_power_grab_async_put_ref(dev_priv, domain))
+		return;
+
 	for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain))
 		intel_power_well_get(dev_priv, power_well);
 
@@ -1916,9 +2043,7 @@ intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
 	intel_wakeref_t wakeref = intel_runtime_pm_get(dev_priv);
 
 	mutex_lock(&power_domains->lock);
-
 	__intel_display_power_get_domain(dev_priv, domain);
-
 	mutex_unlock(&power_domains->lock);
 
 	return wakeref;
@@ -1967,24 +2092,36 @@ intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
 	return wakeref;
 }
 
-static void __intel_display_power_put(struct drm_i915_private *dev_priv,
-				      enum intel_display_power_domain domain)
+static void
+__intel_display_power_put_domain(struct drm_i915_private *dev_priv,
+				 enum intel_display_power_domain domain)
 {
 	struct i915_power_domains *power_domains;
 	struct i915_power_well *power_well;
+	const char *name = intel_display_power_domain_str(domain);
 
 	power_domains = &dev_priv->power_domains;
 
-	mutex_lock(&power_domains->lock);
-
 	WARN(!power_domains->domain_use_count[domain],
 	     "Use count on domain %s is already zero\n",
-	     intel_display_power_domain_str(domain));
+	     name);
+	WARN(async_put_domains_mask(power_domains) & BIT_ULL(domain),
+	     "Async disabling of domain %s is pending\n",
+	     name);
+
 	power_domains->domain_use_count[domain]--;
 
 	for_each_power_domain_well_reverse(dev_priv, power_well, BIT_ULL(domain))
 		intel_power_well_put(dev_priv, power_well);
+}
 
+static void __intel_display_power_put(struct drm_i915_private *dev_priv,
+				      enum intel_display_power_domain domain)
+{
+	struct i915_power_domains *power_domains = &dev_priv->power_domains;
+
+	mutex_lock(&power_domains->lock);
+	__intel_display_power_put_domain(dev_priv, domain);
 	mutex_unlock(&power_domains->lock);
 }
 
@@ -2004,6 +2141,159 @@ void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
 	intel_runtime_pm_put_unchecked(dev_priv);
 }
 
+static void
+queue_async_put_domains_work(struct i915_power_domains *power_domains,
+			     intel_wakeref_t wakeref)
+{
+	WARN_ON(power_domains->async_put_wakeref);
+	power_domains->async_put_wakeref = wakeref;
+	WARN_ON(!queue_delayed_work(system_unbound_wq,
+				    &power_domains->async_put_work,
+				    msecs_to_jiffies(100)));
+}
+
+static void
+release_async_put_domains(struct i915_power_domains *power_domains, u64 mask)
+{
+	struct drm_i915_private *dev_priv =
+		container_of(power_domains, struct drm_i915_private,
+			     power_domains);
+	enum intel_display_power_domain domain;
+	intel_wakeref_t wakeref;
+
+	/*
+	 * The caller must hold already raw wakeref, upgrade that to a proper
+	 * wakeref to make the state checker happy about the HW access during
+	 * power well disabling.
+	 */
+	assert_raw_rpm_wakelock_held(dev_priv);
+	wakeref = intel_runtime_pm_get(dev_priv);
+
+	for_each_power_domain(domain, mask) {
+		/* Clear before put, so put's sanity check is happy. */
+		async_put_domains_clear_domain(power_domains, domain);
+		__intel_display_power_put_domain(dev_priv, domain);
+	}
+
+	intel_runtime_pm_put(dev_priv, wakeref);
+}
+
+static void
+intel_display_power_put_async_work(struct work_struct *work)
+{
+	struct drm_i915_private *dev_priv =
+		container_of(work, struct drm_i915_private,
+			     power_domains.async_put_work.work);
+	struct i915_power_domains *power_domains = &dev_priv->power_domains;
+	intel_wakeref_t new_work_wakeref = intel_runtime_pm_get_raw(dev_priv);
+	intel_wakeref_t old_work_wakeref = 0;
+
+	mutex_lock(&power_domains->lock);
+
+	/*
+	 * Bail out if all the domain refs pending to be released were grabbed
+	 * by subsequent gets or a flush_work.
+	 */
+	old_work_wakeref = fetch_and_zero(&power_domains->async_put_wakeref);
+	if (!old_work_wakeref)
+		goto out_verify;
+
+	release_async_put_domains(power_domains,
+				  power_domains->async_put_domains[0]);
+
+	/* Requeue the work if more domains were async put meanwhile. */
+	if (power_domains->async_put_domains[1]) {
+		power_domains->async_put_domains[0] =
+			fetch_and_zero(&power_domains->async_put_domains[1]);
+		queue_async_put_domains_work(power_domains,
+					     fetch_and_zero(&new_work_wakeref));
+	}
+
+out_verify:
+	verify_async_put_domains_state(power_domains);
+
+	mutex_unlock(&power_domains->lock);
+
+	if (old_work_wakeref)
+		intel_runtime_pm_put_raw(dev_priv, old_work_wakeref);
+	if (new_work_wakeref)
+		intel_runtime_pm_put_raw(dev_priv, new_work_wakeref);
+}
+
+void intel_display_power_put_async(struct drm_i915_private *dev_priv,
+				   enum intel_display_power_domain domain,
+				   intel_wakeref_t wakeref)
+{
+	struct i915_power_domains *power_domains = &dev_priv->power_domains;
+	intel_wakeref_t work_wakeref = intel_runtime_pm_get_raw(dev_priv);
+
+	mutex_lock(&power_domains->lock);
+
+	if (power_domains->domain_use_count[domain] > 1) {
+		__intel_display_power_put_domain(dev_priv, domain);
+
+		goto out_verify;
+	}
+
+	WARN_ON(power_domains->domain_use_count[domain] != 1);
+
+	/* Let a pending work requeue itself or queue a new one. */
+	if (power_domains->async_put_wakeref) {
+		power_domains->async_put_domains[1] |= BIT_ULL(domain);
+	} else {
+		power_domains->async_put_domains[0] |= BIT_ULL(domain);
+		queue_async_put_domains_work(power_domains,
+					     fetch_and_zero(&work_wakeref));
+	}
+
+out_verify:
+	verify_async_put_domains_state(power_domains);
+
+	mutex_unlock(&power_domains->lock);
+
+	if (work_wakeref)
+		intel_runtime_pm_put_raw(dev_priv, work_wakeref);
+
+	intel_runtime_pm_put(dev_priv, wakeref);
+}
+
+void intel_display_power_flush_work(struct drm_i915_private *dev_priv)
+{
+	struct i915_power_domains *power_domains = &dev_priv->power_domains;
+	intel_wakeref_t work_wakeref;
+
+	mutex_lock(&power_domains->lock);
+
+	work_wakeref = fetch_and_zero(&power_domains->async_put_wakeref);
+	if (!work_wakeref)
+		goto out_verify;
+
+	release_async_put_domains(power_domains,
+				  async_put_domains_mask(power_domains));
+	cancel_delayed_work(&power_domains->async_put_work);
+
+out_verify:
+	verify_async_put_domains_state(power_domains);
+
+	mutex_unlock(&power_domains->lock);
+
+	if (work_wakeref)
+		intel_runtime_pm_put_raw(dev_priv, work_wakeref);
+}
+
+static void
+intel_display_power_flush_work_sync(struct drm_i915_private *dev_priv)
+{
+	struct i915_power_domains *power_domains = &dev_priv->power_domains;
+
+	intel_display_power_flush_work(dev_priv);
+	cancel_delayed_work_sync(&power_domains->async_put_work);
+
+	verify_async_put_domains_state(power_domains);
+
+	WARN_ON(power_domains->async_put_wakeref);
+}
+
 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
 void intel_display_power_put(struct drm_i915_private *dev_priv,
 			     enum intel_display_power_domain domain,
@@ -3492,6 +3782,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
 
 	mutex_init(&power_domains->lock);
 
+	INIT_DELAYED_WORK(&power_domains->async_put_work,
+			  intel_display_power_put_async_work);
+
 	/*
 	 * The enabling order will be from lower to higher indexed wells,
 	 * the disabling order is reversed.
@@ -4169,6 +4462,8 @@ void intel_power_domains_fini_hw(struct drm_i915_private *i915)
 	if (!i915_modparams.disable_power_well)
 		intel_display_power_put_unchecked(i915, POWER_DOMAIN_INIT);
 
+	intel_display_power_flush_work_sync(i915);
+
 	intel_power_domains_verify_state(i915);
 
 	/* Keep the power well enabled, but cancel its rpm wakeref. */
@@ -4244,6 +4539,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
 	if (!(i915->csr.allowed_dc_mask & DC_STATE_EN_DC9) &&
 	    suspend_mode == I915_DRM_SUSPEND_IDLE &&
 	    i915->csr.dmc_payload) {
+		intel_display_power_flush_work(i915);
 		intel_power_domains_verify_state(i915);
 		return;
 	}
@@ -4255,6 +4551,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
 	if (!i915_modparams.disable_power_well)
 		intel_display_power_put_unchecked(i915, POWER_DOMAIN_INIT);
 
+	intel_display_power_flush_work(i915);
 	intel_power_domains_verify_state(i915);
 
 	if (INTEL_GEN(i915) >= 11)
@@ -4333,6 +4630,8 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915)
 
 	mutex_lock(&power_domains->lock);
 
+	verify_async_put_domains_state(power_domains);
+
 	dump_domain_info = false;
 	for_each_power_well(i915, power_well) {
 		enum intel_display_power_domain domain;
@@ -4401,7 +4700,6 @@ static void __intel_runtime_pm_get(struct drm_i915_private *i915)
 	WARN_ONCE(ret < 0, "pm_runtime_get_sync() failed: %d\n", ret);
 }
 
-__attribute__((__used__))
 static intel_wakeref_t intel_runtime_pm_get_raw(struct drm_i915_private *i915)
 {
 	__intel_runtime_pm_get(i915);
@@ -4509,7 +4807,6 @@ void intel_runtime_pm_put_unchecked(struct drm_i915_private *i915)
 }
 
 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
-__attribute__((__used__))
 static void intel_runtime_pm_put_raw(struct drm_i915_private *i915,
 				     intel_wakeref_t wref)
 {
@@ -4523,7 +4820,6 @@ void intel_runtime_pm_put(struct drm_i915_private *i915, intel_wakeref_t wref)
 	intel_runtime_pm_put_unchecked(i915);
 }
 #else
-__attribute__((__used__))
 static void intel_runtime_pm_put_raw(struct drm_i915_private *i915,
 				     intel_wakeref_t wref)
 {
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.h b/drivers/gpu/drm/i915/intel_runtime_pm.h
index 69227756de3e..cabf6f900273 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.h
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.h
@@ -57,6 +57,10 @@ intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
 				   enum intel_display_power_domain domain);
 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
 				       enum intel_display_power_domain domain);
+void intel_display_power_put_async(struct drm_i915_private *dev_priv,
+				   enum intel_display_power_domain domain,
+				   intel_wakeref_t wakeref);
+void intel_display_power_flush_work(struct drm_i915_private *dev_priv);
 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
 void intel_display_power_put(struct drm_i915_private *dev_priv,
 			     enum intel_display_power_domain domain,
-- 
2.17.1

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✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add support for asynchronous display power disabling (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Add support for asynchronous display power disabling (rev2)
URL   : https://patchwork.freedesktop.org/series/60242/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
5d071067866a drm/i915: Add support for tracking wakerefs w/o power-on guarantee
d71e181e7a7e drm/i915: Verify power domains state during suspend in all cases
f1694f9c835b drm/i915: Add support for asynchronous display power disabling
defe1cba7dc7 drm/i915: Disable power asynchronously during DP AUX transfers
4ca80e845053 drm/i915: WARN for eDP encoders in intel_dp_detect_dpcd()
ceea4b6eb65d drm/i915: Remove the unneeded AUX power ref from intel_dp_detect()
599e8ef0ba82 drm/i915: Remove the unneeded AUX power ref from intel_dp_hpd_pulse()
-:12: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 1c767b339b39 ("drm/i915: take display port power domain in DP HPD handler")'
#12: 
commit 1c767b339b3938b19076ffdc9d70aa1e4235a45b

-:21: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 7d23e3c37bb3 ("drm/i915: Cleaning up intel_dp_hpd_pulse")'
#21: 
commit 7d23e3c37bb3fc6952dc84007ee60cb533fd2d5c

total: 2 errors, 0 warnings, 0 checks, 68 lines checked
0430dd3adbd0 drm/i915: Replace use of PLLS power domain with DISPLAY_CORE domain
cb2cb878cdd7 drm/i915: Avoid taking the PPS lock for non-eDP/VLV/CHV
e3d148cbe414 drm/i915: Assert that TypeC ports are not used for eDP

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✓ Fi.CI.BAT: success for drm/i915: Add support for asynchronous display power disabling (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Add support for asynchronous display power disabling (rev2)
URL   : https://patchwork.freedesktop.org/series/60242/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6049 -> Patchwork_12969
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_12969:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_basic@bad-close:
    - {fi-cml-u2}:        [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/fi-cml-u2/igt@gem_basic@bad-close.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/fi-cml-u2/igt@gem_basic@bad-close.html

  
Known issues
------------

  Here are the changes found in Patchwork_12969 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-skl-6600u:       [PASS][3] -> [FAIL][4] ([fdo#107707])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/fi-skl-6600u/igt@i915_pm_rpm@basic-pci-d3-state.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/fi-skl-6600u/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_selftest@live_hangcheck:
    - fi-skl-iommu:       [PASS][5] -> [INCOMPLETE][6] ([fdo#108602] / [fdo#108744])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/fi-skl-iommu/igt@i915_selftest@live_hangcheck.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-kbl-7567u:       [PASS][7] -> [WARN][8] ([fdo#109380])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/fi-kbl-7567u/igt@kms_chamelium@common-hpd-after-suspend.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/fi-kbl-7567u/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-c:
    - fi-kbl-7567u:       [PASS][9] -> [SKIP][10] ([fdo#109271]) +23 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/fi-kbl-7567u/igt@kms_pipe_crc_basic@read-crc-pipe-c.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/fi-kbl-7567u/igt@kms_pipe_crc_basic@read-crc-pipe-c.html

  
#### Possible fixes ####

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      [FAIL][11] ([fdo#108511]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live_contexts:
    - fi-skl-gvtdvm:      [DMESG-FAIL][13] ([fdo#110235]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html

  * igt@i915_selftest@live_evict:
    - fi-bsw-kefka:       [DMESG-WARN][15] ([fdo#107709]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/fi-bsw-kefka/igt@i915_selftest@live_evict.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/fi-bsw-kefka/igt@i915_selftest@live_evict.html

  * igt@i915_selftest@live_hangcheck:
    - fi-icl-y:           [INCOMPLETE][17] ([fdo#107713] / [fdo#108569] / [fdo#110581]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/fi-icl-y/igt@i915_selftest@live_hangcheck.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/fi-icl-y/igt@i915_selftest@live_hangcheck.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-blb-e6850:       [INCOMPLETE][19] ([fdo#107718] / [fdo#110581]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/fi-blb-e6850/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/fi-blb-e6850/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  
#### Warnings ####

  * igt@i915_selftest@live_guc:
    - fi-apl-guc:         [INCOMPLETE][21] ([fdo#103927] / [fdo#110581]) -> [INCOMPLETE][22] ([fdo#103927])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/fi-apl-guc/igt@i915_selftest@live_guc.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/fi-apl-guc/igt@i915_selftest@live_guc.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#107707]: https://bugs.freedesktop.org/show_bug.cgi?id=107707
  [fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
  [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380
  [fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235
  [fdo#110581]: https://bugs.freedesktop.org/show_bug.cgi?id=110581


Participating hosts (50 -> 45)
------------------------------

  Additional (2): fi-icl-u2 fi-pnv-d510 
  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_6049 -> Patchwork_12969

  CI_DRM_6049: 5e6e5018d74f5ae297db088c45cea19f939fb225 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4972: f052e49a43cc9704ea5f240df15dd9d3dfed68ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12969: e3d148cbe4140ded01d4f3310de4323ae2f25c64 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

e3d148cbe414 drm/i915: Assert that TypeC ports are not used for eDP
cb2cb878cdd7 drm/i915: Avoid taking the PPS lock for non-eDP/VLV/CHV
0430dd3adbd0 drm/i915: Replace use of PLLS power domain with DISPLAY_CORE domain
599e8ef0ba82 drm/i915: Remove the unneeded AUX power ref from intel_dp_hpd_pulse()
ceea4b6eb65d drm/i915: Remove the unneeded AUX power ref from intel_dp_detect()
4ca80e845053 drm/i915: WARN for eDP encoders in intel_dp_detect_dpcd()
defe1cba7dc7 drm/i915: Disable power asynchronously during DP AUX transfers
f1694f9c835b drm/i915: Add support for asynchronous display power disabling
d71e181e7a7e drm/i915: Verify power domains state during suspend in all cases
5d071067866a drm/i915: Add support for tracking wakerefs w/o power-on guarantee

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/
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Re: [PATCH 09/10] drm/i915: Avoid taking the PPS lock for non-eDP/VLV/CHV

[Ville Syrjälä]

On Fri, May 03, 2019 at 02:26:47AM +0300, Imre Deak wrote:
> On ICL we have to make sure that we enable the AUX power domain in a
> controlled way (corresponding to the port's actual TypeC mode). Since
> the PPS lock - which takes an AUX power ref - is only needed on
> eDP/VLV/CHV avoid taking it in other cases.
> 
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index f56cbda59fb3..1ee9b7ebd801 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -6263,6 +6263,10 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder)
>  
>  	intel_dp->reset_link_params = true;
>  
> +	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
> +	    !intel_dp_is_edp(intel_dp))
> +		return;

vlv/chv need this for all DP ports.

> +
>  	with_pps_lock(intel_dp, wakeref) {
>  		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  			intel_dp->active_pipe = vlv_active_pipe(intel_dp);
> -- 
> 2.17.1

-- 
Ville Syrjälä
Intel
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✓ Fi.CI.IGT: success for drm/i915: Add support for asynchronous display power disabling (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Add support for asynchronous display power disabling (rev2)
URL   : https://patchwork.freedesktop.org/series/60242/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6049_full -> Patchwork_12969_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_12969_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_eio@reset-stress:
    - shard-skl:          [PASS][1] -> [FAIL][2] ([fdo#105957])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/shard-skl5/igt@gem_eio@reset-stress.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/shard-skl10/igt@gem_eio@reset-stress.html

  * igt@gem_workarounds@suspend-resume:
    - shard-skl:          [PASS][3] -> [INCOMPLETE][4] ([fdo#104108] / [fdo#107773])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/shard-skl10/igt@gem_workarounds@suspend-resume.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/shard-skl2/igt@gem_workarounds@suspend-resume.html

  * igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
    - shard-skl:          [PASS][5] -> [INCOMPLETE][6] ([fdo#107807])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/shard-skl3/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/shard-skl3/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html

  * igt@kms_cursor_crc@cursor-128x128-suspend:
    - shard-skl:          [PASS][7] -> [INCOMPLETE][8] ([fdo#104108])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/shard-skl5/igt@kms_cursor_crc@cursor-128x128-suspend.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/shard-skl10/igt@kms_cursor_crc@cursor-128x128-suspend.html

  * igt@kms_cursor_legacy@pipe-c-forked-move:
    - shard-hsw:          [PASS][9] -> [INCOMPLETE][10] ([fdo#103540])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/shard-hsw8/igt@kms_cursor_legacy@pipe-c-forked-move.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/shard-hsw6/igt@kms_cursor_legacy@pipe-c-forked-move.html

  * igt@kms_frontbuffer_tracking@fbc-tilingchange:
    - shard-iclb:         [PASS][11] -> [FAIL][12] ([fdo#103167]) +4 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-tilingchange.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-tilingchange.html

  * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
    - shard-glk:          [PASS][13] -> [SKIP][14] ([fdo#109271])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/shard-glk9/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/shard-glk5/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html

  * igt@kms_plane_scaling@pipe-b-scaler-with-rotation:
    - shard-glk:          [PASS][15] -> [SKIP][16] ([fdo#109271] / [fdo#109278])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/shard-glk9/igt@kms_plane_scaling@pipe-b-scaler-with-rotation.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/shard-glk7/igt@kms_plane_scaling@pipe-b-scaler-with-rotation.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         [PASS][17] -> [SKIP][18] ([fdo#109642])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/shard-iclb1/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_cursor_mmap_gtt:
    - shard-iclb:         [PASS][19] -> [SKIP][20] ([fdo#109441])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_gtt.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/shard-iclb8/igt@kms_psr@psr2_cursor_mmap_gtt.html

  * igt@kms_setmode@basic:
    - shard-apl:          [PASS][21] -> [FAIL][22] ([fdo#99912])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/shard-apl4/igt@kms_setmode@basic.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/shard-apl7/igt@kms_setmode@basic.html
    - shard-kbl:          [PASS][23] -> [FAIL][24] ([fdo#99912])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/shard-kbl2/igt@kms_setmode@basic.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/shard-kbl4/igt@kms_setmode@basic.html

  * igt@kms_sysfs_edid_timing:
    - shard-iclb:         [PASS][25] -> [FAIL][26] ([fdo#100047])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/shard-iclb8/igt@kms_sysfs_edid_timing.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/shard-iclb3/igt@kms_sysfs_edid_timing.html

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
    - shard-apl:          [PASS][27] -> [DMESG-WARN][28] ([fdo#108566]) +8 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/shard-apl1/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/shard-apl5/igt@kms_vblank@pipe-c-ts-continuation-suspend.html

  
#### Possible fixes ####

  * igt@gem_softpin@noreloc-s3:
    - shard-kbl:          [DMESG-WARN][29] ([fdo#108566]) -> [PASS][30] +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/shard-kbl2/igt@gem_softpin@noreloc-s3.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/shard-kbl2/igt@gem_softpin@noreloc-s3.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-apl:          [DMESG-WARN][31] ([fdo#108566]) -> [PASS][32] +7 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/shard-apl4/igt@gem_workarounds@suspend-resume-context.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/shard-apl7/igt@gem_workarounds@suspend-resume-context.html

  * igt@i915_pm_rpm@i2c:
    - shard-iclb:         [FAIL][33] ([fdo#104097]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/shard-iclb6/igt@i915_pm_rpm@i2c.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/shard-iclb7/igt@i915_pm_rpm@i2c.html

  * igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled:
    - shard-skl:          [FAIL][35] ([fdo#103184] / [fdo#103232]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/shard-skl6/igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/shard-skl1/igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-skl:          [FAIL][37] ([fdo#105363]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/shard-skl8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-move:
    - shard-hsw:          [SKIP][39] ([fdo#109271]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/shard-hsw1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-move.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/shard-hsw5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
    - shard-iclb:         [FAIL][41] ([fdo#103167]) -> [PASS][42] +6 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html

  * igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
    - shard-glk:          [SKIP][43] ([fdo#109271]) -> [PASS][44] +1 similar issue
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/shard-glk8/igt@kms_plane@pixel-format-pipe-c-planes-source-clamping.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/shard-glk9/igt@kms_plane@pixel-format-pipe-c-planes-source-clamping.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [FAIL][45] ([fdo#108145]) -> [PASS][46] +1 similar issue
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_plane_scaling@pipe-a-scaler-with-rotation:
    - shard-glk:          [SKIP][47] ([fdo#109271] / [fdo#109278]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/shard-glk8/igt@kms_plane_scaling@pipe-a-scaler-with-rotation.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/shard-glk9/igt@kms_plane_scaling@pipe-a-scaler-with-rotation.html

  * igt@kms_psr@psr2_cursor_mmap_cpu:
    - shard-iclb:         [SKIP][49] ([fdo#109441]) -> [PASS][50] +1 similar issue
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/shard-iclb4/igt@kms_psr@psr2_cursor_mmap_cpu.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html

  
#### Warnings ####

  * igt@kms_flip@flip-vs-suspend:
    - shard-apl:          [DMESG-WARN][51] ([fdo#108566]) -> [FAIL][52] ([fdo#103375])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/shard-apl5/igt@kms_flip@flip-vs-suspend.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/shard-apl8/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt:
    - shard-skl:          [FAIL][53] ([fdo#108040]) -> [FAIL][54] ([fdo#103167])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6049/shard-skl6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/shard-skl1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt.html

  
  [fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#104097]: https://bugs.freedesktop.org/show_bug.cgi?id=104097
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105957]: https://bugs.freedesktop.org/show_bug.cgi?id=105957
  [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_6049 -> Patchwork_12969

  CI_DRM_6049: 5e6e5018d74f5ae297db088c45cea19f939fb225 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4972: f052e49a43cc9704ea5f240df15dd9d3dfed68ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12969: e3d148cbe4140ded01d4f3310de4323ae2f25c64 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12969/
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Re: [PATCH 09/10] drm/i915: Avoid taking the PPS lock for non-eDP/VLV/CHV

[Ville Syrjälä]

On Mon, May 06, 2019 at 03:35:52PM +0300, Ville Syrjälä wrote:
> On Fri, May 03, 2019 at 02:26:47AM +0300, Imre Deak wrote:
> > On ICL we have to make sure that we enable the AUX power domain in a
> > controlled way (corresponding to the port's actual TypeC mode). Since
> > the PPS lock - which takes an AUX power ref - is only needed on
> > eDP/VLV/CHV avoid taking it in other cases.
> > 
> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index f56cbda59fb3..1ee9b7ebd801 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -6263,6 +6263,10 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder)
> >  
> >  	intel_dp->reset_link_params = true;
> >  
> > +	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
> > +	    !intel_dp_is_edp(intel_dp))
> > +		return;
> 
> vlv/chv need this for all DP ports.

Which is what this does. The wording in the commit message confused me.

> 
> > +
> >  	with_pps_lock(intel_dp, wakeref) {
> >  		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> >  			intel_dp->active_pipe = vlv_active_pipe(intel_dp);
> > -- 
> > 2.17.1
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Ville Syrjälä
Intel
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Re: [PATCH 09/10] drm/i915: Avoid taking the PPS lock for non-eDP/VLV/CHV

[Imre Deak]

On Mon, May 06, 2019 at 04:12:50PM +0300, Ville Syrjälä wrote:
> On Mon, May 06, 2019 at 03:35:52PM +0300, Ville Syrjälä wrote:
> > On Fri, May 03, 2019 at 02:26:47AM +0300, Imre Deak wrote:
> > > On ICL we have to make sure that we enable the AUX power domain in a
> > > controlled way (corresponding to the port's actual TypeC mode). Since
> > > the PPS lock - which takes an AUX power ref - is only needed on
> > > eDP/VLV/CHV avoid taking it in other cases.
> > > 
> > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_dp.c | 4 ++++
> > >  1 file changed, 4 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > > index f56cbda59fb3..1ee9b7ebd801 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -6263,6 +6263,10 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder)
> > >  
> > >  	intel_dp->reset_link_params = true;
> > >  
> > > +	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
> > > +	    !intel_dp_is_edp(intel_dp))
> > > +		return;
> > 
> > vlv/chv need this for all DP ports.
> 
> Which is what this does. The wording in the commit message confused me.

Yep, can make it clearer like:

... only needed on eDP on all platforms and eDP/DP on VLV/CHV, ...

> > 
> > > +
> > >  	with_pps_lock(intel_dp, wakeref) {
> > >  		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > >  			intel_dp->active_pipe = vlv_active_pipe(intel_dp);
> > > -- 
> > > 2.17.1
> > 
> > -- 
> > Ville Syrjälä
> > Intel
> 
> -- 
> Ville Syrjälä
> Intel
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Re: [PATCH 01/10] drm/i915: Add support for tracking wakerefs w/o power-on guarantee

[Chris Wilson]

Quoting Imre Deak (2019-05-03 00:26:39)
> @@ -4521,12 +4602,12 @@ void intel_runtime_pm_cleanup(struct drm_i915_private *i915)
>         struct i915_runtime_pm *rpm = &i915->runtime_pm;
>         int count;
>  
> -       count = atomic_fetch_inc(&rpm->wakeref_count); /* balance untrack */
> +       count = atomic_fetch_inc(&rpm->wakeref_track_count); /* balance untrack */
>         WARN(count,
> -            "i915->runtime_pm.wakeref_count=%d on cleanup\n",
> +            "i915->runtime_pm.wakeref_track_count=%d on cleanup\n",
>              count);
>  
> -       untrack_intel_runtime_pm_wakeref(i915);
> +       untrack_intel_runtime_pm_wakeref_raw(i915);

So this basically sums up the dilemma. The warning here should be if the
wakeref_count != 0 (meaning we have someone still using the device) at
cleanup. That track_count may be zero just implies loss of available
information.

Looking through this, I think it would be better if the track_count was
pushed into the runtime_pm.debug substruct, and really does only mean
the number of wakerefs being tracked by the debug backend. I believe that
helps with the separation of intent -- my only condition for the design
is that if you have a wakeref cookie, it is clear that you hold a
reference to the runtime-pm. (Where you want to add new api for
untracked wakerefs... I need to go back to the end again and see if you
really do need untracked wakerefs and if not the async power domain
merely needs to track it own wakeref independently of its clients.)

Bah.
-Chris
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