* [PATCH 01/17] dt-bindings: add Kontron vendor prefix
2019-05-09 15:58 [PATCH 00/17] Add Support for Kontron SMARC-sAMX6i Marco Felsch
@ 2019-05-09 15:58 ` Marco Felsch
2019-05-17 2:31 ` Rob Herring
2019-05-09 15:58 ` [PATCH 02/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: Add iMX6-based Kontron SMARC-sAMX6i module Marco Felsch
` (17 subsequent siblings)
18 siblings, 1 reply; 32+ messages in thread
From: Marco Felsch @ 2019-05-09 15:58 UTC (permalink / raw)
To: robh+dt, shawnguo, linux-imx
Cc: Stefan.Nickl, Gilles.Buloz, Michael.Brunner, thomas.schaefer,
frieder.schrempf, kernel, devicetree
Kontron is a leading embedded computer supplier. More information can be
found on: https://www.kontron.de/
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 8162b0eb4b50..87af42edd799 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -211,6 +211,7 @@ kinetic Kinetic Technologies
kingdisplay King & Display Technology Co., Ltd.
kingnovel Kingnovel Technology Co., Ltd.
koe Kaohsiung Opto-Electronics Inc.
+kontron Kontron S&T AG
kosagi Sutajio Ko-Usagi PTE Ltd.
kyo Kyocera Corporation
lacie LaCie
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH 01/17] dt-bindings: add Kontron vendor prefix
2019-05-09 15:58 ` [PATCH 01/17] dt-bindings: add Kontron vendor prefix Marco Felsch
@ 2019-05-17 2:31 ` Rob Herring
0 siblings, 0 replies; 32+ messages in thread
From: Rob Herring @ 2019-05-17 2:31 UTC (permalink / raw)
To: Marco Felsch
Cc: Shawn Guo, NXP Linux Team, Stefan.Nickl, Gilles.Buloz,
Michael.Brunner, thomas.schaefer, Schrempf Frieder, Sascha Hauer,
devicetree
On Thu, May 9, 2019 at 10:58 AM Marco Felsch <m.felsch@pengutronix.de> wrote:
>
> Kontron is a leading embedded computer supplier. More information can be
> found on: https://www.kontron.de/
>
> Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> 1 file changed, 1 insertion(+)
I've converted this file to json-schema as of v5.2-rc1. See commit
8122de54602e. Sorry, but you will have to rework this patch.
Rob
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 02/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: Add iMX6-based Kontron SMARC-sAMX6i module
2019-05-09 15:58 [PATCH 00/17] Add Support for Kontron SMARC-sAMX6i Marco Felsch
2019-05-09 15:58 ` [PATCH 01/17] dt-bindings: add Kontron vendor prefix Marco Felsch
@ 2019-05-09 15:58 ` Marco Felsch
2019-05-15 16:51 ` Priit Laes
2019-05-20 2:11 ` Shawn Guo
2019-05-09 15:58 ` [PATCH 03/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC SPI0 interface Marco Felsch
` (16 subsequent siblings)
18 siblings, 2 replies; 32+ messages in thread
From: Marco Felsch @ 2019-05-09 15:58 UTC (permalink / raw)
To: robh+dt, shawnguo, linux-imx
Cc: Stefan.Nickl, Gilles.Buloz, Michael.Brunner, thomas.schaefer,
frieder.schrempf, kernel, devicetree, Priit Laes,
Michael Grzeschik
From: Priit Laes <plaes@plaes.org>
SMARC-sAMX6i is a SMARC (Smart Mobility Architecture) compliant
module.
Signed-off-by: Priit Laes <plaes@plaes.org>
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
Based on patch: https://lore.kernel.org/patchwork/patch/762261/
v2:
- common: adapt commit message
- common: add pengutronix copyright
- common: use SPDX license header
- common: rename it to imx6qdl-smx6.dtsi
- common: drop imx6q.dtsi include and model, compatible, memory properties
- common: fix comment style
- common: drop all unnecessary 'status = "disabled"'
- i2c_pfuze: fix sda/scl gpios
- i2c_pfuze: s/i2c_pfuze/i2c_intern
- i2c_pfuze: use GPIO_* defines
- i2c3: fix pinmux
- fec: add phy-reset-gpio
- iomux: drop default 0x80000000 value
- iomux: use unique naming
- regulators: drop container node
- regulators: add all missing
arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi | 418 ++++++++++++++++++
1 file changed, 418 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
new file mode 100644
index 000000000000..e546d46365f5
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
@@ -0,0 +1,418 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright 2017 (C) Priit Laes <plaes@plaes.org>
+ * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr@pengutronix.de>
+ * Copyright 2019 (C) Pengutronix, Marco Felsch <kernel@pengutronix.de>
+ *
+ * Based on initial work by Nikita Yushchenko <nyushchenko at dev.rtsoft.ru>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ reg_1p0v_s0: regulator-1p0v-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "V_1V0_S0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <®_smarc_suppy>;
+ };
+
+ reg_1p35v_vcoredig_s5: regulator-1p35v-vcoredig-s5 {
+ compatible = "regulator-fixed";
+ regulator-name = "V_1V35_VCOREDIG_S5";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <®_3p3v_s5>;
+ };
+
+ reg_1p8v_s5: regulator-1p8v-s5 {
+ compatible = "regulator-fixed";
+ regulator-name = "V_1V8_S5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <®_3p3v_s5>;
+ };
+
+ reg_3p3v_s0: regulator-3p3v-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "V_3V3_S0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <®_3p3v_s5>;
+ };
+
+ reg_3p3v_s0: regulator-3p3v-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "V_3V3_S0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <®_3p3v_s5>;
+ };
+
+ reg_3p3v_s5: regulator-3p3v-s5 {
+ compatible = "regulator-fixed";
+ regulator-name = "V_3V3_S5";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <®_smarc_suppy>;
+ };
+
+ reg_smarc_rtc: regulator-smarc-rtc {
+ compatible = "regulator-fixed";
+ regulator-name = "V_IN_RTC_BATT";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* Module supply range can be 3.00V ... 5.25V */
+ reg_smarc_suppy: regulator-smarc-supply {
+ compatible = "regulator-fixed";
+ regulator-name = "V_IN_WIDE";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ i2c_intern: i2c-gpio-intern {
+ compatible = "i2c-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c_gpio_intern>;
+ sda-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>; /* ~100 kHz */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
+
+/* CAN0 */
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+};
+
+/* CAN1 */
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+};
+
+/* GBE */
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii";
+ phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+};
+
+&i2c_intern {
+ pfuze100@08 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+
+ regulators {
+ reg_v_core_s0: sw1ab {
+ regulator-name = "V_CORE_S0";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vddsoc_s0: sw1c {
+ regulator-name = "V_VDDSOC_S0";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p15v_s0: sw2 {
+ regulator-name = "V_3V15_S0";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* sw3a/b is used in dual mode, but driver does not
+ * support it. Although, there's no need to control
+ * DDR power - so just leaving dummy entries for sw3a
+ * and sw3b for now.
+ */
+ sw3a {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3b {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_1p8v_s0: sw4 {
+ regulator-name = "V_1V8_S0";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* Regulator for USB */
+ reg_5p0v_s0: swbst {
+ regulator-name = "V_5V0_S0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ regulator-boot-on;
+ };
+
+ reg_vsnvs: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vrefddr: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /*
+ * Per schematics, of all VGEN's, only VGEN5 has some
+ * usage ... but even that - over DNI resistor
+ */
+ vgen1 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vgen4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_2p5v_s0: vgen5 {
+ regulator-name = "V_2V5_S0";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+};
+
+/* I2C_PM */
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+};
+
+&iomuxc {
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
+ MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
+ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* RST_GBE0_PHY# */
+ >;
+ };
+
+ pinctrl_i2c_gpio_intern: i2c-gpiointerngrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* SCL */
+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* SDA */
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 /* PCI_A_PRSNT# */
+ MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 /* RST_PCIE_A# */
+ MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 /* PCIE_WAKE# */
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1f8b0
+ /* power, oc muxed but not used by the driver */
+ MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 /* USB power */
+ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 /* USB OC */
+ >;
+ };
+
+ pinctrl_usdhc4: usdhc4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
+ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
+ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
+ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
+ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
+ >;
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ wake-up-gpio = <&gpio6 18 GPIO_ACTIVE_HIGH>;
+ reset-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+};
+
+/* SER0 */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ uart-has-rtscts;
+};
+
+/* SER1 */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+};
+
+/* SER2 */
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ uart-has-rtscts;
+};
+
+/* SER3 */
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+};
+
+/* USB0 */
+&usbotg {
+ /*
+ * no 'imx6-usb-charger-detection'
+ * since USB_OTG_CHD_B pin is not wired
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+};
+
+/* USB1/2 via hub */
+&usbh1 {
+ vbus-supply = <®_5p0v_s0>;
+};
+
+/* SDMMC */
+&usdhc4 {
+ /* Internal eMMC, optional on some boards */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4>;
+ bus-width = <8>;
+ no-1-8-v;
+ non-removable;
+};
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH 02/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: Add iMX6-based Kontron SMARC-sAMX6i module
2019-05-09 15:58 ` [PATCH 02/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: Add iMX6-based Kontron SMARC-sAMX6i module Marco Felsch
@ 2019-05-15 16:51 ` Priit Laes
2019-05-16 15:47 ` Marco Felsch
2019-05-20 2:11 ` Shawn Guo
1 sibling, 1 reply; 32+ messages in thread
From: Priit Laes @ 2019-05-15 16:51 UTC (permalink / raw)
To: Marco Felsch
Cc: robh+dt, shawnguo, linux-imx, Stefan.Nickl, Gilles.Buloz,
Michael.Brunner, thomas.schaefer, frieder.schrempf, kernel,
devicetree, Michael Grzeschik
On Thu, May 09, 2019 at 05:58:19PM +0200, Marco Felsch wrote:
> From: Priit Laes <plaes@plaes.org>
Cool, thanks for picking that up :)
Also, another nice thing to see is that Kontron itself is now involved,
as back in the day when I was asking for extra information regarding
this board (latest BSP / Git tree) I was politely told to GTFO ;)
> SMARC-sAMX6i is a SMARC (Smart Mobility Architecture) compliant
> module.
>
> Signed-off-by: Priit Laes <plaes@plaes.org>
> Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
> Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
> ---
> Based on patch: https://lore.kernel.org/patchwork/patch/762261/
>
> v2:
> - common: adapt commit message
> - common: add pengutronix copyright
> - common: use SPDX license header
> - common: rename it to imx6qdl-smx6.dtsi
> - common: drop imx6q.dtsi include and model, compatible, memory properties
> - common: fix comment style
> - common: drop all unnecessary 'status = "disabled"'
> - i2c_pfuze: fix sda/scl gpios
> - i2c_pfuze: s/i2c_pfuze/i2c_intern
> - i2c_pfuze: use GPIO_* defines
> - i2c3: fix pinmux
> - fec: add phy-reset-gpio
> - iomux: drop default 0x80000000 value
> - iomux: use unique naming
> - regulators: drop container node
> - regulators: add all missing
>
> arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi | 418 ++++++++++++++++++
> 1 file changed, 418 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
>
> diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
> new file mode 100644
> index 000000000000..e546d46365f5
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
> @@ -0,0 +1,418 @@
> +// SPDX-License-Identifier: GPL-2.0 OR X11
> +/*
> + * Copyright 2017 (C) Priit Laes <plaes@plaes.org>
> + * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr@pengutronix.de>
> + * Copyright 2019 (C) Pengutronix, Marco Felsch <kernel@pengutronix.de>
> + *
> + * Based on initial work by Nikita Yushchenko <nyushchenko at dev.rtsoft.ru>
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + reg_1p0v_s0: regulator-1p0v-s0 {
> + compatible = "regulator-fixed";
> + regulator-name = "V_1V0_S0";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + regulator-boot-on;
> + vin-supply = <®_smarc_suppy>;
> + };
> +
> + reg_1p35v_vcoredig_s5: regulator-1p35v-vcoredig-s5 {
> + compatible = "regulator-fixed";
> + regulator-name = "V_1V35_VCOREDIG_S5";
> + regulator-min-microvolt = <1350000>;
> + regulator-max-microvolt = <1350000>;
> + regulator-always-on;
> + regulator-boot-on;
> + vin-supply = <®_3p3v_s5>;
> + };
> +
> + reg_1p8v_s5: regulator-1p8v-s5 {
> + compatible = "regulator-fixed";
> + regulator-name = "V_1V8_S5";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + regulator-boot-on;
> + vin-supply = <®_3p3v_s5>;
> + };
> +
> + reg_3p3v_s0: regulator-3p3v-s0 {
> + compatible = "regulator-fixed";
> + regulator-name = "V_3V3_S0";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + vin-supply = <®_3p3v_s5>;
> + };
> +
> + reg_3p3v_s0: regulator-3p3v-s0 {
> + compatible = "regulator-fixed";
> + regulator-name = "V_3V3_S0";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + vin-supply = <®_3p3v_s5>;
> + };
> +
> + reg_3p3v_s5: regulator-3p3v-s5 {
> + compatible = "regulator-fixed";
> + regulator-name = "V_3V3_S5";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + vin-supply = <®_smarc_suppy>;
> + };
> +
> + reg_smarc_rtc: regulator-smarc-rtc {
> + compatible = "regulator-fixed";
> + regulator-name = "V_IN_RTC_BATT";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + /* Module supply range can be 3.00V ... 5.25V */
> + reg_smarc_suppy: regulator-smarc-supply {
> + compatible = "regulator-fixed";
> + regulator-name = "V_IN_WIDE";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + i2c_intern: i2c-gpio-intern {
> + compatible = "i2c-gpio";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c_gpio_intern>;
> + sda-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + i2c-gpio,delay-us = <2>; /* ~100 kHz */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +};
> +
> +/* CAN0 */
> +&can1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan1>;
> +};
> +
> +/* CAN1 */
> +&can2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan2>;
> +};
> +
> +/* GBE */
> +&fec {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enet>;
> + phy-mode = "rgmii";
> + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
> +};
> +
> +&i2c_intern {
> + pfuze100@08 {
> + compatible = "fsl,pfuze100";
> + reg = <0x08>;
> +
> + regulators {
> + reg_v_core_s0: sw1ab {
> + regulator-name = "V_CORE_S0";
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1875000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + reg_vddsoc_s0: sw1c {
> + regulator-name = "V_VDDSOC_S0";
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1875000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + reg_3p15v_s0: sw2 {
> + regulator-name = "V_3V15_S0";
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + /* sw3a/b is used in dual mode, but driver does not
> + * support it. Although, there's no need to control
> + * DDR power - so just leaving dummy entries for sw3a
> + * and sw3b for now.
> + */
> + sw3a {
> + regulator-min-microvolt = <400000>;
> + regulator-max-microvolt = <1975000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + sw3b {
> + regulator-min-microvolt = <400000>;
> + regulator-max-microvolt = <1975000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + reg_1p8v_s0: sw4 {
> + regulator-name = "V_1V8_S0";
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + /* Regulator for USB */
> + reg_5p0v_s0: swbst {
> + regulator-name = "V_5V0_S0";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5150000>;
> + regulator-boot-on;
> + };
> +
> + reg_vsnvs: vsnvs {
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + reg_vrefddr: vrefddr {
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + /*
> + * Per schematics, of all VGEN's, only VGEN5 has some
> + * usage ... but even that - over DNI resistor
> + */
> + vgen1 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1550000>;
> + };
> +
> + vgen2 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1550000>;
> + };
> +
> + vgen3 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + vgen4 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + reg_2p5v_s0: vgen5 {
> + regulator-name = "V_2V5_S0";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + vgen6 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + };
> + };
> + };
> +};
> +
> +/* I2C_PM */
> +&i2c3 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c3>;
> +};
> +
> +&iomuxc {
> + pinctrl_flexcan1: flexcan1grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
> + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
> + >;
> + };
> +
> + pinctrl_flexcan2: flexcan2grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
> + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
> + >;
> + };
> +
> + pinctrl_enet: enetgrp {
> + fsl,pins = <
> + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
> + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
> + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
> + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
> + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
> + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
> + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
> + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
> + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
> + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
> + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
> + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
> +
> + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
> + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
> + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
> + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* RST_GBE0_PHY# */
> + >;
> + };
> +
> + pinctrl_i2c_gpio_intern: i2c-gpiointerngrp {
> + fsl,pins = <
> + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* SCL */
> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* SDA */
> + >;
> + };
> +
> + pinctrl_i2c3: i2c3grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
> + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_pcie: pciegrp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 /* PCI_A_PRSNT# */
> + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 /* RST_PCIE_A# */
> + MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 /* PCIE_WAKE# */
> + >;
> + };
> +
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
> + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
> + MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1
> + MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart2: uart2grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
> + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart4: uart4grp {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
> + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
> + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
> + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart5: uart5grp {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
> + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
> + >;
> + };
> +
> + pinctrl_usbotg: usbotggrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1f8b0
> + /* power, oc muxed but not used by the driver */
> + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 /* USB power */
> + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 /* USB OC */
> + >;
> + };
> +
> + pinctrl_usdhc4: usdhc4grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059
> + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
> + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
> + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
> + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
> + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
> + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
> + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
> + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
> + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
> + >;
> + };
> +};
> +
> +&pcie {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pcie>;
> + wake-up-gpio = <&gpio6 18 GPIO_ACTIVE_HIGH>;
> + reset-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>;
> +};
> +
> +/* SER0 */
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + uart-has-rtscts;
> +};
> +
> +/* SER1 */
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart2>;
> +};
> +
> +/* SER2 */
> +&uart4 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart4>;
> + uart-has-rtscts;
> +};
> +
> +/* SER3 */
> +&uart5 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart5>;
> +};
> +
> +/* USB0 */
> +&usbotg {
> + /*
> + * no 'imx6-usb-charger-detection'
> + * since USB_OTG_CHD_B pin is not wired
> + */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usbotg>;
> +};
> +
> +/* USB1/2 via hub */
> +&usbh1 {
> + vbus-supply = <®_5p0v_s0>;
> +};
> +
> +/* SDMMC */
> +&usdhc4 {
> + /* Internal eMMC, optional on some boards */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc4>;
> + bus-width = <8>;
> + no-1-8-v;
> + non-removable;
> +};
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 02/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: Add iMX6-based Kontron SMARC-sAMX6i module
2019-05-15 16:51 ` Priit Laes
@ 2019-05-16 15:47 ` Marco Felsch
2019-05-16 16:44 ` Priit Laes
0 siblings, 1 reply; 32+ messages in thread
From: Marco Felsch @ 2019-05-16 15:47 UTC (permalink / raw)
To: Priit Laes
Cc: robh+dt, shawnguo, linux-imx, Stefan.Nickl, Gilles.Buloz,
Michael.Brunner, thomas.schaefer, frieder.schrempf, kernel,
devicetree, Michael Grzeschik
On 19-05-15 16:51, Priit Laes wrote:
> On Thu, May 09, 2019 at 05:58:19PM +0200, Marco Felsch wrote:
> > From: Priit Laes <plaes@plaes.org>
>
> Cool, thanks for picking that up :)
You're welcome ;) Do you have a develboard to test the interfaces I
added? Since I don't have it and the kontron guys didn't reply yet.
>
> Also, another nice thing to see is that Kontron itself is now involved,
> as back in the day when I was asking for extra information regarding
> this board (latest BSP / Git tree) I was politely told to GTFO ;)
Regards,
Marco
>
> > SMARC-sAMX6i is a SMARC (Smart Mobility Architecture) compliant
> > module.
> >
> > Signed-off-by: Priit Laes <plaes@plaes.org>
> > Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
> > Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
> > ---
> > Based on patch: https://lore.kernel.org/patchwork/patch/762261/
> >
> > v2:
> > - common: adapt commit message
> > - common: add pengutronix copyright
> > - common: use SPDX license header
> > - common: rename it to imx6qdl-smx6.dtsi
> > - common: drop imx6q.dtsi include and model, compatible, memory properties
> > - common: fix comment style
> > - common: drop all unnecessary 'status = "disabled"'
> > - i2c_pfuze: fix sda/scl gpios
> > - i2c_pfuze: s/i2c_pfuze/i2c_intern
> > - i2c_pfuze: use GPIO_* defines
> > - i2c3: fix pinmux
> > - fec: add phy-reset-gpio
> > - iomux: drop default 0x80000000 value
> > - iomux: use unique naming
> > - regulators: drop container node
> > - regulators: add all missing
> >
> > arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi | 418 ++++++++++++++++++
> > 1 file changed, 418 insertions(+)
> > create mode 100644 arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
> >
> > diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
> > new file mode 100644
> > index 000000000000..e546d46365f5
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
> > @@ -0,0 +1,418 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR X11
> > +/*
> > + * Copyright 2017 (C) Priit Laes <plaes@plaes.org>
> > + * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr@pengutronix.de>
> > + * Copyright 2019 (C) Pengutronix, Marco Felsch <kernel@pengutronix.de>
> > + *
> > + * Based on initial work by Nikita Yushchenko <nyushchenko at dev.rtsoft.ru>
> > + */
> > +
> > +#include <dt-bindings/gpio/gpio.h>
> > +
> > +/ {
> > + reg_1p0v_s0: regulator-1p0v-s0 {
> > + compatible = "regulator-fixed";
> > + regulator-name = "V_1V0_S0";
> > + regulator-min-microvolt = <1000000>;
> > + regulator-max-microvolt = <1000000>;
> > + regulator-always-on;
> > + regulator-boot-on;
> > + vin-supply = <®_smarc_suppy>;
> > + };
> > +
> > + reg_1p35v_vcoredig_s5: regulator-1p35v-vcoredig-s5 {
> > + compatible = "regulator-fixed";
> > + regulator-name = "V_1V35_VCOREDIG_S5";
> > + regulator-min-microvolt = <1350000>;
> > + regulator-max-microvolt = <1350000>;
> > + regulator-always-on;
> > + regulator-boot-on;
> > + vin-supply = <®_3p3v_s5>;
> > + };
> > +
> > + reg_1p8v_s5: regulator-1p8v-s5 {
> > + compatible = "regulator-fixed";
> > + regulator-name = "V_1V8_S5";
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <1800000>;
> > + regulator-always-on;
> > + regulator-boot-on;
> > + vin-supply = <®_3p3v_s5>;
> > + };
> > +
> > + reg_3p3v_s0: regulator-3p3v-s0 {
> > + compatible = "regulator-fixed";
> > + regulator-name = "V_3V3_S0";
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-always-on;
> > + regulator-boot-on;
> > + vin-supply = <®_3p3v_s5>;
> > + };
> > +
> > + reg_3p3v_s0: regulator-3p3v-s0 {
> > + compatible = "regulator-fixed";
> > + regulator-name = "V_3V3_S0";
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-always-on;
> > + regulator-boot-on;
> > + vin-supply = <®_3p3v_s5>;
> > + };
> > +
> > + reg_3p3v_s5: regulator-3p3v-s5 {
> > + compatible = "regulator-fixed";
> > + regulator-name = "V_3V3_S5";
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-always-on;
> > + regulator-boot-on;
> > + vin-supply = <®_smarc_suppy>;
> > + };
> > +
> > + reg_smarc_rtc: regulator-smarc-rtc {
> > + compatible = "regulator-fixed";
> > + regulator-name = "V_IN_RTC_BATT";
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-always-on;
> > + regulator-boot-on;
> > + };
> > +
> > + /* Module supply range can be 3.00V ... 5.25V */
> > + reg_smarc_suppy: regulator-smarc-supply {
> > + compatible = "regulator-fixed";
> > + regulator-name = "V_IN_WIDE";
> > + regulator-min-microvolt = <5000000>;
> > + regulator-max-microvolt = <5000000>;
> > + regulator-always-on;
> > + regulator-boot-on;
> > + };
> > +
> > + i2c_intern: i2c-gpio-intern {
> > + compatible = "i2c-gpio";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_i2c_gpio_intern>;
> > + sda-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> > + scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> > + i2c-gpio,delay-us = <2>; /* ~100 kHz */
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +};
> > +
> > +/* CAN0 */
> > +&can1 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_flexcan1>;
> > +};
> > +
> > +/* CAN1 */
> > +&can2 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_flexcan2>;
> > +};
> > +
> > +/* GBE */
> > +&fec {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_enet>;
> > + phy-mode = "rgmii";
> > + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
> > +};
> > +
> > +&i2c_intern {
> > + pfuze100@08 {
> > + compatible = "fsl,pfuze100";
> > + reg = <0x08>;
> > +
> > + regulators {
> > + reg_v_core_s0: sw1ab {
> > + regulator-name = "V_CORE_S0";
> > + regulator-min-microvolt = <300000>;
> > + regulator-max-microvolt = <1875000>;
> > + regulator-boot-on;
> > + regulator-always-on;
> > + };
> > +
> > + reg_vddsoc_s0: sw1c {
> > + regulator-name = "V_VDDSOC_S0";
> > + regulator-min-microvolt = <300000>;
> > + regulator-max-microvolt = <1875000>;
> > + regulator-boot-on;
> > + regulator-always-on;
> > + };
> > +
> > + reg_3p15v_s0: sw2 {
> > + regulator-name = "V_3V15_S0";
> > + regulator-min-microvolt = <800000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-boot-on;
> > + regulator-always-on;
> > + };
> > +
> > + /* sw3a/b is used in dual mode, but driver does not
> > + * support it. Although, there's no need to control
> > + * DDR power - so just leaving dummy entries for sw3a
> > + * and sw3b for now.
> > + */
> > + sw3a {
> > + regulator-min-microvolt = <400000>;
> > + regulator-max-microvolt = <1975000>;
> > + regulator-boot-on;
> > + regulator-always-on;
> > + };
> > +
> > + sw3b {
> > + regulator-min-microvolt = <400000>;
> > + regulator-max-microvolt = <1975000>;
> > + regulator-boot-on;
> > + regulator-always-on;
> > + };
> > +
> > + reg_1p8v_s0: sw4 {
> > + regulator-name = "V_1V8_S0";
> > + regulator-min-microvolt = <800000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-boot-on;
> > + regulator-always-on;
> > + };
> > +
> > + /* Regulator for USB */
> > + reg_5p0v_s0: swbst {
> > + regulator-name = "V_5V0_S0";
> > + regulator-min-microvolt = <5000000>;
> > + regulator-max-microvolt = <5150000>;
> > + regulator-boot-on;
> > + };
> > +
> > + reg_vsnvs: vsnvs {
> > + regulator-min-microvolt = <1000000>;
> > + regulator-max-microvolt = <3000000>;
> > + regulator-boot-on;
> > + regulator-always-on;
> > + };
> > +
> > + reg_vrefddr: vrefddr {
> > + regulator-boot-on;
> > + regulator-always-on;
> > + };
> > +
> > + /*
> > + * Per schematics, of all VGEN's, only VGEN5 has some
> > + * usage ... but even that - over DNI resistor
> > + */
> > + vgen1 {
> > + regulator-min-microvolt = <800000>;
> > + regulator-max-microvolt = <1550000>;
> > + };
> > +
> > + vgen2 {
> > + regulator-min-microvolt = <800000>;
> > + regulator-max-microvolt = <1550000>;
> > + };
> > +
> > + vgen3 {
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <3300000>;
> > + };
> > +
> > + vgen4 {
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <3300000>;
> > + };
> > +
> > + reg_2p5v_s0: vgen5 {
> > + regulator-name = "V_2V5_S0";
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <3300000>;
> > + };
> > +
> > + vgen6 {
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <3300000>;
> > + };
> > + };
> > + };
> > +};
> > +
> > +/* I2C_PM */
> > +&i2c3 {
> > + clock-frequency = <100000>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_i2c3>;
> > +};
> > +
> > +&iomuxc {
> > + pinctrl_flexcan1: flexcan1grp {
> > + fsl,pins = <
> > + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
> > + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
> > + >;
> > + };
> > +
> > + pinctrl_flexcan2: flexcan2grp {
> > + fsl,pins = <
> > + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
> > + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
> > + >;
> > + };
> > +
> > + pinctrl_enet: enetgrp {
> > + fsl,pins = <
> > + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
> > + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
> > + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
> > + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
> > + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
> > + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
> > + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
> > + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
> > + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
> > + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
> > + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
> > + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
> > +
> > + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
> > + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
> > + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
> > + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* RST_GBE0_PHY# */
> > + >;
> > + };
> > +
> > + pinctrl_i2c_gpio_intern: i2c-gpiointerngrp {
> > + fsl,pins = <
> > + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* SCL */
> > + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* SDA */
> > + >;
> > + };
> > +
> > + pinctrl_i2c3: i2c3grp {
> > + fsl,pins = <
> > + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
> > + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
> > + >;
> > + };
> > +
> > + pinctrl_pcie: pciegrp {
> > + fsl,pins = <
> > + MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 /* PCI_A_PRSNT# */
> > + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 /* RST_PCIE_A# */
> > + MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 /* PCIE_WAKE# */
> > + >;
> > + };
> > +
> > + pinctrl_uart1: uart1grp {
> > + fsl,pins = <
> > + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
> > + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
> > + MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1
> > + MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1
> > + >;
> > + };
> > +
> > + pinctrl_uart2: uart2grp {
> > + fsl,pins = <
> > + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
> > + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
> > + >;
> > + };
> > +
> > + pinctrl_uart4: uart4grp {
> > + fsl,pins = <
> > + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
> > + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
> > + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
> > + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
> > + >;
> > + };
> > +
> > + pinctrl_uart5: uart5grp {
> > + fsl,pins = <
> > + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
> > + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
> > + >;
> > + };
> > +
> > + pinctrl_usbotg: usbotggrp {
> > + fsl,pins = <
> > + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1f8b0
> > + /* power, oc muxed but not used by the driver */
> > + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 /* USB power */
> > + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 /* USB OC */
> > + >;
> > + };
> > +
> > + pinctrl_usdhc4: usdhc4grp {
> > + fsl,pins = <
> > + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059
> > + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
> > + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
> > + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
> > + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
> > + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
> > + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
> > + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
> > + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
> > + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
> > + >;
> > + };
> > +};
> > +
> > +&pcie {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_pcie>;
> > + wake-up-gpio = <&gpio6 18 GPIO_ACTIVE_HIGH>;
> > + reset-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>;
> > +};
> > +
> > +/* SER0 */
> > +&uart1 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_uart1>;
> > + uart-has-rtscts;
> > +};
> > +
> > +/* SER1 */
> > +&uart2 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_uart2>;
> > +};
> > +
> > +/* SER2 */
> > +&uart4 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_uart4>;
> > + uart-has-rtscts;
> > +};
> > +
> > +/* SER3 */
> > +&uart5 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_uart5>;
> > +};
> > +
> > +/* USB0 */
> > +&usbotg {
> > + /*
> > + * no 'imx6-usb-charger-detection'
> > + * since USB_OTG_CHD_B pin is not wired
> > + */
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_usbotg>;
> > +};
> > +
> > +/* USB1/2 via hub */
> > +&usbh1 {
> > + vbus-supply = <®_5p0v_s0>;
> > +};
> > +
> > +/* SDMMC */
> > +&usdhc4 {
> > + /* Internal eMMC, optional on some boards */
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_usdhc4>;
> > + bus-width = <8>;
> > + no-1-8-v;
> > + non-removable;
> > +};
> > --
> > 2.20.1
> >
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 02/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: Add iMX6-based Kontron SMARC-sAMX6i module
2019-05-16 15:47 ` Marco Felsch
@ 2019-05-16 16:44 ` Priit Laes
0 siblings, 0 replies; 32+ messages in thread
From: Priit Laes @ 2019-05-16 16:44 UTC (permalink / raw)
To: Marco Felsch
Cc: robh+dt, shawnguo, linux-imx, Stefan.Nickl, Gilles.Buloz,
Michael.Brunner, thomas.schaefer, frieder.schrempf, kernel,
devicetree, Michael Grzeschik
On Thu, May 16, 2019 at 05:47:11PM +0200, Marco Felsch wrote:
> On 19-05-15 16:51, Priit Laes wrote:
> > On Thu, May 09, 2019 at 05:58:19PM +0200, Marco Felsch wrote:
> > > From: Priit Laes <plaes@plaes.org>
> >
> > Cool, thanks for picking that up :)
>
> You're welcome ;) Do you have a develboard to test the interfaces I
> added? Since I don't have it and the kontron guys didn't reply yet.
Nope, I had one mil-spec rugged computer for initial prototype
system that was later exchanged to something else because of
issues with the baseboard itself.
>
> >
> > Also, another nice thing to see is that Kontron itself is now involved,
> > as back in the day when I was asking for extra information regarding
> > this board (latest BSP / Git tree) I was politely told to GTFO ;)
>
> Regards,
> Marco
>
> >
> > > SMARC-sAMX6i is a SMARC (Smart Mobility Architecture) compliant
> > > module.
> > >
> > > Signed-off-by: Priit Laes <plaes@plaes.org>
> > > Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
> > > Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
> > > ---
> > > Based on patch: https://lore.kernel.org/patchwork/patch/762261/
> > >
> > > v2:
> > > - common: adapt commit message
> > > - common: add pengutronix copyright
> > > - common: use SPDX license header
> > > - common: rename it to imx6qdl-smx6.dtsi
> > > - common: drop imx6q.dtsi include and model, compatible, memory properties
> > > - common: fix comment style
> > > - common: drop all unnecessary 'status = "disabled"'
> > > - i2c_pfuze: fix sda/scl gpios
> > > - i2c_pfuze: s/i2c_pfuze/i2c_intern
> > > - i2c_pfuze: use GPIO_* defines
> > > - i2c3: fix pinmux
> > > - fec: add phy-reset-gpio
> > > - iomux: drop default 0x80000000 value
> > > - iomux: use unique naming
> > > - regulators: drop container node
> > > - regulators: add all missing
> > >
> > > arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi | 418 ++++++++++++++++++
> > > 1 file changed, 418 insertions(+)
> > > create mode 100644 arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
> > >
> > > diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
> > > new file mode 100644
> > > index 000000000000..e546d46365f5
> > > --- /dev/null
> > > +++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
> > > @@ -0,0 +1,418 @@
> > > +// SPDX-License-Identifier: GPL-2.0 OR X11
> > > +/*
> > > + * Copyright 2017 (C) Priit Laes <plaes@plaes.org>
> > > + * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr@pengutronix.de>
> > > + * Copyright 2019 (C) Pengutronix, Marco Felsch <kernel@pengutronix.de>
> > > + *
> > > + * Based on initial work by Nikita Yushchenko <nyushchenko at dev.rtsoft.ru>
> > > + */
> > > +
> > > +#include <dt-bindings/gpio/gpio.h>
> > > +
> > > +/ {
> > > + reg_1p0v_s0: regulator-1p0v-s0 {
> > > + compatible = "regulator-fixed";
> > > + regulator-name = "V_1V0_S0";
> > > + regulator-min-microvolt = <1000000>;
> > > + regulator-max-microvolt = <1000000>;
> > > + regulator-always-on;
> > > + regulator-boot-on;
> > > + vin-supply = <®_smarc_suppy>;
> > > + };
> > > +
> > > + reg_1p35v_vcoredig_s5: regulator-1p35v-vcoredig-s5 {
> > > + compatible = "regulator-fixed";
> > > + regulator-name = "V_1V35_VCOREDIG_S5";
> > > + regulator-min-microvolt = <1350000>;
> > > + regulator-max-microvolt = <1350000>;
> > > + regulator-always-on;
> > > + regulator-boot-on;
> > > + vin-supply = <®_3p3v_s5>;
> > > + };
> > > +
> > > + reg_1p8v_s5: regulator-1p8v-s5 {
> > > + compatible = "regulator-fixed";
> > > + regulator-name = "V_1V8_S5";
> > > + regulator-min-microvolt = <1800000>;
> > > + regulator-max-microvolt = <1800000>;
> > > + regulator-always-on;
> > > + regulator-boot-on;
> > > + vin-supply = <®_3p3v_s5>;
> > > + };
> > > +
> > > + reg_3p3v_s0: regulator-3p3v-s0 {
> > > + compatible = "regulator-fixed";
> > > + regulator-name = "V_3V3_S0";
> > > + regulator-min-microvolt = <3300000>;
> > > + regulator-max-microvolt = <3300000>;
> > > + regulator-always-on;
> > > + regulator-boot-on;
> > > + vin-supply = <®_3p3v_s5>;
> > > + };
> > > +
> > > + reg_3p3v_s0: regulator-3p3v-s0 {
> > > + compatible = "regulator-fixed";
> > > + regulator-name = "V_3V3_S0";
> > > + regulator-min-microvolt = <3300000>;
> > > + regulator-max-microvolt = <3300000>;
> > > + regulator-always-on;
> > > + regulator-boot-on;
> > > + vin-supply = <®_3p3v_s5>;
> > > + };
> > > +
> > > + reg_3p3v_s5: regulator-3p3v-s5 {
> > > + compatible = "regulator-fixed";
> > > + regulator-name = "V_3V3_S5";
> > > + regulator-min-microvolt = <3300000>;
> > > + regulator-max-microvolt = <3300000>;
> > > + regulator-always-on;
> > > + regulator-boot-on;
> > > + vin-supply = <®_smarc_suppy>;
> > > + };
> > > +
> > > + reg_smarc_rtc: regulator-smarc-rtc {
> > > + compatible = "regulator-fixed";
> > > + regulator-name = "V_IN_RTC_BATT";
> > > + regulator-min-microvolt = <3300000>;
> > > + regulator-max-microvolt = <3300000>;
> > > + regulator-always-on;
> > > + regulator-boot-on;
> > > + };
> > > +
> > > + /* Module supply range can be 3.00V ... 5.25V */
> > > + reg_smarc_suppy: regulator-smarc-supply {
> > > + compatible = "regulator-fixed";
> > > + regulator-name = "V_IN_WIDE";
> > > + regulator-min-microvolt = <5000000>;
> > > + regulator-max-microvolt = <5000000>;
> > > + regulator-always-on;
> > > + regulator-boot-on;
> > > + };
> > > +
> > > + i2c_intern: i2c-gpio-intern {
> > > + compatible = "i2c-gpio";
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_i2c_gpio_intern>;
> > > + sda-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> > > + scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> > > + i2c-gpio,delay-us = <2>; /* ~100 kHz */
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + };
> > > +};
> > > +
> > > +/* CAN0 */
> > > +&can1 {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_flexcan1>;
> > > +};
> > > +
> > > +/* CAN1 */
> > > +&can2 {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_flexcan2>;
> > > +};
> > > +
> > > +/* GBE */
> > > +&fec {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_enet>;
> > > + phy-mode = "rgmii";
> > > + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
> > > +};
> > > +
> > > +&i2c_intern {
> > > + pfuze100@08 {
> > > + compatible = "fsl,pfuze100";
> > > + reg = <0x08>;
> > > +
> > > + regulators {
> > > + reg_v_core_s0: sw1ab {
> > > + regulator-name = "V_CORE_S0";
> > > + regulator-min-microvolt = <300000>;
> > > + regulator-max-microvolt = <1875000>;
> > > + regulator-boot-on;
> > > + regulator-always-on;
> > > + };
> > > +
> > > + reg_vddsoc_s0: sw1c {
> > > + regulator-name = "V_VDDSOC_S0";
> > > + regulator-min-microvolt = <300000>;
> > > + regulator-max-microvolt = <1875000>;
> > > + regulator-boot-on;
> > > + regulator-always-on;
> > > + };
> > > +
> > > + reg_3p15v_s0: sw2 {
> > > + regulator-name = "V_3V15_S0";
> > > + regulator-min-microvolt = <800000>;
> > > + regulator-max-microvolt = <3300000>;
> > > + regulator-boot-on;
> > > + regulator-always-on;
> > > + };
> > > +
> > > + /* sw3a/b is used in dual mode, but driver does not
> > > + * support it. Although, there's no need to control
> > > + * DDR power - so just leaving dummy entries for sw3a
> > > + * and sw3b for now.
> > > + */
> > > + sw3a {
> > > + regulator-min-microvolt = <400000>;
> > > + regulator-max-microvolt = <1975000>;
> > > + regulator-boot-on;
> > > + regulator-always-on;
> > > + };
> > > +
> > > + sw3b {
> > > + regulator-min-microvolt = <400000>;
> > > + regulator-max-microvolt = <1975000>;
> > > + regulator-boot-on;
> > > + regulator-always-on;
> > > + };
> > > +
> > > + reg_1p8v_s0: sw4 {
> > > + regulator-name = "V_1V8_S0";
> > > + regulator-min-microvolt = <800000>;
> > > + regulator-max-microvolt = <3300000>;
> > > + regulator-boot-on;
> > > + regulator-always-on;
> > > + };
> > > +
> > > + /* Regulator for USB */
> > > + reg_5p0v_s0: swbst {
> > > + regulator-name = "V_5V0_S0";
> > > + regulator-min-microvolt = <5000000>;
> > > + regulator-max-microvolt = <5150000>;
> > > + regulator-boot-on;
> > > + };
> > > +
> > > + reg_vsnvs: vsnvs {
> > > + regulator-min-microvolt = <1000000>;
> > > + regulator-max-microvolt = <3000000>;
> > > + regulator-boot-on;
> > > + regulator-always-on;
> > > + };
> > > +
> > > + reg_vrefddr: vrefddr {
> > > + regulator-boot-on;
> > > + regulator-always-on;
> > > + };
> > > +
> > > + /*
> > > + * Per schematics, of all VGEN's, only VGEN5 has some
> > > + * usage ... but even that - over DNI resistor
> > > + */
> > > + vgen1 {
> > > + regulator-min-microvolt = <800000>;
> > > + regulator-max-microvolt = <1550000>;
> > > + };
> > > +
> > > + vgen2 {
> > > + regulator-min-microvolt = <800000>;
> > > + regulator-max-microvolt = <1550000>;
> > > + };
> > > +
> > > + vgen3 {
> > > + regulator-min-microvolt = <1800000>;
> > > + regulator-max-microvolt = <3300000>;
> > > + };
> > > +
> > > + vgen4 {
> > > + regulator-min-microvolt = <1800000>;
> > > + regulator-max-microvolt = <3300000>;
> > > + };
> > > +
> > > + reg_2p5v_s0: vgen5 {
> > > + regulator-name = "V_2V5_S0";
> > > + regulator-min-microvolt = <1800000>;
> > > + regulator-max-microvolt = <3300000>;
> > > + };
> > > +
> > > + vgen6 {
> > > + regulator-min-microvolt = <1800000>;
> > > + regulator-max-microvolt = <3300000>;
> > > + };
> > > + };
> > > + };
> > > +};
> > > +
> > > +/* I2C_PM */
> > > +&i2c3 {
> > > + clock-frequency = <100000>;
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_i2c3>;
> > > +};
> > > +
> > > +&iomuxc {
> > > + pinctrl_flexcan1: flexcan1grp {
> > > + fsl,pins = <
> > > + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
> > > + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
> > > + >;
> > > + };
> > > +
> > > + pinctrl_flexcan2: flexcan2grp {
> > > + fsl,pins = <
> > > + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
> > > + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
> > > + >;
> > > + };
> > > +
> > > + pinctrl_enet: enetgrp {
> > > + fsl,pins = <
> > > + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
> > > + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
> > > + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
> > > + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
> > > + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
> > > + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
> > > + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
> > > + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
> > > + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
> > > + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
> > > + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
> > > + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
> > > +
> > > + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
> > > + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
> > > + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
> > > + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* RST_GBE0_PHY# */
> > > + >;
> > > + };
> > > +
> > > + pinctrl_i2c_gpio_intern: i2c-gpiointerngrp {
> > > + fsl,pins = <
> > > + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* SCL */
> > > + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* SDA */
> > > + >;
> > > + };
> > > +
> > > + pinctrl_i2c3: i2c3grp {
> > > + fsl,pins = <
> > > + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
> > > + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
> > > + >;
> > > + };
> > > +
> > > + pinctrl_pcie: pciegrp {
> > > + fsl,pins = <
> > > + MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 /* PCI_A_PRSNT# */
> > > + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 /* RST_PCIE_A# */
> > > + MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 /* PCIE_WAKE# */
> > > + >;
> > > + };
> > > +
> > > + pinctrl_uart1: uart1grp {
> > > + fsl,pins = <
> > > + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
> > > + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
> > > + MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1
> > > + MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1
> > > + >;
> > > + };
> > > +
> > > + pinctrl_uart2: uart2grp {
> > > + fsl,pins = <
> > > + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
> > > + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
> > > + >;
> > > + };
> > > +
> > > + pinctrl_uart4: uart4grp {
> > > + fsl,pins = <
> > > + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
> > > + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
> > > + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
> > > + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
> > > + >;
> > > + };
> > > +
> > > + pinctrl_uart5: uart5grp {
> > > + fsl,pins = <
> > > + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
> > > + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
> > > + >;
> > > + };
> > > +
> > > + pinctrl_usbotg: usbotggrp {
> > > + fsl,pins = <
> > > + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1f8b0
> > > + /* power, oc muxed but not used by the driver */
> > > + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 /* USB power */
> > > + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 /* USB OC */
> > > + >;
> > > + };
> > > +
> > > + pinctrl_usdhc4: usdhc4grp {
> > > + fsl,pins = <
> > > + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059
> > > + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
> > > + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
> > > + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
> > > + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
> > > + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
> > > + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
> > > + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
> > > + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
> > > + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
> > > + >;
> > > + };
> > > +};
> > > +
> > > +&pcie {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_pcie>;
> > > + wake-up-gpio = <&gpio6 18 GPIO_ACTIVE_HIGH>;
> > > + reset-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>;
> > > +};
> > > +
> > > +/* SER0 */
> > > +&uart1 {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_uart1>;
> > > + uart-has-rtscts;
> > > +};
> > > +
> > > +/* SER1 */
> > > +&uart2 {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_uart2>;
> > > +};
> > > +
> > > +/* SER2 */
> > > +&uart4 {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_uart4>;
> > > + uart-has-rtscts;
> > > +};
> > > +
> > > +/* SER3 */
> > > +&uart5 {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_uart5>;
> > > +};
> > > +
> > > +/* USB0 */
> > > +&usbotg {
> > > + /*
> > > + * no 'imx6-usb-charger-detection'
> > > + * since USB_OTG_CHD_B pin is not wired
> > > + */
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_usbotg>;
> > > +};
> > > +
> > > +/* USB1/2 via hub */
> > > +&usbh1 {
> > > + vbus-supply = <®_5p0v_s0>;
> > > +};
> > > +
> > > +/* SDMMC */
> > > +&usdhc4 {
> > > + /* Internal eMMC, optional on some boards */
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_usdhc4>;
> > > + bus-width = <8>;
> > > + no-1-8-v;
> > > + non-removable;
> > > +};
> > > --
> > > 2.20.1
> > >
> >
>
> --
> Pengutronix e.K. | |
> Industrial Linux Solutions | http://www.pengutronix.de/ |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 02/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: Add iMX6-based Kontron SMARC-sAMX6i module
2019-05-09 15:58 ` [PATCH 02/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: Add iMX6-based Kontron SMARC-sAMX6i module Marco Felsch
2019-05-15 16:51 ` Priit Laes
@ 2019-05-20 2:11 ` Shawn Guo
1 sibling, 0 replies; 32+ messages in thread
From: Shawn Guo @ 2019-05-20 2:11 UTC (permalink / raw)
To: Marco Felsch
Cc: robh+dt, linux-imx, Stefan.Nickl, Gilles.Buloz, Michael.Brunner,
thomas.schaefer, frieder.schrempf, kernel, devicetree,
Priit Laes, Michael Grzeschik
On Thu, May 09, 2019 at 05:58:19PM +0200, Marco Felsch wrote:
> From: Priit Laes <plaes@plaes.org>
>
> SMARC-sAMX6i is a SMARC (Smart Mobility Architecture) compliant
> module.
>
> Signed-off-by: Priit Laes <plaes@plaes.org>
> Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
> Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
> ---
> Based on patch: https://lore.kernel.org/patchwork/patch/762261/
>
> v2:
> - common: adapt commit message
> - common: add pengutronix copyright
> - common: use SPDX license header
> - common: rename it to imx6qdl-smx6.dtsi
> - common: drop imx6q.dtsi include and model, compatible, memory properties
> - common: fix comment style
> - common: drop all unnecessary 'status = "disabled"'
> - i2c_pfuze: fix sda/scl gpios
> - i2c_pfuze: s/i2c_pfuze/i2c_intern
> - i2c_pfuze: use GPIO_* defines
> - i2c3: fix pinmux
> - fec: add phy-reset-gpio
> - iomux: drop default 0x80000000 value
> - iomux: use unique naming
> - regulators: drop container node
> - regulators: add all missing
>
> arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi | 418 ++++++++++++++++++
> 1 file changed, 418 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
>
> diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
> new file mode 100644
> index 000000000000..e546d46365f5
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
> @@ -0,0 +1,418 @@
> +// SPDX-License-Identifier: GPL-2.0 OR X11
> +/*
> + * Copyright 2017 (C) Priit Laes <plaes@plaes.org>
> + * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr@pengutronix.de>
> + * Copyright 2019 (C) Pengutronix, Marco Felsch <kernel@pengutronix.de>
> + *
> + * Based on initial work by Nikita Yushchenko <nyushchenko at dev.rtsoft.ru>
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + reg_1p0v_s0: regulator-1p0v-s0 {
> + compatible = "regulator-fixed";
> + regulator-name = "V_1V0_S0";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + regulator-boot-on;
> + vin-supply = <®_smarc_suppy>;
> + };
> +
> + reg_1p35v_vcoredig_s5: regulator-1p35v-vcoredig-s5 {
> + compatible = "regulator-fixed";
> + regulator-name = "V_1V35_VCOREDIG_S5";
> + regulator-min-microvolt = <1350000>;
> + regulator-max-microvolt = <1350000>;
> + regulator-always-on;
> + regulator-boot-on;
> + vin-supply = <®_3p3v_s5>;
> + };
> +
> + reg_1p8v_s5: regulator-1p8v-s5 {
> + compatible = "regulator-fixed";
> + regulator-name = "V_1V8_S5";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + regulator-boot-on;
> + vin-supply = <®_3p3v_s5>;
> + };
> +
> + reg_3p3v_s0: regulator-3p3v-s0 {
> + compatible = "regulator-fixed";
> + regulator-name = "V_3V3_S0";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + vin-supply = <®_3p3v_s5>;
> + };
> +
> + reg_3p3v_s0: regulator-3p3v-s0 {
> + compatible = "regulator-fixed";
> + regulator-name = "V_3V3_S0";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + vin-supply = <®_3p3v_s5>;
> + };
> +
> + reg_3p3v_s5: regulator-3p3v-s5 {
> + compatible = "regulator-fixed";
> + regulator-name = "V_3V3_S5";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + vin-supply = <®_smarc_suppy>;
> + };
> +
> + reg_smarc_rtc: regulator-smarc-rtc {
> + compatible = "regulator-fixed";
> + regulator-name = "V_IN_RTC_BATT";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + /* Module supply range can be 3.00V ... 5.25V */
> + reg_smarc_suppy: regulator-smarc-supply {
> + compatible = "regulator-fixed";
> + regulator-name = "V_IN_WIDE";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + i2c_intern: i2c-gpio-intern {
> + compatible = "i2c-gpio";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c_gpio_intern>;
> + sda-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + i2c-gpio,delay-us = <2>; /* ~100 kHz */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +};
> +
> +/* CAN0 */
> +&can1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan1>;
> +};
> +
> +/* CAN1 */
> +&can2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan2>;
> +};
> +
> +/* GBE */
> +&fec {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enet>;
> + phy-mode = "rgmii";
> + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
> +};
> +
> +&i2c_intern {
> + pfuze100@08 {
pfuze100: pmic@8
Shawn
> + compatible = "fsl,pfuze100";
> + reg = <0x08>;
> +
> + regulators {
> + reg_v_core_s0: sw1ab {
> + regulator-name = "V_CORE_S0";
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1875000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + reg_vddsoc_s0: sw1c {
> + regulator-name = "V_VDDSOC_S0";
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1875000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + reg_3p15v_s0: sw2 {
> + regulator-name = "V_3V15_S0";
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + /* sw3a/b is used in dual mode, but driver does not
> + * support it. Although, there's no need to control
> + * DDR power - so just leaving dummy entries for sw3a
> + * and sw3b for now.
> + */
> + sw3a {
> + regulator-min-microvolt = <400000>;
> + regulator-max-microvolt = <1975000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + sw3b {
> + regulator-min-microvolt = <400000>;
> + regulator-max-microvolt = <1975000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + reg_1p8v_s0: sw4 {
> + regulator-name = "V_1V8_S0";
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + /* Regulator for USB */
> + reg_5p0v_s0: swbst {
> + regulator-name = "V_5V0_S0";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5150000>;
> + regulator-boot-on;
> + };
> +
> + reg_vsnvs: vsnvs {
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + reg_vrefddr: vrefddr {
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + /*
> + * Per schematics, of all VGEN's, only VGEN5 has some
> + * usage ... but even that - over DNI resistor
> + */
> + vgen1 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1550000>;
> + };
> +
> + vgen2 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1550000>;
> + };
> +
> + vgen3 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + vgen4 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + reg_2p5v_s0: vgen5 {
> + regulator-name = "V_2V5_S0";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + vgen6 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + };
> + };
> + };
> +};
> +
> +/* I2C_PM */
> +&i2c3 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c3>;
> +};
> +
> +&iomuxc {
> + pinctrl_flexcan1: flexcan1grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
> + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
> + >;
> + };
> +
> + pinctrl_flexcan2: flexcan2grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
> + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
> + >;
> + };
> +
> + pinctrl_enet: enetgrp {
> + fsl,pins = <
> + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
> + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
> + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
> + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
> + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
> + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
> + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
> + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
> + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
> + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
> + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
> + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
> +
> + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
> + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
> + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
> + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* RST_GBE0_PHY# */
> + >;
> + };
> +
> + pinctrl_i2c_gpio_intern: i2c-gpiointerngrp {
> + fsl,pins = <
> + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* SCL */
> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* SDA */
> + >;
> + };
> +
> + pinctrl_i2c3: i2c3grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
> + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_pcie: pciegrp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 /* PCI_A_PRSNT# */
> + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 /* RST_PCIE_A# */
> + MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 /* PCIE_WAKE# */
> + >;
> + };
> +
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
> + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
> + MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1
> + MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart2: uart2grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
> + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart4: uart4grp {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
> + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
> + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
> + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart5: uart5grp {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
> + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
> + >;
> + };
> +
> + pinctrl_usbotg: usbotggrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1f8b0
> + /* power, oc muxed but not used by the driver */
> + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 /* USB power */
> + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 /* USB OC */
> + >;
> + };
> +
> + pinctrl_usdhc4: usdhc4grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059
> + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
> + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
> + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
> + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
> + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
> + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
> + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
> + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
> + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
> + >;
> + };
> +};
> +
> +&pcie {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pcie>;
> + wake-up-gpio = <&gpio6 18 GPIO_ACTIVE_HIGH>;
> + reset-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>;
> +};
> +
> +/* SER0 */
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + uart-has-rtscts;
> +};
> +
> +/* SER1 */
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart2>;
> +};
> +
> +/* SER2 */
> +&uart4 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart4>;
> + uart-has-rtscts;
> +};
> +
> +/* SER3 */
> +&uart5 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart5>;
> +};
> +
> +/* USB0 */
> +&usbotg {
> + /*
> + * no 'imx6-usb-charger-detection'
> + * since USB_OTG_CHD_B pin is not wired
> + */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usbotg>;
> +};
> +
> +/* USB1/2 via hub */
> +&usbh1 {
> + vbus-supply = <®_5p0v_s0>;
> +};
> +
> +/* SDMMC */
> +&usdhc4 {
> + /* Internal eMMC, optional on some boards */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc4>;
> + bus-width = <8>;
> + no-1-8-v;
> + non-removable;
> +};
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 03/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC SPI0 interface
2019-05-09 15:58 [PATCH 00/17] Add Support for Kontron SMARC-sAMX6i Marco Felsch
2019-05-09 15:58 ` [PATCH 01/17] dt-bindings: add Kontron vendor prefix Marco Felsch
2019-05-09 15:58 ` [PATCH 02/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: Add iMX6-based Kontron SMARC-sAMX6i module Marco Felsch
@ 2019-05-09 15:58 ` Marco Felsch
2019-05-09 15:58 ` [PATCH 04/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC SDIO interface Marco Felsch
` (15 subsequent siblings)
18 siblings, 0 replies; 32+ messages in thread
From: Marco Felsch @ 2019-05-09 15:58 UTC (permalink / raw)
To: robh+dt, shawnguo, linux-imx
Cc: Stefan.Nickl, Gilles.Buloz, Michael.Brunner, thomas.schaefer,
frieder.schrempf, kernel, devicetree, Michael Grzeschik
From: Michael Grzeschik <m.grzeschik@pengutronix.de>
Add support according the SMARC Spec 1.1 [1] and provided schematics.
Due to the lack of hardware the interface can't be tested right now.
[1] https://sget.org/standards/smarc
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi | 21 +++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
index e546d46365f5..a92f6e31fd71 100644
--- a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
@@ -113,6 +113,14 @@
pinctrl-0 = <&pinctrl_flexcan2>;
};
+/* SPI0 */
+&ecspi4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi4>;
+ cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>,
+ <&gpio3 29 GPIO_ACTIVE_HIGH>;
+};
+
/* GBE */
&fec {
pinctrl-names = "default";
@@ -244,6 +252,19 @@
};
&iomuxc {
+ pinctrl_ecspi4: ecspi4grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
+ MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
+
+ /* SPI_IMX_CS2# - connected to internal flash */
+ MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0
+ /* SPI_IMX_CS0# - connected to SMARC SPI0_CS0# */
+ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
+ >;
+ };
+
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 04/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC SDIO interface
2019-05-09 15:58 [PATCH 00/17] Add Support for Kontron SMARC-sAMX6i Marco Felsch
` (2 preceding siblings ...)
2019-05-09 15:58 ` [PATCH 03/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC SPI0 interface Marco Felsch
@ 2019-05-09 15:58 ` Marco Felsch
2019-05-09 15:58 ` [PATCH 05/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC LCD interface Marco Felsch
` (14 subsequent siblings)
18 siblings, 0 replies; 32+ messages in thread
From: Marco Felsch @ 2019-05-09 15:58 UTC (permalink / raw)
To: robh+dt, shawnguo, linux-imx
Cc: Stefan.Nickl, Gilles.Buloz, Michael.Brunner, thomas.schaefer,
frieder.schrempf, kernel, devicetree
Add support according the SMARC Spec 1.1 [1] and provided schematics.
Due to the lack of hardware the interface can't be tested right now.
[1] https://sget.org/standards/smarc
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
index a92f6e31fd71..b96684ff92e8 100644
--- a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
@@ -364,6 +364,21 @@
>;
};
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x17059
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+
+ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 /* CD */
+ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 /* WP */
+ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PWR_EN */
+ >;
+ };
+
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059
@@ -428,6 +443,15 @@
vbus-supply = <®_5p0v_s0>;
};
+/* SDIO */
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+ no-1-8-v;
+};
+
/* SDMMC */
&usdhc4 {
/* Internal eMMC, optional on some boards */
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 05/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC LCD interface
2019-05-09 15:58 [PATCH 00/17] Add Support for Kontron SMARC-sAMX6i Marco Felsch
` (3 preceding siblings ...)
2019-05-09 15:58 ` [PATCH 04/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC SDIO interface Marco Felsch
@ 2019-05-09 15:58 ` Marco Felsch
2019-05-09 15:58 ` [PATCH 06/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC Management pins Marco Felsch
` (13 subsequent siblings)
18 siblings, 0 replies; 32+ messages in thread
From: Marco Felsch @ 2019-05-09 15:58 UTC (permalink / raw)
To: robh+dt, shawnguo, linux-imx
Cc: Stefan.Nickl, Gilles.Buloz, Michael.Brunner, thomas.schaefer,
frieder.schrempf, kernel, devicetree
Add support according the SMARC Spec 1.1 [1] and provided schematics.
Only the backlight and the i2c was tested due to the lack of hardware.
[1] https://sget.org/standards/smarc
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi | 134 ++++++++++++++++++
1 file changed, 134 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
index b96684ff92e8..577048f96f22 100644
--- a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
@@ -70,6 +70,28 @@
vin-supply = <®_smarc_suppy>;
};
+ reg_smarc_lcdbklt: regulator-smarc-lcdbklt {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcdbklt_en>;
+ regulator-name = "LCD_BKLT_EN";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_smarc_lcdvdd: regulator-smarc-lcdvdd {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcdvdd_en>;
+ regulator-name = "LCD_VDD_EN";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
reg_smarc_rtc: regulator-smarc-rtc {
compatible = "regulator-fixed";
regulator-name = "V_IN_RTC_BATT";
@@ -89,6 +111,41 @@
regulator-boot-on;
};
+ lcd: lcd {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx-parallel-display";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcd>;
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+
+ lcd_in: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lcd_out: endpoint {
+ };
+ };
+ };
+
+ lcd_backlight: lcd-backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm4 0 5000000>;
+ pwm-names = "LCD_BKLT_PWM";
+
+ brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+ default-brightness-level = <4>;
+
+ power-supply = <®_smarc_lcdbklt>;
+ status = "disabled";
+ };
+
i2c_intern: i2c-gpio-intern {
compatible = "i2c-gpio";
pinctrl-names = "default";
@@ -99,6 +156,18 @@
#address-cells = <1>;
#size-cells = <0>;
};
+
+ i2c_lcd: i2c-gpio-lcd {
+ compatible = "i2c-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c_gpio_lcd>;
+ sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>; /* ~100 kHz */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabld";
+ };
};
/* CAN0 */
@@ -308,6 +377,13 @@
>;
};
+ pinctrl_i2c_gpio_lcd: i2c-gpiolcdgrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 /* SCL */
+ MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b0 /* SDA */
+ >;
+ };
+
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
@@ -315,6 +391,52 @@
>;
};
+ pinctrl_lcd: lcdgrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100f1
+ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100f1
+ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100f1
+ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100f1
+ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100f1
+ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100f1
+ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100f1
+ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100f1
+ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100f1
+ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100f1
+ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100f1
+ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100f1
+ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100f1
+ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100f1
+ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100f1
+ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100f1
+ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100f1
+ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100f1
+ MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x100f1
+ MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x100f1
+ MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x100f1
+ MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x100f1
+ MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x100f1
+ MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x100f1
+
+ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f1
+ MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100f1 /* DE */
+ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100f1 /* HSYNC */
+ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100f1 /* VSYNC */
+ >;
+ };
+
+ pinctrl_lcdbklt_en: lcdbkltengrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b1
+ >;
+ };
+
+ pinctrl_lcdvdd_en: lcdvddengrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
+ >;
+ };
+
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 /* PCI_A_PRSNT# */
@@ -323,6 +445,12 @@
>;
};
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
@@ -402,6 +530,12 @@
reset-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>;
};
+/* LCD_BKLT_PWM */
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
+};
+
/* SER0 */
&uart1 {
pinctrl-names = "default";
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 06/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC Management pins
2019-05-09 15:58 [PATCH 00/17] Add Support for Kontron SMARC-sAMX6i Marco Felsch
` (4 preceding siblings ...)
2019-05-09 15:58 ` [PATCH 05/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC LCD interface Marco Felsch
@ 2019-05-09 15:58 ` Marco Felsch
2019-05-09 15:58 ` [PATCH 07/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC GPIO interface Marco Felsch
` (12 subsequent siblings)
18 siblings, 0 replies; 32+ messages in thread
From: Marco Felsch @ 2019-05-09 15:58 UTC (permalink / raw)
To: robh+dt, shawnguo, linux-imx
Cc: Stefan.Nickl, Gilles.Buloz, Michael.Brunner, thomas.schaefer,
frieder.schrempf, kernel, devicetree
Add support according the SMARC Spec 1.1 [1] and provided schematics.
Due to the lack of hardware the interface can't be tested right now.
Kontron don't route all of these pins to the i.MX6, some are routed
to the SoM CPLD.
[1] https://sget.org/standards/smarc
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
index 577048f96f22..7a32767c35f1 100644
--- a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
@@ -321,6 +321,9 @@
};
&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mgmt_gpios>;
+
pinctrl_ecspi4: ecspi4grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
@@ -437,6 +440,20 @@
>;
};
+ pinctrl_mgmt_gpios: mgmt-gpiosgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 /* LID# */
+ MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x1b0b0 /* SLEEP# */
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* CHARGING# */
+ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* CHARGER_PRSNT# */
+ MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0 /* CARRIER_STBY# */
+ MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* BATLOW# */
+ MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0 /* TEST# */
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 /* VDD_IO_SEL_D# */
+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 /* POWER_BTN# */
+ >;
+ };
+
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 /* PCI_A_PRSNT# */
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 07/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC GPIO interface
2019-05-09 15:58 [PATCH 00/17] Add Support for Kontron SMARC-sAMX6i Marco Felsch
` (5 preceding siblings ...)
2019-05-09 15:58 ` [PATCH 06/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC Management pins Marco Felsch
@ 2019-05-09 15:58 ` Marco Felsch
2019-05-09 15:58 ` [PATCH 08/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC HDMI interface Marco Felsch
` (11 subsequent siblings)
18 siblings, 0 replies; 32+ messages in thread
From: Marco Felsch @ 2019-05-09 15:58 UTC (permalink / raw)
To: robh+dt, shawnguo, linux-imx
Cc: Stefan.Nickl, Gilles.Buloz, Michael.Brunner, thomas.schaefer,
frieder.schrempf, kernel, devicetree
Add support according the SMARC Spec 1.1 [1] and provided schematics.
Due to the lack of hardware the interface can't be tested right now.
[1] https://sget.org/standards/smarc
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
index 7a32767c35f1..9b8a1d99d967 100644
--- a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
@@ -322,7 +322,7 @@
&iomuxc {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_mgmt_gpios>;
+ pinctrl-0 = <&pinctrl_mgmt_gpios &pinctrl_gpio>;
pinctrl_ecspi4: ecspi4grp {
fsl,pins = <
@@ -351,6 +351,23 @@
>;
};
+ pinctrl_gpio: gpiogrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b0 /* GPIO0 / CAM0_PWR# */
+ MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b0 /* GPIO1 / CAM1_PWR# */
+ MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b0 /* GPIO2 / CAM0_RST# */
+ MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b0 /* GPIO3 / CAM1_RST# */
+ MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b0 /* GPIO4 / HDA_RST# */
+ MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b0 /* GPIO5 / PWM_OUT */
+ MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b0 /* GPIO6 / TACHIN */
+ MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b0 /* GPIO7 / PCAM_FLD */
+ MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b0 /* GPIO8 / CAN0_ERR# */
+ MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b0 /* GPIO9 / CAN1_ERR# */
+ MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b0 /* GPIO10 */
+ MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b0 /* GPIO11 */
+ >;
+ };
+
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 08/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC HDMI interface
2019-05-09 15:58 [PATCH 00/17] Add Support for Kontron SMARC-sAMX6i Marco Felsch
` (6 preceding siblings ...)
2019-05-09 15:58 ` [PATCH 07/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC GPIO interface Marco Felsch
@ 2019-05-09 15:58 ` Marco Felsch
2019-05-09 15:58 ` [PATCH 09/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC CSI Camera interface Marco Felsch
` (10 subsequent siblings)
18 siblings, 0 replies; 32+ messages in thread
From: Marco Felsch @ 2019-05-09 15:58 UTC (permalink / raw)
To: robh+dt, shawnguo, linux-imx
Cc: Stefan.Nickl, Gilles.Buloz, Michael.Brunner, thomas.schaefer,
frieder.schrempf, kernel, devicetree
Add support according the SMARC Spec 1.1 [1] and provided schematics.
Due to the lack of hardware the interface can't be tested right now.
Since the imx6 HDMI signals are not muxable we only have to add the
dedicated i2c-hdmi signals.
[1] https://sget.org/standards/smarc
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
index 9b8a1d99d967..e0372687d8f4 100644
--- a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
@@ -313,6 +313,13 @@
};
};
+/* HDMI_CTRL */
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+};
+
/* I2C_PM */
&i2c3 {
clock-frequency = <100000>;
@@ -404,6 +411,13 @@
>;
};
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 09/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC CSI Camera interface
2019-05-09 15:58 [PATCH 00/17] Add Support for Kontron SMARC-sAMX6i Marco Felsch
` (7 preceding siblings ...)
2019-05-09 15:58 ` [PATCH 08/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC HDMI interface Marco Felsch
@ 2019-05-09 15:58 ` Marco Felsch
2019-05-09 15:58 ` [PATCH 10/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC I2S interface Marco Felsch
` (9 subsequent siblings)
18 siblings, 0 replies; 32+ messages in thread
From: Marco Felsch @ 2019-05-09 15:58 UTC (permalink / raw)
To: robh+dt, shawnguo, linux-imx
Cc: Stefan.Nickl, Gilles.Buloz, Michael.Brunner, thomas.schaefer,
frieder.schrempf, kernel, devicetree
Add support according the SMARC Spec 1.1 [1] and provided schematics.
As specified in [1] the data lanes are shared to cover the csi and the
parallel case. The case depends on the baseboard so we hide muxing the
data lanes. The csi data lanes are not muxable at all.
[1] https://sget.org/standards/smarc
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi | 30 +++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
index e0372687d8f4..19f97ab26e83 100644
--- a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
@@ -168,6 +168,18 @@
#size-cells = <0>;
status = "disabld";
};
+
+ i2c_cam: i2c-gpio-cam {
+ compatible = "i2c-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c_gpio_cam>;
+ sda-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>; /* ~100 kHz */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabld";
+ };
};
/* CAN0 */
@@ -397,6 +409,13 @@
>;
};
+ pinctrl_i2c_gpio_cam: i2c-gpiocamgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* SCL */
+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* SDA */
+ >;
+ };
+
pinctrl_i2c_gpio_intern: i2c-gpiointerngrp {
fsl,pins = <
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* SCL */
@@ -471,6 +490,12 @@
>;
};
+ pinctrl_mipi_csi: mipi-csigrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x000b0 /* CSI0/1 MCLK */
+ >;
+ };
+
pinctrl_mgmt_gpios: mgmt-gpiosgrp {
fsl,pins = <
MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 /* LID# */
@@ -571,6 +596,11 @@
};
};
+&mipi_csi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mipi_csi>;
+};
+
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 10/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC I2S interface
2019-05-09 15:58 [PATCH 00/17] Add Support for Kontron SMARC-sAMX6i Marco Felsch
` (8 preceding siblings ...)
2019-05-09 15:58 ` [PATCH 09/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC CSI Camera interface Marco Felsch
@ 2019-05-09 15:58 ` Marco Felsch
2019-05-09 15:58 ` [PATCH 11/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC SPI1 interface Marco Felsch
` (8 subsequent siblings)
18 siblings, 0 replies; 32+ messages in thread
From: Marco Felsch @ 2019-05-09 15:58 UTC (permalink / raw)
To: robh+dt, shawnguo, linux-imx
Cc: Stefan.Nickl, Gilles.Buloz, Michael.Brunner, thomas.schaefer,
frieder.schrempf, kernel, devicetree
Add support according the SMARC Spec 1.1 [1] and provided schematics.
Due to the lack of hardware the interface can't be tested right now.
[1] https://sget.org/standards/smarc
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi | 78 +++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
index 19f97ab26e83..864e05b14b6f 100644
--- a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
@@ -8,6 +8,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/sound/fsl-imx-audmux.h>
/ {
reg_1p0v_s0: regulator-1p0v-s0 {
@@ -182,6 +183,52 @@
};
};
+/* I2S0, I2S1 */
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux>;
+
+ audmux_ssi1 {
+ fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>;
+ fsl,port-config = <
+ (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT3) |
+ IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT3) |
+ IMX_AUDMUX_V2_PTCR_SYN |
+ IMX_AUDMUX_V2_PTCR_TFSDIR |
+ IMX_AUDMUX_V2_PTCR_TCLKDIR)
+ IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT3)
+ >;
+ };
+
+ audmux_adu3 {
+ fsl,audmux-port = <MX51_AUDMUX_PORT3>;
+ fsl,port-config = <
+ IMX_AUDMUX_V2_PTCR_SYN
+ IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0)
+ >;
+ };
+
+ audmux_ssi2 {
+ fsl,audmux-port = <MX51_AUDMUX_PORT2_SSI1>;
+ fsl,port-config = <
+ (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) |
+ IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) |
+ IMX_AUDMUX_V2_PTCR_SYN |
+ IMX_AUDMUX_V2_PTCR_TFSDIR |
+ IMX_AUDMUX_V2_PTCR_TCLKDIR)
+ IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4)
+ >;
+ };
+
+ audmux_adu4 {
+ fsl,audmux-port = <MX51_AUDMUX_PORT4>;
+ fsl,port-config = <
+ IMX_AUDMUX_V2_PTCR_SYN
+ IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT2_SSI1)
+ >;
+ };
+};
+
/* CAN0 */
&can1 {
pinctrl-names = "default";
@@ -325,6 +372,13 @@
};
};
+/* I2C_GP */
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+};
+
/* HDMI_CTRL */
&i2c2 {
clock-frequency = <100000>;
@@ -343,6 +397,23 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mgmt_gpios &pinctrl_gpio>;
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
+ MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130b0
+ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
+ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
+
+ MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
+ MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
+ MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
+ MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
+
+ /* AUDIO MCLK */
+ MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x000b0
+ >;
+ };
+
pinctrl_ecspi4: ecspi4grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
@@ -430,6 +501,13 @@
>;
};
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 11/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC SPI1 interface
2019-05-09 15:58 [PATCH 00/17] Add Support for Kontron SMARC-sAMX6i Marco Felsch
` (9 preceding siblings ...)
2019-05-09 15:58 ` [PATCH 10/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC I2S interface Marco Felsch
@ 2019-05-09 15:58 ` Marco Felsch
2019-05-16 11:43 ` Fabio Estevam
2019-05-16 11:43 ` Fabio Estevam
2019-05-09 15:58 ` [PATCH 12/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC Watchdog Marco Felsch
` (7 subsequent siblings)
18 siblings, 2 replies; 32+ messages in thread
From: Marco Felsch @ 2019-05-09 15:58 UTC (permalink / raw)
To: robh+dt, shawnguo, linux-imx
Cc: Stefan.Nickl, Gilles.Buloz, Michael.Brunner, thomas.schaefer,
frieder.schrempf, kernel, devicetree
Add support according the SMARC Spec 1.1 [1] and provided schematics.
Due to the lack of hardware the interface can't be tested right now.
[1] https://sget.org/standards/smarc
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
index 864e05b14b6f..1b2764a9ba7f 100644
--- a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
@@ -241,6 +241,14 @@
pinctrl-0 = <&pinctrl_flexcan2>;
};
+/* SPI1 */
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ fsl,spi-num-chipselects = <2>;
+ cs-gpios = <&gpio2 26 0>, <&gpio2 27 0>;
+};
+
/* SPI0 */
&ecspi4 {
pinctrl-names = "default";
@@ -414,6 +422,17 @@
>;
};
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
+ MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
+ MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
+
+ MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0 /* CS0 */
+ MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 /* CS1 */
+ >;
+ };
+
pinctrl_ecspi4: ecspi4grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH 11/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC SPI1 interface
2019-05-09 15:58 ` [PATCH 11/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC SPI1 interface Marco Felsch
@ 2019-05-16 11:43 ` Fabio Estevam
2019-05-16 11:43 ` Fabio Estevam
1 sibling, 0 replies; 32+ messages in thread
From: Fabio Estevam @ 2019-05-16 11:43 UTC (permalink / raw)
To: Marco Felsch
Cc: Rob Herring, Shawn Guo, NXP Linux Team, Stefan.Nickl,
Gilles.Buloz, Michael.Brunner, thomas.schaefer, frieder.schrempf,
Sascha Hauer,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
On Thu, May 9, 2019 at 12:59 PM Marco Felsch <m.felsch@pengutronix.de> wrote:
> +/* SPI1 */
> +&ecspi2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ecspi2>;
> + fsl,spi-num-chipselects = <2>;
This is a deprecated property and can be removed.
Please check Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt
> + cs-gpios = <&gpio2 26 0>, <&gpio2 27 0>;
Please use the GPIO_ACTIVE_HIGH macros for specifying the GPIO polarity.
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 11/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC SPI1 interface
2019-05-09 15:58 ` [PATCH 11/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC SPI1 interface Marco Felsch
2019-05-16 11:43 ` Fabio Estevam
@ 2019-05-16 11:43 ` Fabio Estevam
2019-05-16 15:47 ` Marco Felsch
1 sibling, 1 reply; 32+ messages in thread
From: Fabio Estevam @ 2019-05-16 11:43 UTC (permalink / raw)
To: Marco Felsch
Cc: Rob Herring, Shawn Guo, NXP Linux Team, Stefan.Nickl,
Gilles.Buloz, Michael.Brunner, thomas.schaefer, frieder.schrempf,
Sascha Hauer,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
On Thu, May 9, 2019 at 12:59 PM Marco Felsch <m.felsch@pengutronix.de> wrote:
> +/* SPI1 */
> +&ecspi2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ecspi2>;
> + fsl,spi-num-chipselects = <2>;
> + cs-gpios = <&gpio2 26 0>, <&gpio2 27 0>;
Same comment as in the other patch.
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 11/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC SPI1 interface
2019-05-16 11:43 ` Fabio Estevam
@ 2019-05-16 15:47 ` Marco Felsch
0 siblings, 0 replies; 32+ messages in thread
From: Marco Felsch @ 2019-05-16 15:47 UTC (permalink / raw)
To: Fabio Estevam
Cc: Rob Herring, Shawn Guo, NXP Linux Team, Stefan.Nickl,
Gilles.Buloz, Michael.Brunner, thomas.schaefer, frieder.schrempf,
Sascha Hauer,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
Hi Fabio,
On 19-05-16 08:43, Fabio Estevam wrote:
> On Thu, May 9, 2019 at 12:59 PM Marco Felsch <m.felsch@pengutronix.de> wrote:
>
> > +/* SPI1 */
> > +&ecspi2 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_ecspi2>;
> > + fsl,spi-num-chipselects = <2>;
> > + cs-gpios = <&gpio2 26 0>, <&gpio2 27 0>;
>
> Same comment as in the other patch.
Thanks for covering that.
Regards,
Marco
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 12/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC Watchdog
2019-05-09 15:58 [PATCH 00/17] Add Support for Kontron SMARC-sAMX6i Marco Felsch
` (10 preceding siblings ...)
2019-05-09 15:58 ` [PATCH 11/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC SPI1 interface Marco Felsch
@ 2019-05-09 15:58 ` Marco Felsch
2019-05-09 15:58 ` [PATCH 13/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC module eeprom Marco Felsch
` (6 subsequent siblings)
18 siblings, 0 replies; 32+ messages in thread
From: Marco Felsch @ 2019-05-09 15:58 UTC (permalink / raw)
To: robh+dt, shawnguo, linux-imx
Cc: Stefan.Nickl, Gilles.Buloz, Michael.Brunner, thomas.schaefer,
frieder.schrempf, kernel, devicetree
Add support according the SMARC Spec 1.1 [1] and provided schematics.
Kontron connected the pin to the SoM CPLD too. The CPLD performs after a
30s timeout so we need to enable the watchdog per default.
[1] https://sget.org/standards/smarc
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
index 1b2764a9ba7f..e62f349a351a 100644
--- a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
@@ -691,6 +691,12 @@
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
>;
};
+
+ pinctrl_wdog1: wdog1rp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0
+ >;
+ };
};
&mipi_csi {
@@ -770,3 +776,10 @@
no-1-8-v;
non-removable;
};
+
+&wdog1 {
+ /* CPLD is feeded by watchdog (hardwired) */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog1>;
+ status = "okay";
+};
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 13/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC module eeprom
2019-05-09 15:58 [PATCH 00/17] Add Support for Kontron SMARC-sAMX6i Marco Felsch
` (11 preceding siblings ...)
2019-05-09 15:58 ` [PATCH 12/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC Watchdog Marco Felsch
@ 2019-05-09 15:58 ` Marco Felsch
2019-05-09 15:58 ` [PATCH 14/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add boot spi-nor Marco Felsch
` (5 subsequent siblings)
18 siblings, 0 replies; 32+ messages in thread
From: Marco Felsch @ 2019-05-09 15:58 UTC (permalink / raw)
To: robh+dt, shawnguo, linux-imx
Cc: Stefan.Nickl, Gilles.Buloz, Michael.Brunner, thomas.schaefer,
frieder.schrempf, kernel, devicetree
Add support according the SMARC Spec 1.1 [1] and provided schematics.
[1] https://sget.org/standards/smarc
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
index e62f349a351a..0b45b3062358 100644
--- a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
@@ -399,6 +399,13 @@
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ eeprom_module: eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ pagesize = <32>;
+ };
};
&iomuxc {
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 14/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add boot spi-nor
2019-05-09 15:58 [PATCH 00/17] Add Support for Kontron SMARC-sAMX6i Marco Felsch
` (12 preceding siblings ...)
2019-05-09 15:58 ` [PATCH 13/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC module eeprom Marco Felsch
@ 2019-05-09 15:58 ` Marco Felsch
2019-05-09 15:58 ` [PATCH 15/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add power management support Marco Felsch
` (4 subsequent siblings)
18 siblings, 0 replies; 32+ messages in thread
From: Marco Felsch @ 2019-05-09 15:58 UTC (permalink / raw)
To: robh+dt, shawnguo, linux-imx
Cc: Stefan.Nickl, Gilles.Buloz, Michael.Brunner, thomas.schaefer,
frieder.schrempf, kernel, devicetree, Michael Grzeschik
From: Michael Grzeschik <m.grzeschik@pengutronix.de>
Since Kontron still uses silicon version below 1.3 they have add a
spi-nor to implement Workaround #1 of erratum ERR006282.
Sigend-off-by; Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
index 0b45b3062358..7e60142f09c1 100644
--- a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
@@ -255,6 +255,14 @@
pinctrl-0 = <&pinctrl_ecspi4>;
cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>,
<&gpio3 29 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ /* default boot source: workaround #1 for errata ERR006282 */
+ m25p80@0 {
+ compatible = "winbond,w25q16dw", "jedec,spi-nor";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
};
/* GBE */
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 15/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add power management support
2019-05-09 15:58 [PATCH 00/17] Add Support for Kontron SMARC-sAMX6i Marco Felsch
` (13 preceding siblings ...)
2019-05-09 15:58 ` [PATCH 14/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add boot spi-nor Marco Felsch
@ 2019-05-09 15:58 ` Marco Felsch
2019-05-09 15:58 ` [PATCH 16/17] ARCH: arm: dts: imx6q-kontron-samx6i: add Kontron SMARC Quad/Dual SoM Marco Felsch
` (3 subsequent siblings)
18 siblings, 0 replies; 32+ messages in thread
From: Marco Felsch @ 2019-05-09 15:58 UTC (permalink / raw)
To: robh+dt, shawnguo, linux-imx
Cc: Stefan.Nickl, Gilles.Buloz, Michael.Brunner, thomas.schaefer,
frieder.schrempf, kernel, devicetree
Specify the SoC and ARM vin-supply to enable frequency scaling.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
index 7e60142f09c1..3d1cffcd2d89 100644
--- a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
@@ -732,6 +732,18 @@
pinctrl-0 = <&pinctrl_pwm4>;
};
+®_arm {
+ vin-supply = <®_v_core_s0>;
+};
+
+®_pu {
+ vin-supply = <®_vddsoc_s0>;
+};
+
+®_soc {
+ vin-supply = <®_vddsoc_s0>;
+};
+
/* SER0 */
&uart1 {
pinctrl-names = "default";
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 16/17] ARCH: arm: dts: imx6q-kontron-samx6i: add Kontron SMARC Quad/Dual SoM
2019-05-09 15:58 [PATCH 00/17] Add Support for Kontron SMARC-sAMX6i Marco Felsch
` (14 preceding siblings ...)
2019-05-09 15:58 ` [PATCH 15/17] ARCH: arm: dts: imx6qdl-kontron-samx6i: add power management support Marco Felsch
@ 2019-05-09 15:58 ` Marco Felsch
2019-05-09 15:58 ` [PATCH 17/17] ARCH: arm: dts: imx6dl-kontron-samx6i: add Kontron SMARC Dual-Lite/Solo SoM Marco Felsch
` (2 subsequent siblings)
18 siblings, 0 replies; 32+ messages in thread
From: Marco Felsch @ 2019-05-09 15:58 UTC (permalink / raw)
To: robh+dt, shawnguo, linux-imx
Cc: Stefan.Nickl, Gilles.Buloz, Michael.Brunner, thomas.schaefer,
frieder.schrempf, kernel, devicetree
Add dtsi for iMX6 Quad/Dual based SMARC SoM's from Kontron.
The differences between the quad/dual and the dual-lite/solo are:
* quad/dual has a 2nd IPU
* quad/dual has three chip selects for SMARC SPI0 interface
* quad/dual has a pcie_wake# signal
Only the 3th spi-cs signal is added by this commit.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi | 36 +++++++++++++++++++++
1 file changed, 36 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi
diff --git a/arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi
new file mode 100644
index 000000000000..2618eccfe50d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright 2019 (C) Pengutronix, Marco Felsch <kernel@pengutronix.de>
+ */
+
+#include "imx6q.dtsi"
+#include "imx6qdl-kontron-samx6i.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Kontron SMARC sAMX6i Quad/Dual";
+ compatible = "kontron,imx6q-samx6i", "fsl,imx6q";
+};
+
+/* Quad/Dual SoMs have 3 chip-select signals */
+&ecspi4 {
+ fsl,spi-num-chipselects = <3>;
+ cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>,
+ <&gpio3 29 GPIO_ACTIVE_HIGH>,
+ <&gpio3 25 GPIO_ACTIVE_HIGH>;
+};
+
+&pinctrl_ecspi4 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
+ MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
+
+ /* SPI4_IMX_CS2# - connected to internal flash */
+ MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0
+ /* SPI4_IMX_CS0# - connected to SMARC SPI0_CS0# */
+ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
+ /* SPI4_CS3# - connected to SMARC SPI0_CS1# */
+ MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x1b0b0
+ >;
+};
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH 17/17] ARCH: arm: dts: imx6dl-kontron-samx6i: add Kontron SMARC Dual-Lite/Solo SoM
2019-05-09 15:58 [PATCH 00/17] Add Support for Kontron SMARC-sAMX6i Marco Felsch
` (15 preceding siblings ...)
2019-05-09 15:58 ` [PATCH 16/17] ARCH: arm: dts: imx6q-kontron-samx6i: add Kontron SMARC Quad/Dual SoM Marco Felsch
@ 2019-05-09 15:58 ` Marco Felsch
2019-05-20 1:29 ` [PATCH 00/17] Add Support for Kontron SMARC-sAMX6i Shawn Guo
2019-05-20 2:16 ` Shawn Guo
18 siblings, 0 replies; 32+ messages in thread
From: Marco Felsch @ 2019-05-09 15:58 UTC (permalink / raw)
To: robh+dt, shawnguo, linux-imx
Cc: Stefan.Nickl, Gilles.Buloz, Michael.Brunner, thomas.schaefer,
frieder.schrempf, kernel, devicetree
Add dtsi for iMX6 Dual-Lite/Solo based SMARC SoM's from Kontron.
The differences between the quad/dual and the dual-lite/solo are:
* dual-lite/solo has no 2nd IPU and maps those signals as GPIOs
* dual-lite/solo has only two chip select signals for the SMARC SPI0
interface
* dual-lite/solo has no pcie_wake# signal
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
arch/arm/boot/dts/imx6dl-kontron-samx6i.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6dl-kontron-samx6i.dtsi
diff --git a/arch/arm/boot/dts/imx6dl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6dl-kontron-samx6i.dtsi
new file mode 100644
index 000000000000..a864fdbd5f16
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-kontron-samx6i.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright 2019 (C) Pengutronix, Marco Felsch <kernel@pengutronix.de>
+ */
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-kontron-samx6i.dtsi"
+
+/ {
+ model = "Kontron SMARC sAMX6i Dual-Lite/Solo";
+ compatible = "kontron,imx6dl-samx6i", "fsl,imx6dl";
+};
--
2.20.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH 00/17] Add Support for Kontron SMARC-sAMX6i
2019-05-09 15:58 [PATCH 00/17] Add Support for Kontron SMARC-sAMX6i Marco Felsch
` (16 preceding siblings ...)
2019-05-09 15:58 ` [PATCH 17/17] ARCH: arm: dts: imx6dl-kontron-samx6i: add Kontron SMARC Dual-Lite/Solo SoM Marco Felsch
@ 2019-05-20 1:29 ` Shawn Guo
2019-05-20 2:16 ` Shawn Guo
18 siblings, 0 replies; 32+ messages in thread
From: Shawn Guo @ 2019-05-20 1:29 UTC (permalink / raw)
To: Marco Felsch
Cc: robh+dt, linux-imx, Stefan.Nickl, Gilles.Buloz, Michael.Brunner,
thomas.schaefer, frieder.schrempf, kernel, devicetree
On Thu, May 09, 2019 at 05:58:17PM +0200, Marco Felsch wrote:
> Marco Felsch (14):
> dt-bindings: add Kontron vendor prefix
> ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC SDIO interface
> ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC LCD interface
> ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC Management pins
> ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC GPIO interface
> ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC HDMI interface
> ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC CSI Camera interface
> ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC I2S interface
> ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC SPI1 interface
> ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC Watchdog
> ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC module eeprom
> ARCH: arm: dts: imx6qdl-kontron-samx6i: add power management support
> ARCH: arm: dts: imx6q-kontron-samx6i: add Kontron SMARC Quad/Dual SoM
> ARCH: arm: dts: imx6dl-kontron-samx6i: add Kontron SMARC
> Dual-Lite/Solo SoM
>
> Michael Grzeschik (2):
> ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC SPI0 interface
> ARCH: arm: dts: imx6qdl-kontron-samx6i: add boot spi-nor
>
> Priit Laes (1):
> ARCH: arm: dts: imx6qdl-kontron-samx6i: Add iMX6-based Kontron
> SMARC-sAMX6i module
'ARM: dts: ...' for prefix please.
Shawn
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 00/17] Add Support for Kontron SMARC-sAMX6i
2019-05-09 15:58 [PATCH 00/17] Add Support for Kontron SMARC-sAMX6i Marco Felsch
` (17 preceding siblings ...)
2019-05-20 1:29 ` [PATCH 00/17] Add Support for Kontron SMARC-sAMX6i Shawn Guo
@ 2019-05-20 2:16 ` Shawn Guo
2019-05-21 8:29 ` Marco Felsch
18 siblings, 1 reply; 32+ messages in thread
From: Shawn Guo @ 2019-05-20 2:16 UTC (permalink / raw)
To: Marco Felsch
Cc: robh+dt, linux-imx, Stefan.Nickl, Gilles.Buloz, Michael.Brunner,
thomas.schaefer, frieder.schrempf, kernel, devicetree
On Thu, May 09, 2019 at 05:58:17PM +0200, Marco Felsch wrote:
> Hi,
>
> this series adds the Kontron SoM 'SMARC-sAMX6i' which is compatible to
> the SMARC 1.1 standard [1]. Most of the muxing can be done within the
> SoM dtsi since the standard defines a unique SoM hardware interface.
>
> This series is based on Priit Laes initial commit [2] which adds the
> initial support. I addressed the comments and changed the copyright
> since there where a lot of fixes.
>
> Testers are welcome :) since I used a custome baseboard which doesn't
> use all of the interfaces.
>
> [1] https://sget.org/standards/smarc
> [2] https://lore.kernel.org/patchwork/patch/762261/
>
> Marco Felsch (14):
> dt-bindings: add Kontron vendor prefix
> ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC SDIO interface
> ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC LCD interface
> ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC Management pins
> ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC GPIO interface
> ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC HDMI interface
> ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC CSI Camera interface
> ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC I2S interface
> ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC SPI1 interface
> ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC Watchdog
> ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC module eeprom
> ARCH: arm: dts: imx6qdl-kontron-samx6i: add power management support
> ARCH: arm: dts: imx6q-kontron-samx6i: add Kontron SMARC Quad/Dual SoM
> ARCH: arm: dts: imx6dl-kontron-samx6i: add Kontron SMARC
> Dual-Lite/Solo SoM
>
> Michael Grzeschik (2):
> ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC SPI0 interface
> ARCH: arm: dts: imx6qdl-kontron-samx6i: add boot spi-nor
>
> Priit Laes (1):
> ARCH: arm: dts: imx6qdl-kontron-samx6i: Add iMX6-based Kontron
> SMARC-sAMX6i module
Do we really need so many patches for adding a single board support, or
can we squash some of them?
Shawn
>
> .../devicetree/bindings/vendor-prefixes.txt | 1 +
> arch/arm/boot/dts/imx6dl-kontron-samx6i.dtsi | 12 +
> arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi | 36 +
> arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi | 812 ++++++++++++++++++
> 4 files changed, 861 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6dl-kontron-samx6i.dtsi
> create mode 100644 arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi
> create mode 100644 arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
>
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 00/17] Add Support for Kontron SMARC-sAMX6i
2019-05-20 2:16 ` Shawn Guo
@ 2019-05-21 8:29 ` Marco Felsch
2019-05-21 9:11 ` Shawn Guo
0 siblings, 1 reply; 32+ messages in thread
From: Marco Felsch @ 2019-05-21 8:29 UTC (permalink / raw)
To: Shawn Guo
Cc: robh+dt, linux-imx, Stefan.Nickl, Gilles.Buloz, Michael.Brunner,
thomas.schaefer, frieder.schrempf, kernel, devicetree
Hi Shawn,
On 19-05-20 10:16, Shawn Guo wrote:
> On Thu, May 09, 2019 at 05:58:17PM +0200, Marco Felsch wrote:
> > Hi,
> >
> > this series adds the Kontron SoM 'SMARC-sAMX6i' which is compatible to
> > the SMARC 1.1 standard [1]. Most of the muxing can be done within the
> > SoM dtsi since the standard defines a unique SoM hardware interface.
> >
> > This series is based on Priit Laes initial commit [2] which adds the
> > initial support. I addressed the comments and changed the copyright
> > since there where a lot of fixes.
> >
> > Testers are welcome :) since I used a custome baseboard which doesn't
> > use all of the interfaces.
> >
> > [1] https://sget.org/standards/smarc
> > [2] https://lore.kernel.org/patchwork/patch/762261/
> >
> > Marco Felsch (14):
> > dt-bindings: add Kontron vendor prefix
> > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC SDIO interface
> > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC LCD interface
> > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC Management pins
> > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC GPIO interface
> > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC HDMI interface
> > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC CSI Camera interface
> > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC I2S interface
> > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC SPI1 interface
> > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC Watchdog
> > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC module eeprom
> > ARCH: arm: dts: imx6qdl-kontron-samx6i: add power management support
> > ARCH: arm: dts: imx6q-kontron-samx6i: add Kontron SMARC Quad/Dual SoM
> > ARCH: arm: dts: imx6dl-kontron-samx6i: add Kontron SMARC
> > Dual-Lite/Solo SoM
> >
> > Michael Grzeschik (2):
> > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC SPI0 interface
> > ARCH: arm: dts: imx6qdl-kontron-samx6i: add boot spi-nor
> >
> > Priit Laes (1):
> > ARCH: arm: dts: imx6qdl-kontron-samx6i: Add iMX6-based Kontron
> > SMARC-sAMX6i module
>
> Do we really need so many patches for adding a single board support, or
> can we squash some of them?
I wanted to keep them logical ordered but I can squash them if you want.
Regards,
Marco
> Shawn
>
> >
> > .../devicetree/bindings/vendor-prefixes.txt | 1 +
> > arch/arm/boot/dts/imx6dl-kontron-samx6i.dtsi | 12 +
> > arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi | 36 +
> > arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi | 812 ++++++++++++++++++
> > 4 files changed, 861 insertions(+)
> > create mode 100644 arch/arm/boot/dts/imx6dl-kontron-samx6i.dtsi
> > create mode 100644 arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi
> > create mode 100644 arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
> >
> > --
> > 2.20.1
> >
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 00/17] Add Support for Kontron SMARC-sAMX6i
2019-05-21 8:29 ` Marco Felsch
@ 2019-05-21 9:11 ` Shawn Guo
2019-05-22 10:57 ` Marco Felsch
0 siblings, 1 reply; 32+ messages in thread
From: Shawn Guo @ 2019-05-21 9:11 UTC (permalink / raw)
To: Marco Felsch
Cc: robh+dt, linux-imx, Stefan.Nickl, Gilles.Buloz, Michael.Brunner,
thomas.schaefer, frieder.schrempf, kernel, devicetree
On Tue, May 21, 2019 at 10:29:03AM +0200, Marco Felsch wrote:
> Hi Shawn,
>
> On 19-05-20 10:16, Shawn Guo wrote:
> > On Thu, May 09, 2019 at 05:58:17PM +0200, Marco Felsch wrote:
> > > Hi,
> > >
> > > this series adds the Kontron SoM 'SMARC-sAMX6i' which is compatible to
> > > the SMARC 1.1 standard [1]. Most of the muxing can be done within the
> > > SoM dtsi since the standard defines a unique SoM hardware interface.
> > >
> > > This series is based on Priit Laes initial commit [2] which adds the
> > > initial support. I addressed the comments and changed the copyright
> > > since there where a lot of fixes.
> > >
> > > Testers are welcome :) since I used a custome baseboard which doesn't
> > > use all of the interfaces.
> > >
> > > [1] https://sget.org/standards/smarc
> > > [2] https://lore.kernel.org/patchwork/patch/762261/
> > >
> > > Marco Felsch (14):
> > > dt-bindings: add Kontron vendor prefix
> > > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC SDIO interface
> > > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC LCD interface
> > > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC Management pins
> > > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC GPIO interface
> > > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC HDMI interface
> > > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC CSI Camera interface
> > > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC I2S interface
> > > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC SPI1 interface
> > > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC Watchdog
> > > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC module eeprom
> > > ARCH: arm: dts: imx6qdl-kontron-samx6i: add power management support
> > > ARCH: arm: dts: imx6q-kontron-samx6i: add Kontron SMARC Quad/Dual SoM
> > > ARCH: arm: dts: imx6dl-kontron-samx6i: add Kontron SMARC
> > > Dual-Lite/Solo SoM
> > >
> > > Michael Grzeschik (2):
> > > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC SPI0 interface
> > > ARCH: arm: dts: imx6qdl-kontron-samx6i: add boot spi-nor
> > >
> > > Priit Laes (1):
> > > ARCH: arm: dts: imx6qdl-kontron-samx6i: Add iMX6-based Kontron
> > > SMARC-sAMX6i module
> >
> > Do we really need so many patches for adding a single board support, or
> > can we squash some of them?
>
> I wanted to keep them logical ordered but I can squash them if you want.
Please squash, thanks.
Shawn
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 00/17] Add Support for Kontron SMARC-sAMX6i
2019-05-21 9:11 ` Shawn Guo
@ 2019-05-22 10:57 ` Marco Felsch
2019-05-23 0:24 ` Shawn Guo
0 siblings, 1 reply; 32+ messages in thread
From: Marco Felsch @ 2019-05-22 10:57 UTC (permalink / raw)
To: Shawn Guo
Cc: devicetree, Gilles.Buloz, Michael.Brunner, frieder.schrempf,
thomas.schaefer, robh+dt, Stefan.Nickl, linux-imx, kernel
On 19-05-21 17:11, Shawn Guo wrote:
> On Tue, May 21, 2019 at 10:29:03AM +0200, Marco Felsch wrote:
> > Hi Shawn,
> >
> > On 19-05-20 10:16, Shawn Guo wrote:
> > > On Thu, May 09, 2019 at 05:58:17PM +0200, Marco Felsch wrote:
> > > > Hi,
> > > >
> > > > this series adds the Kontron SoM 'SMARC-sAMX6i' which is compatible to
> > > > the SMARC 1.1 standard [1]. Most of the muxing can be done within the
> > > > SoM dtsi since the standard defines a unique SoM hardware interface.
> > > >
> > > > This series is based on Priit Laes initial commit [2] which adds the
> > > > initial support. I addressed the comments and changed the copyright
> > > > since there where a lot of fixes.
> > > >
> > > > Testers are welcome :) since I used a custome baseboard which doesn't
> > > > use all of the interfaces.
> > > >
> > > > [1] https://sget.org/standards/smarc
> > > > [2] https://lore.kernel.org/patchwork/patch/762261/
> > > >
> > > > Marco Felsch (14):
> > > > dt-bindings: add Kontron vendor prefix
> > > > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC SDIO interface
> > > > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC LCD interface
> > > > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC Management pins
> > > > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC GPIO interface
> > > > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC HDMI interface
> > > > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC CSI Camera interface
> > > > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC I2S interface
> > > > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC SPI1 interface
> > > > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC Watchdog
> > > > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC module eeprom
> > > > ARCH: arm: dts: imx6qdl-kontron-samx6i: add power management support
> > > > ARCH: arm: dts: imx6q-kontron-samx6i: add Kontron SMARC Quad/Dual SoM
> > > > ARCH: arm: dts: imx6dl-kontron-samx6i: add Kontron SMARC
> > > > Dual-Lite/Solo SoM
> > > >
> > > > Michael Grzeschik (2):
> > > > ARCH: arm: dts: imx6qdl-kontron-samx6i: add SMARC SPI0 interface
> > > > ARCH: arm: dts: imx6qdl-kontron-samx6i: add boot spi-nor
> > > >
> > > > Priit Laes (1):
> > > > ARCH: arm: dts: imx6qdl-kontron-samx6i: Add iMX6-based Kontron
> > > > SMARC-sAMX6i module
> > >
> > > Do we really need so many patches for adding a single board support, or
> > > can we squash some of them?
> >
> > I wanted to keep them logical ordered but I can squash them if you want.
>
> Please squash, thanks.
Okay, last question. Should I keep Priit Laes patch seperate and add one
patch above or should I squash all of them?
Regards,
Marco
>
> Shawn
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 00/17] Add Support for Kontron SMARC-sAMX6i
2019-05-22 10:57 ` Marco Felsch
@ 2019-05-23 0:24 ` Shawn Guo
0 siblings, 0 replies; 32+ messages in thread
From: Shawn Guo @ 2019-05-23 0:24 UTC (permalink / raw)
To: Marco Felsch
Cc: devicetree, Gilles.Buloz, Michael.Brunner, frieder.schrempf,
thomas.schaefer, robh+dt, Stefan.Nickl, linux-imx, kernel
On Wed, May 22, 2019 at 12:57:39PM +0200, Marco Felsch wrote:
> Okay, last question. Should I keep Priit Laes patch seperate and add one
> patch above or should I squash all of them?
It's fine to keep Priit's patch as separate.
Shawn
^ permalink raw reply [flat|nested] 32+ messages in thread