From: Manikanta Maddireddy <mmaddireddy@nvidia.com> To: thierry.reding@gmail.com, bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com, jonathanh@nvidia.com, lorenzo.pieralisi@arm.com, vidyas@nvidia.com Cc: linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manikanta Maddireddy <mmaddireddy@nvidia.com> Subject: [PATCH V4 12/28] PCI: tegra: Enable PCIe xclk clock clamping Date: Thu, 16 May 2019 11:22:51 +0530 [thread overview] Message-ID: <20190516055307.25737-13-mmaddireddy@nvidia.com> (raw) In-Reply-To: <20190516055307.25737-1-mmaddireddy@nvidia.com> Enable xclk clock clamping when entering L1. Clamp threshold will determine the time spent waiting for clock module to turn on xclk after signaling it. Default threshold value in Tegra124 and Tegra210 is not enough to turn on xclk clock. Increase the clamp threshold to meet the clock module timing in Tegra124 and Tegra210. Default threshold value is enough in Tegra20, Tegra30 and Tegra186. Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> --- V4: No change V3: No change V2: Took care of typos in commit log and coding style comments. drivers/pci/controller/pci-tegra.c | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index d3da03a10e04..96cd75821872 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -219,8 +219,14 @@ #define RP_VEND_CTL2_PCA_ENABLE (1 << 7) #define RP_PRIV_MISC 0x00000fe0 -#define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xe << 0) -#define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xf << 0) +#define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xe << 0) +#define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xf << 0) +#define RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_MASK (0x7f << 16) +#define RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD (0xf << 16) +#define RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE (1 << 23) +#define RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD_MASK (0x7f << 24) +#define RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD (0xf << 24) +#define RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE (1 << 31) #define RP_LINK_CONTROL_STATUS 0x00000090 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 @@ -298,6 +304,7 @@ struct tegra_pcie_soc { bool has_gen2; bool force_pca_enable; bool program_uphy; + bool update_clamp_threshold; struct { struct { u32 rp_ectl_2_r1; @@ -529,6 +536,7 @@ static void tegra_pcie_port_reset(struct tegra_pcie_port *port) static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port) { + const struct tegra_pcie_soc *soc = port->pcie->soc; u32 value; /* Enable AER capability */ @@ -549,6 +557,19 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port) value = readl(port->base + RP_VEND_XP_BIST); value |= RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE; writel(value, port->base + RP_VEND_XP_BIST); + + value = readl(port->base + RP_PRIV_MISC); + value |= RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE; + value |= RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE; + + if (soc->update_clamp_threshold) { + value &= ~(RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_MASK | + RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD_MASK); + value |= RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD | + RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD; + } + + writel(value, port->base + RP_PRIV_MISC); } static void tegra_pcie_program_ectl_settings(struct tegra_pcie_port *port) @@ -2334,6 +2355,7 @@ static const struct tegra_pcie_soc tegra20_pcie = { .has_gen2 = false, .force_pca_enable = false, .program_uphy = true, + .update_clamp_threshold = false, .ectl.enable = false, }; @@ -2358,6 +2380,7 @@ static const struct tegra_pcie_soc tegra30_pcie = { .has_gen2 = false, .force_pca_enable = false, .program_uphy = true, + .update_clamp_threshold = false, .ectl.enable = false, }; @@ -2375,6 +2398,7 @@ static const struct tegra_pcie_soc tegra124_pcie = { .has_gen2 = true, .force_pca_enable = false, .program_uphy = true, + .update_clamp_threshold = true, .ectl.enable = false, }; @@ -2392,6 +2416,7 @@ static const struct tegra_pcie_soc tegra210_pcie = { .has_gen2 = true, .force_pca_enable = true, .program_uphy = true, + .update_clamp_threshold = true, .ectl = { .regs = { .rp_ectl_2_r1 = 0x0000000f, @@ -2428,6 +2453,7 @@ static const struct tegra_pcie_soc tegra186_pcie = { .has_gen2 = true, .force_pca_enable = false, .program_uphy = false, + .update_clamp_threshold = false, .ectl.enable = false, }; -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Manikanta Maddireddy <mmaddireddy@nvidia.com> To: <thierry.reding@gmail.com>, <bhelgaas@google.com>, <robh+dt@kernel.org>, <mark.rutland@arm.com>, <jonathanh@nvidia.com>, <lorenzo.pieralisi@arm.com>, <vidyas@nvidia.com> Cc: <linux-tegra@vger.kernel.org>, <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>, Manikanta Maddireddy <mmaddireddy@nvidia.com> Subject: [PATCH V4 12/28] PCI: tegra: Enable PCIe xclk clock clamping Date: Thu, 16 May 2019 11:22:51 +0530 [thread overview] Message-ID: <20190516055307.25737-13-mmaddireddy@nvidia.com> (raw) In-Reply-To: <20190516055307.25737-1-mmaddireddy@nvidia.com> Enable xclk clock clamping when entering L1. Clamp threshold will determine the time spent waiting for clock module to turn on xclk after signaling it. Default threshold value in Tegra124 and Tegra210 is not enough to turn on xclk clock. Increase the clamp threshold to meet the clock module timing in Tegra124 and Tegra210. Default threshold value is enough in Tegra20, Tegra30 and Tegra186. Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> --- V4: No change V3: No change V2: Took care of typos in commit log and coding style comments. drivers/pci/controller/pci-tegra.c | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index d3da03a10e04..96cd75821872 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -219,8 +219,14 @@ #define RP_VEND_CTL2_PCA_ENABLE (1 << 7) #define RP_PRIV_MISC 0x00000fe0 -#define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xe << 0) -#define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xf << 0) +#define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xe << 0) +#define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xf << 0) +#define RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_MASK (0x7f << 16) +#define RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD (0xf << 16) +#define RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE (1 << 23) +#define RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD_MASK (0x7f << 24) +#define RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD (0xf << 24) +#define RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE (1 << 31) #define RP_LINK_CONTROL_STATUS 0x00000090 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 @@ -298,6 +304,7 @@ struct tegra_pcie_soc { bool has_gen2; bool force_pca_enable; bool program_uphy; + bool update_clamp_threshold; struct { struct { u32 rp_ectl_2_r1; @@ -529,6 +536,7 @@ static void tegra_pcie_port_reset(struct tegra_pcie_port *port) static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port) { + const struct tegra_pcie_soc *soc = port->pcie->soc; u32 value; /* Enable AER capability */ @@ -549,6 +557,19 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port) value = readl(port->base + RP_VEND_XP_BIST); value |= RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE; writel(value, port->base + RP_VEND_XP_BIST); + + value = readl(port->base + RP_PRIV_MISC); + value |= RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE; + value |= RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE; + + if (soc->update_clamp_threshold) { + value &= ~(RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_MASK | + RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD_MASK); + value |= RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD | + RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD; + } + + writel(value, port->base + RP_PRIV_MISC); } static void tegra_pcie_program_ectl_settings(struct tegra_pcie_port *port) @@ -2334,6 +2355,7 @@ static const struct tegra_pcie_soc tegra20_pcie = { .has_gen2 = false, .force_pca_enable = false, .program_uphy = true, + .update_clamp_threshold = false, .ectl.enable = false, }; @@ -2358,6 +2380,7 @@ static const struct tegra_pcie_soc tegra30_pcie = { .has_gen2 = false, .force_pca_enable = false, .program_uphy = true, + .update_clamp_threshold = false, .ectl.enable = false, }; @@ -2375,6 +2398,7 @@ static const struct tegra_pcie_soc tegra124_pcie = { .has_gen2 = true, .force_pca_enable = false, .program_uphy = true, + .update_clamp_threshold = true, .ectl.enable = false, }; @@ -2392,6 +2416,7 @@ static const struct tegra_pcie_soc tegra210_pcie = { .has_gen2 = true, .force_pca_enable = true, .program_uphy = true, + .update_clamp_threshold = true, .ectl = { .regs = { .rp_ectl_2_r1 = 0x0000000f, @@ -2428,6 +2453,7 @@ static const struct tegra_pcie_soc tegra186_pcie = { .has_gen2 = true, .force_pca_enable = false, .program_uphy = false, + .update_clamp_threshold = false, .ectl.enable = false, }; -- 2.17.1
next prev parent reply other threads:[~2019-05-16 5:52 UTC|newest] Thread overview: 123+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-05-16 5:52 [PATCH V4 00/28] Enable Tegra PCIe root port features Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 01/28] soc/tegra: pmc: Export tegra_powergate_power_on() Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 02/28] PCI: tegra: Handle failure cases in tegra_pcie_power_on() Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 03/28] PCI: tegra: Rearrange Tegra PCIe driver functions Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 04/28] PCI: tegra: Mask AFI_INTR in runtime suspend Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-06-04 13:08 ` Thierry Reding 2019-05-16 5:52 ` [PATCH V4 05/28] PCI: tegra: Fix PCIe host power up sequence Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 06/28] PCI: tegra: Add PCIe Gen2 link speed support Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 07/28] PCI: tegra: Advertise PCIe Advanced Error Reporting (AER) capability Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 08/28] PCI: tegra: Program UPHY electrical settings for Tegra210 Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 09/28] PCI: tegra: Enable opportunistic UpdateFC and ACK Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 10/28] PCI: tegra: Disable AFI dynamic clock gating Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 11/28] PCI: tegra: Process pending DLL transactions before entering L1 or L2 Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy [this message] 2019-05-16 5:52 ` [PATCH V4 12/28] PCI: tegra: Enable PCIe xclk clock clamping Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 13/28] PCI: tegra: Increase the deskew retry time Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 14/28] PCI: tegra: Add SW fixup for RAW violations Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 15/28] PCI: tegra: Update flow control timer frequency in Tegra210 Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 16/28] PCI: tegra: Set target speed as Gen1 before starting LTSSM Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 17/28] PCI: tegra: Fix PLLE power down issue due to CLKREQ# signal Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 18/28] PCI: tegra: Program AFI_CACHE* registers only for Tegra20 Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 19/28] PCI: tegra: Change PRSNT_SENSE IRQ log to debug Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 20/28] PCI: tegra: Use legacy IRQ for port service drivers Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-20 20:37 ` Bjorn Helgaas 2019-05-21 9:07 ` Manikanta Maddireddy 2019-05-21 9:07 ` Manikanta Maddireddy 2019-05-16 5:53 ` [PATCH V4 21/28] PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of soc struct Manikanta Maddireddy 2019-05-16 5:53 ` Manikanta Maddireddy 2019-05-16 5:53 ` [PATCH V4 22/28] PCI: tegra: Access endpoint config only if PCIe link is up Manikanta Maddireddy 2019-05-16 5:53 ` Manikanta Maddireddy 2019-06-04 13:14 ` Thierry Reding 2019-06-04 14:10 ` Manikanta Maddireddy 2019-06-04 14:10 ` Manikanta Maddireddy 2019-06-10 4:38 ` Manikanta Maddireddy 2019-06-10 4:38 ` Manikanta Maddireddy 2019-06-13 14:39 ` Lorenzo Pieralisi 2019-06-13 14:39 ` Lorenzo Pieralisi 2019-06-13 15:42 ` Thierry Reding 2019-06-17 10:01 ` Manikanta Maddireddy 2019-06-17 10:01 ` Manikanta Maddireddy 2019-06-17 11:47 ` Thierry Reding 2019-06-17 19:30 ` Bjorn Helgaas 2019-06-18 5:36 ` Manikanta Maddireddy 2019-06-18 5:36 ` Manikanta Maddireddy 2019-06-18 10:49 ` Thierry Reding 2019-06-18 10:49 ` Thierry Reding 2019-06-18 12:32 ` Johannes Berg 2019-06-18 12:32 ` Johannes Berg 2019-06-18 13:40 ` Thierry Reding 2019-06-18 13:40 ` Thierry Reding 2019-06-18 14:48 ` Johannes Berg 2019-06-18 14:48 ` Johannes Berg 2019-06-19 13:38 ` Bjorn Helgaas 2019-06-19 13:38 ` Bjorn Helgaas 2019-06-19 13:40 ` Johannes Berg 2019-06-19 13:40 ` Johannes Berg 2019-05-16 5:53 ` [PATCH V4 23/28] dt-bindings: pci: tegra: Document PCIe DPD pinctrl optional prop Manikanta Maddireddy 2019-05-16 5:53 ` Manikanta Maddireddy 2019-05-16 5:53 ` [PATCH V4 24/28] arm64: tegra: Add PEX DPD states as pinctrl properties Manikanta Maddireddy 2019-05-16 5:53 ` Manikanta Maddireddy 2019-05-16 5:53 ` [PATCH V4 25/28] PCI: tegra: Put PEX CLK & BIAS pads in DPD mode Manikanta Maddireddy 2019-05-16 5:53 ` Manikanta Maddireddy 2019-05-16 5:53 ` [PATCH V4 26/28] PCI: Add DT binding for "reset-gpios" property Manikanta Maddireddy 2019-05-16 5:53 ` Manikanta Maddireddy 2019-06-17 11:30 ` Thierry Reding 2019-06-17 11:38 ` Manikanta Maddireddy 2019-06-17 11:38 ` Manikanta Maddireddy 2019-06-17 11:48 ` Thierry Reding 2019-05-16 5:53 ` [PATCH V4 27/28] PCI: tegra: Add support for GPIO based PERST# Manikanta Maddireddy 2019-05-16 5:53 ` Manikanta Maddireddy 2019-06-04 13:22 ` Thierry Reding 2019-06-13 15:24 ` Lorenzo Pieralisi 2019-06-14 10:37 ` Manikanta Maddireddy 2019-06-14 10:37 ` Manikanta Maddireddy 2019-06-14 14:32 ` Lorenzo Pieralisi 2019-06-14 14:38 ` Manikanta Maddireddy 2019-06-14 14:38 ` Manikanta Maddireddy 2019-06-14 14:50 ` Lorenzo Pieralisi 2019-06-14 14:56 ` Manikanta Maddireddy 2019-06-14 14:56 ` Manikanta Maddireddy 2019-06-14 15:23 ` Thierry Reding 2019-06-14 15:59 ` Lorenzo Pieralisi 2019-06-14 15:59 ` Lorenzo Pieralisi 2019-06-14 16:30 ` Manikanta Maddireddy 2019-06-14 16:30 ` Manikanta Maddireddy 2019-06-14 16:53 ` Lorenzo Pieralisi 2019-06-14 17:23 ` Manikanta Maddireddy 2019-06-14 17:23 ` Manikanta Maddireddy 2019-06-17 9:48 ` Lorenzo Pieralisi 2019-06-17 10:27 ` Manikanta Maddireddy 2019-06-17 10:27 ` Manikanta Maddireddy 2019-06-17 10:39 ` Lorenzo Pieralisi 2019-06-17 11:29 ` Thierry Reding 2019-06-17 11:26 ` Thierry Reding 2019-05-16 5:53 ` [PATCH V4 28/28] PCI: tegra: Change link retry log level to debug Manikanta Maddireddy 2019-05-16 5:53 ` Manikanta Maddireddy 2019-06-04 13:22 ` Thierry Reding 2019-05-16 13:12 ` [PATCH V4 00/28] Enable Tegra PCIe root port features Bjorn Helgaas 2019-05-17 8:38 ` Manikanta Maddireddy 2019-05-17 8:38 ` Manikanta Maddireddy 2019-06-10 4:45 ` Manikanta Maddireddy 2019-06-10 4:45 ` Manikanta Maddireddy 2019-06-10 17:33 ` Lorenzo Pieralisi
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