From: Manikanta Maddireddy <mmaddireddy@nvidia.com> To: thierry.reding@gmail.com, bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com, jonathanh@nvidia.com, lorenzo.pieralisi@arm.com, vidyas@nvidia.com Cc: linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manikanta Maddireddy <mmaddireddy@nvidia.com> Subject: [PATCH V4 21/28] PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of soc struct Date: Thu, 16 May 2019 11:23:00 +0530 [thread overview] Message-ID: <20190516055307.25737-22-mmaddireddy@nvidia.com> (raw) In-Reply-To: <20190516055307.25737-1-mmaddireddy@nvidia.com> Tegra186 and Tegra30 have three PCIe root ports. AFI_PEX2_CTRL register is defined for third root port. Offset of this register in Tegra186 is different from Tegra30, so add offset as part of soc data structure. Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> --- V4: No change V3: No change V2: No change drivers/pci/controller/pci-tegra.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index 0024bc42b400..d20c88a79e00 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -169,7 +169,6 @@ #define AFI_PEX0_CTRL 0x110 #define AFI_PEX1_CTRL 0x118 -#define AFI_PEX2_CTRL 0x128 #define AFI_PEX_CTRL_RST (1 << 0) #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) #define AFI_PEX_CTRL_REFCLK_EN (1 << 3) @@ -308,6 +307,7 @@ struct tegra_pcie_soc { unsigned int num_ports; const struct tegra_pcie_port_soc *ports; unsigned int msi_base_shift; + unsigned long afi_pex2_ctrl; u32 pads_pll_ctl; u32 tx_ref_sel; u32 pads_refclk_cfg0; @@ -518,6 +518,7 @@ static struct pci_ops tegra_pcie_ops = { static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port) { + const struct tegra_pcie_soc *soc = port->pcie->soc; unsigned long ret = 0; switch (port->index) { @@ -530,7 +531,7 @@ static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port) break; case 2: - ret = AFI_PEX2_CTRL; + ret = soc->afi_pex2_ctrl; break; } @@ -2431,6 +2432,7 @@ static const struct tegra_pcie_soc tegra20_pcie = { .num_ports = 2, .ports = tegra20_pcie_ports, .msi_base_shift = 0, + .afi_pex2_ctrl = 0x128, .pads_pll_ctl = PADS_PLL_CTL_TEGRA20, .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10, .pads_refclk_cfg0 = 0xfa5cfa5c, @@ -2548,6 +2550,7 @@ static const struct tegra_pcie_soc tegra186_pcie = { .num_ports = 3, .ports = tegra186_pcie_ports, .msi_base_shift = 8, + .afi_pex2_ctrl = 0x19c, .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, .pads_refclk_cfg0 = 0x80b880b8, -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Manikanta Maddireddy <mmaddireddy@nvidia.com> To: <thierry.reding@gmail.com>, <bhelgaas@google.com>, <robh+dt@kernel.org>, <mark.rutland@arm.com>, <jonathanh@nvidia.com>, <lorenzo.pieralisi@arm.com>, <vidyas@nvidia.com> Cc: <linux-tegra@vger.kernel.org>, <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>, Manikanta Maddireddy <mmaddireddy@nvidia.com> Subject: [PATCH V4 21/28] PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of soc struct Date: Thu, 16 May 2019 11:23:00 +0530 [thread overview] Message-ID: <20190516055307.25737-22-mmaddireddy@nvidia.com> (raw) In-Reply-To: <20190516055307.25737-1-mmaddireddy@nvidia.com> Tegra186 and Tegra30 have three PCIe root ports. AFI_PEX2_CTRL register is defined for third root port. Offset of this register in Tegra186 is different from Tegra30, so add offset as part of soc data structure. Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> --- V4: No change V3: No change V2: No change drivers/pci/controller/pci-tegra.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index 0024bc42b400..d20c88a79e00 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -169,7 +169,6 @@ #define AFI_PEX0_CTRL 0x110 #define AFI_PEX1_CTRL 0x118 -#define AFI_PEX2_CTRL 0x128 #define AFI_PEX_CTRL_RST (1 << 0) #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) #define AFI_PEX_CTRL_REFCLK_EN (1 << 3) @@ -308,6 +307,7 @@ struct tegra_pcie_soc { unsigned int num_ports; const struct tegra_pcie_port_soc *ports; unsigned int msi_base_shift; + unsigned long afi_pex2_ctrl; u32 pads_pll_ctl; u32 tx_ref_sel; u32 pads_refclk_cfg0; @@ -518,6 +518,7 @@ static struct pci_ops tegra_pcie_ops = { static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port) { + const struct tegra_pcie_soc *soc = port->pcie->soc; unsigned long ret = 0; switch (port->index) { @@ -530,7 +531,7 @@ static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port) break; case 2: - ret = AFI_PEX2_CTRL; + ret = soc->afi_pex2_ctrl; break; } @@ -2431,6 +2432,7 @@ static const struct tegra_pcie_soc tegra20_pcie = { .num_ports = 2, .ports = tegra20_pcie_ports, .msi_base_shift = 0, + .afi_pex2_ctrl = 0x128, .pads_pll_ctl = PADS_PLL_CTL_TEGRA20, .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10, .pads_refclk_cfg0 = 0xfa5cfa5c, @@ -2548,6 +2550,7 @@ static const struct tegra_pcie_soc tegra186_pcie = { .num_ports = 3, .ports = tegra186_pcie_ports, .msi_base_shift = 8, + .afi_pex2_ctrl = 0x19c, .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, .pads_refclk_cfg0 = 0x80b880b8, -- 2.17.1
next prev parent reply other threads:[~2019-05-16 5:53 UTC|newest] Thread overview: 123+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-05-16 5:52 [PATCH V4 00/28] Enable Tegra PCIe root port features Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 01/28] soc/tegra: pmc: Export tegra_powergate_power_on() Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 02/28] PCI: tegra: Handle failure cases in tegra_pcie_power_on() Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 03/28] PCI: tegra: Rearrange Tegra PCIe driver functions Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 04/28] PCI: tegra: Mask AFI_INTR in runtime suspend Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-06-04 13:08 ` Thierry Reding 2019-05-16 5:52 ` [PATCH V4 05/28] PCI: tegra: Fix PCIe host power up sequence Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 06/28] PCI: tegra: Add PCIe Gen2 link speed support Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 07/28] PCI: tegra: Advertise PCIe Advanced Error Reporting (AER) capability Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 08/28] PCI: tegra: Program UPHY electrical settings for Tegra210 Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 09/28] PCI: tegra: Enable opportunistic UpdateFC and ACK Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 10/28] PCI: tegra: Disable AFI dynamic clock gating Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 11/28] PCI: tegra: Process pending DLL transactions before entering L1 or L2 Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 12/28] PCI: tegra: Enable PCIe xclk clock clamping Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 13/28] PCI: tegra: Increase the deskew retry time Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 14/28] PCI: tegra: Add SW fixup for RAW violations Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 15/28] PCI: tegra: Update flow control timer frequency in Tegra210 Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 16/28] PCI: tegra: Set target speed as Gen1 before starting LTSSM Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 17/28] PCI: tegra: Fix PLLE power down issue due to CLKREQ# signal Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 18/28] PCI: tegra: Program AFI_CACHE* registers only for Tegra20 Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 19/28] PCI: tegra: Change PRSNT_SENSE IRQ log to debug Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-16 5:52 ` [PATCH V4 20/28] PCI: tegra: Use legacy IRQ for port service drivers Manikanta Maddireddy 2019-05-16 5:52 ` Manikanta Maddireddy 2019-05-20 20:37 ` Bjorn Helgaas 2019-05-21 9:07 ` Manikanta Maddireddy 2019-05-21 9:07 ` Manikanta Maddireddy 2019-05-16 5:53 ` Manikanta Maddireddy [this message] 2019-05-16 5:53 ` [PATCH V4 21/28] PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of soc struct Manikanta Maddireddy 2019-05-16 5:53 ` [PATCH V4 22/28] PCI: tegra: Access endpoint config only if PCIe link is up Manikanta Maddireddy 2019-05-16 5:53 ` Manikanta Maddireddy 2019-06-04 13:14 ` Thierry Reding 2019-06-04 14:10 ` Manikanta Maddireddy 2019-06-04 14:10 ` Manikanta Maddireddy 2019-06-10 4:38 ` Manikanta Maddireddy 2019-06-10 4:38 ` Manikanta Maddireddy 2019-06-13 14:39 ` Lorenzo Pieralisi 2019-06-13 14:39 ` Lorenzo Pieralisi 2019-06-13 15:42 ` Thierry Reding 2019-06-17 10:01 ` Manikanta Maddireddy 2019-06-17 10:01 ` Manikanta Maddireddy 2019-06-17 11:47 ` Thierry Reding 2019-06-17 19:30 ` Bjorn Helgaas 2019-06-18 5:36 ` Manikanta Maddireddy 2019-06-18 5:36 ` Manikanta Maddireddy 2019-06-18 10:49 ` Thierry Reding 2019-06-18 10:49 ` Thierry Reding 2019-06-18 12:32 ` Johannes Berg 2019-06-18 12:32 ` Johannes Berg 2019-06-18 13:40 ` Thierry Reding 2019-06-18 13:40 ` Thierry Reding 2019-06-18 14:48 ` Johannes Berg 2019-06-18 14:48 ` Johannes Berg 2019-06-19 13:38 ` Bjorn Helgaas 2019-06-19 13:38 ` Bjorn Helgaas 2019-06-19 13:40 ` Johannes Berg 2019-06-19 13:40 ` Johannes Berg 2019-05-16 5:53 ` [PATCH V4 23/28] dt-bindings: pci: tegra: Document PCIe DPD pinctrl optional prop Manikanta Maddireddy 2019-05-16 5:53 ` Manikanta Maddireddy 2019-05-16 5:53 ` [PATCH V4 24/28] arm64: tegra: Add PEX DPD states as pinctrl properties Manikanta Maddireddy 2019-05-16 5:53 ` Manikanta Maddireddy 2019-05-16 5:53 ` [PATCH V4 25/28] PCI: tegra: Put PEX CLK & BIAS pads in DPD mode Manikanta Maddireddy 2019-05-16 5:53 ` Manikanta Maddireddy 2019-05-16 5:53 ` [PATCH V4 26/28] PCI: Add DT binding for "reset-gpios" property Manikanta Maddireddy 2019-05-16 5:53 ` Manikanta Maddireddy 2019-06-17 11:30 ` Thierry Reding 2019-06-17 11:38 ` Manikanta Maddireddy 2019-06-17 11:38 ` Manikanta Maddireddy 2019-06-17 11:48 ` Thierry Reding 2019-05-16 5:53 ` [PATCH V4 27/28] PCI: tegra: Add support for GPIO based PERST# Manikanta Maddireddy 2019-05-16 5:53 ` Manikanta Maddireddy 2019-06-04 13:22 ` Thierry Reding 2019-06-13 15:24 ` Lorenzo Pieralisi 2019-06-14 10:37 ` Manikanta Maddireddy 2019-06-14 10:37 ` Manikanta Maddireddy 2019-06-14 14:32 ` Lorenzo Pieralisi 2019-06-14 14:38 ` Manikanta Maddireddy 2019-06-14 14:38 ` Manikanta Maddireddy 2019-06-14 14:50 ` Lorenzo Pieralisi 2019-06-14 14:56 ` Manikanta Maddireddy 2019-06-14 14:56 ` Manikanta Maddireddy 2019-06-14 15:23 ` Thierry Reding 2019-06-14 15:59 ` Lorenzo Pieralisi 2019-06-14 15:59 ` Lorenzo Pieralisi 2019-06-14 16:30 ` Manikanta Maddireddy 2019-06-14 16:30 ` Manikanta Maddireddy 2019-06-14 16:53 ` Lorenzo Pieralisi 2019-06-14 17:23 ` Manikanta Maddireddy 2019-06-14 17:23 ` Manikanta Maddireddy 2019-06-17 9:48 ` Lorenzo Pieralisi 2019-06-17 10:27 ` Manikanta Maddireddy 2019-06-17 10:27 ` Manikanta Maddireddy 2019-06-17 10:39 ` Lorenzo Pieralisi 2019-06-17 11:29 ` Thierry Reding 2019-06-17 11:26 ` Thierry Reding 2019-05-16 5:53 ` [PATCH V4 28/28] PCI: tegra: Change link retry log level to debug Manikanta Maddireddy 2019-05-16 5:53 ` Manikanta Maddireddy 2019-06-04 13:22 ` Thierry Reding 2019-05-16 13:12 ` [PATCH V4 00/28] Enable Tegra PCIe root port features Bjorn Helgaas 2019-05-17 8:38 ` Manikanta Maddireddy 2019-05-17 8:38 ` Manikanta Maddireddy 2019-06-10 4:45 ` Manikanta Maddireddy 2019-06-10 4:45 ` Manikanta Maddireddy 2019-06-10 17:33 ` Lorenzo Pieralisi
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