* [PATCH v2] clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register
@ 2019-06-04 15:40 ` megous
0 siblings, 0 replies; 10+ messages in thread
From: megous @ 2019-06-04 15:40 UTC (permalink / raw)
To: linux-sunxi
Cc: Ondrej Jirman, Maxime Ripard, Chen-Yu Tsai, Michael Turquette,
Stephen Boyd, moderated list:ARM/Allwinner sunXi SoC support,
open list:COMMON CLK FRAMEWORK, open list
From: Ondrej Jirman <megous@megous.com>
The current code defines W1 clock gate to be at 0x1cc, overlaying it
with the IR gate.
Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
causing interrupt floods on H6 (because interrupt flags can't be cleared,
due to IR module's bus being disabled).
Signed-off-by: Ondrej Jirman <megous@megous.com>
Fixes: b7c7b05065aa77ae ("clk: sunxi-ng: add support for H6 PRCM CCU")
---
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
index 27554eaf6929..8d05d4f1f8a1 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
@@ -104,7 +104,7 @@ static SUNXI_CCU_GATE(r_apb2_i2c_clk, "r-apb2-i2c", "r-apb2",
static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
0x1cc, BIT(0), 0);
static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1",
- 0x1cc, BIT(0), 0);
+ 0x1ec, BIT(0), 0);
/* Information of IR(RX) mod clock is gathered from BSP source code */
static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
--
2.21.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2] clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register
@ 2019-06-04 15:40 ` megous
0 siblings, 0 replies; 10+ messages in thread
From: megous @ 2019-06-04 15:40 UTC (permalink / raw)
To: linux-sunxi
Cc: Ondrej Jirman, Maxime Ripard, Michael Turquette, open list,
Stephen Boyd, Chen-Yu Tsai, open list:COMMON CLK FRAMEWORK,
moderated list:ARM/Allwinner sunXi SoC support
From: Ondrej Jirman <megous@megous.com>
The current code defines W1 clock gate to be at 0x1cc, overlaying it
with the IR gate.
Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
causing interrupt floods on H6 (because interrupt flags can't be cleared,
due to IR module's bus being disabled).
Signed-off-by: Ondrej Jirman <megous@megous.com>
Fixes: b7c7b05065aa77ae ("clk: sunxi-ng: add support for H6 PRCM CCU")
---
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
index 27554eaf6929..8d05d4f1f8a1 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
@@ -104,7 +104,7 @@ static SUNXI_CCU_GATE(r_apb2_i2c_clk, "r-apb2-i2c", "r-apb2",
static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
0x1cc, BIT(0), 0);
static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1",
- 0x1cc, BIT(0), 0);
+ 0x1ec, BIT(0), 0);
/* Information of IR(RX) mod clock is gathered from BSP source code */
static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
--
2.21.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [linux-sunxi] [PATCH v2] clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register
2019-06-04 15:40 ` megous
@ 2019-06-04 16:14 ` Clément Péron
-1 siblings, 0 replies; 10+ messages in thread
From: Clément Péron @ 2019-06-04 16:14 UTC (permalink / raw)
To: megous
Cc: linux-sunxi, Maxime Ripard, Chen-Yu Tsai, Michael Turquette,
Stephen Boyd, moderated list:ARM/Allwinner sunXi SoC support,
open list:COMMON CLK FRAMEWORK, open list
Hi Ondrej,
On Tue, 4 Jun 2019 at 17:40, megous via linux-sunxi
<linux-sunxi@googlegroups.com> wrote:
>
> From: Ondrej Jirman <megous@megous.com>
>
> The current code defines W1 clock gate to be at 0x1cc, overlaying it
> with the IR gate.
>
> Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
> causing interrupt floods on H6 (because interrupt flags can't be cleared,
> due to IR module's bus being disabled).
>
> Signed-off-by: Ondrej Jirman <megous@megous.com>
> Fixes: b7c7b05065aa77ae ("clk: sunxi-ng: add support for H6 PRCM CCU")
> ---
> drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> index 27554eaf6929..8d05d4f1f8a1 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> @@ -104,7 +104,7 @@ static SUNXI_CCU_GATE(r_apb2_i2c_clk, "r-apb2-i2c", "r-apb2",
> static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
> 0x1cc, BIT(0), 0);
> static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1",
> - 0x1cc, BIT(0), 0);
> + 0x1ec, BIT(0), 0);
Just for information where did you find this information?
Using the vendor kernel or user manual?
Thanks,
Clément
>
> /* Information of IR(RX) mod clock is gathered from BSP source code */
> static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
> --
> 2.21.0
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
> To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20190604154036.23211-1-megous%40megous.com.
> For more options, visit https://groups.google.com/d/optout.
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [linux-sunxi] [PATCH v2] clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register
@ 2019-06-04 16:14 ` Clément Péron
0 siblings, 0 replies; 10+ messages in thread
From: Clément Péron @ 2019-06-04 16:14 UTC (permalink / raw)
To: megous
Cc: Maxime Ripard, Michael Turquette, Chen-Yu Tsai, open list,
Stephen Boyd, linux-sunxi, open list:COMMON CLK FRAMEWORK,
moderated list:ARM/Allwinner sunXi SoC support
Hi Ondrej,
On Tue, 4 Jun 2019 at 17:40, megous via linux-sunxi
<linux-sunxi@googlegroups.com> wrote:
>
> From: Ondrej Jirman <megous@megous.com>
>
> The current code defines W1 clock gate to be at 0x1cc, overlaying it
> with the IR gate.
>
> Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
> causing interrupt floods on H6 (because interrupt flags can't be cleared,
> due to IR module's bus being disabled).
>
> Signed-off-by: Ondrej Jirman <megous@megous.com>
> Fixes: b7c7b05065aa77ae ("clk: sunxi-ng: add support for H6 PRCM CCU")
> ---
> drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> index 27554eaf6929..8d05d4f1f8a1 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> @@ -104,7 +104,7 @@ static SUNXI_CCU_GATE(r_apb2_i2c_clk, "r-apb2-i2c", "r-apb2",
> static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
> 0x1cc, BIT(0), 0);
> static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1",
> - 0x1cc, BIT(0), 0);
> + 0x1ec, BIT(0), 0);
Just for information where did you find this information?
Using the vendor kernel or user manual?
Thanks,
Clément
>
> /* Information of IR(RX) mod clock is gathered from BSP source code */
> static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
> --
> 2.21.0
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
> To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20190604154036.23211-1-megous%40megous.com.
> For more options, visit https://groups.google.com/d/optout.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [linux-sunxi] [PATCH v2] clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register
2019-06-04 16:14 ` Clément Péron
@ 2019-06-04 16:21 ` Ondřej Jirman
-1 siblings, 0 replies; 10+ messages in thread
From: Ondřej Jirman @ 2019-06-04 16:21 UTC (permalink / raw)
To: Clément Péron
Cc: linux-sunxi, Maxime Ripard, Chen-Yu Tsai, Michael Turquette,
Stephen Boyd, moderated list:ARM/Allwinner sunXi SoC support,
open list:COMMON CLK FRAMEWORK, open list
Hi Clément,
On Tue, Jun 04, 2019 at 06:14:15PM +0200, Clément Péron wrote:
> Hi Ondrej,
>
> On Tue, 4 Jun 2019 at 17:40, megous via linux-sunxi
> <linux-sunxi@googlegroups.com> wrote:
> >
> > From: Ondrej Jirman <megous@megous.com>
> >
> > The current code defines W1 clock gate to be at 0x1cc, overlaying it
> > with the IR gate.
> >
> > Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
> > causing interrupt floods on H6 (because interrupt flags can't be cleared,
> > due to IR module's bus being disabled).
> >
> > Signed-off-by: Ondrej Jirman <megous@megous.com>
> > Fixes: b7c7b05065aa77ae ("clk: sunxi-ng: add support for H6 PRCM CCU")
> > ---
> > drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> > index 27554eaf6929..8d05d4f1f8a1 100644
> > --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> > @@ -104,7 +104,7 @@ static SUNXI_CCU_GATE(r_apb2_i2c_clk, "r-apb2-i2c", "r-apb2",
> > static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
> > 0x1cc, BIT(0), 0);
> > static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1",
> > - 0x1cc, BIT(0), 0);
> > + 0x1ec, BIT(0), 0);
> Just for information where did you find this information?
> Using the vendor kernel or user manual?
Informed guess. All gates and resets are in the same register. And
you can see below that reset register for w1 is 0x1ec. (reset register
for ir is 0x1cc)
regards,
o.
> Thanks,
> Clément
>
> >
> > /* Information of IR(RX) mod clock is gathered from BSP source code */
> > static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
> > --
> > 2.21.0
> >
> > --
> > You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
> > To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20190604154036.23211-1-megous%40megous.com.
> > For more options, visit https://groups.google.com/d/optout.
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [linux-sunxi] [PATCH v2] clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register
@ 2019-06-04 16:21 ` Ondřej Jirman
0 siblings, 0 replies; 10+ messages in thread
From: Ondřej Jirman @ 2019-06-04 16:21 UTC (permalink / raw)
To: Clément Péron
Cc: Maxime Ripard, Michael Turquette, Chen-Yu Tsai, open list,
Stephen Boyd, linux-sunxi, open list:COMMON CLK FRAMEWORK,
moderated list:ARM/Allwinner sunXi SoC support
Hi Clément,
On Tue, Jun 04, 2019 at 06:14:15PM +0200, Clément Péron wrote:
> Hi Ondrej,
>
> On Tue, 4 Jun 2019 at 17:40, megous via linux-sunxi
> <linux-sunxi@googlegroups.com> wrote:
> >
> > From: Ondrej Jirman <megous@megous.com>
> >
> > The current code defines W1 clock gate to be at 0x1cc, overlaying it
> > with the IR gate.
> >
> > Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
> > causing interrupt floods on H6 (because interrupt flags can't be cleared,
> > due to IR module's bus being disabled).
> >
> > Signed-off-by: Ondrej Jirman <megous@megous.com>
> > Fixes: b7c7b05065aa77ae ("clk: sunxi-ng: add support for H6 PRCM CCU")
> > ---
> > drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> > index 27554eaf6929..8d05d4f1f8a1 100644
> > --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> > @@ -104,7 +104,7 @@ static SUNXI_CCU_GATE(r_apb2_i2c_clk, "r-apb2-i2c", "r-apb2",
> > static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
> > 0x1cc, BIT(0), 0);
> > static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1",
> > - 0x1cc, BIT(0), 0);
> > + 0x1ec, BIT(0), 0);
> Just for information where did you find this information?
> Using the vendor kernel or user manual?
Informed guess. All gates and resets are in the same register. And
you can see below that reset register for w1 is 0x1ec. (reset register
for ir is 0x1cc)
regards,
o.
> Thanks,
> Clément
>
> >
> > /* Information of IR(RX) mod clock is gathered from BSP source code */
> > static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
> > --
> > 2.21.0
> >
> > --
> > You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
> > To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20190604154036.23211-1-megous%40megous.com.
> > For more options, visit https://groups.google.com/d/optout.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [linux-sunxi] [PATCH v2] clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register
2019-06-04 16:21 ` Ondřej Jirman
@ 2019-06-04 16:36 ` Clément Péron
-1 siblings, 0 replies; 10+ messages in thread
From: Clément Péron @ 2019-06-04 16:36 UTC (permalink / raw)
To: Clément Péron, linux-sunxi, Maxime Ripard,
Chen-Yu Tsai, Michael Turquette, Stephen Boyd,
moderated list:ARM/Allwinner sunXi SoC support,
open list:COMMON CLK FRAMEWORK, open list
Hi Ondrej,
On Tue, 4 Jun 2019 at 18:21, Ondřej Jirman <megous@megous.com> wrote:
>
> Hi Clément,
>
> On Tue, Jun 04, 2019 at 06:14:15PM +0200, Clément Péron wrote:
> > Hi Ondrej,
> >
> > On Tue, 4 Jun 2019 at 17:40, megous via linux-sunxi
> > <linux-sunxi@googlegroups.com> wrote:
> > >
> > > From: Ondrej Jirman <megous@megous.com>
> > >
> > > The current code defines W1 clock gate to be at 0x1cc, overlaying it
> > > with the IR gate.
> > >
> > > Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
> > > causing interrupt floods on H6 (because interrupt flags can't be cleared,
> > > due to IR module's bus being disabled).
> > >
> > > Signed-off-by: Ondrej Jirman <megous@megous.com>
> > > Fixes: b7c7b05065aa77ae ("clk: sunxi-ng: add support for H6 PRCM CCU")
> > > ---
> > > drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> > > index 27554eaf6929..8d05d4f1f8a1 100644
> > > --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> > > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> > > @@ -104,7 +104,7 @@ static SUNXI_CCU_GATE(r_apb2_i2c_clk, "r-apb2-i2c", "r-apb2",
> > > static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
> > > 0x1cc, BIT(0), 0);
> > > static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1",
> > > - 0x1cc, BIT(0), 0);
> > > + 0x1ec, BIT(0), 0);
> > Just for information where did you find this information?
> > Using the vendor kernel or user manual?
>
> Informed guess. All gates and resets are in the same register. And
> you can see below that reset register for w1 is 0x1ec. (reset register
> for ir is 0x1cc)
Ok, I thinks this can confirm the value:
https://github.com/orangepi-xunlong/OrangePiH6_Linux4_9/blob/master/drivers/clk/sunxi/clk-sun50iw6.h#L161
Acked-by: Clément Péron <peron.clem@gmail.com>
Regards,
Clément
>
> regards,
> o.
>
> > Thanks,
> > Clément
> >
> > >
> > > /* Information of IR(RX) mod clock is gathered from BSP source code */
> > > static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
> > > --
> > > 2.21.0
> > >
> > > --
> > > You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> > > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
> > > To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20190604154036.23211-1-megous%40megous.com.
> > > For more options, visit https://groups.google.com/d/optout.
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [linux-sunxi] [PATCH v2] clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register
@ 2019-06-04 16:36 ` Clément Péron
0 siblings, 0 replies; 10+ messages in thread
From: Clément Péron @ 2019-06-04 16:36 UTC (permalink / raw)
To: Clément Péron, linux-sunxi, Maxime Ripard,
Chen-Yu Tsai, Michael Turquette, Stephen Boyd,
moderated list:ARM/Allwinner sunXi SoC support,
open list:COMMON CLK FRAMEWORK, open list
Hi Ondrej,
On Tue, 4 Jun 2019 at 18:21, Ondřej Jirman <megous@megous.com> wrote:
>
> Hi Clément,
>
> On Tue, Jun 04, 2019 at 06:14:15PM +0200, Clément Péron wrote:
> > Hi Ondrej,
> >
> > On Tue, 4 Jun 2019 at 17:40, megous via linux-sunxi
> > <linux-sunxi@googlegroups.com> wrote:
> > >
> > > From: Ondrej Jirman <megous@megous.com>
> > >
> > > The current code defines W1 clock gate to be at 0x1cc, overlaying it
> > > with the IR gate.
> > >
> > > Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
> > > causing interrupt floods on H6 (because interrupt flags can't be cleared,
> > > due to IR module's bus being disabled).
> > >
> > > Signed-off-by: Ondrej Jirman <megous@megous.com>
> > > Fixes: b7c7b05065aa77ae ("clk: sunxi-ng: add support for H6 PRCM CCU")
> > > ---
> > > drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> > > index 27554eaf6929..8d05d4f1f8a1 100644
> > > --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> > > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> > > @@ -104,7 +104,7 @@ static SUNXI_CCU_GATE(r_apb2_i2c_clk, "r-apb2-i2c", "r-apb2",
> > > static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
> > > 0x1cc, BIT(0), 0);
> > > static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1",
> > > - 0x1cc, BIT(0), 0);
> > > + 0x1ec, BIT(0), 0);
> > Just for information where did you find this information?
> > Using the vendor kernel or user manual?
>
> Informed guess. All gates and resets are in the same register. And
> you can see below that reset register for w1 is 0x1ec. (reset register
> for ir is 0x1cc)
Ok, I thinks this can confirm the value:
https://github.com/orangepi-xunlong/OrangePiH6_Linux4_9/blob/master/drivers/clk/sunxi/clk-sun50iw6.h#L161
Acked-by: Clément Péron <peron.clem@gmail.com>
Regards,
Clément
>
> regards,
> o.
>
> > Thanks,
> > Clément
> >
> > >
> > > /* Information of IR(RX) mod clock is gathered from BSP source code */
> > > static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
> > > --
> > > 2.21.0
> > >
> > > --
> > > You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> > > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
> > > To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20190604154036.23211-1-megous%40megous.com.
> > > For more options, visit https://groups.google.com/d/optout.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2] clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register
2019-06-04 15:40 ` megous
@ 2019-06-05 11:49 ` Maxime Ripard
-1 siblings, 0 replies; 10+ messages in thread
From: Maxime Ripard @ 2019-06-05 11:49 UTC (permalink / raw)
To: megous
Cc: linux-sunxi, Chen-Yu Tsai, Michael Turquette, Stephen Boyd,
moderated list:ARM/Allwinner sunXi SoC support,
open list:COMMON CLK FRAMEWORK, open list
[-- Attachment #1: Type: text/plain, Size: 633 bytes --]
On Tue, Jun 04, 2019 at 05:40:36PM +0200, megous@megous.com wrote:
> From: Ondrej Jirman <megous@megous.com>
>
> The current code defines W1 clock gate to be at 0x1cc, overlaying it
> with the IR gate.
>
> Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
> causing interrupt floods on H6 (because interrupt flags can't be cleared,
> due to IR module's bus being disabled).
>
> Signed-off-by: Ondrej Jirman <megous@megous.com>
> Fixes: b7c7b05065aa77ae ("clk: sunxi-ng: add support for H6 PRCM CCU")
Applied, thanks
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2] clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register
@ 2019-06-05 11:49 ` Maxime Ripard
0 siblings, 0 replies; 10+ messages in thread
From: Maxime Ripard @ 2019-06-05 11:49 UTC (permalink / raw)
To: megous
Cc: Stephen Boyd, Michael Turquette, Chen-Yu Tsai, open list,
linux-sunxi, open list:COMMON CLK FRAMEWORK,
moderated list:ARM/Allwinner sunXi SoC support
[-- Attachment #1.1: Type: text/plain, Size: 633 bytes --]
On Tue, Jun 04, 2019 at 05:40:36PM +0200, megous@megous.com wrote:
> From: Ondrej Jirman <megous@megous.com>
>
> The current code defines W1 clock gate to be at 0x1cc, overlaying it
> with the IR gate.
>
> Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
> causing interrupt floods on H6 (because interrupt flags can't be cleared,
> due to IR module's bus being disabled).
>
> Signed-off-by: Ondrej Jirman <megous@megous.com>
> Fixes: b7c7b05065aa77ae ("clk: sunxi-ng: add support for H6 PRCM CCU")
Applied, thanks
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2019-06-05 11:50 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-06-04 15:40 [PATCH v2] clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register megous
2019-06-04 15:40 ` megous
2019-06-04 16:14 ` [linux-sunxi] " Clément Péron
2019-06-04 16:14 ` Clément Péron
2019-06-04 16:21 ` Ondřej Jirman
2019-06-04 16:21 ` Ondřej Jirman
2019-06-04 16:36 ` Clément Péron
2019-06-04 16:36 ` Clément Péron
2019-06-05 11:49 ` Maxime Ripard
2019-06-05 11:49 ` Maxime Ripard
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.