From: Will Deacon <will.deacon@arm.com>
To: Marc Gonzalez <marc.w.gonzalez@free.fr>, joro@8bytes.org
Cc: Robin Murphy <robin.murphy@arm.com>,
MSM <linux-arm-msm@vger.kernel.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
iommu <iommu@lists.linux-foundation.org>,
AngeloGioacchino Del Regno <kholk11@gmail.com>,
Jeffrey Hugo <jeffrey.l.hugo@gmail.com>,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>
Subject: Re: [PATCH v3] iommu/arm-smmu: Avoid constant zero in TLBI writes
Date: Wed, 5 Jun 2019 13:19:00 +0100 [thread overview]
Message-ID: <20190605121900.GJ15030@fuggles.cambridge.arm.com> (raw)
In-Reply-To: <09a290f1-27a0-5ee3-16b9-659ef2ba99dc@free.fr>
[+Joerg on To:]
On Mon, Jun 03, 2019 at 02:15:37PM +0200, Marc Gonzalez wrote:
> From: Robin Murphy <robin.murphy@arm.com>
>
> Apparently, some Qualcomm arm64 platforms which appear to expose their
> SMMU global register space are still, in fact, using a hypervisor to
> mediate it by trapping and emulating register accesses. Sadly, some
> deployed versions of said trapping code have bugs wherein they go
> horribly wrong for stores using r31 (i.e. XZR/WZR) as the source
> register.
>
> While this can be mitigated for GCC today by tweaking the constraints
> for the implementation of writel_relaxed(), to avoid any potential
> arms race with future compilers more aggressively optimising register
> allocation, the simple way is to just remove all the problematic
> constant zeros. For the write-only TLB operations, the actual value is
> irrelevant anyway and any old nearby variable will provide a suitable
> GPR to encode. The one point at which we really do need a zero to clear
> a context bank happens before any of the TLB maintenance where crashes
> have been reported, so is apparently not a problem... :/
>
> Reported-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
> Tested-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
Acked-by: Will Deacon <will.deacon@arm.com>
Joerg -- Please can you take this as a fix for 5.2, with a Cc stable?
Cheers,
Will
WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will.deacon@arm.com>
To: Marc Gonzalez <marc.w.gonzalez@free.fr>, joro@8bytes.org
Cc: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>,
MSM <linux-arm-msm@vger.kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
iommu <iommu@lists.linux-foundation.org>,
Andy Gross <agross@kernel.org>,
AngeloGioacchino Del Regno <kholk11@gmail.com>,
Robin Murphy <robin.murphy@arm.com>,
Linux ARM <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v3] iommu/arm-smmu: Avoid constant zero in TLBI writes
Date: Wed, 5 Jun 2019 13:19:00 +0100 [thread overview]
Message-ID: <20190605121900.GJ15030@fuggles.cambridge.arm.com> (raw)
In-Reply-To: <09a290f1-27a0-5ee3-16b9-659ef2ba99dc@free.fr>
[+Joerg on To:]
On Mon, Jun 03, 2019 at 02:15:37PM +0200, Marc Gonzalez wrote:
> From: Robin Murphy <robin.murphy@arm.com>
>
> Apparently, some Qualcomm arm64 platforms which appear to expose their
> SMMU global register space are still, in fact, using a hypervisor to
> mediate it by trapping and emulating register accesses. Sadly, some
> deployed versions of said trapping code have bugs wherein they go
> horribly wrong for stores using r31 (i.e. XZR/WZR) as the source
> register.
>
> While this can be mitigated for GCC today by tweaking the constraints
> for the implementation of writel_relaxed(), to avoid any potential
> arms race with future compilers more aggressively optimising register
> allocation, the simple way is to just remove all the problematic
> constant zeros. For the write-only TLB operations, the actual value is
> irrelevant anyway and any old nearby variable will provide a suitable
> GPR to encode. The one point at which we really do need a zero to clear
> a context bank happens before any of the TLB maintenance where crashes
> have been reported, so is apparently not a problem... :/
>
> Reported-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
> Tested-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
Acked-by: Will Deacon <will.deacon@arm.com>
Joerg -- Please can you take this as a fix for 5.2, with a Cc stable?
Cheers,
Will
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will.deacon@arm.com>
To: Marc Gonzalez <marc.w.gonzalez@free.fr>, joro@8bytes.org
Cc: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>,
MSM <linux-arm-msm@vger.kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
iommu <iommu@lists.linux-foundation.org>,
Andy Gross <agross@kernel.org>,
AngeloGioacchino Del Regno <kholk11@gmail.com>,
Robin Murphy <robin.murphy@arm.com>,
Linux ARM <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v3] iommu/arm-smmu: Avoid constant zero in TLBI writes
Date: Wed, 5 Jun 2019 13:19:00 +0100 [thread overview]
Message-ID: <20190605121900.GJ15030@fuggles.cambridge.arm.com> (raw)
In-Reply-To: <09a290f1-27a0-5ee3-16b9-659ef2ba99dc@free.fr>
[+Joerg on To:]
On Mon, Jun 03, 2019 at 02:15:37PM +0200, Marc Gonzalez wrote:
> From: Robin Murphy <robin.murphy@arm.com>
>
> Apparently, some Qualcomm arm64 platforms which appear to expose their
> SMMU global register space are still, in fact, using a hypervisor to
> mediate it by trapping and emulating register accesses. Sadly, some
> deployed versions of said trapping code have bugs wherein they go
> horribly wrong for stores using r31 (i.e. XZR/WZR) as the source
> register.
>
> While this can be mitigated for GCC today by tweaking the constraints
> for the implementation of writel_relaxed(), to avoid any potential
> arms race with future compilers more aggressively optimising register
> allocation, the simple way is to just remove all the problematic
> constant zeros. For the write-only TLB operations, the actual value is
> irrelevant anyway and any old nearby variable will provide a suitable
> GPR to encode. The one point at which we really do need a zero to clear
> a context bank happens before any of the TLB maintenance where crashes
> have been reported, so is apparently not a problem... :/
>
> Reported-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
> Tested-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
Acked-by: Will Deacon <will.deacon@arm.com>
Joerg -- Please can you take this as a fix for 5.2, with a Cc stable?
Cheers,
Will
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-06-05 12:19 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-29 11:55 [PATCH v2] iommu/arm-smmu: Avoid constant zero in TLBI writes Marc Gonzalez
2019-05-29 11:55 ` Marc Gonzalez
2019-05-29 11:55 ` Marc Gonzalez
2019-05-29 13:05 ` Will Deacon
2019-05-29 13:05 ` Will Deacon
2019-05-29 13:05 ` Will Deacon
2019-05-29 14:31 ` Marc Gonzalez
2019-05-29 14:31 ` Marc Gonzalez
2019-05-29 14:31 ` Marc Gonzalez
2019-06-03 12:15 ` [PATCH v3] " Marc Gonzalez
2019-06-03 12:15 ` Marc Gonzalez
2019-06-03 12:15 ` Marc Gonzalez
2019-06-05 12:19 ` Will Deacon [this message]
2019-06-05 12:19 ` Will Deacon
2019-06-05 12:19 ` Will Deacon
2019-06-07 10:40 ` Marc Gonzalez
2019-06-07 10:40 ` Marc Gonzalez
2019-06-07 10:40 ` Marc Gonzalez
2019-06-12 8:10 ` Joerg Roedel
2019-06-12 8:10 ` Joerg Roedel
2019-06-12 8:10 ` Joerg Roedel
2019-06-14 11:24 ` Marc Gonzalez
2019-06-14 11:24 ` Marc Gonzalez
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