From: Icenowy Zheng <icenowy@aosc.io> To: Rob Herring <robh+dt@kernel.org>, Maxime Ripard <maxime.ripard@bootlin.com>, Chen-Yu Tsai <wens@csie.org>, Linus Walleij <linus.walleij@linaro.org> Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com, Icenowy Zheng <icenowy@aosc.io> Subject: [PATCH v3 9/9] ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3 Date: Sun, 23 Jun 2019 12:38:01 +0800 [thread overview] Message-ID: <20190623043801.14040-10-icenowy@aosc.io> (raw) In-Reply-To: <20190623043801.14040-1-icenowy@aosc.io> Lichee zero plus is a core board made by Sipeed, which includes on-board TF slot or SMT SD NAND, and optional SPI NOR or eMMC, a UART debug header, a microUSB slot and a gold finger connector for expansion. It can use either Sochip S3 or Allwinner S3L SoC. Add the basic device tree for the core board, w/o optional onboard storage, and with S3 SoC. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- Changes in v3: - Drop common regulator DTSI usage and added vcc3v3 regulator. arch/arm/boot/dts/Makefile | 1 + .../boot/dts/sun8i-s3-lichee-zero-plus.dts | 8 ++++ .../dts/sun8i-s3-s3l-lichee-zero-plus.dtsi | 44 +++++++++++++++++++ 3 files changed, 53 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts create mode 100644 arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index c4742afe41a7..d24dec29245e 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1113,6 +1113,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-r16-nintendo-super-nes-classic.dtb \ sun8i-r16-parrot.dtb \ sun8i-r40-bananapi-m2-ultra.dtb \ + sun8i-s3-lichee-zero-plus.dtb \ sun8i-t3-cqa3t-bv3.dtb \ sun8i-v3s-licheepi-zero.dtb \ sun8i-v3s-licheepi-zero-dock.dtb \ diff --git a/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts b/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts new file mode 100644 index 000000000000..7d2f6b145190 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> + */ + +/dts-v1/; +#include "sun8i-s3.dtsi" +#include "sun8i-s3-s3l-lichee-zero-plus.dtsi" diff --git a/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi b/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi new file mode 100644 index 000000000000..e68f738c3046 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> + */ + +#include <dt-bindings/gpio/gpio.h> + +/ { + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + vmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pb_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; -- 2.21.0
WARNING: multiple messages have this Message-ID (diff)
From: Icenowy Zheng <icenowy@aosc.io> To: Rob Herring <robh+dt@kernel.org>, Maxime Ripard <maxime.ripard@bootlin.com>, Chen-Yu Tsai <wens@csie.org>, Linus Walleij <linus.walleij@linaro.org> Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Icenowy Zheng <icenowy@aosc.io> Subject: [PATCH v3 9/9] ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3 Date: Sun, 23 Jun 2019 12:38:01 +0800 [thread overview] Message-ID: <20190623043801.14040-10-icenowy@aosc.io> (raw) In-Reply-To: <20190623043801.14040-1-icenowy@aosc.io> Lichee zero plus is a core board made by Sipeed, which includes on-board TF slot or SMT SD NAND, and optional SPI NOR or eMMC, a UART debug header, a microUSB slot and a gold finger connector for expansion. It can use either Sochip S3 or Allwinner S3L SoC. Add the basic device tree for the core board, w/o optional onboard storage, and with S3 SoC. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- Changes in v3: - Drop common regulator DTSI usage and added vcc3v3 regulator. arch/arm/boot/dts/Makefile | 1 + .../boot/dts/sun8i-s3-lichee-zero-plus.dts | 8 ++++ .../dts/sun8i-s3-s3l-lichee-zero-plus.dtsi | 44 +++++++++++++++++++ 3 files changed, 53 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts create mode 100644 arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index c4742afe41a7..d24dec29245e 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1113,6 +1113,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-r16-nintendo-super-nes-classic.dtb \ sun8i-r16-parrot.dtb \ sun8i-r40-bananapi-m2-ultra.dtb \ + sun8i-s3-lichee-zero-plus.dtb \ sun8i-t3-cqa3t-bv3.dtb \ sun8i-v3s-licheepi-zero.dtb \ sun8i-v3s-licheepi-zero-dock.dtb \ diff --git a/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts b/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts new file mode 100644 index 000000000000..7d2f6b145190 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> + */ + +/dts-v1/; +#include "sun8i-s3.dtsi" +#include "sun8i-s3-s3l-lichee-zero-plus.dtsi" diff --git a/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi b/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi new file mode 100644 index 000000000000..e68f738c3046 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> + */ + +#include <dt-bindings/gpio/gpio.h> + +/ { + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + vmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pb_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; -- 2.21.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-06-23 4:40 UTC|newest] Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-06-23 4:37 [PATCH v3 0/9] Support for Allwinner V3/S3L and Sochip S3 Icenowy Zheng 2019-06-23 4:37 ` Icenowy Zheng 2019-06-23 4:37 ` Icenowy Zheng 2019-06-23 4:37 ` [PATCH v3 1/9] pinctrl: sunxi: v3s: introduce support for V3 Icenowy Zheng 2019-06-23 4:37 ` Icenowy Zheng 2019-06-23 4:37 ` Icenowy Zheng 2019-06-24 12:40 ` Maxime Ripard 2019-06-24 12:40 ` Maxime Ripard 2019-06-24 12:40 ` Maxime Ripard 2019-06-25 13:57 ` Linus Walleij 2019-06-25 13:57 ` Linus Walleij 2019-06-25 13:57 ` Linus Walleij 2019-06-25 14:10 ` Maxime Ripard 2019-06-25 14:10 ` Maxime Ripard 2019-06-25 14:10 ` Maxime Ripard 2019-06-23 4:37 ` [PATCH v3 2/9] clk: sunxi-ng: v3s: add the missing PLL_DDR1 Icenowy Zheng 2019-06-23 4:37 ` Icenowy Zheng 2019-06-23 4:37 ` [PATCH v3 3/9] dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU Icenowy Zheng 2019-06-23 4:37 ` Icenowy Zheng 2019-06-23 4:37 ` Icenowy Zheng 2019-06-23 4:37 ` [PATCH v3 4/9] clk: sunxi-ng: v3s: add Allwinner V3 support Icenowy Zheng 2019-06-23 4:37 ` Icenowy Zheng 2019-06-23 4:37 ` Icenowy Zheng 2019-07-09 22:56 ` Rob Herring 2019-07-09 22:56 ` Rob Herring 2019-06-23 4:37 ` [PATCH v3 5/9] dt-bindings: vendor-prefixes: add SoChip Icenowy Zheng 2019-06-23 4:37 ` Icenowy Zheng 2019-06-25 13:55 ` Linus Walleij 2019-06-25 13:55 ` Linus Walleij 2019-06-25 13:55 ` Linus Walleij 2019-06-25 17:39 ` Rob Herring 2019-06-25 17:39 ` Rob Herring 2019-06-25 17:39 ` Rob Herring 2019-06-23 4:37 ` [PATCH v3 6/9] ARM: sunxi: dts: s3/s3l/v3: add DTSI files for S3/S3L/V3 SoCs Icenowy Zheng 2019-06-23 4:37 ` Icenowy Zheng 2019-06-23 4:37 ` [PATCH v3 7/9] dt-bindings: vendor-prefixes: add Sipeed Icenowy Zheng 2019-06-23 4:37 ` Icenowy Zheng 2019-07-09 22:57 ` Rob Herring 2019-07-09 22:57 ` Rob Herring 2019-07-09 22:57 ` Rob Herring 2019-06-23 4:38 ` [PATCH v3 8/9] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board Icenowy Zheng 2019-06-23 4:38 ` Icenowy Zheng 2019-06-23 4:38 ` Icenowy Zheng 2019-06-24 12:42 ` Maxime Ripard 2019-06-24 12:42 ` Maxime Ripard 2019-06-24 12:42 ` Maxime Ripard 2019-06-23 4:38 ` Icenowy Zheng [this message] 2019-06-23 4:38 ` [PATCH v3 9/9] ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3 Icenowy Zheng 2019-06-24 12:43 ` Maxime Ripard 2019-06-24 12:43 ` Maxime Ripard 2019-06-24 12:43 ` Maxime Ripard 2019-06-24 13:43 ` Icenowy Zheng 2019-06-24 13:43 ` Icenowy Zheng 2019-06-24 13:43 ` Icenowy Zheng 2019-06-24 13:48 ` Maxime Ripard 2019-06-24 13:48 ` Maxime Ripard 2019-06-24 13:48 ` Maxime Ripard
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