From: Maxime Ripard <maxime.ripard@bootlin.com>
To: Icenowy Zheng <icenowy@aosc.io>
Cc: Rob Herring <robh+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Linus Walleij <linus.walleij@linaro.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com
Subject: Re: [PATCH v3 8/9] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board
Date: Mon, 24 Jun 2019 14:42:03 +0200 [thread overview]
Message-ID: <20190624124203.r7vnlt6zzufoarte@flea> (raw)
In-Reply-To: <20190623043801.14040-9-icenowy@aosc.io>
[-- Attachment #1: Type: text/plain, Size: 1496 bytes --]
Hi,
On Sun, Jun 23, 2019 at 12:38:00PM +0800, Icenowy Zheng wrote:
> The Lichee Zero Plus is a core board made by Sipeed, with a microUSB
> connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI Flash.
> It has a gold finger connector for expansion, and UART is available from
> reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or
> Allwinner V3L SoCs.
>
> Add the device tree binding of the basic version of the core board --
> w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> No changes in v3.
>
> Patch introduced in v2.
>
> Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml
> index 000a00d12d6a..48c126a7a848 100644
> --- a/Documentation/devicetree/bindings/arm/sunxi.yaml
> +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
> @@ -353,6 +353,11 @@ properties:
> - const: licheepi,licheepi-zero
> - const: allwinner,sun8i-v3s
>
> + - description: Lichee Zero Plus (with S3, without eMMC/SPI Flash)
> + items:
> + - const: sipeed,lichee-zero-plus
> + - const: allwinner,sun8i-s3
> +
I didn't notice this before, but since this is not a LicheePi, it
should be before it, not after.
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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WARNING: multiple messages have this Message-ID (diff)
From: Maxime Ripard <maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org>
To: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>,
Linus Walleij
<linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org
Subject: Re: [PATCH v3 8/9] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board
Date: Mon, 24 Jun 2019 14:42:03 +0200 [thread overview]
Message-ID: <20190624124203.r7vnlt6zzufoarte@flea> (raw)
In-Reply-To: <20190623043801.14040-9-icenowy-h8G6r0blFSE@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 1516 bytes --]
Hi,
On Sun, Jun 23, 2019 at 12:38:00PM +0800, Icenowy Zheng wrote:
> The Lichee Zero Plus is a core board made by Sipeed, with a microUSB
> connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI Flash.
> It has a gold finger connector for expansion, and UART is available from
> reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or
> Allwinner V3L SoCs.
>
> Add the device tree binding of the basic version of the core board --
> w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC.
>
> Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
> ---
> No changes in v3.
>
> Patch introduced in v2.
>
> Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml
> index 000a00d12d6a..48c126a7a848 100644
> --- a/Documentation/devicetree/bindings/arm/sunxi.yaml
> +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
> @@ -353,6 +353,11 @@ properties:
> - const: licheepi,licheepi-zero
> - const: allwinner,sun8i-v3s
>
> + - description: Lichee Zero Plus (with S3, without eMMC/SPI Flash)
> + items:
> + - const: sipeed,lichee-zero-plus
> + - const: allwinner,sun8i-s3
> +
I didn't notice this before, but since this is not a LicheePi, it
should be before it, not after.
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
WARNING: multiple messages have this Message-ID (diff)
From: Maxime Ripard <maxime.ripard@bootlin.com>
To: Icenowy Zheng <icenowy@aosc.io>
Cc: devicetree@vger.kernel.org,
Linus Walleij <linus.walleij@linaro.org>,
linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org,
linux-gpio@vger.kernel.org, Chen-Yu Tsai <wens@csie.org>,
Rob Herring <robh+dt@kernel.org>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 8/9] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board
Date: Mon, 24 Jun 2019 14:42:03 +0200 [thread overview]
Message-ID: <20190624124203.r7vnlt6zzufoarte@flea> (raw)
In-Reply-To: <20190623043801.14040-9-icenowy@aosc.io>
[-- Attachment #1.1: Type: text/plain, Size: 1496 bytes --]
Hi,
On Sun, Jun 23, 2019 at 12:38:00PM +0800, Icenowy Zheng wrote:
> The Lichee Zero Plus is a core board made by Sipeed, with a microUSB
> connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI Flash.
> It has a gold finger connector for expansion, and UART is available from
> reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or
> Allwinner V3L SoCs.
>
> Add the device tree binding of the basic version of the core board --
> w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> No changes in v3.
>
> Patch introduced in v2.
>
> Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml
> index 000a00d12d6a..48c126a7a848 100644
> --- a/Documentation/devicetree/bindings/arm/sunxi.yaml
> +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
> @@ -353,6 +353,11 @@ properties:
> - const: licheepi,licheepi-zero
> - const: allwinner,sun8i-v3s
>
> + - description: Lichee Zero Plus (with S3, without eMMC/SPI Flash)
> + items:
> + - const: sipeed,lichee-zero-plus
> + - const: allwinner,sun8i-s3
> +
I didn't notice this before, but since this is not a LicheePi, it
should be before it, not after.
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
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next prev parent reply other threads:[~2019-06-24 12:42 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-23 4:37 [PATCH v3 0/9] Support for Allwinner V3/S3L and Sochip S3 Icenowy Zheng
2019-06-23 4:37 ` Icenowy Zheng
2019-06-23 4:37 ` Icenowy Zheng
2019-06-23 4:37 ` [PATCH v3 1/9] pinctrl: sunxi: v3s: introduce support for V3 Icenowy Zheng
2019-06-23 4:37 ` Icenowy Zheng
2019-06-23 4:37 ` Icenowy Zheng
2019-06-24 12:40 ` Maxime Ripard
2019-06-24 12:40 ` Maxime Ripard
2019-06-24 12:40 ` Maxime Ripard
2019-06-25 13:57 ` Linus Walleij
2019-06-25 13:57 ` Linus Walleij
2019-06-25 13:57 ` Linus Walleij
2019-06-25 14:10 ` Maxime Ripard
2019-06-25 14:10 ` Maxime Ripard
2019-06-25 14:10 ` Maxime Ripard
2019-06-23 4:37 ` [PATCH v3 2/9] clk: sunxi-ng: v3s: add the missing PLL_DDR1 Icenowy Zheng
2019-06-23 4:37 ` Icenowy Zheng
2019-06-23 4:37 ` [PATCH v3 3/9] dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU Icenowy Zheng
2019-06-23 4:37 ` Icenowy Zheng
2019-06-23 4:37 ` Icenowy Zheng
2019-06-23 4:37 ` [PATCH v3 4/9] clk: sunxi-ng: v3s: add Allwinner V3 support Icenowy Zheng
2019-06-23 4:37 ` Icenowy Zheng
2019-06-23 4:37 ` Icenowy Zheng
2019-07-09 22:56 ` Rob Herring
2019-07-09 22:56 ` Rob Herring
2019-06-23 4:37 ` [PATCH v3 5/9] dt-bindings: vendor-prefixes: add SoChip Icenowy Zheng
2019-06-23 4:37 ` Icenowy Zheng
2019-06-25 13:55 ` Linus Walleij
2019-06-25 13:55 ` Linus Walleij
2019-06-25 13:55 ` Linus Walleij
2019-06-25 17:39 ` Rob Herring
2019-06-25 17:39 ` Rob Herring
2019-06-25 17:39 ` Rob Herring
2019-06-23 4:37 ` [PATCH v3 6/9] ARM: sunxi: dts: s3/s3l/v3: add DTSI files for S3/S3L/V3 SoCs Icenowy Zheng
2019-06-23 4:37 ` Icenowy Zheng
2019-06-23 4:37 ` [PATCH v3 7/9] dt-bindings: vendor-prefixes: add Sipeed Icenowy Zheng
2019-06-23 4:37 ` Icenowy Zheng
2019-07-09 22:57 ` Rob Herring
2019-07-09 22:57 ` Rob Herring
2019-07-09 22:57 ` Rob Herring
2019-06-23 4:38 ` [PATCH v3 8/9] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board Icenowy Zheng
2019-06-23 4:38 ` Icenowy Zheng
2019-06-23 4:38 ` Icenowy Zheng
2019-06-24 12:42 ` Maxime Ripard [this message]
2019-06-24 12:42 ` Maxime Ripard
2019-06-24 12:42 ` Maxime Ripard
2019-06-23 4:38 ` [PATCH v3 9/9] ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3 Icenowy Zheng
2019-06-23 4:38 ` Icenowy Zheng
2019-06-24 12:43 ` Maxime Ripard
2019-06-24 12:43 ` Maxime Ripard
2019-06-24 12:43 ` Maxime Ripard
2019-06-24 13:43 ` Icenowy Zheng
2019-06-24 13:43 ` Icenowy Zheng
2019-06-24 13:43 ` Icenowy Zheng
2019-06-24 13:48 ` Maxime Ripard
2019-06-24 13:48 ` Maxime Ripard
2019-06-24 13:48 ` Maxime Ripard
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