From: Vandita Kulkarni <vandita.kulkarni@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com
Subject: [PATCH 2/4] drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl
Date: Tue, 2 Jul 2019 09:48:48 +0530 [thread overview]
Message-ID: <20190702041850.4293-3-vandita.kulkarni@intel.com> (raw)
In-Reply-To: <20190702041850.4293-1-vandita.kulkarni@intel.com>
Rest of the latency programming remains same as
that of ICL.
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 556eba2636fe..e3980676bcef 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -404,8 +404,8 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
- /* For EHL set latency optimization for PCS_DW1 lanes */
- if (IS_ELKHARTLAKE(dev_priv)) {
+ /* EHL and TGL, set latency optimization for PCS_DW1 lanes */
+ if (IS_ELKHARTLAKE(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) {
tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port));
tmp &= ~LATENCY_OPTIM_MASK;
tmp |= LATENCY_OPTIM_VAL(0);
--
2.21.0.5.gaeb582a
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next prev parent reply other threads:[~2019-07-02 4:44 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-02 4:18 [PATCH 0/4] Support mipi dsi video mode on TGL Vandita Kulkarni
2019-07-02 4:18 ` [PATCH 1/4] drm/i915/tgl/dsi: Program TRANS_VBLANK register Vandita Kulkarni
2019-07-16 9:58 ` Shankar, Uma
2019-07-30 6:24 ` Kulkarni, Vandita
2019-07-02 4:18 ` Vandita Kulkarni [this message]
2019-07-16 10:12 ` [PATCH 2/4] drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl Shankar, Uma
2019-07-02 4:18 ` [PATCH 3/4] drm/i915/tgl/dsi: Do not override TA_SURE Vandita Kulkarni
2019-07-16 10:16 ` Shankar, Uma
2019-07-02 4:18 ` [PATCH 4/4] drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping Vandita Kulkarni
2019-07-16 10:24 ` Shankar, Uma
2019-07-02 5:21 ` ✓ Fi.CI.BAT: success for Support mipi dsi video mode on TGL Patchwork
2019-07-03 2:02 ` ✓ Fi.CI.IGT: " Patchwork
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