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From: Vandita Kulkarni <vandita.kulkarni@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com
Subject: [PATCH 3/4] drm/i915/tgl/dsi: Do not override TA_SURE
Date: Tue,  2 Jul 2019 09:48:49 +0530	[thread overview]
Message-ID: <20190702041850.4293-4-vandita.kulkarni@intel.com> (raw)
In-Reply-To: <20190702041850.4293-1-vandita.kulkarni@intel.com>

Do not override TA_SURE timing parameter to
zero for DSI 8X frequency 800MHz or below on
TGL.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 26 ++++++++++++++------------
 1 file changed, 14 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index e3980676bcef..d1c50a4186f0 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -530,18 +530,20 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
 	 * a value '0' inside TA_PARAM_REGISTERS otherwise
 	 * leave all fields at HW default values.
 	 */
-	if (intel_dsi_bitrate(intel_dsi) <= 800000) {
-		for_each_dsi_port(port, intel_dsi->ports) {
-			tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
-			tmp &= ~TA_SURE_MASK;
-			tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
-			I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp);
-
-			/* shadow register inside display core */
-			tmp = I915_READ(DSI_TA_TIMING_PARAM(port));
-			tmp &= ~TA_SURE_MASK;
-			tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
-			I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
+	if (IS_GEN(dev_priv, 11)) {
+		if (intel_dsi_bitrate(intel_dsi) <= 800000) {
+			for_each_dsi_port(port, intel_dsi->ports) {
+				tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
+				tmp &= ~TA_SURE_MASK;
+				tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
+				I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp);
+
+				/* shadow register inside display core */
+				tmp = I915_READ(DSI_TA_TIMING_PARAM(port));
+				tmp &= ~TA_SURE_MASK;
+				tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
+				I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
+			}
 		}
 	}
 
-- 
2.21.0.5.gaeb582a

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  parent reply	other threads:[~2019-07-02  4:44 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-02  4:18 [PATCH 0/4] Support mipi dsi video mode on TGL Vandita Kulkarni
2019-07-02  4:18 ` [PATCH 1/4] drm/i915/tgl/dsi: Program TRANS_VBLANK register Vandita Kulkarni
2019-07-16  9:58   ` Shankar, Uma
2019-07-30  6:24     ` Kulkarni, Vandita
2019-07-02  4:18 ` [PATCH 2/4] drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl Vandita Kulkarni
2019-07-16 10:12   ` Shankar, Uma
2019-07-02  4:18 ` Vandita Kulkarni [this message]
2019-07-16 10:16   ` [PATCH 3/4] drm/i915/tgl/dsi: Do not override TA_SURE Shankar, Uma
2019-07-02  4:18 ` [PATCH 4/4] drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping Vandita Kulkarni
2019-07-16 10:24   ` Shankar, Uma
2019-07-02  5:21 ` ✓ Fi.CI.BAT: success for Support mipi dsi video mode on TGL Patchwork
2019-07-03  2:02 ` ✓ Fi.CI.IGT: " Patchwork

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