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From: Vandita Kulkarni <vandita.kulkarni@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com
Subject: [PATCH 4/4] drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping
Date: Tue,  2 Jul 2019 09:48:50 +0530	[thread overview]
Message-ID: <20190702041850.4293-5-vandita.kulkarni@intel.com> (raw)
In-Reply-To: <20190702041850.4293-1-vandita.kulkarni@intel.com>

No need to keep it on till IO enabling.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index d1c50a4186f0..99ce8c708353 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -609,8 +609,12 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
 	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
 
 	for_each_dsi_port(port, intel_dsi->ports) {
-		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+		if (INTEL_GEN(dev_priv) >= 12)
+			val |= DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+		else
+			val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
 	}
+
 	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
 
 	POSTING_READ(DPCLKA_CFGCR0_ICL);
@@ -955,6 +959,8 @@ static void
 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *pipe_config)
 {
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
 	/* step 4a: power up all lanes of the DDI used by DSI */
 	gen11_dsi_power_up_lanes(encoder);
 
@@ -977,7 +983,8 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
 	gen11_dsi_configure_transcoder(encoder, pipe_config);
 
 	/* Step 4l: Gate DDI clocks */
-	gen11_dsi_gate_clocks(encoder);
+	if (IS_GEN(dev_priv, 11))
+		gen11_dsi_gate_clocks(encoder);
 }
 
 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
-- 
2.21.0.5.gaeb582a

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  parent reply	other threads:[~2019-07-02  4:44 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-02  4:18 [PATCH 0/4] Support mipi dsi video mode on TGL Vandita Kulkarni
2019-07-02  4:18 ` [PATCH 1/4] drm/i915/tgl/dsi: Program TRANS_VBLANK register Vandita Kulkarni
2019-07-16  9:58   ` Shankar, Uma
2019-07-30  6:24     ` Kulkarni, Vandita
2019-07-02  4:18 ` [PATCH 2/4] drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl Vandita Kulkarni
2019-07-16 10:12   ` Shankar, Uma
2019-07-02  4:18 ` [PATCH 3/4] drm/i915/tgl/dsi: Do not override TA_SURE Vandita Kulkarni
2019-07-16 10:16   ` Shankar, Uma
2019-07-02  4:18 ` Vandita Kulkarni [this message]
2019-07-16 10:24   ` [PATCH 4/4] drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping Shankar, Uma
2019-07-02  5:21 ` ✓ Fi.CI.BAT: success for Support mipi dsi video mode on TGL Patchwork
2019-07-03  2:02 ` ✓ Fi.CI.IGT: " Patchwork

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