[PATCH 0/4] MCR fixes

[PATCH 0/4] MCR fixes

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

A few bugs in programming the MCR register sneaked in past review.

First of all fls() usage is wrong and suffers from off-by-one problem.

Secondly the assert in WaProgramMgsrForL3BankSpecificMmioReads is also wrong
due inverted logic.

With MCR programming fixed we can stop ignoring the engine workarounds
verification of GEN8_L3SQCREG4.

Tvrtko Ursulin (4):
  drm/i915: Fix GEN8_MCR_SELECTOR programming
  drm/i915: Fix WaProgramMgsrForL3BankSpecificMmioReads
  drm/i915: Move intel_calculate_mcr_s_ss_select to intel_sseu.c
  drm/i915/icl: Verify engine workarounds in GEN8_L3SQCREG4

 drivers/gpu/drm/i915/gt/intel_engine_cs.c   | 19 --------
 drivers/gpu/drm/i915/gt/intel_sseu.c        | 24 ++++++++++
 drivers/gpu/drm/i915/gt/intel_sseu.h        |  2 +
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 53 ++++++++-------------
 drivers/gpu/drm/i915/i915_drv.h             |  2 -
 5 files changed, 45 insertions(+), 55 deletions(-)

-- 
2.20.1

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[PATCH 1/4] drm/i915: Fix GEN8_MCR_SELECTOR programming

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

fls returns bit positions starting from one for the lsb and the MCR
register expects zero based (sub)slice addressing.

Incorrent MCR programming can have the effect of directing MMIO reads of
registers in the 0xb100-0xb3ff range to invalid subslice returning zeroes
instead of actual content.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Fixes: 1e40d4aea57b ("drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads")
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index bdf279fa3b2e..ee15d1934486 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -975,9 +975,14 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
 u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
 {
 	const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
+	unsigned int slice = fls(sseu->slice_mask) - 1;
+	unsigned int subslice;
 	u32 mcr_s_ss_select;
-	u32 slice = fls(sseu->slice_mask);
-	u32 subslice = fls(sseu->subslice_mask[slice]);
+
+	GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
+	subslice = fls(sseu->subslice_mask[slice]);
+	GEM_BUG_ON(!subslice);
+	subslice--;
 
 	if (IS_GEN(dev_priv, 10))
 		mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
-- 
2.20.1

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Re: [PATCH 1/4] drm/i915: Fix GEN8_MCR_SELECTOR programming

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-07-09 22:06:17)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> fls returns bit positions starting from one for the lsb and the MCR
> register expects zero based (sub)slice addressing.
> 
> Incorrent MCR programming can have the effect of directing MMIO reads of
> registers in the 0xb100-0xb3ff range to invalid subslice returning zeroes
> instead of actual content.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Fixes: 1e40d4aea57b ("drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads")

Makes sense to me, just from my meagre understanding of arrays
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

> ---
>  drivers/gpu/drm/i915/gt/intel_engine_cs.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index bdf279fa3b2e..ee15d1934486 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -975,9 +975,14 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
>  u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
>  {
>         const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
> +       unsigned int slice = fls(sseu->slice_mask) - 1;

I'd vote for __fls() here instead of fls() - 1.

> +       unsigned int subslice;
>         u32 mcr_s_ss_select;
> -       u32 slice = fls(sseu->slice_mask);
> -       u32 subslice = fls(sseu->subslice_mask[slice]);
> +
> +       GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
> +       subslice = fls(sseu->subslice_mask[slice]);
> +       GEM_BUG_ON(!subslice);
> +       subslice--;

And I think we're a bit late on the BUG_ON here (it's shouldn't change
after probing) so could be happily reduced to __fls().
-Chris
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Re: [PATCH 1/4] drm/i915: Fix GEN8_MCR_SELECTOR programming

[Tvrtko Ursulin]

On 09/07/2019 22:09, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-07-09 22:06:17)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> fls returns bit positions starting from one for the lsb and the MCR
>> register expects zero based (sub)slice addressing.
>>
>> Incorrent MCR programming can have the effect of directing MMIO reads of
>> registers in the 0xb100-0xb3ff range to invalid subslice returning zeroes
>> instead of actual content.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Fixes: 1e40d4aea57b ("drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads")
> 
> Makes sense to me, just from my meagre understanding of arrays
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> 
>> ---
>>   drivers/gpu/drm/i915/gt/intel_engine_cs.c | 9 +++++++--
>>   1 file changed, 7 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> index bdf279fa3b2e..ee15d1934486 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> @@ -975,9 +975,14 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
>>   u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
>>   {
>>          const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
>> +       unsigned int slice = fls(sseu->slice_mask) - 1;
> 
> I'd vote for __fls() here instead of fls() - 1.

With fls() I get zero slice mask check for free, in the array out of 
bounds check below.

> 
>> +       unsigned int subslice;
>>          u32 mcr_s_ss_select;
>> -       u32 slice = fls(sseu->slice_mask);
>> -       u32 subslice = fls(sseu->subslice_mask[slice]);
>> +
>> +       GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
>> +       subslice = fls(sseu->subslice_mask[slice]);
>> +       GEM_BUG_ON(!subslice);
>> +       subslice--;
> 
> And I think we're a bit late on the BUG_ON here (it's shouldn't change
> after probing) so could be happily reduced to __fls().

Why late? This one is not checking the array for out of bounds, just if 
zero subslice mask happens to be in a valid slot. Too paranoid?

Regards,

Tvrtko


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[PATCH 2/4] drm/i915: Fix WaProgramMgsrForL3BankSpecificMmioReads

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Two issues in this code:

1.
fls() usage is incorrect causing off by one in subslice mask lookup,
which in other words means subslice mask of all zeroes is always used
(subslice mask of a slice which is not present, or even out of bounds
array access), rendering the checks in wa_init_mcr either futile or
random.

2.
Condition in WARN_ON is not correct. It is doing a bitwise and operation
between a positive (present subslices) and negative mask (disabled L3
banks).

This means that with corrected fls() usage the assert would always
incorrectly fail.

We can fix this by invereting the fuse bits in the check.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Fixes: fe864b76c2ab ("drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads")
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 26 ++++++++++-----------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 9e069286d3ce..b5f19ad48d22 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -776,26 +776,26 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
 	 * something more complex that requires checking the range of every
 	 * MMIO read).
 	 */
-	if (INTEL_GEN(i915) >= 10 &&
-	    is_power_of_2(sseu->slice_mask)) {
+	if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
 		/*
-		 * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
-		 * enabled subslice, no need to redirect MCR packet
+		 * Read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
+		 * enabled subslice, no need to redirect MCR packet.
 		 */
-		u32 slice = fls(sseu->slice_mask);
-		u32 fuse3 =
-			intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3);
-		u8 ss_mask = sseu->subslice_mask[slice];
+		unsigned int slice = fls(sseu->slice_mask) - 1;
+		u8 ss, en, dis;
 
-		u8 enabled_mask = (ss_mask | ss_mask >>
-				   GEN10_L3BANK_PAIR_COUNT) & GEN10_L3BANK_MASK;
-		u8 disabled_mask = fuse3 & GEN10_L3BANK_MASK;
+		GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
+		ss = sseu->subslice_mask[slice];
+
+		en = (ss | ss >> GEN10_L3BANK_PAIR_COUNT) & GEN10_L3BANK_MASK;
+		dis = intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3) &
+		      GEN10_L3BANK_MASK;
 
 		/*
 		 * Production silicon should have matched L3Bank and
-		 * subslice enabled
+		 * subslice enabled.
 		 */
-		WARN_ON((enabled_mask & disabled_mask) != enabled_mask);
+		WARN_ON((en & ~dis) != en);
 	}
 
 	if (INTEL_GEN(i915) >= 11)
-- 
2.20.1

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Re: [PATCH 2/4] drm/i915: Fix WaProgramMgsrForL3BankSpecificMmioReads

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-07-09 22:06:18)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Two issues in this code:
> 
> 1.
> fls() usage is incorrect causing off by one in subslice mask lookup,
> which in other words means subslice mask of all zeroes is always used
> (subslice mask of a slice which is not present, or even out of bounds
> array access), rendering the checks in wa_init_mcr either futile or
> random.
> 
> 2.
> Condition in WARN_ON is not correct. It is doing a bitwise and operation
> between a positive (present subslices) and negative mask (disabled L3
> banks).
> 
> This means that with corrected fls() usage the assert would always
> incorrectly fail.
> 
> We can fix this by invereting the fuse bits in the check.

s/invereting/inverting/

> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Fixes: fe864b76c2ab ("drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads")
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 26 ++++++++++-----------
>  1 file changed, 13 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 9e069286d3ce..b5f19ad48d22 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -776,26 +776,26 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
>          * something more complex that requires checking the range of every
>          * MMIO read).
>          */
> -       if (INTEL_GEN(i915) >= 10 &&
> -           is_power_of_2(sseu->slice_mask)) {
> +       if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
>                 /*
> -                * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
> -                * enabled subslice, no need to redirect MCR packet
> +                * Read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
> +                * enabled subslice, no need to redirect MCR packet.
>                  */
> -               u32 slice = fls(sseu->slice_mask);
> -               u32 fuse3 =
> -                       intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3);
> -               u8 ss_mask = sseu->subslice_mask[slice];
> +               unsigned int slice = fls(sseu->slice_mask) - 1;
> +               u8 ss, en, dis;
>  
> -               u8 enabled_mask = (ss_mask | ss_mask >>
> -                                  GEN10_L3BANK_PAIR_COUNT) & GEN10_L3BANK_MASK;
> -               u8 disabled_mask = fuse3 & GEN10_L3BANK_MASK;
> +               GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
> +               ss = sseu->subslice_mask[slice];
> +
> +               en = (ss | ss >> GEN10_L3BANK_PAIR_COUNT) & GEN10_L3BANK_MASK;
> +               dis = intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3) &
> +                     GEN10_L3BANK_MASK;

Ok.

>                 /*
>                  * Production silicon should have matched L3Bank and
> -                * subslice enabled
> +                * subslice enabled.
>                  */
> -               WARN_ON((enabled_mask & disabled_mask) != enabled_mask);
> +               WARN_ON((en & ~dis) != en);

That certainly makes more sense. I always feared that was some deep
magic to reflect the underlying HW.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [PATCH 2/4] drm/i915: Fix WaProgramMgsrForL3BankSpecificMmioReads

[Tvrtko Ursulin]

On 09/07/2019 22:11, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-07-09 22:06:18)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Two issues in this code:
>>
>> 1.
>> fls() usage is incorrect causing off by one in subslice mask lookup,
>> which in other words means subslice mask of all zeroes is always used
>> (subslice mask of a slice which is not present, or even out of bounds
>> array access), rendering the checks in wa_init_mcr either futile or
>> random.
>>
>> 2.
>> Condition in WARN_ON is not correct. It is doing a bitwise and operation
>> between a positive (present subslices) and negative mask (disabled L3
>> banks).
>>
>> This means that with corrected fls() usage the assert would always
>> incorrectly fail.
>>
>> We can fix this by invereting the fuse bits in the check.
> 
> s/invereting/inverting/
> 
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Fixes: fe864b76c2ab ("drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads")
>> ---
>>   drivers/gpu/drm/i915/gt/intel_workarounds.c | 26 ++++++++++-----------
>>   1 file changed, 13 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index 9e069286d3ce..b5f19ad48d22 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -776,26 +776,26 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
>>           * something more complex that requires checking the range of every
>>           * MMIO read).
>>           */
>> -       if (INTEL_GEN(i915) >= 10 &&
>> -           is_power_of_2(sseu->slice_mask)) {
>> +       if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
>>                  /*
>> -                * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
>> -                * enabled subslice, no need to redirect MCR packet
>> +                * Read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
>> +                * enabled subslice, no need to redirect MCR packet.
>>                   */
>> -               u32 slice = fls(sseu->slice_mask);
>> -               u32 fuse3 =
>> -                       intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3);
>> -               u8 ss_mask = sseu->subslice_mask[slice];
>> +               unsigned int slice = fls(sseu->slice_mask) - 1;
>> +               u8 ss, en, dis;
>>   
>> -               u8 enabled_mask = (ss_mask | ss_mask >>
>> -                                  GEN10_L3BANK_PAIR_COUNT) & GEN10_L3BANK_MASK;
>> -               u8 disabled_mask = fuse3 & GEN10_L3BANK_MASK;
>> +               GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
>> +               ss = sseu->subslice_mask[slice];
>> +
>> +               en = (ss | ss >> GEN10_L3BANK_PAIR_COUNT) & GEN10_L3BANK_MASK;
>> +               dis = intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3) &
>> +                     GEN10_L3BANK_MASK;
> 
> Ok.
> 
>>                  /*
>>                   * Production silicon should have matched L3Bank and
>> -                * subslice enabled
>> +                * subslice enabled.
>>                   */
>> -               WARN_ON((enabled_mask & disabled_mask) != enabled_mask);
>> +               WARN_ON((en & ~dis) != en);
> 
> That certainly makes more sense. I always feared that was some deep
> magic to reflect the underlying HW.

It could still be magic and I am not confident to merge this. Well.. 
maybe.. It does fix out of bounds access. But it makes the WARN_ON fire 
on a SKU with subslice mask of 0b1100 1111 and L3 fuse bits of 0xb0100. 
Is that better or worse than a WARN_ON which never fires? :)

According to the docs these l3 fuse bits mean L3 banks 2 & 6 are not 
present. But what is the relationship with subslices 4 & 5 I couldn't 
find info on. I'll keep trying.

I also chatted with Lionel about this, since he typically knows GPU 
innards quite well, but in this case he also wasn't sure of this code.

> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

Thanks!

Regards,

Tvrtko
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[PATCH v2 2/4] drm/i915: Fix WaProgramMgsrForL3BankSpecificMmioReads

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Two issues in this code:

1.
fls() usage is incorrect causing off by one in subslice mask lookup,
which in other words means subslice mask of all zeroes is always used
(subslice mask of a slice which is not present, or even out of bounds
array access), rendering the checks in wa_init_mcr either futile or
random.

2.
Condition in WARN_ON is not correct. It is doing a bitwise and operation
between a positive (present subslices) and negative mask (disabled L3
banks).

This means that with corrected fls() usage the assert would always
incorrectly fail.

We can fix this by inverting the fuse bits in the check.

v2:
 * Simplify check for logic and redability.
 * Improve commentary explaining what is really happening ie. what the
   assert is really trying to check and why.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Fixes: fe864b76c2ab ("drm/i915: Implement WaProgramMgsrForL3BankSpecificMmioReads")
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # v1
Cc: Michał Winiarski <michal.winiarski@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 80 ++++++++++-----------
 1 file changed, 40 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 9e069286d3ce..80f1159e5cda 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -761,7 +761,27 @@ static void
 wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
 {
 	const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
-	u32 mcr_slice_subslice_mask;
+	u32 mcr_mask, mcr;
+
+	/*
+	 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
+	 * Before any MMIO read into slice/subslice specific registers, MCR
+	 * packet control register needs to be programmed to point to any
+	 * enabled s/ss pair. Otherwise, incorrect values will be returned.
+	 * This means each subsequent MMIO read will be forwarded to an
+	 * specific s/ss combination, but this is OK since these registers
+	 * are consistent across s/ss in almost all cases. In the rare
+	 * occasions, such as INSTDONE, where this value is dependent
+	 * on s/ss combo, the read should be done with read_subslice_reg.
+	 */
+	mcr = intel_calculate_mcr_s_ss_select(i915);
+
+	if (INTEL_GEN(i915) >= 11)
+		mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
+	else
+		mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
+
+	wa_write_masked_or(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);
 
 	/*
 	 * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
@@ -776,49 +796,29 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
 	 * something more complex that requires checking the range of every
 	 * MMIO read).
 	 */
-	if (INTEL_GEN(i915) >= 10 &&
-	    is_power_of_2(sseu->slice_mask)) {
+	if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
 		/*
-		 * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
-		 * enabled subslice, no need to redirect MCR packet
+		 * GEN8_MCR_SELECTOR contains dual-purpose bits which select
+		 * both to which subslice, or to which L3 bank, the respective
+		 * mmio reads will go.
+		 * Since we have selected one enabled subslice in
+		 * WaProgramMgsrForCorrectSliceSpecificMmioReads, we now
+		 * need to check if the L3 bank of the equal "instance" is also
+		 * enabled.
+		 * If that is not the case we could try to find a number which
+		 * works for both, or going even further, implement a dynamic
+		 * scheme where we switch at before every affected mmio read.
+		 * Fortunately neither seems to be needed at the moment for
+		 * current parts and current driver behaviour.
 		 */
-		u32 slice = fls(sseu->slice_mask);
-		u32 fuse3 =
-			intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3);
-		u8 ss_mask = sseu->subslice_mask[slice];
-
-		u8 enabled_mask = (ss_mask | ss_mask >>
-				   GEN10_L3BANK_PAIR_COUNT) & GEN10_L3BANK_MASK;
-		u8 disabled_mask = fuse3 & GEN10_L3BANK_MASK;
+		unsigned int mcr_ss = BIT((mcr >> 24) & 0x7);
+		unsigned int l3_fuse =
+			intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3) &
+			GEN10_L3BANK_MASK;
+		unsigned int l3_en = ~(l3_fuse << 4 | l3_fuse);
 
-		/*
-		 * Production silicon should have matched L3Bank and
-		 * subslice enabled
-		 */
-		WARN_ON((enabled_mask & disabled_mask) != enabled_mask);
+		WARN_ON(!(mcr_ss & l3_en));
 	}
-
-	if (INTEL_GEN(i915) >= 11)
-		mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
-					  GEN11_MCR_SUBSLICE_MASK;
-	else
-		mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK |
-					  GEN8_MCR_SUBSLICE_MASK;
-	/*
-	 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
-	 * Before any MMIO read into slice/subslice specific registers, MCR
-	 * packet control register needs to be programmed to point to any
-	 * enabled s/ss pair. Otherwise, incorrect values will be returned.
-	 * This means each subsequent MMIO read will be forwarded to an
-	 * specific s/ss combination, but this is OK since these registers
-	 * are consistent across s/ss in almost all cases. In the rare
-	 * occasions, such as INSTDONE, where this value is dependent
-	 * on s/ss combo, the read should be done with read_subslice_reg.
-	 */
-	wa_write_masked_or(wal,
-			   GEN8_MCR_SELECTOR,
-			   mcr_slice_subslice_mask,
-			   intel_calculate_mcr_s_ss_select(i915));
 }
 
 static void
-- 
2.20.1

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Re: [PATCH v2 2/4] drm/i915: Fix WaProgramMgsrForL3BankSpecificMmioReads

[Summers, Stuart]

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On Thu, 2019-07-11 at 16:59 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

This is generally much more readable than the previous implementation,
thanks! Some minor comments below...

> 
> Two issues in this code:
> 
> 1.
> fls() usage is incorrect causing off by one in subslice mask lookup,
> which in other words means subslice mask of all zeroes is always used
> (subslice mask of a slice which is not present, or even out of bounds
> array access), rendering the checks in wa_init_mcr either futile or
> random.
> 
> 2.
> Condition in WARN_ON is not correct. It is doing a bitwise and
> operation
> between a positive (present subslices) and negative mask (disabled L3
> banks).
> 
> This means that with corrected fls() usage the assert would always
> incorrectly fail.
> 
> We can fix this by inverting the fuse bits in the check.
> 
> v2:
>  * Simplify check for logic and redability.
>  * Improve commentary explaining what is really happening ie. what
> the
>    assert is really trying to check and why.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Fixes: fe864b76c2ab ("drm/i915: Implement
> WaProgramMgsrForL3BankSpecificMmioReads")
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # v1
> Cc: Michał Winiarski <michal.winiarski@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 80 ++++++++++---------
> --
>  1 file changed, 40 insertions(+), 40 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 9e069286d3ce..80f1159e5cda 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -761,7 +761,27 @@ static void
>  wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
>  {
>  	const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
> -	u32 mcr_slice_subslice_mask;
> +	u32 mcr_mask, mcr;
> +
> +	/*
> +	 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
> +	 * Before any MMIO read into slice/subslice specific registers,
> MCR
> +	 * packet control register needs to be programmed to point to
> any
> +	 * enabled s/ss pair. Otherwise, incorrect values will be
> returned.
> +	 * This means each subsequent MMIO read will be forwarded to an
> +	 * specific s/ss combination, but this is OK since these
> registers
> +	 * are consistent across s/ss in almost all cases. In the rare
> +	 * occasions, such as INSTDONE, where this value is dependent
> +	 * on s/ss combo, the read should be done with
> read_subslice_reg.
> +	 */
> +	mcr = intel_calculate_mcr_s_ss_select(i915);
> +
> +	if (INTEL_GEN(i915) >= 11)
> +		mcr_mask = GEN11_MCR_SLICE_MASK |
> GEN11_MCR_SUBSLICE_MASK;
> +	else
> +		mcr_mask = GEN8_MCR_SLICE_MASK |
> GEN8_MCR_SUBSLICE_MASK;
> +
> +	wa_write_masked_or(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);

Was there a specific reason to move this up to the top? Or this is
purely to move this functionality all together rather than spread out
through the function? Looking at the documentation, we do want to
specifically apply WaProgramMgsrForL3BankSpecificMmioReads before any
other workarounds. So maybe just move this whole block to the bottom of
the function instead? 

>  
>  	/*
>  	 * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
> @@ -776,49 +796,29 @@ wa_init_mcr(struct drm_i915_private *i915,
> struct i915_wa_list *wal)
>  	 * something more complex that requires checking the range of
> every
>  	 * MMIO read).
>  	 */
> -	if (INTEL_GEN(i915) >= 10 &&
> -	    is_power_of_2(sseu->slice_mask)) {
> +	if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
>  		/*
> -		 * read FUSE3 for enabled L3 Bank IDs, if L3 Bank
> matches
> -		 * enabled subslice, no need to redirect MCR packet
> +		 * GEN8_MCR_SELECTOR contains dual-purpose bits which
> select
> +		 * both to which subslice, or to which L3 bank, the
> respective
> +		 * mmio reads will go.
> +		 * Since we have selected one enabled subslice in
> +		 * WaProgramMgsrForCorrectSliceSpecificMmioReads, we
> now
> +		 * need to check if the L3 bank of the equal "instance"
> is also
> +		 * enabled.
> +		 * If that is not the case we could try to find a
> number which
> +		 * works for both, or going even further, implement a
> dynamic
> +		 * scheme where we switch at before every affected mmio

s/at //?

> read.
> +		 * Fortunately neither seems to be needed at the moment
> for
> +		 * current parts and current driver behaviour.
>  		 */
> -		u32 slice = fls(sseu->slice_mask);
> -		u32 fuse3 =
> -			intel_uncore_read(&i915->uncore,
> GEN10_MIRROR_FUSE3);
> -		u8 ss_mask = sseu->subslice_mask[slice];
> -
> -		u8 enabled_mask = (ss_mask | ss_mask >>
> -				   GEN10_L3BANK_PAIR_COUNT) &
> GEN10_L3BANK_MASK;
> -		u8 disabled_mask = fuse3 & GEN10_L3BANK_MASK;
> +		unsigned int mcr_ss = BIT((mcr >> 24) & 0x7);

Can you add macros for these magic numbers?

> +		unsigned int l3_fuse =
> +			intel_uncore_read(&i915->uncore,
> GEN10_MIRROR_FUSE3) &
> +			GEN10_L3BANK_MASK;
> +		unsigned int l3_en = ~(l3_fuse << 4 | l3_fuse);

Macro here for the 4?

Thanks,
Stuart

>  
> -		/*
> -		 * Production silicon should have matched L3Bank and
> -		 * subslice enabled
> -		 */
> -		WARN_ON((enabled_mask & disabled_mask) !=
> enabled_mask);
> +		WARN_ON(!(mcr_ss & l3_en));
>  	}
> -
> -	if (INTEL_GEN(i915) >= 11)
> -		mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
> -					  GEN11_MCR_SUBSLICE_MASK;
> -	else
> -		mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK |
> -					  GEN8_MCR_SUBSLICE_MASK;
> -	/*
> -	 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
> -	 * Before any MMIO read into slice/subslice specific registers,
> MCR
> -	 * packet control register needs to be programmed to point to
> any
> -	 * enabled s/ss pair. Otherwise, incorrect values will be
> returned.
> -	 * This means each subsequent MMIO read will be forwarded to an
> -	 * specific s/ss combination, but this is OK since these
> registers
> -	 * are consistent across s/ss in almost all cases. In the rare
> -	 * occasions, such as INSTDONE, where this value is dependent
> -	 * on s/ss combo, the read should be done with
> read_subslice_reg.
> -	 */
> -	wa_write_masked_or(wal,
> -			   GEN8_MCR_SELECTOR,
> -			   mcr_slice_subslice_mask,
> -			   intel_calculate_mcr_s_ss_select(i915));
>  }
>  
>  static void

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Re: [PATCH v2 2/4] drm/i915: Fix WaProgramMgsrForL3BankSpecificMmioReads

[Tvrtko Ursulin]

On 12/07/2019 00:51, Summers, Stuart wrote:
> On Thu, 2019-07-11 at 16:59 +0100, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> This is generally much more readable than the previous implementation,
> thanks! Some minor comments below...
> 
>>
>> Two issues in this code:
>>
>> 1.
>> fls() usage is incorrect causing off by one in subslice mask lookup,
>> which in other words means subslice mask of all zeroes is always used
>> (subslice mask of a slice which is not present, or even out of bounds
>> array access), rendering the checks in wa_init_mcr either futile or
>> random.
>>
>> 2.
>> Condition in WARN_ON is not correct. It is doing a bitwise and
>> operation
>> between a positive (present subslices) and negative mask (disabled L3
>> banks).
>>
>> This means that with corrected fls() usage the assert would always
>> incorrectly fail.
>>
>> We can fix this by inverting the fuse bits in the check.
>>
>> v2:
>>   * Simplify check for logic and redability.
>>   * Improve commentary explaining what is really happening ie. what
>> the
>>     assert is really trying to check and why.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Fixes: fe864b76c2ab ("drm/i915: Implement
>> WaProgramMgsrForL3BankSpecificMmioReads")
>> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # v1
>> Cc: Michał Winiarski <michal.winiarski@intel.com>
>> ---
>>   drivers/gpu/drm/i915/gt/intel_workarounds.c | 80 ++++++++++---------
>> --
>>   1 file changed, 40 insertions(+), 40 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index 9e069286d3ce..80f1159e5cda 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -761,7 +761,27 @@ static void
>>   wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
>>   {
>>   	const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
>> -	u32 mcr_slice_subslice_mask;
>> +	u32 mcr_mask, mcr;
>> +
>> +	/*
>> +	 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
>> +	 * Before any MMIO read into slice/subslice specific registers,
>> MCR
>> +	 * packet control register needs to be programmed to point to
>> any
>> +	 * enabled s/ss pair. Otherwise, incorrect values will be
>> returned.
>> +	 * This means each subsequent MMIO read will be forwarded to an
>> +	 * specific s/ss combination, but this is OK since these
>> registers
>> +	 * are consistent across s/ss in almost all cases. In the rare
>> +	 * occasions, such as INSTDONE, where this value is dependent
>> +	 * on s/ss combo, the read should be done with
>> read_subslice_reg.
>> +	 */
>> +	mcr = intel_calculate_mcr_s_ss_select(i915);
>> +
>> +	if (INTEL_GEN(i915) >= 11)
>> +		mcr_mask = GEN11_MCR_SLICE_MASK |
>> GEN11_MCR_SUBSLICE_MASK;
>> +	else
>> +		mcr_mask = GEN8_MCR_SLICE_MASK |
>> GEN8_MCR_SUBSLICE_MASK;
>> +
>> +	wa_write_masked_or(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);
> 
> Was there a specific reason to move this up to the top? Or this is

Yes, so below can check the actually selected MCR instead of deriving it 
from slice/subslice mask as stored in the driver.

> purely to move this functionality all together rather than spread out
> through the function? Looking at the documentation, we do want to
> specifically apply WaProgramMgsrForL3BankSpecificMmioReads before any
> other workarounds. So maybe just move this whole block to the bottom of
> the function instead?

I think it works better if MCR selection is first. Going forward, and 
for robustness, this probably needs to be improved to do both 
workarounds in a single block. Along the lines of ffs(ss_ena & l3_ena). 
And WARN_ON if no common bits. Oh well.. now I got no excuses not to do 
it...

>>   
>>   	/*
>>   	 * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
>> @@ -776,49 +796,29 @@ wa_init_mcr(struct drm_i915_private *i915,
>> struct i915_wa_list *wal)
>>   	 * something more complex that requires checking the range of
>> every
>>   	 * MMIO read).
>>   	 */
>> -	if (INTEL_GEN(i915) >= 10 &&
>> -	    is_power_of_2(sseu->slice_mask)) {
>> +	if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
>>   		/*
>> -		 * read FUSE3 for enabled L3 Bank IDs, if L3 Bank
>> matches
>> -		 * enabled subslice, no need to redirect MCR packet
>> +		 * GEN8_MCR_SELECTOR contains dual-purpose bits which
>> select
>> +		 * both to which subslice, or to which L3 bank, the
>> respective
>> +		 * mmio reads will go.
>> +		 * Since we have selected one enabled subslice in
>> +		 * WaProgramMgsrForCorrectSliceSpecificMmioReads, we
>> now
>> +		 * need to check if the L3 bank of the equal "instance"
>> is also
>> +		 * enabled.
>> +		 * If that is not the case we could try to find a
>> number which
>> +		 * works for both, or going even further, implement a
>> dynamic
>> +		 * scheme where we switch at before every affected mmio
> 
> s/at //?
> 
>> read.
>> +		 * Fortunately neither seems to be needed at the moment
>> for
>> +		 * current parts and current driver behaviour.
>>   		 */
>> -		u32 slice = fls(sseu->slice_mask);
>> -		u32 fuse3 =
>> -			intel_uncore_read(&i915->uncore,
>> GEN10_MIRROR_FUSE3);
>> -		u8 ss_mask = sseu->subslice_mask[slice];
>> -
>> -		u8 enabled_mask = (ss_mask | ss_mask >>
>> -				   GEN10_L3BANK_PAIR_COUNT) &
>> GEN10_L3BANK_MASK;
>> -		u8 disabled_mask = fuse3 & GEN10_L3BANK_MASK;
>> +		unsigned int mcr_ss = BIT((mcr >> 24) & 0x7);
> 
> Can you add macros for these magic numbers?
> 
>> +		unsigned int l3_fuse =
>> +			intel_uncore_read(&i915->uncore,
>> GEN10_MIRROR_FUSE3) &
>> +			GEN10_L3BANK_MASK;
>> +		unsigned int l3_en = ~(l3_fuse << 4 | l3_fuse);
> 
> Macro here for the 4?

I knew someone would ask for it. You give fixes, people want perfection. 
;) Will do.

Regards,

Tvrtko

> Thanks,
> Stuart
> 
>>   
>> -		/*
>> -		 * Production silicon should have matched L3Bank and
>> -		 * subslice enabled
>> -		 */
>> -		WARN_ON((enabled_mask & disabled_mask) !=
>> enabled_mask);
>> +		WARN_ON(!(mcr_ss & l3_en));
>>   	}
>> -
>> -	if (INTEL_GEN(i915) >= 11)
>> -		mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
>> -					  GEN11_MCR_SUBSLICE_MASK;
>> -	else
>> -		mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK |
>> -					  GEN8_MCR_SUBSLICE_MASK;
>> -	/*
>> -	 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
>> -	 * Before any MMIO read into slice/subslice specific registers,
>> MCR
>> -	 * packet control register needs to be programmed to point to
>> any
>> -	 * enabled s/ss pair. Otherwise, incorrect values will be
>> returned.
>> -	 * This means each subsequent MMIO read will be forwarded to an
>> -	 * specific s/ss combination, but this is OK since these
>> registers
>> -	 * are consistent across s/ss in almost all cases. In the rare
>> -	 * occasions, such as INSTDONE, where this value is dependent
>> -	 * on s/ss combo, the read should be done with
>> read_subslice_reg.
>> -	 */
>> -	wa_write_masked_or(wal,
>> -			   GEN8_MCR_SELECTOR,
>> -			   mcr_slice_subslice_mask,
>> -			   intel_calculate_mcr_s_ss_select(i915));
>>   }
>>   
>>   static void
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[PATCH 3/4] drm/i915: Move intel_calculate_mcr_s_ss_select to intel_sseu.c

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

It is a more appropriate home for it.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 24 -----------------------
 drivers/gpu/drm/i915/gt/intel_sseu.c      | 24 +++++++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_sseu.h      |  2 ++
 drivers/gpu/drm/i915/i915_drv.h           |  2 --
 4 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index ee15d1934486..ee2db060e349 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -972,30 +972,6 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
 	}
 }
 
-u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
-{
-	const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
-	unsigned int slice = fls(sseu->slice_mask) - 1;
-	unsigned int subslice;
-	u32 mcr_s_ss_select;
-
-	GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
-	subslice = fls(sseu->subslice_mask[slice]);
-	GEM_BUG_ON(!subslice);
-	subslice--;
-
-	if (IS_GEN(dev_priv, 10))
-		mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
-				  GEN8_MCR_SUBSLICE(subslice);
-	else if (INTEL_GEN(dev_priv) >= 11)
-		mcr_s_ss_select = GEN11_MCR_SLICE(slice) |
-				  GEN11_MCR_SUBSLICE(subslice);
-	else
-		mcr_s_ss_select = 0;
-
-	return mcr_s_ss_select;
-}
-
 static u32
 read_subslice_reg(struct intel_engine_cs *engine, int slice, int subslice,
 		  i915_reg_t reg)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index a0756f006f5f..c12cc476391f 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -157,3 +157,27 @@ u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
 
 	return rpcs;
 }
+
+u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *i915)
+{
+	const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
+	unsigned int slice = fls(sseu->slice_mask) - 1;
+	unsigned int subslice;
+	u32 mcr_s_ss_select;
+
+	GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
+	subslice = fls(sseu->subslice_mask[slice]);
+	GEM_BUG_ON(!subslice);
+	subslice--;
+
+	if (IS_GEN(i915, 10))
+		mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
+				  GEN8_MCR_SUBSLICE(subslice);
+	else if (INTEL_GEN(i915) >= 11)
+		mcr_s_ss_select = GEN11_MCR_SLICE(slice) |
+				  GEN11_MCR_SUBSLICE(subslice);
+	else
+		mcr_s_ss_select = 0;
+
+	return mcr_s_ss_select;
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index b50d0401a4e2..fbd86ed45612 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -72,4 +72,6 @@ intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
 u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
 			 const struct intel_sseu *req_sseu);
 
+u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *i915);
+
 #endif /* __INTEL_SSEU_H__ */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f9878cbef4d9..983a182d280e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2403,8 +2403,6 @@ extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
 
-u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv);
-
 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
 {
 	unsigned long delay;
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 3/4] drm/i915: Move intel_calculate_mcr_s_ss_select to intel_sseu.c

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-07-09 22:06:19)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> It is a more appropriate home for it.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
_______________________________________________
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[PATCH 4/4] drm/i915/icl: Verify engine workarounds in GEN8_L3SQCREG4

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Having fixed the incorect MCR programming in an earlier patch, we can now
stop ignoring read back of GEN8_L3SQCREG4 during engine workaround
verification.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 27 +++++----------------
 1 file changed, 6 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b5f19ad48d22..0fa43ff7366c 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -176,19 +176,6 @@ wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
 	wa_write_masked_or(wal, reg, val, val);
 }
 
-static void
-ignore_wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask, u32 val)
-{
-	struct i915_wa wa = {
-		.reg  = reg,
-		.mask = mask,
-		.val  = val,
-		/* Bonkers HW, skip verifying */
-	};
-
-	_wa_add(wal, &wa);
-}
-
 #define WA_SET_BIT_MASKED(addr, mask) \
 	wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_ENABLE(mask))
 
@@ -1234,10 +1221,9 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 			     _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE);
 
 		/* WaPipelineFlushCoherentLines:icl */
-		ignore_wa_write_or(wal,
-				   GEN8_L3SQCREG4,
-				   GEN8_LQSC_FLUSH_COHERENT_LINES,
-				   GEN8_LQSC_FLUSH_COHERENT_LINES);
+		wa_write_or(wal,
+			    GEN8_L3SQCREG4,
+			    GEN8_LQSC_FLUSH_COHERENT_LINES);
 
 		/*
 		 * Wa_1405543622:icl
@@ -1264,10 +1250,9 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 		 * Wa_1405733216:icl
 		 * Formerly known as WaDisableCleanEvicts
 		 */
-		ignore_wa_write_or(wal,
-				   GEN8_L3SQCREG4,
-				   GEN11_LQSC_CLEAN_EVICT_DISABLE,
-				   GEN11_LQSC_CLEAN_EVICT_DISABLE);
+		wa_write_or(wal,
+			    GEN8_L3SQCREG4,
+			    GEN11_LQSC_CLEAN_EVICT_DISABLE);
 
 		/* WaForwardProgressSoftReset:icl */
 		wa_write_or(wal,
-- 
2.20.1

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Re: [PATCH 4/4] drm/i915/icl: Verify engine workarounds in GEN8_L3SQCREG4

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-07-09 22:06:20)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Having fixed the incorect MCR programming in an earlier patch, we can now
> stop ignoring read back of GEN8_L3SQCREG4 during engine workaround
> verification.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Our testing is useful for something, too bad I didn't believe it.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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✓ Fi.CI.BAT: success for MCR fixes

[Patchwork]

== Series Details ==

Series: MCR fixes
URL   : https://patchwork.freedesktop.org/series/63457/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6446 -> Patchwork_13590
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13590/

Known issues
------------

  Here are the changes found in Patchwork_13590 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      [PASS][1] -> [FAIL][2] ([fdo#108511])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13590/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html

  * igt@prime_vgem@basic-fence-flip:
    - fi-ilk-650:         [PASS][3] -> [DMESG-WARN][4] ([fdo#106387])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-ilk-650/igt@prime_vgem@basic-fence-flip.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13590/fi-ilk-650/igt@prime_vgem@basic-fence-flip.html

  
#### Possible fixes ####

  * {igt@gem_ctx_switch@legacy-render}:
    - fi-cml-u:           [INCOMPLETE][5] ([fdo#110566]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-cml-u/igt@gem_ctx_switch@legacy-render.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13590/fi-cml-u/igt@gem_ctx_switch@legacy-render.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][7] ([fdo#109485]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13590/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
  [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
  [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
  [fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566


Participating hosts (51 -> 45)
------------------------------

  Additional (2): fi-byt-j1900 fi-snb-2600 
  Missing    (8): fi-kbl-soraka fi-byt-squawks fi-bsw-cyan fi-pnv-d510 fi-elk-e7500 fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_6446 -> Patchwork_13590

  CI_DRM_6446: 835fbe24abe47946fc514871f5cbe334d0be9854 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13590: 1cbd435fa30d7cf590c0e6260359be85dcd3f139 @ git://anongit.freedesktop.org/gfx-ci/linux


== Kernel 32bit build ==

Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13590/build_32bit.log

  CALL    scripts/checksyscalls.sh
  CALL    scripts/atomic/check-atomics.sh
  CHK     include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready  (#1)
  Building modules, stage 2.
  MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2


== Linux commits ==

1cbd435fa30d drm/i915/icl: Verify engine workarounds in GEN8_L3SQCREG4
700a2f938ef9 drm/i915: Move intel_calculate_mcr_s_ss_select to intel_sseu.c
4e1ae32681f0 drm/i915: Fix WaProgramMgsrForL3BankSpecificMmioReads
e757434337b0 drm/i915: Fix GEN8_MCR_SELECTOR programming

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13590/
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✓ Fi.CI.IGT: success for MCR fixes

[Patchwork]

== Series Details ==

Series: MCR fixes
URL   : https://patchwork.freedesktop.org/series/63457/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6446_full -> Patchwork_13590_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_13590_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_workarounds@suspend-resume:
    - shard-kbl:          [PASS][1] -> [DMESG-WARN][2] ([fdo#108566])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/shard-kbl4/igt@gem_workarounds@suspend-resume.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13590/shard-kbl3/igt@gem_workarounds@suspend-resume.html

  * igt@i915_pm_rpm@pm-tiling:
    - shard-glk:          [PASS][3] -> [INCOMPLETE][4] ([fdo#103359] / [k.org#198133])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/shard-glk5/igt@i915_pm_rpm@pm-tiling.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13590/shard-glk4/igt@i915_pm_rpm@pm-tiling.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-apl:          [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) +2 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/shard-apl7/igt@i915_suspend@fence-restore-tiled2untiled.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13590/shard-apl2/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_color@pipe-b-ctm-red-to-blue:
    - shard-skl:          [PASS][7] -> [FAIL][8] ([fdo#107201])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/shard-skl1/igt@kms_color@pipe-b-ctm-red-to-blue.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13590/shard-skl7/igt@kms_color@pipe-b-ctm-red-to-blue.html

  * igt@kms_flip_tiling@flip-changes-tiling-yf:
    - shard-skl:          [PASS][9] -> [FAIL][10] ([fdo#108228] / [fdo#108303])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/shard-skl3/igt@kms_flip_tiling@flip-changes-tiling-yf.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13590/shard-skl6/igt@kms_flip_tiling@flip-changes-tiling-yf.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
    - shard-skl:          [PASS][11] -> [FAIL][12] ([fdo#108145])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13590/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html

  * igt@perf@polling:
    - shard-skl:          [PASS][13] -> [FAIL][14] ([fdo#110728])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/shard-skl5/igt@perf@polling.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13590/shard-skl10/igt@perf@polling.html

  
#### Possible fixes ####

  * igt@i915_pm_rpm@debugfs-read:
    - shard-skl:          [INCOMPLETE][15] ([fdo#107807]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/shard-skl5/igt@i915_pm_rpm@debugfs-read.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13590/shard-skl6/igt@i915_pm_rpm@debugfs-read.html

  * igt@i915_suspend@sysfs-reader:
    - shard-apl:          [DMESG-WARN][17] ([fdo#108566]) -> [PASS][18] +5 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/shard-apl6/igt@i915_suspend@sysfs-reader.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13590/shard-apl1/igt@i915_suspend@sysfs-reader.html

  * igt@kms_color@pipe-c-ctm-green-to-red:
    - shard-skl:          [FAIL][19] ([fdo#107201]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/shard-skl1/igt@kms_color@pipe-c-ctm-green-to-red.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13590/shard-skl9/igt@kms_color@pipe-c-ctm-green-to-red.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          [FAIL][21] ([fdo#108145]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13590/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_setmode@basic:
    - shard-apl:          [FAIL][23] ([fdo#99912]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/shard-apl8/igt@kms_setmode@basic.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13590/shard-apl6/igt@kms_setmode@basic.html

  
#### Warnings ####

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render:
    - shard-skl:          [FAIL][25] ([fdo#108040]) -> [FAIL][26] ([fdo#103167])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/shard-skl1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13590/shard-skl1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html

  
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#107201]: https://bugs.freedesktop.org/show_bug.cgi?id=107201
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108228]: https://bugs.freedesktop.org/show_bug.cgi?id=108228
  [fdo#108303]: https://bugs.freedesktop.org/show_bug.cgi?id=108303
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_6446 -> Patchwork_13590

  CI_DRM_6446: 835fbe24abe47946fc514871f5cbe334d0be9854 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13590: 1cbd435fa30d7cf590c0e6260359be85dcd3f139 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13590/
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for MCR fixes (rev2)

[Patchwork]

== Series Details ==

Series: MCR fixes (rev2)
URL   : https://patchwork.freedesktop.org/series/63457/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6461 -> Patchwork_13626
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/

Known issues
------------

  Here are the changes found in Patchwork_13626 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_close_race@basic-threads:
    - fi-icl-u2:          [PASS][1] -> [INCOMPLETE][2] ([fdo#107713])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/fi-icl-u2/igt@gem_close_race@basic-threads.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/fi-icl-u2/igt@gem_close_race@basic-threads.html

  * igt@gem_exec_suspend@basic-s3:
    - fi-blb-e6850:       [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html

  
#### Possible fixes ####

  * igt@i915_selftest@live_contexts:
    - fi-skl-iommu:       [INCOMPLETE][5] ([fdo#111050]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/fi-skl-iommu/igt@i915_selftest@live_contexts.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/fi-skl-iommu/igt@i915_selftest@live_contexts.html

  * igt@i915_selftest@live_execlists:
    - fi-skl-gvtdvm:      [DMESG-FAIL][7] ([fdo#111108]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
    - fi-bwr-2160:        [DMESG-WARN][9] -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/fi-bwr-2160/igt@i915_selftest@live_execlists.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/fi-bwr-2160/igt@i915_selftest@live_execlists.html

  * igt@i915_selftest@live_hangcheck:
    - fi-bwr-2160:        [DMESG-FAIL][11] -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/fi-bwr-2160/igt@i915_selftest@live_hangcheck.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/fi-bwr-2160/igt@i915_selftest@live_hangcheck.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][13] ([fdo#109485]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-dsi:         [FAIL][15] ([fdo#103167]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/fi-icl-dsi/igt@kms_frontbuffer_tracking@basic.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/fi-icl-dsi/igt@kms_frontbuffer_tracking@basic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046 
  [fdo#111050]: https://bugs.freedesktop.org/show_bug.cgi?id=111050
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111108]: https://bugs.freedesktop.org/show_bug.cgi?id=111108


Participating hosts (52 -> 45)
------------------------------

  Missing    (7): fi-skl-guc fi-byt-squawks fi-bsw-cyan fi-icl-u3 fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_6461 -> Patchwork_13626

  CI_DRM_6461: c16e87caedb5fa63f7731443573348fe1e222c50 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5094: d7f140b5b02d054183a74842b4579cf7f5533927 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13626: 524a74bd73ba307f2a952efaaa0b44698b80b883 @ git://anongit.freedesktop.org/gfx-ci/linux


== Kernel 32bit build ==

Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/build_32bit.log

  CALL    scripts/checksyscalls.sh
  CALL    scripts/atomic/check-atomics.sh
  CHK     include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready  (#1)
  Building modules, stage 2.
  MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2


== Linux commits ==

524a74bd73ba drm/i915/icl: Verify engine workarounds in GEN8_L3SQCREG4
e82441f3a21e drm/i915: Move intel_calculate_mcr_s_ss_select to intel_sseu.c
c16516bace19 drm/i915: Fix WaProgramMgsrForL3BankSpecificMmioReads
628bc6728418 drm/i915: Fix GEN8_MCR_SELECTOR programming

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.IGT: failure for MCR fixes (rev2)

[Patchwork]

== Series Details ==

Series: MCR fixes (rev2)
URL   : https://patchwork.freedesktop.org/series/63457/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_6461_full -> Patchwork_13626_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_13626_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_13626_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_13626_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_exec_suspend@basic-s3:
    - shard-iclb:         NOTRUN -> [SKIP][1] +12 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-iclb6/igt@gem_exec_suspend@basic-s3.html

  * igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-a:
    - shard-iclb:         [PASS][2] -> [SKIP][3] +79 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-iclb3/igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-a.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-iclb8/igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-a.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt:
    - shard-iclb:         [PASS][4] -> [FAIL][5] +28 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-gtt:
    - shard-iclb:         NOTRUN -> [FAIL][6] +6 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-gtt.html

  * igt@perf_pmu@busy-accuracy-98-vcs1:
    - shard-iclb:         NOTRUN -> [TIMEOUT][7] +2 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-iclb8/igt@perf_pmu@busy-accuracy-98-vcs1.html

  * igt@perf_pmu@render-node-busy-idle-vcs0:
    - shard-iclb:         [PASS][8] -> [TIMEOUT][9]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-iclb7/igt@perf_pmu@render-node-busy-idle-vcs0.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-iclb6/igt@perf_pmu@render-node-busy-idle-vcs0.html

  
#### Warnings ####

  * igt@gem_exec_parse@cmd-crossing-page:
    - shard-iclb:         [SKIP][10] ([fdo#109289]) -> [SKIP][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-iclb2/igt@gem_exec_parse@cmd-crossing-page.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-iclb8/igt@gem_exec_parse@cmd-crossing-page.html

  * igt@i915_pm_sseu@full-enable:
    - shard-iclb:         [SKIP][12] ([fdo#109288]) -> [SKIP][13]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-iclb3/igt@i915_pm_sseu@full-enable.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-iclb8/igt@i915_pm_sseu@full-enable.html

  * igt@kms_busy@extended-pageflip-hang-newfb-render-e:
    - shard-iclb:         [SKIP][14] ([fdo#109278]) -> [SKIP][15] +1 similar issue
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-iclb2/igt@kms_busy@extended-pageflip-hang-newfb-render-e.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-iclb8/igt@kms_busy@extended-pageflip-hang-newfb-render-e.html

  * igt@kms_flip@2x-flip-vs-panning-vs-hang-interruptible:
    - shard-iclb:         [SKIP][16] ([fdo#109274]) -> [SKIP][17]
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-iclb7/igt@kms_flip@2x-flip-vs-panning-vs-hang-interruptible.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-iclb6/igt@kms_flip@2x-flip-vs-panning-vs-hang-interruptible.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@gem_ctx_switch@legacy-default}:
    - shard-iclb:         NOTRUN -> [SKIP][18]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-iclb6/igt@gem_ctx_switch@legacy-default.html

  * {igt@gem_ctx_switch@legacy-vebox-heavy-queue}:
    - shard-iclb:         [PASS][19] -> [SKIP][20] +2 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-iclb2/igt@gem_ctx_switch@legacy-vebox-heavy-queue.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-iclb8/igt@gem_ctx_switch@legacy-vebox-heavy-queue.html

  
Known issues
------------

  Here are the changes found in Patchwork_13626_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_params@invalid-bsd2-flag-on-blt:
    - shard-iclb:         [PASS][21] -> [SKIP][22] ([fdo#109276]) +2 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-iclb4/igt@gem_exec_params@invalid-bsd2-flag-on-blt.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-iclb7/igt@gem_exec_params@invalid-bsd2-flag-on-blt.html

  * igt@gem_tiled_swapping@non-threaded:
    - shard-apl:          [PASS][23] -> [DMESG-WARN][24] ([fdo#108686])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-apl7/igt@gem_tiled_swapping@non-threaded.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-apl1/igt@gem_tiled_swapping@non-threaded.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-apl:          [PASS][25] -> [DMESG-WARN][26] ([fdo#108566]) +2 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-apl7/igt@gem_workarounds@suspend-resume-context.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-apl1/igt@gem_workarounds@suspend-resume-context.html

  * igt@i915_suspend@forcewake:
    - shard-skl:          [PASS][27] -> [INCOMPLETE][28] ([fdo#104108])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-skl10/igt@i915_suspend@forcewake.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-skl5/igt@i915_suspend@forcewake.html

  * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
    - shard-iclb:         [PASS][29] -> [FAIL][30] ([fdo#103167]) +3 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html

  * igt@kms_psr@psr2_primary_mmap_gtt:
    - shard-iclb:         [PASS][31] -> [SKIP][32] ([fdo#109441])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-iclb4/igt@kms_psr@psr2_primary_mmap_gtt.html

  * igt@kms_vblank@pipe-b-query-idle-hang:
    - shard-iclb:         [PASS][33] -> [SKIP][34] ([fdo#109278]) +3 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-iclb7/igt@kms_vblank@pipe-b-query-idle-hang.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-iclb6/igt@kms_vblank@pipe-b-query-idle-hang.html

  * igt@perf@blocking:
    - shard-skl:          [PASS][35] -> [FAIL][36] ([fdo#110728])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-skl1/igt@perf@blocking.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-skl5/igt@perf@blocking.html

  * igt@perf_pmu@busy-idle-no-semaphores-bcs0:
    - shard-iclb:         [PASS][37] -> [TIMEOUT][38] ([fdo#109673]) +2 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-iclb2/igt@perf_pmu@busy-idle-no-semaphores-bcs0.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-iclb8/igt@perf_pmu@busy-idle-no-semaphores-bcs0.html

  * igt@perf_pmu@busy-start-vcs2:
    - shard-iclb:         [PASS][39] -> [INCOMPLETE][40] ([fdo#107713]) +4 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-iclb4/igt@perf_pmu@busy-start-vcs2.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-iclb7/igt@perf_pmu@busy-start-vcs2.html

  * igt@perf_pmu@rc6:
    - shard-kbl:          [PASS][41] -> [SKIP][42] ([fdo#109271]) +1 similar issue
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-kbl1/igt@perf_pmu@rc6.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-kbl7/igt@perf_pmu@rc6.html

  * igt@tools_test@tools_test:
    - shard-snb:          [PASS][43] -> [SKIP][44] ([fdo#109271])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-snb1/igt@tools_test@tools_test.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-snb6/igt@tools_test@tools_test.html

  
#### Possible fixes ####

  * igt@gem_exec_balancer@smoke:
    - shard-iclb:         [SKIP][45] ([fdo#110854]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-iclb8/igt@gem_exec_balancer@smoke.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-iclb2/igt@gem_exec_balancer@smoke.html

  * igt@gem_persistent_relocs@forked-interruptible-thrashing:
    - shard-hsw:          [INCOMPLETE][47] ([fdo#103540]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-hsw5/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-hsw5/igt@gem_persistent_relocs@forked-interruptible-thrashing.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
    - shard-hsw:          [FAIL][49] ([fdo#105767]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-hsw5/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-hsw5/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html

  * igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-ytiled:
    - shard-skl:          [FAIL][51] ([fdo#103184] / [fdo#103232]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-skl1/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-ytiled.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-skl5/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-ytiled.html

  * igt@kms_flip@absolute-wf_vblank:
    - shard-skl:          [FAIL][53] -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-skl3/igt@kms_flip@absolute-wf_vblank.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-skl7/igt@kms_flip@absolute-wf_vblank.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move:
    - shard-iclb:         [INCOMPLETE][55] ([fdo#106978] / [fdo#107713]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move.html

  * igt@kms_frontbuffer_tracking@psr-suspend:
    - shard-skl:          [INCOMPLETE][57] ([fdo#104108] / [fdo#106978]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-skl1/igt@kms_frontbuffer_tracking@psr-suspend.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-skl3/igt@kms_frontbuffer_tracking@psr-suspend.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-apl:          [DMESG-WARN][59] ([fdo#108566]) -> [PASS][60] +2 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-apl5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
    - shard-skl:          [FAIL][61] ([fdo#108145]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html

  * igt@kms_psr2_su@page_flip:
    - shard-iclb:         [SKIP][63] ([fdo#109642] / [fdo#111068]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-iclb8/igt@kms_psr2_su@page_flip.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-iclb2/igt@kms_psr2_su@page_flip.html

  * igt@kms_psr@psr2_basic:
    - shard-iclb:         [SKIP][65] ([fdo#109441]) -> [PASS][66] +2 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-iclb4/igt@kms_psr@psr2_basic.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-iclb2/igt@kms_psr@psr2_basic.html

  * igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
    - shard-iclb:         [INCOMPLETE][67] ([fdo#107713]) -> [PASS][68] +1 similar issue
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-iclb7/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-iclb8/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html

  
#### Warnings ####

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc:
    - shard-skl:          [FAIL][69] ([fdo#108040]) -> [FAIL][70] ([fdo#103167])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6461/shard-skl6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/shard-skl10/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
  [fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109288]: https://bugs.freedesktop.org/show_bug.cgi?id=109288
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
  [fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
  [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_6461 -> Patchwork_13626

  CI_DRM_6461: c16e87caedb5fa63f7731443573348fe1e222c50 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5094: d7f140b5b02d054183a74842b4579cf7f5533927 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13626: 524a74bd73ba307f2a952efaaa0b44698b80b883 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13626/
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