* [PATCH 01/22] drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
2019-07-13 1:09 [PATCH 00/22] Tiger Lake part 2 Lucas De Marchi
@ 2019-07-13 1:09 ` Lucas De Marchi
2019-07-18 20:35 ` Atwood, Matthew S
2019-07-13 1:09 ` [PATCH 02/22] drm/i915/tgl: select correct bit for port select Lucas De Marchi
` (26 subsequent siblings)
27 siblings, 1 reply; 64+ messages in thread
From: Lucas De Marchi @ 2019-07-13 1:09 UTC (permalink / raw)
To: intel-gfx
According to the spec when initializing the display in TGL we should not
set PORT_CL_DW12 for the Aux channel of the combo PHYs. We will re-use the
power well hooks from ICL so only set this register on gen < 12.
v2: Generalize check for gen 12 (suggested by José)
v3: Rebase after enum phy introduction
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 93a148684c53..dd2a50b8ba0a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -458,8 +458,10 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
val = I915_READ(regs->driver);
I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
- val = I915_READ(ICL_PORT_CL_DW12(phy));
- I915_WRITE(ICL_PORT_CL_DW12(phy), val | ICL_LANE_ENABLE_AUX);
+ if (INTEL_GEN(dev_priv) < 12) {
+ val = I915_READ(ICL_PORT_CL_DW12(phy));
+ I915_WRITE(ICL_PORT_CL_DW12(phy), val | ICL_LANE_ENABLE_AUX);
+ }
hsw_wait_for_power_well_enable(dev_priv, power_well);
@@ -487,8 +489,10 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
u32 val;
- val = I915_READ(ICL_PORT_CL_DW12(phy));
- I915_WRITE(ICL_PORT_CL_DW12(phy), val & ~ICL_LANE_ENABLE_AUX);
+ if (INTEL_GEN(dev_priv) < 12) {
+ val = I915_READ(ICL_PORT_CL_DW12(phy));
+ I915_WRITE(ICL_PORT_CL_DW12(phy), val & ~ICL_LANE_ENABLE_AUX);
+ }
val = I915_READ(regs->driver);
I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
--
2.21.0
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^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 01/22] drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
2019-07-13 1:09 ` [PATCH 01/22] drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization Lucas De Marchi
@ 2019-07-18 20:35 ` Atwood, Matthew S
0 siblings, 0 replies; 64+ messages in thread
From: Atwood, Matthew S @ 2019-07-18 20:35 UTC (permalink / raw)
To: intel-gfx, De Marchi, Lucas
On Fri, 2019-07-12 at 18:09 -0700, Lucas De Marchi wrote:
> According to the spec when initializing the display in TGL we should
> not
> set PORT_CL_DW12 for the Aux channel of the combo PHYs. We will re-
> use the
> power well hooks from ICL so only set this register on gen < 12.
>
> v2: Generalize check for gen 12 (suggested by José)
> v3: Rebase after enum phy introduction
>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 93a148684c53..dd2a50b8ba0a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -458,8 +458,10 @@ icl_combo_phy_aux_power_well_enable(struct
> drm_i915_private *dev_priv,
> val = I915_READ(regs->driver);
> I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
>
> - val = I915_READ(ICL_PORT_CL_DW12(phy));
> - I915_WRITE(ICL_PORT_CL_DW12(phy), val | ICL_LANE_ENABLE_AUX);
> + if (INTEL_GEN(dev_priv) < 12) {
> + val = I915_READ(ICL_PORT_CL_DW12(phy));
> + I915_WRITE(ICL_PORT_CL_DW12(phy), val |
> ICL_LANE_ENABLE_AUX);
> + }
>
> hsw_wait_for_power_well_enable(dev_priv, power_well);
>
> @@ -487,8 +489,10 @@ icl_combo_phy_aux_power_well_disable(struct
> drm_i915_private *dev_priv,
> enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
> u32 val;
>
> - val = I915_READ(ICL_PORT_CL_DW12(phy));
> - I915_WRITE(ICL_PORT_CL_DW12(phy), val & ~ICL_LANE_ENABLE_AUX);
> + if (INTEL_GEN(dev_priv) < 12) {
> + val = I915_READ(ICL_PORT_CL_DW12(phy));
> + I915_WRITE(ICL_PORT_CL_DW12(phy), val &
> ~ICL_LANE_ENABLE_AUX);
> + }
>
> val = I915_READ(regs->driver);
> I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 02/22] drm/i915/tgl: select correct bit for port select
2019-07-13 1:09 [PATCH 00/22] Tiger Lake part 2 Lucas De Marchi
2019-07-13 1:09 ` [PATCH 01/22] drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization Lucas De Marchi
@ 2019-07-13 1:09 ` Lucas De Marchi
2019-07-16 21:37 ` Srivatsa, Anusha
2019-07-18 20:20 ` Atwood, Matthew S
2019-07-13 1:09 ` [PATCH 03/22] drm/i915/tgl: update ddi/tc clock_off bits Lucas De Marchi
` (25 subsequent siblings)
27 siblings, 2 replies; 64+ messages in thread
From: Lucas De Marchi @ 2019-07-13 1:09 UTC (permalink / raw)
To: intel-gfx; +Cc: Mahesh Kumar
From: Mahesh Kumar <mahesh1.kumar@intel.com>
Bit definitions for port-select got changed for TRANS_CLK_SEL &
TRANS_DDI_FUNC_CTL registers in TGL.
v2 (Lucas):
- Nuke TRANS_DDI_PORT_NONE since it's 0: we are already clearing
{TGL_,}TRANS_DDI_PORT_MASK (suggested by Ville)
- Also cover haswell_get_ddi_port_state() in intel_display.c that was
missing
- Define macros using the _SHIFT macros so we don't lose other users
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 47 +++++++++++++++-----
drivers/gpu/drm/i915/display/intel_display.c | 6 ++-
drivers/gpu/drm/i915/i915_reg.h | 11 +++--
3 files changed, 50 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 8445244aa593..339c01e567ab 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1773,7 +1773,10 @@ void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
temp = TRANS_DDI_FUNC_ENABLE;
- temp |= TRANS_DDI_SELECT_PORT(port);
+ if (INTEL_GEN(dev_priv) >= 12)
+ temp |= TGL_TRANS_DDI_SELECT_PORT(port);
+ else
+ temp |= TRANS_DDI_SELECT_PORT(port);
switch (crtc_state->pipe_bpp) {
case 18:
@@ -1853,8 +1856,13 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
u32 val = I915_READ(reg);
- val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
- val |= TRANS_DDI_PORT_NONE;
+ if (INTEL_GEN(dev_priv) >= 12) {
+ val &= ~(TRANS_DDI_FUNC_ENABLE | TGL_TRANS_DDI_PORT_MASK |
+ TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
+ } else {
+ val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
+ TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
+ }
I915_WRITE(reg, val);
if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
@@ -2006,10 +2014,19 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
mst_pipe_mask = 0;
for_each_pipe(dev_priv, p) {
enum transcoder cpu_transcoder = (enum transcoder)p;
+ unsigned int port_mask, ddi_select;
+
+ if (INTEL_GEN(dev_priv) >= 12) {
+ port_mask = TGL_TRANS_DDI_PORT_MASK;
+ ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
+ } else {
+ port_mask = TRANS_DDI_PORT_MASK;
+ ddi_select = TRANS_DDI_SELECT_PORT(port);
+ }
tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
- if ((tmp & TRANS_DDI_PORT_MASK) != TRANS_DDI_SELECT_PORT(port))
+ if ((tmp & port_mask) != ddi_select)
continue;
if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
@@ -2126,9 +2143,14 @@ void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
enum port port = encoder->port;
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- if (cpu_transcoder != TRANSCODER_EDP)
- I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
- TRANS_CLK_SEL_PORT(port));
+ if (cpu_transcoder != TRANSCODER_EDP) {
+ if (INTEL_GEN(dev_priv) >= 12)
+ I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+ TGL_TRANS_CLK_SEL_PORT(port));
+ else
+ I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+ TRANS_CLK_SEL_PORT(port));
+ }
}
void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
@@ -2136,9 +2158,14 @@ void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- if (cpu_transcoder != TRANSCODER_EDP)
- I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
- TRANS_CLK_SEL_DISABLED);
+ if (cpu_transcoder != TRANSCODER_EDP) {
+ if (INTEL_GEN(dev_priv) >= 12)
+ I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+ TGL_TRANS_CLK_SEL_DISABLED);
+ else
+ I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
+ TRANS_CLK_SEL_DISABLED);
+ }
}
static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e25b82d07d4f..51e4f6798a6b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10353,7 +10353,11 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
- port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
+ if (INTEL_GEN(dev_priv) >= 12)
+ port = (tmp & TGL_TRANS_DDI_PORT_MASK) >>
+ TGL_TRANS_DDI_PORT_SHIFT;
+ else
+ port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
if (INTEL_GEN(dev_priv) >= 11)
icelake_get_ddi_pll(dev_priv, port, pipe_config);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0dd4506323f2..def71fd2e4d1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9391,10 +9391,12 @@ enum skl_power_gate {
#define TRANS_DDI_FUNC_ENABLE (1 << 31)
/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
-#define TRANS_DDI_PORT_MASK (7 << 28)
#define TRANS_DDI_PORT_SHIFT 28
-#define TRANS_DDI_SELECT_PORT(x) ((x) << 28)
-#define TRANS_DDI_PORT_NONE (0 << 28)
+#define TGL_TRANS_DDI_PORT_SHIFT 27
+#define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT)
+#define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT)
+#define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT)
+#define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT)
#define TRANS_DDI_MODE_SELECT_MASK (7 << 24)
#define TRANS_DDI_MODE_SELECT_HDMI (0 << 24)
#define TRANS_DDI_MODE_SELECT_DVI (1 << 24)
@@ -9604,6 +9606,9 @@ enum skl_power_gate {
/* For each transcoder, we need to select the corresponding port clock */
#define TRANS_CLK_SEL_DISABLED (0x0 << 29)
#define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29)
+#define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28)
+#define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28)
+
#define CDCLK_FREQ _MMIO(0x46200)
--
2.21.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 02/22] drm/i915/tgl: select correct bit for port select
2019-07-13 1:09 ` [PATCH 02/22] drm/i915/tgl: select correct bit for port select Lucas De Marchi
@ 2019-07-16 21:37 ` Srivatsa, Anusha
2019-07-18 20:20 ` Atwood, Matthew S
1 sibling, 0 replies; 64+ messages in thread
From: Srivatsa, Anusha @ 2019-07-16 21:37 UTC (permalink / raw)
To: De Marchi, Lucas, intel-gfx; +Cc: Mahesh Kumar
>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>Lucas De Marchi
>Sent: Friday, July 12, 2019 6:09 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Mahesh Kumar <mahesh1.kumar@intel.com>
>Subject: [Intel-gfx] [PATCH 02/22] drm/i915/tgl: select correct bit for port select
>
>From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
>Bit definitions for port-select got changed for TRANS_CLK_SEL &
>TRANS_DDI_FUNC_CTL registers in TGL.
>
>v2 (Lucas):
> - Nuke TRANS_DDI_PORT_NONE since it's 0: we are already clearing
> {TGL_,}TRANS_DDI_PORT_MASK (suggested by Ville)
> - Also cover haswell_get_ddi_port_state() in intel_display.c that was
> missing
> - Define macros using the _SHIFT macros so we don't lose other users
Looks good.
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_ddi.c | 47 +++++++++++++++-----
> drivers/gpu/drm/i915/display/intel_display.c | 6 ++-
> drivers/gpu/drm/i915/i915_reg.h | 11 +++--
> 3 files changed, 50 insertions(+), 14 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
>b/drivers/gpu/drm/i915/display/intel_ddi.c
>index 8445244aa593..339c01e567ab 100644
>--- a/drivers/gpu/drm/i915/display/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>@@ -1773,7 +1773,10 @@ void intel_ddi_enable_transcoder_func(const struct
>intel_crtc_state *crtc_state)
>
> /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
> temp = TRANS_DDI_FUNC_ENABLE;
>- temp |= TRANS_DDI_SELECT_PORT(port);
>+ if (INTEL_GEN(dev_priv) >= 12)
>+ temp |= TGL_TRANS_DDI_SELECT_PORT(port);
>+ else
>+ temp |= TRANS_DDI_SELECT_PORT(port);
>
> switch (crtc_state->pipe_bpp) {
> case 18:
>@@ -1853,8 +1856,13 @@ void intel_ddi_disable_transcoder_func(const struct
>intel_crtc_state *crtc_state
> i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
> u32 val = I915_READ(reg);
>
>- val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
>TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
>- val |= TRANS_DDI_PORT_NONE;
>+ if (INTEL_GEN(dev_priv) >= 12) {
>+ val &= ~(TRANS_DDI_FUNC_ENABLE |
>TGL_TRANS_DDI_PORT_MASK |
>+ TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
>+ } else {
>+ val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK
>|
>+ TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
>+ }
> I915_WRITE(reg, val);
>
> if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME && @@ -
>2006,10 +2014,19 @@ static void intel_ddi_get_encoder_pipes(struct
>intel_encoder *encoder,
> mst_pipe_mask = 0;
> for_each_pipe(dev_priv, p) {
> enum transcoder cpu_transcoder = (enum transcoder)p;
>+ unsigned int port_mask, ddi_select;
>+
>+ if (INTEL_GEN(dev_priv) >= 12) {
>+ port_mask = TGL_TRANS_DDI_PORT_MASK;
>+ ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
>+ } else {
>+ port_mask = TRANS_DDI_PORT_MASK;
>+ ddi_select = TRANS_DDI_SELECT_PORT(port);
>+ }
>
> tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
>
>- if ((tmp & TRANS_DDI_PORT_MASK) !=
>TRANS_DDI_SELECT_PORT(port))
>+ if ((tmp & port_mask) != ddi_select)
> continue;
>
> if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == @@ -2126,9
>+2143,14 @@ void intel_ddi_enable_pipe_clock(const struct intel_crtc_state
>*crtc_state)
> enum port port = encoder->port;
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
>- if (cpu_transcoder != TRANSCODER_EDP)
>- I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
>- TRANS_CLK_SEL_PORT(port));
>+ if (cpu_transcoder != TRANSCODER_EDP) {
>+ if (INTEL_GEN(dev_priv) >= 12)
>+ I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
>+ TGL_TRANS_CLK_SEL_PORT(port));
>+ else
>+ I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
>+ TRANS_CLK_SEL_PORT(port));
>+ }
> }
>
> void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) @@
>-2136,9 +2158,14 @@ void intel_ddi_disable_pipe_clock(const struct
>intel_crtc_state *crtc_state)
> struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
>- if (cpu_transcoder != TRANSCODER_EDP)
>- I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
>- TRANS_CLK_SEL_DISABLED);
>+ if (cpu_transcoder != TRANSCODER_EDP) {
>+ if (INTEL_GEN(dev_priv) >= 12)
>+ I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
>+ TGL_TRANS_CLK_SEL_DISABLED);
>+ else
>+ I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
>+ TRANS_CLK_SEL_DISABLED);
>+ }
> }
>
> static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, diff --git
>a/drivers/gpu/drm/i915/display/intel_display.c
>b/drivers/gpu/drm/i915/display/intel_display.c
>index e25b82d07d4f..51e4f6798a6b 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -10353,7 +10353,11 @@ static void haswell_get_ddi_port_state(struct
>intel_crtc *crtc,
>
> tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config-
>>cpu_transcoder));
>
>- port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
>+ if (INTEL_GEN(dev_priv) >= 12)
>+ port = (tmp & TGL_TRANS_DDI_PORT_MASK) >>
>+ TGL_TRANS_DDI_PORT_SHIFT;
>+ else
>+ port = (tmp & TRANS_DDI_PORT_MASK) >>
>TRANS_DDI_PORT_SHIFT;
>
> if (INTEL_GEN(dev_priv) >= 11)
> icelake_get_ddi_pll(dev_priv, port, pipe_config); diff --git
>a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index
>0dd4506323f2..def71fd2e4d1 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -9391,10 +9391,12 @@ enum skl_power_gate {
>
> #define TRANS_DDI_FUNC_ENABLE (1 << 31)
> /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
>-#define TRANS_DDI_PORT_MASK (7 << 28)
> #define TRANS_DDI_PORT_SHIFT 28
>-#define TRANS_DDI_SELECT_PORT(x) ((x) << 28)
>-#define TRANS_DDI_PORT_NONE (0 << 28)
>+#define TGL_TRANS_DDI_PORT_SHIFT 27
>+#define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT)
>+#define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT)
>+#define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT)
>+#define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) <<
>TGL_TRANS_DDI_PORT_SHIFT)
> #define TRANS_DDI_MODE_SELECT_MASK (7 << 24)
> #define TRANS_DDI_MODE_SELECT_HDMI (0 << 24)
> #define TRANS_DDI_MODE_SELECT_DVI (1 << 24)
>@@ -9604,6 +9606,9 @@ enum skl_power_gate {
> /* For each transcoder, we need to select the corresponding port clock */
> #define TRANS_CLK_SEL_DISABLED (0x0 << 29)
> #define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29)
>+#define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28)
>+#define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28)
>+
>
> #define CDCLK_FREQ _MMIO(0x46200)
>
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 02/22] drm/i915/tgl: select correct bit for port select
2019-07-13 1:09 ` [PATCH 02/22] drm/i915/tgl: select correct bit for port select Lucas De Marchi
2019-07-16 21:37 ` Srivatsa, Anusha
@ 2019-07-18 20:20 ` Atwood, Matthew S
1 sibling, 0 replies; 64+ messages in thread
From: Atwood, Matthew S @ 2019-07-18 20:20 UTC (permalink / raw)
To: intel-gfx, De Marchi, Lucas; +Cc: mahesh1.kumar
On Fri, 2019-07-12 at 18:09 -0700, Lucas De Marchi wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
> Bit definitions for port-select got changed for TRANS_CLK_SEL &
> TRANS_DDI_FUNC_CTL registers in TGL.
>
> v2 (Lucas):
> - Nuke TRANS_DDI_PORT_NONE since it's 0: we are already clearing
> {TGL_,}TRANS_DDI_PORT_MASK (suggested by Ville)
> - Also cover haswell_get_ddi_port_state() in intel_display.c that
> was
> missing
> - Define macros using the _SHIFT macros so we don't lose other
> users
>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 47 +++++++++++++++---
> --
> drivers/gpu/drm/i915/display/intel_display.c | 6 ++-
> drivers/gpu/drm/i915/i915_reg.h | 11 +++--
> 3 files changed, 50 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 8445244aa593..339c01e567ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1773,7 +1773,10 @@ void intel_ddi_enable_transcoder_func(const
> struct intel_crtc_state *crtc_state)
>
> /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode
> */
> temp = TRANS_DDI_FUNC_ENABLE;
> - temp |= TRANS_DDI_SELECT_PORT(port);
> + if (INTEL_GEN(dev_priv) >= 12)
> + temp |= TGL_TRANS_DDI_SELECT_PORT(port);
> + else
> + temp |= TRANS_DDI_SELECT_PORT(port);
>
> switch (crtc_state->pipe_bpp) {
> case 18:
> @@ -1853,8 +1856,13 @@ void intel_ddi_disable_transcoder_func(const
> struct intel_crtc_state *crtc_state
> i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
> u32 val = I915_READ(reg);
>
> - val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
> TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
> - val |= TRANS_DDI_PORT_NONE;
> + if (INTEL_GEN(dev_priv) >= 12) {
> + val &= ~(TRANS_DDI_FUNC_ENABLE |
> TGL_TRANS_DDI_PORT_MASK |
> + TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
> + } else {
> + val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
> + TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
> + }
> I915_WRITE(reg, val);
>
> if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
> @@ -2006,10 +2014,19 @@ static void
> intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
> mst_pipe_mask = 0;
> for_each_pipe(dev_priv, p) {
> enum transcoder cpu_transcoder = (enum transcoder)p;
> + unsigned int port_mask, ddi_select;
> +
> + if (INTEL_GEN(dev_priv) >= 12) {
> + port_mask = TGL_TRANS_DDI_PORT_MASK;
> + ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
> + } else {
> + port_mask = TRANS_DDI_PORT_MASK;
> + ddi_select = TRANS_DDI_SELECT_PORT(port);
> + }
>
> tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
>
> - if ((tmp & TRANS_DDI_PORT_MASK) !=
> TRANS_DDI_SELECT_PORT(port))
> + if ((tmp & port_mask) != ddi_select)
> continue;
>
> if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
> @@ -2126,9 +2143,14 @@ void intel_ddi_enable_pipe_clock(const struct
> intel_crtc_state *crtc_state)
> enum port port = encoder->port;
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> - if (cpu_transcoder != TRANSCODER_EDP)
> - I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
> - TRANS_CLK_SEL_PORT(port));
> + if (cpu_transcoder != TRANSCODER_EDP) {
> + if (INTEL_GEN(dev_priv) >= 12)
> + I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
> + TGL_TRANS_CLK_SEL_PORT(port));
> + else
> + I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
> + TRANS_CLK_SEL_PORT(port));
> + }
> }
>
> void intel_ddi_disable_pipe_clock(const struct intel_crtc_state
> *crtc_state)
> @@ -2136,9 +2158,14 @@ void intel_ddi_disable_pipe_clock(const struct
> intel_crtc_state *crtc_state)
> struct drm_i915_private *dev_priv = to_i915(crtc_state-
> >base.crtc->dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> - if (cpu_transcoder != TRANSCODER_EDP)
> - I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
> - TRANS_CLK_SEL_DISABLED);
> + if (cpu_transcoder != TRANSCODER_EDP) {
> + if (INTEL_GEN(dev_priv) >= 12)
> + I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
> + TGL_TRANS_CLK_SEL_DISABLED);
> + else
> + I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
> + TRANS_CLK_SEL_DISABLED);
> + }
> }
>
> static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index e25b82d07d4f..51e4f6798a6b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -10353,7 +10353,11 @@ static void
> haswell_get_ddi_port_state(struct intel_crtc *crtc,
>
> tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config-
> >cpu_transcoder));
>
> - port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
> + if (INTEL_GEN(dev_priv) >= 12)
> + port = (tmp & TGL_TRANS_DDI_PORT_MASK) >>
> + TGL_TRANS_DDI_PORT_SHIFT;
> + else
> + port = (tmp & TRANS_DDI_PORT_MASK) >>
> TRANS_DDI_PORT_SHIFT;
>
> if (INTEL_GEN(dev_priv) >= 11)
> icelake_get_ddi_pll(dev_priv, port, pipe_config);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 0dd4506323f2..def71fd2e4d1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9391,10 +9391,12 @@ enum skl_power_gate {
>
> #define TRANS_DDI_FUNC_ENABLE (1 << 31)
> /* Those bits are ignored by pipe EDP since it can only connect to
> DDI A */
> -#define TRANS_DDI_PORT_MASK (7 << 28)
> #define TRANS_DDI_PORT_SHIFT 28
> -#define TRANS_DDI_SELECT_PORT(x) ((x) << 28)
> -#define TRANS_DDI_PORT_NONE (0 << 28)
> +#define TGL_TRANS_DDI_PORT_SHIFT 27
> +#define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT)
> +#define TGL_TRANS_DDI_PORT_MASK (0xf <<
> TGL_TRANS_DDI_PORT_SHIFT)
> +#define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT)
> +#define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) <<
> TGL_TRANS_DDI_PORT_SHIFT)
> #define TRANS_DDI_MODE_SELECT_MASK (7 << 24)
> #define TRANS_DDI_MODE_SELECT_HDMI (0 << 24)
> #define TRANS_DDI_MODE_SELECT_DVI (1 << 24)
> @@ -9604,6 +9606,9 @@ enum skl_power_gate {
> /* For each transcoder, we need to select the corresponding port
> clock */
> #define TRANS_CLK_SEL_DISABLED (0x0 << 29)
> #define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29)
> +#define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28)
> +#define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28)
> +
>
> #define CDCLK_FREQ _MMIO(0x46200)
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 03/22] drm/i915/tgl: update ddi/tc clock_off bits
2019-07-13 1:09 [PATCH 00/22] Tiger Lake part 2 Lucas De Marchi
2019-07-13 1:09 ` [PATCH 01/22] drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization Lucas De Marchi
2019-07-13 1:09 ` [PATCH 02/22] drm/i915/tgl: select correct bit for port select Lucas De Marchi
@ 2019-07-13 1:09 ` Lucas De Marchi
2019-07-16 22:41 ` Srivatsa, Anusha
2019-07-18 21:09 ` Atwood, Matthew S
2019-07-13 1:09 ` [PATCH 04/22] drm/i915/tgl: Add hpd interrupt handling Lucas De Marchi
` (24 subsequent siblings)
27 siblings, 2 replies; 64+ messages in thread
From: Lucas De Marchi @ 2019-07-13 1:09 UTC (permalink / raw)
To: intel-gfx; +Cc: Mahesh Kumar
From: Mahesh Kumar <mahesh1.kumar@intel.com>
In GEN 12 PORT_C DDI clk_off bit is not equally distanced to A/B,
it's at offset 24. Similarly TC port (5/6) clk off bits are at
offset 22/23. Extend the macros to cover the additional ports.
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index def71fd2e4d1..d873d9fbbf0e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9749,8 +9749,9 @@ enum skl_power_gate {
#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24))
-#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
- 21 : (tc_port) + 12))
+#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \
+ (tc_port) + 12 : \
+ (tc_port) - PORT_TC4 + 21))
#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
--
2.21.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 03/22] drm/i915/tgl: update ddi/tc clock_off bits
2019-07-13 1:09 ` [PATCH 03/22] drm/i915/tgl: update ddi/tc clock_off bits Lucas De Marchi
@ 2019-07-16 22:41 ` Srivatsa, Anusha
2019-07-18 21:09 ` Atwood, Matthew S
1 sibling, 0 replies; 64+ messages in thread
From: Srivatsa, Anusha @ 2019-07-16 22:41 UTC (permalink / raw)
To: De Marchi, Lucas, intel-gfx; +Cc: Mahesh Kumar
>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>Lucas De Marchi
>Sent: Friday, July 12, 2019 6:09 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Mahesh Kumar <mahesh1.kumar@intel.com>
>Subject: [Intel-gfx] [PATCH 03/22] drm/i915/tgl: update ddi/tc clock_off bits
>
>From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
>In GEN 12 PORT_C DDI clk_off bit is not equally distanced to A/B, it's at offset 24.
>Similarly TC port (5/6) clk off bits are at offset 22/23. Extend the macros to cover
>the additional ports.
>
>Cc: Matt Roper <matthew.d.roper@intel.com>
>Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Checked with spec, looks good.
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>---
> drivers/gpu/drm/i915/i915_reg.h | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index def71fd2e4d1..d873d9fbbf0e 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -9749,8 +9749,9 @@ enum skl_power_gate {
>
> #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
> #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11,
>24))
>-#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) ==
>PORT_TC4 ? \
>- 21 : (tc_port) + 12))
>+#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) <
>PORT_TC4 ? \
>+ (tc_port) + 12 : \
>+ (tc_port) - PORT_TC4 + 21))
> #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
> #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 <<
>ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) <<
>ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 03/22] drm/i915/tgl: update ddi/tc clock_off bits
2019-07-13 1:09 ` [PATCH 03/22] drm/i915/tgl: update ddi/tc clock_off bits Lucas De Marchi
2019-07-16 22:41 ` Srivatsa, Anusha
@ 2019-07-18 21:09 ` Atwood, Matthew S
1 sibling, 0 replies; 64+ messages in thread
From: Atwood, Matthew S @ 2019-07-18 21:09 UTC (permalink / raw)
To: intel-gfx, De Marchi, Lucas; +Cc: mahesh1.kumar
On Fri, 2019-07-12 at 18:09 -0700, Lucas De Marchi wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
> In GEN 12 PORT_C DDI clk_off bit is not equally distanced to A/B,
> it's at offset 24. Similarly TC port (5/6) clk off bits are at
> offset 22/23. Extend the macros to cover the additional ports.
>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index def71fd2e4d1..d873d9fbbf0e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9749,8 +9749,9 @@ enum skl_power_gate {
>
> #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
> #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10,
> 11, 24))
> -#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) ==
> PORT_TC4 ? \
> - 21 : (tc_port) +
> 12))
> +#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 <<
> ((tc_port) < PORT_TC4 ? \
> + (tc_port) + 12 :
> \
> + (tc_port) -
> PORT_TC4 + 21))
> #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
> #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 <<
> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) <<
> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 04/22] drm/i915/tgl: Add hpd interrupt handling
2019-07-13 1:09 [PATCH 00/22] Tiger Lake part 2 Lucas De Marchi
` (2 preceding siblings ...)
2019-07-13 1:09 ` [PATCH 03/22] drm/i915/tgl: update ddi/tc clock_off bits Lucas De Marchi
@ 2019-07-13 1:09 ` Lucas De Marchi
2019-07-19 13:47 ` Ville Syrjälä
2019-07-13 1:09 ` [PATCH 05/22] drm/i915/tgl: Update north display hotplug detection to TGL connections Lucas De Marchi
` (23 subsequent siblings)
27 siblings, 1 reply; 64+ messages in thread
From: Lucas De Marchi @ 2019-07-13 1:09 UTC (permalink / raw)
To: intel-gfx
Add hotdplug detection for all ports on TGP. icp_hpd_detection_setup()
is refactored to be shared with TGP.
While we increase the number of pins, add a BUILD_BUG_ON() to avoid
going over the number of bits allowed.
Cc: Jose Souza <jose.souza@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_hotplug.c | 6 +
drivers/gpu/drm/i915/i915_drv.h | 4 +
drivers/gpu/drm/i915/i915_irq.c | 128 +++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 28 +++-
4 files changed, 154 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
index ea3de4acc850..a7833f45dc4d 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -104,6 +104,12 @@ enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
if (IS_CNL_WITH_PORT_F(dev_priv))
return HPD_PORT_E;
return HPD_PORT_F;
+ case PORT_G:
+ return HPD_PORT_G;
+ case PORT_H:
+ return HPD_PORT_H;
+ case PORT_I:
+ return HPD_PORT_I;
default:
MISSING_CASE(port);
return HPD_NONE;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cf7e92ca72e9..069337f11872 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -153,6 +153,10 @@ enum hpd_pin {
HPD_PORT_D,
HPD_PORT_E,
HPD_PORT_F,
+ HPD_PORT_G,
+ HPD_PORT_H,
+ HPD_PORT_I,
+
HPD_NUM_PINS
};
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7c5ba5cbea34..a7a90674db89 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -148,6 +148,18 @@ static const u32 hpd_mcc[HPD_NUM_PINS] = {
[HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP
};
+static const u32 hpd_tgp[HPD_NUM_PINS] = {
+ [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
+ [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
+ [HPD_PORT_C] = SDE_DDIC_HOTPLUG_TGP,
+ [HPD_PORT_D] = SDE_TC1_HOTPLUG_ICP,
+ [HPD_PORT_E] = SDE_TC2_HOTPLUG_ICP,
+ [HPD_PORT_F] = SDE_TC3_HOTPLUG_ICP,
+ [HPD_PORT_G] = SDE_TC4_HOTPLUG_ICP,
+ [HPD_PORT_H] = SDE_TC5_HOTPLUG_TGP,
+ [HPD_PORT_I] = SDE_TC6_HOTPLUG_TGP,
+};
+
static void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
i915_reg_t iir, i915_reg_t ier)
{
@@ -1706,6 +1718,40 @@ static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
}
}
+static bool tgp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
+{
+ switch (pin) {
+ case HPD_PORT_A:
+ return val & ICP_DDIA_HPD_LONG_DETECT;
+ case HPD_PORT_B:
+ return val & ICP_DDIB_HPD_LONG_DETECT;
+ case HPD_PORT_C:
+ return val & TGP_DDIC_HPD_LONG_DETECT;
+ default:
+ return false;
+ }
+}
+
+static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
+{
+ switch (pin) {
+ case HPD_PORT_D:
+ return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
+ case HPD_PORT_E:
+ return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
+ case HPD_PORT_F:
+ return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
+ case HPD_PORT_G:
+ return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
+ case HPD_PORT_H:
+ return val & ICP_TC_HPD_LONG_DETECT(PORT_TC5);
+ case HPD_PORT_I:
+ return val & ICP_TC_HPD_LONG_DETECT(PORT_TC6);
+ default:
+ return false;
+ }
+}
+
static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
{
switch (pin) {
@@ -1785,6 +1831,8 @@ static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
{
enum hpd_pin pin;
+ BUILD_BUG_ON(sizeof(int) * 8 < HPD_NUM_PINS);
+
for_each_hpd_pin(pin) {
if ((hpd[pin] & hotplug_trigger) == 0)
continue;
@@ -2549,6 +2597,43 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir,
gmbus_irq_handler(dev_priv);
}
+static void tgp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
+{
+ u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
+ u32 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
+ u32 pin_mask = 0, long_mask = 0;
+
+ if (ddi_hotplug_trigger) {
+ u32 dig_hotplug_reg;
+
+ dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
+ I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
+
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ ddi_hotplug_trigger,
+ dig_hotplug_reg, hpd_tgp,
+ tgp_ddi_port_hotplug_long_detect);
+ }
+
+ if (tc_hotplug_trigger) {
+ u32 dig_hotplug_reg;
+
+ dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
+ I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
+
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ tc_hotplug_trigger,
+ dig_hotplug_reg, hpd_tgp,
+ tgp_tc_port_hotplug_long_detect);
+ }
+
+ if (pin_mask)
+ intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
+
+ if (pch_iir & SDE_GMBUS_ICP)
+ gmbus_irq_handler(dev_priv);
+}
+
static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
{
u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
@@ -2968,7 +3053,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
I915_WRITE(SDEIIR, iir);
ret = IRQ_HANDLED;
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_MCC)
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
+ tgp_irq_handler(dev_priv, iir);
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MCC)
icp_irq_handler(dev_priv, iir, hpd_mcc);
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
icp_irq_handler(dev_priv, iir, hpd_icp);
@@ -3765,20 +3852,18 @@ static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
ibx_hpd_detection_setup(dev_priv);
}
-static void icp_hpd_detection_setup(struct drm_i915_private *dev_priv)
+static void icp_hpd_detection_setup(struct drm_i915_private *dev_priv,
+ u32 ddi_hotplug_enable_mask,
+ u32 tc_hotplug_enable_mask)
{
u32 hotplug;
hotplug = I915_READ(SHOTPLUG_CTL_DDI);
- hotplug |= ICP_DDIA_HPD_ENABLE |
- ICP_DDIB_HPD_ENABLE;
+ hotplug |= ddi_hotplug_enable_mask;
I915_WRITE(SHOTPLUG_CTL_DDI, hotplug);
hotplug = I915_READ(SHOTPLUG_CTL_TC);
- hotplug |= ICP_TC_HPD_ENABLE(PORT_TC1) |
- ICP_TC_HPD_ENABLE(PORT_TC2) |
- ICP_TC_HPD_ENABLE(PORT_TC3) |
- ICP_TC_HPD_ENABLE(PORT_TC4);
+ hotplug |= tc_hotplug_enable_mask;
I915_WRITE(SHOTPLUG_CTL_TC, hotplug);
}
@@ -3791,7 +3876,21 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
- icp_hpd_detection_setup(dev_priv);
+ icp_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK,
+ ICP_TC_HPD_ENABLE_MASK);
+}
+
+static void tgp_hpd_irq_setup(struct drm_i915_private *dev_priv)
+{
+ u32 hotplug_irqs, enabled_irqs;
+
+ hotplug_irqs = SDE_DDI_MASK_TGP | SDE_TC_MASK_TGP;
+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_tgp);
+
+ ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
+
+ icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK,
+ TGP_TC_HPD_ENABLE_MASK);
}
static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
@@ -3828,7 +3927,9 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
gen11_hpd_detection_setup(dev_priv);
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
+ tgp_hpd_irq_setup(dev_priv);
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
icp_hpd_irq_setup(dev_priv);
}
@@ -4278,7 +4379,12 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
I915_WRITE(SDEIMR, ~mask);
- icp_hpd_detection_setup(dev_priv);
+ if (HAS_PCH_TGP(dev_priv))
+ icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK,
+ TGP_TC_HPD_ENABLE_MASK);
+ else
+ icp_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK,
+ ICP_TC_HPD_ENABLE_MASK);
}
static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d873d9fbbf0e..fbc5146a5931 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7868,12 +7868,15 @@ enum {
SDE_FDI_RXB_CPT | \
SDE_FDI_RXA_CPT)
-/* south display engine interrupt: ICP */
+/* south display engine interrupt: ICP/TGP */
+#define SDE_TC6_HOTPLUG_TGP (1 << 29)
+#define SDE_TC5_HOTPLUG_TGP (1 << 28)
#define SDE_TC4_HOTPLUG_ICP (1 << 27)
#define SDE_TC3_HOTPLUG_ICP (1 << 26)
#define SDE_TC2_HOTPLUG_ICP (1 << 25)
#define SDE_TC1_HOTPLUG_ICP (1 << 24)
#define SDE_GMBUS_ICP (1 << 23)
+#define SDE_DDIC_HOTPLUG_TGP (1 << 18)
#define SDE_DDIB_HOTPLUG_ICP (1 << 17)
#define SDE_DDIA_HOTPLUG_ICP (1 << 16)
#define SDE_TC_HOTPLUG_ICP(tc_port) (1 << ((tc_port) + 24))
@@ -7884,6 +7887,11 @@ enum {
SDE_TC3_HOTPLUG_ICP | \
SDE_TC2_HOTPLUG_ICP | \
SDE_TC1_HOTPLUG_ICP)
+#define SDE_DDI_MASK_TGP (SDE_DDIC_HOTPLUG_TGP | \
+ SDE_DDI_MASK_ICP)
+#define SDE_TC_MASK_TGP (SDE_TC6_HOTPLUG_TGP | \
+ SDE_TC5_HOTPLUG_TGP | \
+ SDE_TC_MASK_ICP)
#define SDEISR _MMIO(0xc4000)
#define SDEIMR _MMIO(0xc4004)
@@ -7951,6 +7959,12 @@ enum {
*/
#define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
+#define TGP_DDIC_HPD_ENABLE (1 << 11)
+#define TGP_DDIC_HPD_STATUS_MASK (3 << 8)
+#define TGP_DDIC_HPD_NO_DETECT (0 << 8)
+#define TGP_DDIC_HPD_SHORT_DETECT (1 << 8)
+#define TGP_DDIC_HPD_LONG_DETECT (2 << 8)
+#define TGP_DDIC_HPD_SHORT_LONG_DETECT (3 << 8)
#define ICP_DDIB_HPD_ENABLE (1 << 7)
#define ICP_DDIB_HPD_STATUS_MASK (3 << 4)
#define ICP_DDIB_HPD_NO_DETECT (0 << 4)
@@ -8074,6 +8088,18 @@ enum {
#define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
#define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
+#define ICP_DDI_HPD_ENABLE_MASK (ICP_DDIB_HPD_ENABLE | \
+ ICP_DDIA_HPD_ENABLE)
+#define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC4) | \
+ ICP_TC_HPD_ENABLE(PORT_TC3) | \
+ ICP_TC_HPD_ENABLE(PORT_TC2) | \
+ ICP_TC_HPD_ENABLE(PORT_TC1))
+#define TGP_DDI_HPD_ENABLE_MASK (TGP_DDIC_HPD_ENABLE | \
+ ICP_DDI_HPD_ENABLE_MASK)
+#define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC6) | \
+ ICP_TC_HPD_ENABLE(PORT_TC5) | \
+ ICP_TC_HPD_ENABLE_MASK)
+
#define _PCH_DPLL_A 0xc6014
#define _PCH_DPLL_B 0xc6018
#define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
--
2.21.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 04/22] drm/i915/tgl: Add hpd interrupt handling
2019-07-13 1:09 ` [PATCH 04/22] drm/i915/tgl: Add hpd interrupt handling Lucas De Marchi
@ 2019-07-19 13:47 ` Ville Syrjälä
2019-07-19 16:45 ` Lucas De Marchi
0 siblings, 1 reply; 64+ messages in thread
From: Ville Syrjälä @ 2019-07-19 13:47 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Fri, Jul 12, 2019 at 06:09:22PM -0700, Lucas De Marchi wrote:
> Add hotdplug detection for all ports on TGP. icp_hpd_detection_setup()
> is refactored to be shared with TGP.
>
> While we increase the number of pins, add a BUILD_BUG_ON() to avoid
> going over the number of bits allowed.
>
> Cc: Jose Souza <jose.souza@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_hotplug.c | 6 +
> drivers/gpu/drm/i915/i915_drv.h | 4 +
> drivers/gpu/drm/i915/i915_irq.c | 128 +++++++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 28 +++-
> 4 files changed, 154 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
> index ea3de4acc850..a7833f45dc4d 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> @@ -104,6 +104,12 @@ enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
> if (IS_CNL_WITH_PORT_F(dev_priv))
> return HPD_PORT_E;
> return HPD_PORT_F;
> + case PORT_G:
> + return HPD_PORT_G;
> + case PORT_H:
> + return HPD_PORT_H;
> + case PORT_I:
> + return HPD_PORT_I;
> default:
> MISSING_CASE(port);
> return HPD_NONE;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index cf7e92ca72e9..069337f11872 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -153,6 +153,10 @@ enum hpd_pin {
> HPD_PORT_D,
> HPD_PORT_E,
> HPD_PORT_F,
> + HPD_PORT_G,
> + HPD_PORT_H,
> + HPD_PORT_I,
> +
> HPD_NUM_PINS
> };
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 7c5ba5cbea34..a7a90674db89 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -148,6 +148,18 @@ static const u32 hpd_mcc[HPD_NUM_PINS] = {
> [HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP
> };
>
> +static const u32 hpd_tgp[HPD_NUM_PINS] = {
> + [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
> + [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
> + [HPD_PORT_C] = SDE_DDIC_HOTPLUG_TGP,
> + [HPD_PORT_D] = SDE_TC1_HOTPLUG_ICP,
> + [HPD_PORT_E] = SDE_TC2_HOTPLUG_ICP,
> + [HPD_PORT_F] = SDE_TC3_HOTPLUG_ICP,
> + [HPD_PORT_G] = SDE_TC4_HOTPLUG_ICP,
> + [HPD_PORT_H] = SDE_TC5_HOTPLUG_TGP,
> + [HPD_PORT_I] = SDE_TC6_HOTPLUG_TGP,
> +};
> +
> static void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
> i915_reg_t iir, i915_reg_t ier)
> {
> @@ -1706,6 +1718,40 @@ static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
> }
> }
>
> +static bool tgp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
> +{
> + switch (pin) {
> + case HPD_PORT_A:
> + return val & ICP_DDIA_HPD_LONG_DETECT;
> + case HPD_PORT_B:
> + return val & ICP_DDIB_HPD_LONG_DETECT;
> + case HPD_PORT_C:
> + return val & TGP_DDIC_HPD_LONG_DETECT;
> + default:
> + return false;
> + }
> +}
> +
> +static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
> +{
> + switch (pin) {
> + case HPD_PORT_D:
> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
> + case HPD_PORT_E:
> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
> + case HPD_PORT_F:
> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
> + case HPD_PORT_G:
> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
> + case HPD_PORT_H:
> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC5);
> + case HPD_PORT_I:
> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC6);
> + default:
> + return false;
> + }
> +}
> +
> static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
> {
> switch (pin) {
> @@ -1785,6 +1831,8 @@ static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
> {
> enum hpd_pin pin;
>
> + BUILD_BUG_ON(sizeof(int) * 8 < HPD_NUM_PINS);
BUILD_BUG_ON(HPD_NUM_PINS > BITS_PER_TYPE(*pin_mask));
would be a clearer way to express that.
--
Ville Syrjälä
Intel
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 04/22] drm/i915/tgl: Add hpd interrupt handling
2019-07-19 13:47 ` Ville Syrjälä
@ 2019-07-19 16:45 ` Lucas De Marchi
2019-07-19 17:08 ` Ville Syrjälä
0 siblings, 1 reply; 64+ messages in thread
From: Lucas De Marchi @ 2019-07-19 16:45 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Fri, Jul 19, 2019 at 04:47:45PM +0300, Ville Syrjälä wrote:
>On Fri, Jul 12, 2019 at 06:09:22PM -0700, Lucas De Marchi wrote:
>> Add hotdplug detection for all ports on TGP. icp_hpd_detection_setup()
>> is refactored to be shared with TGP.
>>
>> While we increase the number of pins, add a BUILD_BUG_ON() to avoid
>> going over the number of bits allowed.
>>
>> Cc: Jose Souza <jose.souza@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_hotplug.c | 6 +
>> drivers/gpu/drm/i915/i915_drv.h | 4 +
>> drivers/gpu/drm/i915/i915_irq.c | 128 +++++++++++++++++--
>> drivers/gpu/drm/i915/i915_reg.h | 28 +++-
>> 4 files changed, 154 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
>> index ea3de4acc850..a7833f45dc4d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
>> +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
>> @@ -104,6 +104,12 @@ enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
>> if (IS_CNL_WITH_PORT_F(dev_priv))
>> return HPD_PORT_E;
>> return HPD_PORT_F;
>> + case PORT_G:
>> + return HPD_PORT_G;
>> + case PORT_H:
>> + return HPD_PORT_H;
>> + case PORT_I:
>> + return HPD_PORT_I;
>> default:
>> MISSING_CASE(port);
>> return HPD_NONE;
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index cf7e92ca72e9..069337f11872 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -153,6 +153,10 @@ enum hpd_pin {
>> HPD_PORT_D,
>> HPD_PORT_E,
>> HPD_PORT_F,
>> + HPD_PORT_G,
>> + HPD_PORT_H,
>> + HPD_PORT_I,
>> +
>> HPD_NUM_PINS
>> };
>>
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> index 7c5ba5cbea34..a7a90674db89 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -148,6 +148,18 @@ static const u32 hpd_mcc[HPD_NUM_PINS] = {
>> [HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP
>> };
>>
>> +static const u32 hpd_tgp[HPD_NUM_PINS] = {
>> + [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
>> + [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
>> + [HPD_PORT_C] = SDE_DDIC_HOTPLUG_TGP,
>> + [HPD_PORT_D] = SDE_TC1_HOTPLUG_ICP,
>> + [HPD_PORT_E] = SDE_TC2_HOTPLUG_ICP,
>> + [HPD_PORT_F] = SDE_TC3_HOTPLUG_ICP,
>> + [HPD_PORT_G] = SDE_TC4_HOTPLUG_ICP,
>> + [HPD_PORT_H] = SDE_TC5_HOTPLUG_TGP,
>> + [HPD_PORT_I] = SDE_TC6_HOTPLUG_TGP,
>> +};
>> +
>> static void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
>> i915_reg_t iir, i915_reg_t ier)
>> {
>> @@ -1706,6 +1718,40 @@ static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
>> }
>> }
>>
>> +static bool tgp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
>> +{
>> + switch (pin) {
>> + case HPD_PORT_A:
>> + return val & ICP_DDIA_HPD_LONG_DETECT;
>> + case HPD_PORT_B:
>> + return val & ICP_DDIB_HPD_LONG_DETECT;
>> + case HPD_PORT_C:
>> + return val & TGP_DDIC_HPD_LONG_DETECT;
>> + default:
>> + return false;
>> + }
>> +}
>> +
>> +static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
>> +{
>> + switch (pin) {
>> + case HPD_PORT_D:
>> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
>> + case HPD_PORT_E:
>> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
>> + case HPD_PORT_F:
>> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
>> + case HPD_PORT_G:
>> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
>> + case HPD_PORT_H:
>> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC5);
>> + case HPD_PORT_I:
>> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC6);
>> + default:
>> + return false;
>> + }
>> +}
>> +
>> static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
>> {
>> switch (pin) {
>> @@ -1785,6 +1831,8 @@ static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
>> {
>> enum hpd_pin pin;
>>
>> + BUILD_BUG_ON(sizeof(int) * 8 < HPD_NUM_PINS);
>
>BUILD_BUG_ON(HPD_NUM_PINS > BITS_PER_TYPE(*pin_mask));
>would be a clearer way to express that.
For the BITS_PER_TYPE, ok. But for the swapped order, checkpatch doesn't
agree:
8b77abf61be2 (HEAD) drm/i915/tgl: Add hpd interrupt handling
-:117: WARNING:CONSTANT_COMPARISON: Comparisons should place the constant on the right side of the test
#117: FILE: drivers/gpu/drm/i915/i915_irq.c:1852:
+ BUILD_BUG_ON(HPD_NUM_PINS > BITS_PER_TYPE(*pin_mask));
Note: Initially I did with the same order you suggested and had to swap
it while cleaning up the checkpatch warnings.
Lucas De Marchi
>
>--
>Ville Syrjälä
>Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 04/22] drm/i915/tgl: Add hpd interrupt handling
2019-07-19 16:45 ` Lucas De Marchi
@ 2019-07-19 17:08 ` Ville Syrjälä
2019-07-19 17:14 ` Ville Syrjälä
0 siblings, 1 reply; 64+ messages in thread
From: Ville Syrjälä @ 2019-07-19 17:08 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Fri, Jul 19, 2019 at 09:45:16AM -0700, Lucas De Marchi wrote:
> On Fri, Jul 19, 2019 at 04:47:45PM +0300, Ville Syrjälä wrote:
> >On Fri, Jul 12, 2019 at 06:09:22PM -0700, Lucas De Marchi wrote:
> >> Add hotdplug detection for all ports on TGP. icp_hpd_detection_setup()
> >> is refactored to be shared with TGP.
> >>
> >> While we increase the number of pins, add a BUILD_BUG_ON() to avoid
> >> going over the number of bits allowed.
> >>
> >> Cc: Jose Souza <jose.souza@intel.com>
> >> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/display/intel_hotplug.c | 6 +
> >> drivers/gpu/drm/i915/i915_drv.h | 4 +
> >> drivers/gpu/drm/i915/i915_irq.c | 128 +++++++++++++++++--
> >> drivers/gpu/drm/i915/i915_reg.h | 28 +++-
> >> 4 files changed, 154 insertions(+), 12 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
> >> index ea3de4acc850..a7833f45dc4d 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> >> @@ -104,6 +104,12 @@ enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
> >> if (IS_CNL_WITH_PORT_F(dev_priv))
> >> return HPD_PORT_E;
> >> return HPD_PORT_F;
> >> + case PORT_G:
> >> + return HPD_PORT_G;
> >> + case PORT_H:
> >> + return HPD_PORT_H;
> >> + case PORT_I:
> >> + return HPD_PORT_I;
> >> default:
> >> MISSING_CASE(port);
> >> return HPD_NONE;
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> >> index cf7e92ca72e9..069337f11872 100644
> >> --- a/drivers/gpu/drm/i915/i915_drv.h
> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> @@ -153,6 +153,10 @@ enum hpd_pin {
> >> HPD_PORT_D,
> >> HPD_PORT_E,
> >> HPD_PORT_F,
> >> + HPD_PORT_G,
> >> + HPD_PORT_H,
> >> + HPD_PORT_I,
> >> +
> >> HPD_NUM_PINS
> >> };
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> >> index 7c5ba5cbea34..a7a90674db89 100644
> >> --- a/drivers/gpu/drm/i915/i915_irq.c
> >> +++ b/drivers/gpu/drm/i915/i915_irq.c
> >> @@ -148,6 +148,18 @@ static const u32 hpd_mcc[HPD_NUM_PINS] = {
> >> [HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP
> >> };
> >>
> >> +static const u32 hpd_tgp[HPD_NUM_PINS] = {
> >> + [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
> >> + [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
> >> + [HPD_PORT_C] = SDE_DDIC_HOTPLUG_TGP,
> >> + [HPD_PORT_D] = SDE_TC1_HOTPLUG_ICP,
> >> + [HPD_PORT_E] = SDE_TC2_HOTPLUG_ICP,
> >> + [HPD_PORT_F] = SDE_TC3_HOTPLUG_ICP,
> >> + [HPD_PORT_G] = SDE_TC4_HOTPLUG_ICP,
> >> + [HPD_PORT_H] = SDE_TC5_HOTPLUG_TGP,
> >> + [HPD_PORT_I] = SDE_TC6_HOTPLUG_TGP,
> >> +};
> >> +
> >> static void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
> >> i915_reg_t iir, i915_reg_t ier)
> >> {
> >> @@ -1706,6 +1718,40 @@ static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
> >> }
> >> }
> >>
> >> +static bool tgp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
> >> +{
> >> + switch (pin) {
> >> + case HPD_PORT_A:
> >> + return val & ICP_DDIA_HPD_LONG_DETECT;
> >> + case HPD_PORT_B:
> >> + return val & ICP_DDIB_HPD_LONG_DETECT;
> >> + case HPD_PORT_C:
> >> + return val & TGP_DDIC_HPD_LONG_DETECT;
> >> + default:
> >> + return false;
> >> + }
> >> +}
> >> +
> >> +static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
> >> +{
> >> + switch (pin) {
> >> + case HPD_PORT_D:
> >> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
> >> + case HPD_PORT_E:
> >> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
> >> + case HPD_PORT_F:
> >> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
> >> + case HPD_PORT_G:
> >> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
> >> + case HPD_PORT_H:
> >> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC5);
> >> + case HPD_PORT_I:
> >> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC6);
> >> + default:
> >> + return false;
> >> + }
> >> +}
> >> +
> >> static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
> >> {
> >> switch (pin) {
> >> @@ -1785,6 +1831,8 @@ static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
> >> {
> >> enum hpd_pin pin;
> >>
> >> + BUILD_BUG_ON(sizeof(int) * 8 < HPD_NUM_PINS);
> >
> >BUILD_BUG_ON(HPD_NUM_PINS > BITS_PER_TYPE(*pin_mask));
> >would be a clearer way to express that.
>
> For the BITS_PER_TYPE, ok. But for the swapped order, checkpatch doesn't
> agree:
>
> 8b77abf61be2 (HEAD) drm/i915/tgl: Add hpd interrupt handling
> -:117: WARNING:CONSTANT_COMPARISON: Comparisons should place the constant on the right side of the test
> #117: FILE: drivers/gpu/drm/i915/i915_irq.c:1852:
> + BUILD_BUG_ON(HPD_NUM_PINS > BITS_PER_TYPE(*pin_mask));
>
> Note: Initially I did with the same order you suggested and had to swap
> it while cleaning up the checkpatch warnings.
Checkpatch is stupid. HPD_NUM_PINS is clearly the "variable" we're trying
to check here, not the constant we're checking against.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 04/22] drm/i915/tgl: Add hpd interrupt handling
2019-07-19 17:08 ` Ville Syrjälä
@ 2019-07-19 17:14 ` Ville Syrjälä
2019-07-19 17:28 ` Lucas De Marchi
0 siblings, 1 reply; 64+ messages in thread
From: Ville Syrjälä @ 2019-07-19 17:14 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Fri, Jul 19, 2019 at 08:08:47PM +0300, Ville Syrjälä wrote:
> On Fri, Jul 19, 2019 at 09:45:16AM -0700, Lucas De Marchi wrote:
> > On Fri, Jul 19, 2019 at 04:47:45PM +0300, Ville Syrjälä wrote:
> > >On Fri, Jul 12, 2019 at 06:09:22PM -0700, Lucas De Marchi wrote:
> > >> Add hotdplug detection for all ports on TGP. icp_hpd_detection_setup()
> > >> is refactored to be shared with TGP.
> > >>
> > >> While we increase the number of pins, add a BUILD_BUG_ON() to avoid
> > >> going over the number of bits allowed.
> > >>
> > >> Cc: Jose Souza <jose.souza@intel.com>
> > >> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > >> ---
> > >> drivers/gpu/drm/i915/display/intel_hotplug.c | 6 +
> > >> drivers/gpu/drm/i915/i915_drv.h | 4 +
> > >> drivers/gpu/drm/i915/i915_irq.c | 128 +++++++++++++++++--
> > >> drivers/gpu/drm/i915/i915_reg.h | 28 +++-
> > >> 4 files changed, 154 insertions(+), 12 deletions(-)
> > >>
> > >> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
> > >> index ea3de4acc850..a7833f45dc4d 100644
> > >> --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> > >> +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> > >> @@ -104,6 +104,12 @@ enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
> > >> if (IS_CNL_WITH_PORT_F(dev_priv))
> > >> return HPD_PORT_E;
> > >> return HPD_PORT_F;
> > >> + case PORT_G:
> > >> + return HPD_PORT_G;
> > >> + case PORT_H:
> > >> + return HPD_PORT_H;
> > >> + case PORT_I:
> > >> + return HPD_PORT_I;
> > >> default:
> > >> MISSING_CASE(port);
> > >> return HPD_NONE;
> > >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > >> index cf7e92ca72e9..069337f11872 100644
> > >> --- a/drivers/gpu/drm/i915/i915_drv.h
> > >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> > >> @@ -153,6 +153,10 @@ enum hpd_pin {
> > >> HPD_PORT_D,
> > >> HPD_PORT_E,
> > >> HPD_PORT_F,
> > >> + HPD_PORT_G,
> > >> + HPD_PORT_H,
> > >> + HPD_PORT_I,
> > >> +
> > >> HPD_NUM_PINS
> > >> };
> > >>
> > >> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > >> index 7c5ba5cbea34..a7a90674db89 100644
> > >> --- a/drivers/gpu/drm/i915/i915_irq.c
> > >> +++ b/drivers/gpu/drm/i915/i915_irq.c
> > >> @@ -148,6 +148,18 @@ static const u32 hpd_mcc[HPD_NUM_PINS] = {
> > >> [HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP
> > >> };
> > >>
> > >> +static const u32 hpd_tgp[HPD_NUM_PINS] = {
> > >> + [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
> > >> + [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
> > >> + [HPD_PORT_C] = SDE_DDIC_HOTPLUG_TGP,
> > >> + [HPD_PORT_D] = SDE_TC1_HOTPLUG_ICP,
> > >> + [HPD_PORT_E] = SDE_TC2_HOTPLUG_ICP,
> > >> + [HPD_PORT_F] = SDE_TC3_HOTPLUG_ICP,
> > >> + [HPD_PORT_G] = SDE_TC4_HOTPLUG_ICP,
> > >> + [HPD_PORT_H] = SDE_TC5_HOTPLUG_TGP,
> > >> + [HPD_PORT_I] = SDE_TC6_HOTPLUG_TGP,
> > >> +};
> > >> +
> > >> static void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
> > >> i915_reg_t iir, i915_reg_t ier)
> > >> {
> > >> @@ -1706,6 +1718,40 @@ static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
> > >> }
> > >> }
> > >>
> > >> +static bool tgp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
> > >> +{
> > >> + switch (pin) {
> > >> + case HPD_PORT_A:
> > >> + return val & ICP_DDIA_HPD_LONG_DETECT;
> > >> + case HPD_PORT_B:
> > >> + return val & ICP_DDIB_HPD_LONG_DETECT;
> > >> + case HPD_PORT_C:
> > >> + return val & TGP_DDIC_HPD_LONG_DETECT;
> > >> + default:
> > >> + return false;
> > >> + }
> > >> +}
> > >> +
> > >> +static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
> > >> +{
> > >> + switch (pin) {
> > >> + case HPD_PORT_D:
> > >> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
> > >> + case HPD_PORT_E:
> > >> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
> > >> + case HPD_PORT_F:
> > >> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
> > >> + case HPD_PORT_G:
> > >> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
> > >> + case HPD_PORT_H:
> > >> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC5);
> > >> + case HPD_PORT_I:
> > >> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC6);
> > >> + default:
> > >> + return false;
> > >> + }
> > >> +}
> > >> +
> > >> static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
> > >> {
> > >> switch (pin) {
> > >> @@ -1785,6 +1831,8 @@ static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
> > >> {
> > >> enum hpd_pin pin;
> > >>
> > >> + BUILD_BUG_ON(sizeof(int) * 8 < HPD_NUM_PINS);
> > >
> > >BUILD_BUG_ON(HPD_NUM_PINS > BITS_PER_TYPE(*pin_mask));
> > >would be a clearer way to express that.
> >
> > For the BITS_PER_TYPE, ok. But for the swapped order, checkpatch doesn't
> > agree:
> >
> > 8b77abf61be2 (HEAD) drm/i915/tgl: Add hpd interrupt handling
> > -:117: WARNING:CONSTANT_COMPARISON: Comparisons should place the constant on the right side of the test
> > #117: FILE: drivers/gpu/drm/i915/i915_irq.c:1852:
> > + BUILD_BUG_ON(HPD_NUM_PINS > BITS_PER_TYPE(*pin_mask));
> >
> > Note: Initially I did with the same order you suggested and had to swap
> > it while cleaning up the checkpatch warnings.
>
> Checkpatch is stupid. HPD_NUM_PINS is clearly the "variable" we're trying
> to check here, not the constant we're checking against.
Well, I guess you can argue either way. But this is the way my brain
wants to read this :)
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 04/22] drm/i915/tgl: Add hpd interrupt handling
2019-07-19 17:14 ` Ville Syrjälä
@ 2019-07-19 17:28 ` Lucas De Marchi
0 siblings, 0 replies; 64+ messages in thread
From: Lucas De Marchi @ 2019-07-19 17:28 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Fri, Jul 19, 2019 at 08:14:40PM +0300, Ville Syrjälä wrote:
>On Fri, Jul 19, 2019 at 08:08:47PM +0300, Ville Syrjälä wrote:
>> On Fri, Jul 19, 2019 at 09:45:16AM -0700, Lucas De Marchi wrote:
>> > On Fri, Jul 19, 2019 at 04:47:45PM +0300, Ville Syrjälä wrote:
>> > >On Fri, Jul 12, 2019 at 06:09:22PM -0700, Lucas De Marchi wrote:
>> > >> Add hotdplug detection for all ports on TGP. icp_hpd_detection_setup()
>> > >> is refactored to be shared with TGP.
>> > >>
>> > >> While we increase the number of pins, add a BUILD_BUG_ON() to avoid
>> > >> going over the number of bits allowed.
>> > >>
>> > >> Cc: Jose Souza <jose.souza@intel.com>
>> > >> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> > >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> > >> ---
>> > >> drivers/gpu/drm/i915/display/intel_hotplug.c | 6 +
>> > >> drivers/gpu/drm/i915/i915_drv.h | 4 +
>> > >> drivers/gpu/drm/i915/i915_irq.c | 128 +++++++++++++++++--
>> > >> drivers/gpu/drm/i915/i915_reg.h | 28 +++-
>> > >> 4 files changed, 154 insertions(+), 12 deletions(-)
>> > >>
>> > >> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
>> > >> index ea3de4acc850..a7833f45dc4d 100644
>> > >> --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
>> > >> +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
>> > >> @@ -104,6 +104,12 @@ enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
>> > >> if (IS_CNL_WITH_PORT_F(dev_priv))
>> > >> return HPD_PORT_E;
>> > >> return HPD_PORT_F;
>> > >> + case PORT_G:
>> > >> + return HPD_PORT_G;
>> > >> + case PORT_H:
>> > >> + return HPD_PORT_H;
>> > >> + case PORT_I:
>> > >> + return HPD_PORT_I;
>> > >> default:
>> > >> MISSING_CASE(port);
>> > >> return HPD_NONE;
>> > >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> > >> index cf7e92ca72e9..069337f11872 100644
>> > >> --- a/drivers/gpu/drm/i915/i915_drv.h
>> > >> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> > >> @@ -153,6 +153,10 @@ enum hpd_pin {
>> > >> HPD_PORT_D,
>> > >> HPD_PORT_E,
>> > >> HPD_PORT_F,
>> > >> + HPD_PORT_G,
>> > >> + HPD_PORT_H,
>> > >> + HPD_PORT_I,
>> > >> +
>> > >> HPD_NUM_PINS
>> > >> };
>> > >>
>> > >> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> > >> index 7c5ba5cbea34..a7a90674db89 100644
>> > >> --- a/drivers/gpu/drm/i915/i915_irq.c
>> > >> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> > >> @@ -148,6 +148,18 @@ static const u32 hpd_mcc[HPD_NUM_PINS] = {
>> > >> [HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP
>> > >> };
>> > >>
>> > >> +static const u32 hpd_tgp[HPD_NUM_PINS] = {
>> > >> + [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
>> > >> + [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
>> > >> + [HPD_PORT_C] = SDE_DDIC_HOTPLUG_TGP,
>> > >> + [HPD_PORT_D] = SDE_TC1_HOTPLUG_ICP,
>> > >> + [HPD_PORT_E] = SDE_TC2_HOTPLUG_ICP,
>> > >> + [HPD_PORT_F] = SDE_TC3_HOTPLUG_ICP,
>> > >> + [HPD_PORT_G] = SDE_TC4_HOTPLUG_ICP,
>> > >> + [HPD_PORT_H] = SDE_TC5_HOTPLUG_TGP,
>> > >> + [HPD_PORT_I] = SDE_TC6_HOTPLUG_TGP,
>> > >> +};
>> > >> +
>> > >> static void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
>> > >> i915_reg_t iir, i915_reg_t ier)
>> > >> {
>> > >> @@ -1706,6 +1718,40 @@ static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
>> > >> }
>> > >> }
>> > >>
>> > >> +static bool tgp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
>> > >> +{
>> > >> + switch (pin) {
>> > >> + case HPD_PORT_A:
>> > >> + return val & ICP_DDIA_HPD_LONG_DETECT;
>> > >> + case HPD_PORT_B:
>> > >> + return val & ICP_DDIB_HPD_LONG_DETECT;
>> > >> + case HPD_PORT_C:
>> > >> + return val & TGP_DDIC_HPD_LONG_DETECT;
>> > >> + default:
>> > >> + return false;
>> > >> + }
>> > >> +}
>> > >> +
>> > >> +static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
>> > >> +{
>> > >> + switch (pin) {
>> > >> + case HPD_PORT_D:
>> > >> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
>> > >> + case HPD_PORT_E:
>> > >> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
>> > >> + case HPD_PORT_F:
>> > >> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
>> > >> + case HPD_PORT_G:
>> > >> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
>> > >> + case HPD_PORT_H:
>> > >> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC5);
>> > >> + case HPD_PORT_I:
>> > >> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC6);
>> > >> + default:
>> > >> + return false;
>> > >> + }
>> > >> +}
>> > >> +
>> > >> static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
>> > >> {
>> > >> switch (pin) {
>> > >> @@ -1785,6 +1831,8 @@ static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
>> > >> {
>> > >> enum hpd_pin pin;
>> > >>
>> > >> + BUILD_BUG_ON(sizeof(int) * 8 < HPD_NUM_PINS);
>> > >
>> > >BUILD_BUG_ON(HPD_NUM_PINS > BITS_PER_TYPE(*pin_mask));
>> > >would be a clearer way to express that.
>> >
>> > For the BITS_PER_TYPE, ok. But for the swapped order, checkpatch doesn't
>> > agree:
>> >
>> > 8b77abf61be2 (HEAD) drm/i915/tgl: Add hpd interrupt handling
>> > -:117: WARNING:CONSTANT_COMPARISON: Comparisons should place the constant on the right side of the test
>> > #117: FILE: drivers/gpu/drm/i915/i915_irq.c:1852:
>> > + BUILD_BUG_ON(HPD_NUM_PINS > BITS_PER_TYPE(*pin_mask));
>> >
>> > Note: Initially I did with the same order you suggested and had to swap
>> > it while cleaning up the checkpatch warnings.
>>
>> Checkpatch is stupid. HPD_NUM_PINS is clearly the "variable" we're trying
>> to check here, not the constant we're checking against.
>
>Well, I guess you can argue either way. But this is the way my brain
>wants to read this :)
my brain read it that way, too. Then after reading the warning I
thought: humnn... there's a constant written in stone and one that
depends on the size of that type: maybe I'm wrong and checkpatch is
right. So I changed the order.
Since we both agree prefer HPD_NUM_PINS as a variable, I will
ignore checkpatch here and swap it back.
Lucas De Marchi
>
>--
>Ville Syrjälä
>Intel
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 05/22] drm/i915/tgl: Update north display hotplug detection to TGL connections
2019-07-13 1:09 [PATCH 00/22] Tiger Lake part 2 Lucas De Marchi
` (3 preceding siblings ...)
2019-07-13 1:09 ` [PATCH 04/22] drm/i915/tgl: Add hpd interrupt handling Lucas De Marchi
@ 2019-07-13 1:09 ` Lucas De Marchi
2019-07-16 23:09 ` Srivatsa, Anusha
2019-07-13 1:09 ` [PATCH 06/22] drm/i915/tgl: handle DP aux interrupts Lucas De Marchi
` (22 subsequent siblings)
27 siblings, 1 reply; 64+ messages in thread
From: Lucas De Marchi @ 2019-07-13 1:09 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
TGL has 3 combophys and 6 TC/TBT ports, so it has 2 more TC/TBT ports
than ICL and the PORT_C on TGL is a combophy.
So here adding a new hpd north table and function to detect long
pulse for TGL.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 51 +++++++++++++++++++++++++++++----
drivers/gpu/drm/i915/i915_reg.h | 12 ++++++--
2 files changed, 56 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a7a90674db89..256bd2c072c1 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -56,6 +56,8 @@
* and related files, but that will be described in separate chapters.
*/
+typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
+
static const u32 hpd_ilk[HPD_NUM_PINS] = {
[HPD_PORT_A] = DE_DP_A_HOTPLUG,
};
@@ -133,6 +135,15 @@ static const u32 hpd_gen11[HPD_NUM_PINS] = {
[HPD_PORT_F] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG
};
+static const u32 hpd_gen12[HPD_NUM_PINS] = {
+ [HPD_PORT_D] = GEN11_TC1_HOTPLUG | GEN11_TBT1_HOTPLUG,
+ [HPD_PORT_E] = GEN11_TC2_HOTPLUG | GEN11_TBT2_HOTPLUG,
+ [HPD_PORT_F] = GEN11_TC3_HOTPLUG | GEN11_TBT3_HOTPLUG,
+ [HPD_PORT_G] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG,
+ [HPD_PORT_H] = GEN12_TC5_HOTPLUG | GEN12_TBT5_HOTPLUG,
+ [HPD_PORT_I] = GEN12_TC6_HOTPLUG | GEN12_TBT6_HOTPLUG
+};
+
static const u32 hpd_icp[HPD_NUM_PINS] = {
[HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
[HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
@@ -1676,6 +1687,26 @@ static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
}
}
+static bool gen12_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
+{
+ switch (pin) {
+ case HPD_PORT_D:
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
+ case HPD_PORT_E:
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
+ case HPD_PORT_F:
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
+ case HPD_PORT_G:
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
+ case HPD_PORT_H:
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC5);
+ case HPD_PORT_I:
+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC6);
+ default:
+ return false;
+ }
+}
+
static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
{
switch (pin) {
@@ -2869,6 +2900,16 @@ static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
u32 pin_mask = 0, long_mask = 0;
u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
+ long_pulse_detect_func long_pulse_detect;
+ const u32 *hpd;
+
+ if (INTEL_GEN(dev_priv) >= 12) {
+ long_pulse_detect = gen12_port_hotplug_long_detect;
+ hpd = hpd_gen12;
+ } else {
+ long_pulse_detect = gen11_port_hotplug_long_detect;
+ hpd = hpd_gen11;
+ }
if (trigger_tc) {
u32 dig_hotplug_reg;
@@ -2877,8 +2918,7 @@ static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
I915_WRITE(GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tc,
- dig_hotplug_reg, hpd_gen11,
- gen11_port_hotplug_long_detect);
+ dig_hotplug_reg, hpd, long_pulse_detect);
}
if (trigger_tbt) {
@@ -2888,8 +2928,7 @@ static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
I915_WRITE(GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg);
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tbt,
- dig_hotplug_reg, hpd_gen11,
- gen11_port_hotplug_long_detect);
+ dig_hotplug_reg, hpd, long_pulse_detect);
}
if (pin_mask)
@@ -3915,9 +3954,11 @@ static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
{
u32 hotplug_irqs, enabled_irqs;
+ const u32 *hpd;
u32 val;
- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_gen11);
+ hpd = INTEL_GEN(dev_priv) >= 12 ? hpd_gen12 : hpd_gen11;
+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd);
hotplug_irqs = GEN11_DE_TC_HOTPLUG_MASK | GEN11_DE_TBT_HOTPLUG_MASK;
val = I915_READ(GEN11_DE_HPD_IMR);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fbc5146a5931..ff703baf105f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7471,21 +7471,29 @@ enum {
#define GEN11_DE_HPD_IMR _MMIO(0x44474)
#define GEN11_DE_HPD_IIR _MMIO(0x44478)
#define GEN11_DE_HPD_IER _MMIO(0x4447c)
+#define GEN12_TC6_HOTPLUG (1 << 21)
+#define GEN12_TC5_HOTPLUG (1 << 20)
#define GEN11_TC4_HOTPLUG (1 << 19)
#define GEN11_TC3_HOTPLUG (1 << 18)
#define GEN11_TC2_HOTPLUG (1 << 17)
#define GEN11_TC1_HOTPLUG (1 << 16)
#define GEN11_TC_HOTPLUG(tc_port) (1 << ((tc_port) + 16))
-#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC4_HOTPLUG | \
+#define GEN11_DE_TC_HOTPLUG_MASK (GEN12_TC6_HOTPLUG | \
+ GEN12_TC5_HOTPLUG | \
+ GEN11_TC4_HOTPLUG | \
GEN11_TC3_HOTPLUG | \
GEN11_TC2_HOTPLUG | \
GEN11_TC1_HOTPLUG)
+#define GEN12_TBT6_HOTPLUG (1 << 5)
+#define GEN12_TBT5_HOTPLUG (1 << 4)
#define GEN11_TBT4_HOTPLUG (1 << 3)
#define GEN11_TBT3_HOTPLUG (1 << 2)
#define GEN11_TBT2_HOTPLUG (1 << 1)
#define GEN11_TBT1_HOTPLUG (1 << 0)
#define GEN11_TBT_HOTPLUG(tc_port) (1 << (tc_port))
-#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT4_HOTPLUG | \
+#define GEN11_DE_TBT_HOTPLUG_MASK (GEN12_TBT6_HOTPLUG | \
+ GEN12_TBT5_HOTPLUG | \
+ GEN11_TBT4_HOTPLUG | \
GEN11_TBT3_HOTPLUG | \
GEN11_TBT2_HOTPLUG | \
GEN11_TBT1_HOTPLUG)
--
2.21.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 05/22] drm/i915/tgl: Update north display hotplug detection to TGL connections
2019-07-13 1:09 ` [PATCH 05/22] drm/i915/tgl: Update north display hotplug detection to TGL connections Lucas De Marchi
@ 2019-07-16 23:09 ` Srivatsa, Anusha
0 siblings, 0 replies; 64+ messages in thread
From: Srivatsa, Anusha @ 2019-07-16 23:09 UTC (permalink / raw)
To: De Marchi, Lucas, intel-gfx
>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>Lucas De Marchi
>Sent: Friday, July 12, 2019 6:09 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 05/22] drm/i915/tgl: Update north display hotplug
>detection to TGL connections
>
>From: José Roberto de Souza <jose.souza@intel.com>
>
>TGL has 3 combophys and 6 TC/TBT ports, so it has 2 more TC/TBT ports than ICL
>and the PORT_C on TGL is a combophy.
>So here adding a new hpd north table and function to detect long pulse for TGL.
>
>Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>---
> drivers/gpu/drm/i915/i915_irq.c | 51 +++++++++++++++++++++++++++++----
>drivers/gpu/drm/i915/i915_reg.h | 12 ++++++--
> 2 files changed, 56 insertions(+), 7 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index a7a90674db89..256bd2c072c1 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -56,6 +56,8 @@
> * and related files, but that will be described in separate chapters.
> */
>
>+typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
>+
> static const u32 hpd_ilk[HPD_NUM_PINS] = {
> [HPD_PORT_A] = DE_DP_A_HOTPLUG,
> };
>@@ -133,6 +135,15 @@ static const u32 hpd_gen11[HPD_NUM_PINS] = {
> [HPD_PORT_F] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG };
>
>+static const u32 hpd_gen12[HPD_NUM_PINS] = {
>+ [HPD_PORT_D] = GEN11_TC1_HOTPLUG | GEN11_TBT1_HOTPLUG,
>+ [HPD_PORT_E] = GEN11_TC2_HOTPLUG | GEN11_TBT2_HOTPLUG,
>+ [HPD_PORT_F] = GEN11_TC3_HOTPLUG | GEN11_TBT3_HOTPLUG,
>+ [HPD_PORT_G] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG,
>+ [HPD_PORT_H] = GEN12_TC5_HOTPLUG | GEN12_TBT5_HOTPLUG,
>+ [HPD_PORT_I] = GEN12_TC6_HOTPLUG | GEN12_TBT6_HOTPLUG };
>+
> static const u32 hpd_icp[HPD_NUM_PINS] = {
> [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
> [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
>@@ -1676,6 +1687,26 @@ static bool gen11_port_hotplug_long_detect(enum
>hpd_pin pin, u32 val)
> }
> }
>
>+static bool gen12_port_hotplug_long_detect(enum hpd_pin pin, u32 val) {
>+ switch (pin) {
>+ case HPD_PORT_D:
>+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
>+ case HPD_PORT_E:
>+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
>+ case HPD_PORT_F:
>+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
>+ case HPD_PORT_G:
>+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
>+ case HPD_PORT_H:
>+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC5);
>+ case HPD_PORT_I:
>+ return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC6);
>+ default:
>+ return false;
>+ }
>+}
>+
> static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val) {
> switch (pin) {
>@@ -2869,6 +2900,16 @@ static void gen11_hpd_irq_handler(struct
>drm_i915_private *dev_priv, u32 iir)
> u32 pin_mask = 0, long_mask = 0;
> u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
> u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
>+ long_pulse_detect_func long_pulse_detect;
>+ const u32 *hpd;
>+
>+ if (INTEL_GEN(dev_priv) >= 12) {
>+ long_pulse_detect = gen12_port_hotplug_long_detect;
>+ hpd = hpd_gen12;
>+ } else {
>+ long_pulse_detect = gen11_port_hotplug_long_detect;
>+ hpd = hpd_gen11;
>+ }
>
> if (trigger_tc) {
> u32 dig_hotplug_reg;
>@@ -2877,8 +2918,7 @@ static void gen11_hpd_irq_handler(struct
>drm_i915_private *dev_priv, u32 iir)
> I915_WRITE(GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
>
> intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
>trigger_tc,
>- dig_hotplug_reg, hpd_gen11,
>- gen11_port_hotplug_long_detect);
>+ dig_hotplug_reg, hpd, long_pulse_detect);
> }
>
> if (trigger_tbt) {
>@@ -2888,8 +2928,7 @@ static void gen11_hpd_irq_handler(struct
>drm_i915_private *dev_priv, u32 iir)
> I915_WRITE(GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg);
>
> intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
>trigger_tbt,
>- dig_hotplug_reg, hpd_gen11,
>- gen11_port_hotplug_long_detect);
>+ dig_hotplug_reg, hpd, long_pulse_detect);
> }
>
> if (pin_mask)
>@@ -3915,9 +3954,11 @@ static void gen11_hpd_detection_setup(struct
>drm_i915_private *dev_priv) static void gen11_hpd_irq_setup(struct
>drm_i915_private *dev_priv) {
> u32 hotplug_irqs, enabled_irqs;
>+ const u32 *hpd;
> u32 val;
>
>- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_gen11);
>+ hpd = INTEL_GEN(dev_priv) >= 12 ? hpd_gen12 : hpd_gen11;
>+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd);
> hotplug_irqs = GEN11_DE_TC_HOTPLUG_MASK |
>GEN11_DE_TBT_HOTPLUG_MASK;
>
> val = I915_READ(GEN11_DE_HPD_IMR);
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index fbc5146a5931..ff703baf105f 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -7471,21 +7471,29 @@ enum {
> #define GEN11_DE_HPD_IMR _MMIO(0x44474)
> #define GEN11_DE_HPD_IIR _MMIO(0x44478)
> #define GEN11_DE_HPD_IER _MMIO(0x4447c)
>+#define GEN12_TC6_HOTPLUG (1 << 21)
>+#define GEN12_TC5_HOTPLUG (1 << 20)
> #define GEN11_TC4_HOTPLUG (1 << 19)
> #define GEN11_TC3_HOTPLUG (1 << 18)
> #define GEN11_TC2_HOTPLUG (1 << 17)
> #define GEN11_TC1_HOTPLUG (1 << 16)
> #define GEN11_TC_HOTPLUG(tc_port) (1 << ((tc_port) + 16))
>-#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC4_HOTPLUG
>| \
>+#define GEN11_DE_TC_HOTPLUG_MASK (GEN12_TC6_HOTPLUG
>| \
>+ GEN12_TC5_HOTPLUG | \
>+ GEN11_TC4_HOTPLUG | \
> GEN11_TC3_HOTPLUG | \
> GEN11_TC2_HOTPLUG | \
> GEN11_TC1_HOTPLUG)
>+#define GEN12_TBT6_HOTPLUG (1 << 5)
>+#define GEN12_TBT5_HOTPLUG (1 << 4)
> #define GEN11_TBT4_HOTPLUG (1 << 3)
> #define GEN11_TBT3_HOTPLUG (1 << 2)
> #define GEN11_TBT2_HOTPLUG (1 << 1)
> #define GEN11_TBT1_HOTPLUG (1 << 0)
> #define GEN11_TBT_HOTPLUG(tc_port) (1 << (tc_port))
>-#define GEN11_DE_TBT_HOTPLUG_MASK
> (GEN11_TBT4_HOTPLUG | \
>+#define GEN11_DE_TBT_HOTPLUG_MASK
> (GEN12_TBT6_HOTPLUG | \
>+ GEN12_TBT5_HOTPLUG | \
>+ GEN11_TBT4_HOTPLUG | \
> GEN11_TBT3_HOTPLUG | \
> GEN11_TBT2_HOTPLUG | \
> GEN11_TBT1_HOTPLUG)
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 06/22] drm/i915/tgl: handle DP aux interrupts
2019-07-13 1:09 [PATCH 00/22] Tiger Lake part 2 Lucas De Marchi
` (4 preceding siblings ...)
2019-07-13 1:09 ` [PATCH 05/22] drm/i915/tgl: Update north display hotplug detection to TGL connections Lucas De Marchi
@ 2019-07-13 1:09 ` Lucas De Marchi
2019-07-17 0:14 ` Srivatsa, Anusha
2019-07-13 1:09 ` [PATCH 07/22] drm/i915/dmc: Load DMC on TGL Lucas De Marchi
` (21 subsequent siblings)
27 siblings, 1 reply; 64+ messages in thread
From: Lucas De Marchi @ 2019-07-13 1:09 UTC (permalink / raw)
To: intel-gfx
For Tiger Lake the DE Port Interrupt Definition bits changed, so use the
new bit definitions.
Cc: Jose Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 16 +++++++++++-----
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 256bd2c072c1..6350e9dee653 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2939,19 +2939,25 @@ static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
{
- u32 mask = GEN8_AUX_CHANNEL_A;
+ u32 mask;
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ /* TODO: Add AUX entries for USBC */
+ return TGL_DE_PORT_AUX_DDIA |
+ TGL_DE_PORT_AUX_DDIB |
+ TGL_DE_PORT_AUX_DDIC;
+ mask = GEN8_AUX_CHANNEL_A;
if (INTEL_GEN(dev_priv) >= 9)
mask |= GEN9_AUX_CHANNEL_B |
GEN9_AUX_CHANNEL_C |
GEN9_AUX_CHANNEL_D;
- if (IS_CNL_WITH_PORT_F(dev_priv))
+ if (IS_CNL_WITH_PORT_F(dev_priv) || IS_GEN(dev_priv, 11))
mask |= CNL_AUX_CHANNEL_F;
- if (INTEL_GEN(dev_priv) >= 11)
- mask |= ICL_AUX_CHANNEL_E |
- CNL_AUX_CHANNEL_F;
+ if (IS_GEN(dev_priv, 11))
+ mask |= ICL_AUX_CHANNEL_E;
return mask;
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ff703baf105f..41c8b40eebd5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7428,6 +7428,9 @@ enum {
#define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
#define BXT_DE_PORT_GMBUS (1 << 1)
#define GEN8_AUX_CHANNEL_A (1 << 0)
+#define TGL_DE_PORT_AUX_DDIC (1 << 2)
+#define TGL_DE_PORT_AUX_DDIB (1 << 1)
+#define TGL_DE_PORT_AUX_DDIA (1 << 0)
#define GEN8_DE_MISC_ISR _MMIO(0x44460)
#define GEN8_DE_MISC_IMR _MMIO(0x44464)
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 06/22] drm/i915/tgl: handle DP aux interrupts
2019-07-13 1:09 ` [PATCH 06/22] drm/i915/tgl: handle DP aux interrupts Lucas De Marchi
@ 2019-07-17 0:14 ` Srivatsa, Anusha
0 siblings, 0 replies; 64+ messages in thread
From: Srivatsa, Anusha @ 2019-07-17 0:14 UTC (permalink / raw)
To: De Marchi, Lucas, intel-gfx
>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>Lucas De Marchi
>Sent: Friday, July 12, 2019 6:09 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 06/22] drm/i915/tgl: handle DP aux interrupts
>
>For Tiger Lake the DE Port Interrupt Definition bits changed, so use the new bit
>definitions.
>
>Cc: Jose Souza <jose.souza@intel.com>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>---
> drivers/gpu/drm/i915/i915_irq.c | 16 +++++++++++-----
>drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 2 files changed, 14 insertions(+), 5 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index 256bd2c072c1..6350e9dee653 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -2939,19 +2939,25 @@ static void gen11_hpd_irq_handler(struct
>drm_i915_private *dev_priv, u32 iir)
>
> static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv) {
>- u32 mask = GEN8_AUX_CHANNEL_A;
>+ u32 mask;
>+
>+ if (INTEL_GEN(dev_priv) >= 12)
>+ /* TODO: Add AUX entries for USBC */
>+ return TGL_DE_PORT_AUX_DDIA |
>+ TGL_DE_PORT_AUX_DDIB |
>+ TGL_DE_PORT_AUX_DDIC;
>
>+ mask = GEN8_AUX_CHANNEL_A;
> if (INTEL_GEN(dev_priv) >= 9)
> mask |= GEN9_AUX_CHANNEL_B |
> GEN9_AUX_CHANNEL_C |
> GEN9_AUX_CHANNEL_D;
>
>- if (IS_CNL_WITH_PORT_F(dev_priv))
>+ if (IS_CNL_WITH_PORT_F(dev_priv) || IS_GEN(dev_priv, 11))
> mask |= CNL_AUX_CHANNEL_F;
>
>- if (INTEL_GEN(dev_priv) >= 11)
>- mask |= ICL_AUX_CHANNEL_E |
>- CNL_AUX_CHANNEL_F;
>+ if (IS_GEN(dev_priv, 11))
>+ mask |= ICL_AUX_CHANNEL_E;
>
> return mask;
> }
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index ff703baf105f..41c8b40eebd5 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -7428,6 +7428,9 @@ enum {
> #define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
> #define BXT_DE_PORT_GMBUS (1 << 1)
> #define GEN8_AUX_CHANNEL_A (1 << 0)
>+#define TGL_DE_PORT_AUX_DDIC (1 << 2)
>+#define TGL_DE_PORT_AUX_DDIB (1 << 1)
>+#define TGL_DE_PORT_AUX_DDIA (1 << 0)
>
> #define GEN8_DE_MISC_ISR _MMIO(0x44460) #define GEN8_DE_MISC_IMR
>_MMIO(0x44464)
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 07/22] drm/i915/dmc: Load DMC on TGL
2019-07-13 1:09 [PATCH 00/22] Tiger Lake part 2 Lucas De Marchi
` (5 preceding siblings ...)
2019-07-13 1:09 ` [PATCH 06/22] drm/i915/tgl: handle DP aux interrupts Lucas De Marchi
@ 2019-07-13 1:09 ` Lucas De Marchi
2019-07-19 10:44 ` Anshuman Gupta
2019-07-19 16:05 ` Atwood, Matthew S
2019-07-13 1:09 ` [PATCH 08/22] drm/i915/tgl: Add DKL phy pll registers Lucas De Marchi
` (20 subsequent siblings)
27 siblings, 2 replies; 64+ messages in thread
From: Lucas De Marchi @ 2019-07-13 1:09 UTC (permalink / raw)
To: intel-gfx
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
Add Support to load DMC v2.02 on TGL.
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/intel_csr.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 6ef74531588a..865b987dee8e 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -39,6 +39,11 @@
#define GEN12_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE
+#define TGL_CSR_PATH "i915/tgl_dmc_ver2_02.bin"
+#define TGL_CSR_VERSION_REQUIRED CSR_VERSION(2, 2)
+#define TGL_CSR_MAX_FW_SIZE 0x6000
+MODULE_FIRMWARE(TGL_CSR_PATH);
+
#define ICL_CSR_PATH "i915/icl_dmc_ver1_07.bin"
#define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
#define ICL_CSR_MAX_FW_SIZE 0x6000
@@ -674,6 +679,8 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
intel_csr_runtime_pm_get(dev_priv);
if (INTEL_GEN(dev_priv) >= 12) {
+ csr->fw_path = TGL_CSR_PATH;
+ csr->required_version = TGL_CSR_VERSION_REQUIRED;
/* Allow to load fw via parameter using the last known size */
csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
} else if (IS_GEN(dev_priv, 11)) {
--
2.21.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 07/22] drm/i915/dmc: Load DMC on TGL
2019-07-13 1:09 ` [PATCH 07/22] drm/i915/dmc: Load DMC on TGL Lucas De Marchi
@ 2019-07-19 10:44 ` Anshuman Gupta
2019-07-19 15:34 ` Lucas De Marchi
2019-07-19 16:05 ` Atwood, Matthew S
1 sibling, 1 reply; 64+ messages in thread
From: Anshuman Gupta @ 2019-07-19 10:44 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On 2019-07-12 at 18:09:25 -0700, Lucas De Marchi wrote:
> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
> Add Support to load DMC v2.02 on TGL.
>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_csr.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> index 6ef74531588a..865b987dee8e 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -39,6 +39,11 @@
>
> #define GEN12_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE
>
> +#define TGL_CSR_PATH "i915/tgl_dmc_ver2_02.bin"
> +#define TGL_CSR_VERSION_REQUIRED CSR_VERSION(2, 2)
> +#define TGL_CSR_MAX_FW_SIZE 0x6000
> +MODULE_FIRMWARE(TGL_CSR_PATH);
> +
> #define ICL_CSR_PATH "i915/icl_dmc_ver1_07.bin"
> #define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
> #define ICL_CSR_MAX_FW_SIZE 0x6000
> @@ -674,6 +679,8 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
> intel_csr_runtime_pm_get(dev_priv);
>
> if (INTEL_GEN(dev_priv) >= 12) {
> + csr->fw_path = TGL_CSR_PATH;
> + csr->required_version = TGL_CSR_VERSION_REQUIRED;
> /* Allow to load fw via parameter using the last known size */
> csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
> } else if (IS_GEN(dev_priv, 11)) {
LGTM, one concern about DMC fw minor version.
if this is decided latest upstream version,
I will provide my RB.
> --
> 2.21.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 07/22] drm/i915/dmc: Load DMC on TGL
2019-07-19 10:44 ` Anshuman Gupta
@ 2019-07-19 15:34 ` Lucas De Marchi
0 siblings, 0 replies; 64+ messages in thread
From: Lucas De Marchi @ 2019-07-19 15:34 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
On Fri, Jul 19, 2019 at 04:14:27PM +0530, Anshuman Gupta wrote:
>On 2019-07-12 at 18:09:25 -0700, Lucas De Marchi wrote:
>> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>>
>> Add Support to load DMC v2.02 on TGL.
>>
>> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_csr.c | 7 +++++++
>> 1 file changed, 7 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
>> index 6ef74531588a..865b987dee8e 100644
>> --- a/drivers/gpu/drm/i915/intel_csr.c
>> +++ b/drivers/gpu/drm/i915/intel_csr.c
>> @@ -39,6 +39,11 @@
>>
>> #define GEN12_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE
>>
>> +#define TGL_CSR_PATH "i915/tgl_dmc_ver2_02.bin"
>> +#define TGL_CSR_VERSION_REQUIRED CSR_VERSION(2, 2)
>> +#define TGL_CSR_MAX_FW_SIZE 0x6000
>> +MODULE_FIRMWARE(TGL_CSR_PATH);
>> +
>> #define ICL_CSR_PATH "i915/icl_dmc_ver1_07.bin"
>> #define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
>> #define ICL_CSR_MAX_FW_SIZE 0x6000
>> @@ -674,6 +679,8 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
>> intel_csr_runtime_pm_get(dev_priv);
>>
>> if (INTEL_GEN(dev_priv) >= 12) {
>> + csr->fw_path = TGL_CSR_PATH;
>> + csr->required_version = TGL_CSR_VERSION_REQUIRED;
>> /* Allow to load fw via parameter using the last known size */
>> csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
>> } else if (IS_GEN(dev_priv, 11)) {
>LGTM, one concern about DMC fw minor version.
>if this is decided latest upstream version,
>I will provide my RB.
José, 2.02 or 2.03?
Lucas De Marchi
>
>> --
>> 2.21.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 07/22] drm/i915/dmc: Load DMC on TGL
2019-07-13 1:09 ` [PATCH 07/22] drm/i915/dmc: Load DMC on TGL Lucas De Marchi
2019-07-19 10:44 ` Anshuman Gupta
@ 2019-07-19 16:05 ` Atwood, Matthew S
1 sibling, 0 replies; 64+ messages in thread
From: Atwood, Matthew S @ 2019-07-19 16:05 UTC (permalink / raw)
To: intel-gfx, De Marchi, Lucas
On Fri, 2019-07-12 at 18:09 -0700, Lucas De Marchi wrote:
> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
> Add Support to load DMC v2.02 on TGL.
>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_csr.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_csr.c
> b/drivers/gpu/drm/i915/intel_csr.c
> index 6ef74531588a..865b987dee8e 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -39,6 +39,11 @@
>
> #define GEN12_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE
>
> +#define TGL_CSR_PATH "i915/tgl_dmc_ver2_02.bin"
> +#define TGL_CSR_VERSION_REQUIRED CSR_VERSION(2, 2)
> +#define TGL_CSR_MAX_FW_SIZE 0x6000
> +MODULE_FIRMWARE(TGL_CSR_PATH);
> +
> #define ICL_CSR_PATH "i915/icl_dmc_ver1_07.bin"
> #define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
> #define ICL_CSR_MAX_FW_SIZE 0x6000
> @@ -674,6 +679,8 @@ void intel_csr_ucode_init(struct drm_i915_private
> *dev_priv)
> intel_csr_runtime_pm_get(dev_priv);
>
> if (INTEL_GEN(dev_priv) >= 12) {
> + csr->fw_path = TGL_CSR_PATH;
> + csr->required_version = TGL_CSR_VERSION_REQUIRED;
> /* Allow to load fw via parameter using the last known
> size */
> csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
> } else if (IS_GEN(dev_priv, 11)) {
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 08/22] drm/i915/tgl: Add DKL phy pll registers
2019-07-13 1:09 [PATCH 00/22] Tiger Lake part 2 Lucas De Marchi
` (6 preceding siblings ...)
2019-07-13 1:09 ` [PATCH 07/22] drm/i915/dmc: Load DMC on TGL Lucas De Marchi
@ 2019-07-13 1:09 ` Lucas De Marchi
2019-07-19 21:22 ` Atwood, Matthew S
2019-07-13 1:09 ` [PATCH 09/22] drm/i915/tgl: re-indent code to prepare for DKL changes Lucas De Marchi
` (19 subsequent siblings)
27 siblings, 1 reply; 64+ messages in thread
From: Lucas De Marchi @ 2019-07-13 1:09 UTC (permalink / raw)
To: intel-gfx
From: Vandita Kulkarni <vandita.kulkarni@intel.com>
These are the registers needed to program Dekel PHY. Some register
definitions reuse the MG PHY definitions. Add a comment on those so we
don't need to duplicate the functions for programming them.
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 94 +++++++++++++++++++++++++++++++++
1 file changed, 94 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 41c8b40eebd5..70872c9391ff 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10026,6 +10026,100 @@ enum skl_power_gate {
_TGL_DPLL1_CFGCR1, \
_TGL_TBTPLL_CFGCR1)
+#define _DKL_PHY1_BASE 0x168000
+#define _DKL_PHY2_BASE 0x169000
+#define _DKL_PHY3_BASE 0x16A000
+#define _DKL_PHY4_BASE 0x16B000
+#define _DKL_PHY5_BASE 0x16C000
+#define _DKL_PHY6_BASE 0x16D000
+
+/* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */
+#define _DKL_PLL_DIV0 0x200
+#define DKL_PLL_DIV0_INTEG_COEFF(x) ((x) << 16)
+#define DKL_PLL_DIV0_INTEG_COEFF_MASK (0x1F << 16)
+#define DKL_PLL_DIV0_PROP_COEFF(x) ((x) << 12)
+#define DKL_PLL_DIV0_PROP_COEFF_MASK (0xF << 12)
+#define DKL_PLL_DIV0_FBPREDIV(x) ((x) << 8)
+#define DKL_PLL_DIV0_FBPREDIV_MASK (0xF << 8)
+#define DKL_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
+#define DKL_PLL_DIV0_FBDIV_INT_MASK (0xFF << 0)
+#define DKL_PLL_DIV0(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_PLL_DIV0)
+
+#define _DKL_PLL_DIV1 0x204
+#define DKL_PLL_DIV1_IREF_TRIM(x) ((x) << 16)
+#define DKL_PLL_DIV1_IREF_TRIM_MASK (0x1F << 16)
+#define DKL_PLL_DIV1_TDC_TARGET_CNT(x) ((x) << 0)
+#define DKL_PLL_DIV1_TDC_TARGET_CNT_MASK (0xFF << 0)
+#define DKL_PLL_DIV1(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_PLL_DIV1)
+
+#define _DKL_PLL_SSC 0x210
+#define DKL_PLL_SSC_IREF_NDIV_RATIO(x) ((x) << 29)
+#define DKL_PLL_SSC_IREF_NDIV_RATIO_MASK (0x7 << 29)
+#define DKL_PLL_SSC_STEP_LEN(x) ((x) << 16)
+#define DKL_PLL_SSC_STEP_LEN_MASK (0xFF << 16)
+#define DKL_PLL_SSC_STEP_NUM(x) ((x) << 11)
+#define DKL_PLL_SSC_STEP_NUM_MASK (0x7 << 11)
+#define DKL_PLL_SSC_EN (1 << 9)
+#define DKL_PLL_SSC(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_PLL_SSC)
+
+#define _DKL_PLL_BIAS 0x214
+#define DKL_PLL_BIAS_FRAC_EN_H (1 << 30)
+#define DKL_PLL_BIAS_FBDIV_FRAC(x) ((x) << 8)
+#define DKL_PLL_BIAS_FBDIV_FRAC_MASK (0xFF << 8)
+#define DKL_PLL_BIAS(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_PLL_BIAS)
+
+#define _DKL_PLL_TDC_COLDST_BIAS 0x218
+#define DKL_PLL_TDC_SSC_STEP_SIZE(x) ((x) << 8)
+#define DKL_PLL_TDC_SSC_STEP_SIZE_MASK (0xFF << 8)
+#define DKL_PLL_TDC_FEED_FWD_GAIN(x) ((x) << 0)
+#define DKL_PLL_TDC_FEED_FWD_GAIN_MASK (0xFF << 0)
+#define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \
+ _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_PLL_TDC_COLDST_BIAS)
+
+#define _DKL_REFCLKIN_CTL 0x12C
+/* Bits are the same as MG_REFCLKIN_CTL */
+#define DKL_REFCLKIN_CTL(tc_port) _MMIO(_PORT(tc_port, \
+ _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_REFCLKIN_CTL)
+
+#define _DKL_CLKTOP2_HSCLKCTL 0xD4
+/* Bits are the same as MG_CLKTOP2_HSCLKCTL */
+#define DKL_CLKTOP2_HSCLKCTL(tc_port) _MMIO(_PORT(tc_port, \
+ _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_CLKTOP2_HSCLKCTL)
+
+#define _DKL_CLKTOP2_CORECLKCTL1 0xD8
+/* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */
+#define DKL_CLKTOP2_CORECLKCTL1(tc_port) _MMIO(_PORT(tc_port, \
+ _DKL_PHY1_BASE, \
+ _DKL_PHY2_BASE) + \
+ _DKL_CLKTOP2_CORECLKCTL1)
+
+/*
+ * Each Dekel PHY is addressed through a 4KB aperture. Each PHY has more than
+ * 4KB of register space, so a separate index is programmed in HIP_INDEX_REG0
+ * or HIP_INDEX_REG1, based on the port number, to set the upper 2 address
+ * bits that point the 4KB window into the full PHY register space.
+ */
+#define _HIP_INDEX_REG0 0x1010A0
+#define _HIP_INDEX_REG1 0x1010A4
+#define HIP_INDEX_REG(tc_port) _MMIO((tc_port) < 3 \
+ ? _HIP_INDEX_REG0 \
+ : _HIP_INDEX_REG1)
+#define HIP_INDEX_VAL(index, tc_port) ((index) << (((tc_port) * 8) % 32))
+
/* BXT display engine PLL */
#define BXT_DE_PLL_CTL _MMIO(0x6d000)
#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
--
2.21.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 08/22] drm/i915/tgl: Add DKL phy pll registers
2019-07-13 1:09 ` [PATCH 08/22] drm/i915/tgl: Add DKL phy pll registers Lucas De Marchi
@ 2019-07-19 21:22 ` Atwood, Matthew S
0 siblings, 0 replies; 64+ messages in thread
From: Atwood, Matthew S @ 2019-07-19 21:22 UTC (permalink / raw)
To: intel-gfx, De Marchi, Lucas
On Fri, 2019-07-12 at 18:09 -0700, Lucas De Marchi wrote:
> From: Vandita Kulkarni <vandita.kulkarni@intel.com>
>
> These are the registers needed to program Dekel PHY. Some register
> definitions reuse the MG PHY definitions. Add a comment on those so
> we
> don't need to duplicate the functions for programming them.
>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 94
> +++++++++++++++++++++++++++++++++
> 1 file changed, 94 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 41c8b40eebd5..70872c9391ff 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10026,6 +10026,100 @@ enum skl_power_gate {
> _TGL_DPLL1_CFGCR1, \
> _TGL_TBTPLL_CFGCR1)
>
> +#define _DKL_PHY1_BASE 0x168000
> +#define _DKL_PHY2_BASE 0x169000
> +#define _DKL_PHY3_BASE 0x16A000
> +#define _DKL_PHY4_BASE 0x16B000
> +#define _DKL_PHY5_BASE 0x16C000
> +#define _DKL_PHY6_BASE 0x16D000
> +
> +/* DEKEL PHY MMIO Address = Phy base + (internal address &
> ~index_mask) */
> +#define _DKL_PLL_DIV0 0x200
> +#define DKL_PLL_DIV0_INTEG_COEFF(x) ((x) << 16)
> +#define DKL_PLL_DIV0_INTEG_COEFF_MASK (0x1F << 16)
> +#define DKL_PLL_DIV0_PROP_COEFF(x) ((x) << 12)
> +#define DKL_PLL_DIV0_PROP_COEFF_MASK (0xF << 12)
> +#define DKL_PLL_DIV0_FBPREDIV(x) ((x) << 8)
> +#define DKL_PLL_DIV0_FBPREDIV_MASK (0xF << 8)
> +#define DKL_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
> +#define DKL_PLL_DIV0_FBDIV_INT_MASK (0xFF << 0)
> +#define DKL_PLL_DIV0(tc_port) _MMIO(_PORT(tc_port,
> _DKL_PHY1_BASE, \
> + _DKL_PHY2_BASE) + \
> + _DKL_PLL_DIV0)
> +
> +#define _DKL_PLL_DIV1 0x204
> +#define DKL_PLL_DIV1_IREF_TRIM(x) ((x) << 16)
> +#define DKL_PLL_DIV1_IREF_TRIM_MASK (0x1F << 16)
> +#define DKL_PLL_DIV1_TDC_TARGET_CNT(x) ((x) << 0)
> +#define DKL_PLL_DIV1_TDC_TARGET_CNT_MASK (0xFF << 0)
> +#define DKL_PLL_DIV1(tc_port) _MMIO(_PORT(tc_port,
> _DKL_PHY1_BASE, \
> + _DKL_PHY2_BASE) + \
> + _DKL_PLL_DIV1)
> +
> +#define _DKL_PLL_SSC 0x210
> +#define DKL_PLL_SSC_IREF_NDIV_RATIO(x) ((x) << 29)
> +#define DKL_PLL_SSC_IREF_NDIV_RATIO_MASK (0x7 << 29)
> +#define DKL_PLL_SSC_STEP_LEN(x) ((x) << 16)
> +#define DKL_PLL_SSC_STEP_LEN_MASK (0xFF << 16)
> +#define DKL_PLL_SSC_STEP_NUM(x) ((x) << 11)
> +#define DKL_PLL_SSC_STEP_NUM_MASK (0x7 << 11)
> +#define DKL_PLL_SSC_EN (1 << 9)
> +#define DKL_PLL_SSC(tc_port) _MMIO(_PORT(tc_port,
> _DKL_PHY1_BASE, \
> + _DKL_PHY2_BASE) + \
> + _DKL_PLL_SSC)
> +
> +#define _DKL_PLL_BIAS 0x214
> +#define DKL_PLL_BIAS_FRAC_EN_H (1 << 30)
> +#define DKL_PLL_BIAS_FBDIV_FRAC(x) ((x) << 8)
> +#define DKL_PLL_BIAS_FBDIV_FRAC_MASK (0xFF << 8)
> +#define DKL_PLL_BIAS(tc_port) _MMIO(_PORT(tc_port,
> _DKL_PHY1_BASE, \
> + _DKL_PHY2_BASE) + \
> + _DKL_PLL_BIAS)
> +
> +#define _DKL_PLL_TDC_COLDST_BIAS 0x218
> +#define DKL_PLL_TDC_SSC_STEP_SIZE(x) ((x) << 8)
> +#define DKL_PLL_TDC_SSC_STEP_SIZE_MASK (0xFF << 8)
> +#define DKL_PLL_TDC_FEED_FWD_GAIN(x) ((x) << 0)
> +#define DKL_PLL_TDC_FEED_FWD_GAIN_MASK (0xFF << 0)
> +#define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \
> + _DKL_PHY1_BASE, \
> + _DKL_PHY2_BASE) +
> \
> + _DKL_PLL_TDC_COLDS
> T_BIAS)
> +
> +#define _DKL_REFCLKIN_CTL 0x12C
> +/* Bits are the same as MG_REFCLKIN_CTL */
> +#define DKL_REFCLKIN_CTL(tc_port) _MMIO(_PORT(tc_port, \
> + _DKL_PHY1_BASE, \
> + _DKL_PHY2_BASE) + \
> + _DKL_REFCLKIN_CTL)
> +
> +#define _DKL_CLKTOP2_HSCLKCTL 0xD4
> +/* Bits are the same as MG_CLKTOP2_HSCLKCTL */
> +#define DKL_CLKTOP2_HSCLKCTL(tc_port) _MMIO(_PORT(tc_port, \
> + _DKL_PHY1_BASE, \
> + _DKL_PHY2_BASE) + \
> + _DKL_CLKTOP2_HSCLKCTL)
> +
> +#define _DKL_CLKTOP2_CORECLKCTL1 0xD8
> +/* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */
> +#define DKL_CLKTOP2_CORECLKCTL1(tc_port) _MMIO(_PORT(tc_port, \
> + _DKL_PHY1_B
> ASE, \
> + _DKL_PHY2_B
> ASE) + \
> + _DKL_CLKTOP2_CORE
> CLKCTL1)
> +
> +/*
> + * Each Dekel PHY is addressed through a 4KB aperture. Each PHY has
> more than
> + * 4KB of register space, so a separate index is programmed in
> HIP_INDEX_REG0
> + * or HIP_INDEX_REG1, based on the port number, to set the upper 2
> address
> + * bits that point the 4KB window into the full PHY register space.
> + */
> +#define _HIP_INDEX_REG0 0x1010A0
> +#define _HIP_INDEX_REG1 0x1010A4
> +#define HIP_INDEX_REG(tc_port) _MMIO((tc_port) < 3 \
> + ? _HIP_INDEX_REG0 \
> + : _HIP_INDEX_REG1)
> +#define HIP_INDEX_VAL(index, tc_port) ((index) << (((tc_port)
> * 8) % 32))
> +
> /* BXT display engine PLL */
> #define BXT_DE_PLL_CTL _MMIO(0x6d000)
> #define BXT_DE_PLL_RATIO(x) (x) /*
> {60,65,100} * 19.2MHz */
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^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 09/22] drm/i915/tgl: re-indent code to prepare for DKL changes
2019-07-13 1:09 [PATCH 00/22] Tiger Lake part 2 Lucas De Marchi
` (7 preceding siblings ...)
2019-07-13 1:09 ` [PATCH 08/22] drm/i915/tgl: Add DKL phy pll registers Lucas De Marchi
@ 2019-07-13 1:09 ` Lucas De Marchi
2019-07-22 22:31 ` Atwood, Matthew S
2019-07-13 1:09 ` [PATCH 10/22] drm/i915/tgl: Add DKL phy pll state calculations Lucas De Marchi
` (18 subsequent siblings)
27 siblings, 1 reply; 64+ messages in thread
From: Lucas De Marchi @ 2019-07-13 1:09 UTC (permalink / raw)
To: intel-gfx
The final save operation into pll_state of the calculations done will
be different for DKL PHY. Prepare for that by reindenting code so it's
easier to check for correctness. This one has no change in behavior.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 119 ++++++++++--------
1 file changed, 66 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 319a26a1ec10..7312a47f79ad 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2804,60 +2804,73 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
}
ssc_steplog = 4;
- pll_state->mg_pll_div0 = (m2div_rem > 0 ? MG_PLL_DIV0_FRACNEN_H : 0) |
- MG_PLL_DIV0_FBDIV_FRAC(m2div_frac) |
- MG_PLL_DIV0_FBDIV_INT(m2div_int);
-
- pll_state->mg_pll_div1 = MG_PLL_DIV1_IREF_NDIVRATIO(iref_ndiv) |
- MG_PLL_DIV1_DITHER_DIV_2 |
- MG_PLL_DIV1_NDIVRATIO(1) |
- MG_PLL_DIV1_FBPREDIV(m1div);
-
- pll_state->mg_pll_lf = MG_PLL_LF_TDCTARGETCNT(tdc_targetcnt) |
- MG_PLL_LF_AFCCNTSEL_512 |
- MG_PLL_LF_GAINCTRL(1) |
- MG_PLL_LF_INT_COEFF(int_coeff) |
- MG_PLL_LF_PROP_COEFF(prop_coeff);
-
- pll_state->mg_pll_frac_lock = MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 |
- MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 |
- MG_PLL_FRAC_LOCK_LOCKTHRESH(10) |
- MG_PLL_FRAC_LOCK_DCODITHEREN |
- MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(feedfwgain);
- if (use_ssc || m2div_rem > 0)
- pll_state->mg_pll_frac_lock |= MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN;
-
- pll_state->mg_pll_ssc = (use_ssc ? MG_PLL_SSC_EN : 0) |
- MG_PLL_SSC_TYPE(2) |
- MG_PLL_SSC_STEPLENGTH(ssc_steplen) |
- MG_PLL_SSC_STEPNUM(ssc_steplog) |
- MG_PLL_SSC_FLLEN |
- MG_PLL_SSC_STEPSIZE(ssc_stepsize);
-
- pll_state->mg_pll_tdc_coldst_bias = MG_PLL_TDC_COLDST_COLDSTART |
- MG_PLL_TDC_COLDST_IREFINT_EN |
- MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(iref_pulse_w) |
- MG_PLL_TDC_TDCOVCCORR_EN |
- MG_PLL_TDC_TDCSEL(3);
-
- pll_state->mg_pll_bias = MG_PLL_BIAS_BIAS_GB_SEL(3) |
- MG_PLL_BIAS_INIT_DCOAMP(0x3F) |
- MG_PLL_BIAS_BIAS_BONUS(10) |
- MG_PLL_BIAS_BIASCAL_EN |
- MG_PLL_BIAS_CTRIM(12) |
- MG_PLL_BIAS_VREF_RDAC(4) |
- MG_PLL_BIAS_IREFTRIM(iref_trim);
-
- if (refclk_khz == 38400) {
- pll_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
- pll_state->mg_pll_bias_mask = 0;
- } else {
- pll_state->mg_pll_tdc_coldst_bias_mask = -1U;
- pll_state->mg_pll_bias_mask = -1U;
- }
+ /* write pll_state calculations */
+ {
+ pll_state->mg_pll_div0 =
+ (m2div_rem > 0 ? MG_PLL_DIV0_FRACNEN_H : 0) |
+ MG_PLL_DIV0_FBDIV_FRAC(m2div_frac) |
+ MG_PLL_DIV0_FBDIV_INT(m2div_int);
+
+ pll_state->mg_pll_div1 =
+ MG_PLL_DIV1_IREF_NDIVRATIO(iref_ndiv) |
+ MG_PLL_DIV1_DITHER_DIV_2 |
+ MG_PLL_DIV1_NDIVRATIO(1) |
+ MG_PLL_DIV1_FBPREDIV(m1div);
+
+ pll_state->mg_pll_lf =
+ MG_PLL_LF_TDCTARGETCNT(tdc_targetcnt) |
+ MG_PLL_LF_AFCCNTSEL_512 |
+ MG_PLL_LF_GAINCTRL(1) |
+ MG_PLL_LF_INT_COEFF(int_coeff) |
+ MG_PLL_LF_PROP_COEFF(prop_coeff);
+
+ pll_state->mg_pll_frac_lock =
+ MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 |
+ MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 |
+ MG_PLL_FRAC_LOCK_LOCKTHRESH(10) |
+ MG_PLL_FRAC_LOCK_DCODITHEREN |
+ MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(feedfwgain);
+ if (use_ssc || m2div_rem > 0)
+ pll_state->mg_pll_frac_lock |=
+ MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN;
+
+ pll_state->mg_pll_ssc =
+ (use_ssc ? MG_PLL_SSC_EN : 0) |
+ MG_PLL_SSC_TYPE(2) |
+ MG_PLL_SSC_STEPLENGTH(ssc_steplen) |
+ MG_PLL_SSC_STEPNUM(ssc_steplog) |
+ MG_PLL_SSC_FLLEN |
+ MG_PLL_SSC_STEPSIZE(ssc_stepsize);
+
+ pll_state->mg_pll_tdc_coldst_bias =
+ MG_PLL_TDC_COLDST_COLDSTART |
+ MG_PLL_TDC_COLDST_IREFINT_EN |
+ MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(iref_pulse_w) |
+ MG_PLL_TDC_TDCOVCCORR_EN |
+ MG_PLL_TDC_TDCSEL(3);
+
+ pll_state->mg_pll_bias =
+ MG_PLL_BIAS_BIAS_GB_SEL(3) |
+ MG_PLL_BIAS_INIT_DCOAMP(0x3F) |
+ MG_PLL_BIAS_BIAS_BONUS(10) |
+ MG_PLL_BIAS_BIASCAL_EN |
+ MG_PLL_BIAS_CTRIM(12) |
+ MG_PLL_BIAS_VREF_RDAC(4) |
+ MG_PLL_BIAS_IREFTRIM(iref_trim);
+
+ if (refclk_khz == 38400) {
+ pll_state->mg_pll_tdc_coldst_bias_mask =
+ MG_PLL_TDC_COLDST_COLDSTART;
+ pll_state->mg_pll_bias_mask = 0;
+ } else {
+ pll_state->mg_pll_tdc_coldst_bias_mask = -1U;
+ pll_state->mg_pll_bias_mask = -1U;
+ }
- pll_state->mg_pll_tdc_coldst_bias &= pll_state->mg_pll_tdc_coldst_bias_mask;
- pll_state->mg_pll_bias &= pll_state->mg_pll_bias_mask;
+ pll_state->mg_pll_tdc_coldst_bias &=
+ pll_state->mg_pll_tdc_coldst_bias_mask;
+ pll_state->mg_pll_bias &= pll_state->mg_pll_bias_mask;
+ }
return true;
}
--
2.21.0
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^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 09/22] drm/i915/tgl: re-indent code to prepare for DKL changes
2019-07-13 1:09 ` [PATCH 09/22] drm/i915/tgl: re-indent code to prepare for DKL changes Lucas De Marchi
@ 2019-07-22 22:31 ` Atwood, Matthew S
0 siblings, 0 replies; 64+ messages in thread
From: Atwood, Matthew S @ 2019-07-22 22:31 UTC (permalink / raw)
To: intel-gfx, De Marchi, Lucas
On Fri, 2019-07-12 at 18:09 -0700, Lucas De Marchi wrote:
> The final save operation into pll_state of the calculations done will
> be different for DKL PHY. Prepare for that by reindenting code so
> it's
> easier to check for correctness. This one has no change in behavior.
>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 119 ++++++++++----
> ----
> 1 file changed, 66 insertions(+), 53 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 319a26a1ec10..7312a47f79ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2804,60 +2804,73 @@ static bool icl_calc_mg_pll_state(struct
> intel_crtc_state *crtc_state,
> }
> ssc_steplog = 4;
>
> - pll_state->mg_pll_div0 = (m2div_rem > 0 ? MG_PLL_DIV0_FRACNEN_H
> : 0) |
> - MG_PLL_DIV0_FBDIV_FRAC(m2div_frac) |
> - MG_PLL_DIV0_FBDIV_INT(m2div_int);
> -
> - pll_state->mg_pll_div1 = MG_PLL_DIV1_IREF_NDIVRATIO(iref_ndiv)
> |
> - MG_PLL_DIV1_DITHER_DIV_2 |
> - MG_PLL_DIV1_NDIVRATIO(1) |
> - MG_PLL_DIV1_FBPREDIV(m1div);
> -
> - pll_state->mg_pll_lf = MG_PLL_LF_TDCTARGETCNT(tdc_targetcnt) |
> - MG_PLL_LF_AFCCNTSEL_512 |
> - MG_PLL_LF_GAINCTRL(1) |
> - MG_PLL_LF_INT_COEFF(int_coeff) |
> - MG_PLL_LF_PROP_COEFF(prop_coeff);
> -
> - pll_state->mg_pll_frac_lock = MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32
> |
> - MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_3
> 2 |
> - MG_PLL_FRAC_LOCK_LOCKTHRESH(10) |
> - MG_PLL_FRAC_LOCK_DCODITHEREN |
> - MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(fee
> dfwgain);
> - if (use_ssc || m2div_rem > 0)
> - pll_state->mg_pll_frac_lock |=
> MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN;
> -
> - pll_state->mg_pll_ssc = (use_ssc ? MG_PLL_SSC_EN : 0) |
> - MG_PLL_SSC_TYPE(2) |
> - MG_PLL_SSC_STEPLENGTH(ssc_steplen) |
> - MG_PLL_SSC_STEPNUM(ssc_steplog) |
> - MG_PLL_SSC_FLLEN |
> - MG_PLL_SSC_STEPSIZE(ssc_stepsize);
> -
> - pll_state->mg_pll_tdc_coldst_bias = MG_PLL_TDC_COLDST_COLDSTART
> |
> - MG_PLL_TDC_COLDST_IREFINT_E
> N |
> - MG_PLL_TDC_COLDST_REFBIAS_S
> TART_PULSE_W(iref_pulse_w) |
> - MG_PLL_TDC_TDCOVCCORR_EN |
> - MG_PLL_TDC_TDCSEL(3);
> -
> - pll_state->mg_pll_bias = MG_PLL_BIAS_BIAS_GB_SEL(3) |
> - MG_PLL_BIAS_INIT_DCOAMP(0x3F) |
> - MG_PLL_BIAS_BIAS_BONUS(10) |
> - MG_PLL_BIAS_BIASCAL_EN |
> - MG_PLL_BIAS_CTRIM(12) |
> - MG_PLL_BIAS_VREF_RDAC(4) |
> - MG_PLL_BIAS_IREFTRIM(iref_trim);
> -
> - if (refclk_khz == 38400) {
> - pll_state->mg_pll_tdc_coldst_bias_mask =
> MG_PLL_TDC_COLDST_COLDSTART;
> - pll_state->mg_pll_bias_mask = 0;
> - } else {
> - pll_state->mg_pll_tdc_coldst_bias_mask = -1U;
> - pll_state->mg_pll_bias_mask = -1U;
> - }
> + /* write pll_state calculations */
> + {
> + pll_state->mg_pll_div0 =
> + (m2div_rem > 0 ? MG_PLL_DIV0_FRACNEN_H : 0) |
> + MG_PLL_DIV0_FBDIV_FRAC(m2div_frac) |
> + MG_PLL_DIV0_FBDIV_INT(m2div_int);
> +
> + pll_state->mg_pll_div1 =
> + MG_PLL_DIV1_IREF_NDIVRATIO(iref_ndiv) |
> + MG_PLL_DIV1_DITHER_DIV_2 |
> + MG_PLL_DIV1_NDIVRATIO(1) |
> + MG_PLL_DIV1_FBPREDIV(m1div);
> +
> + pll_state->mg_pll_lf =
> + MG_PLL_LF_TDCTARGETCNT(tdc_targetcnt) |
> + MG_PLL_LF_AFCCNTSEL_512 |
> + MG_PLL_LF_GAINCTRL(1) |
> + MG_PLL_LF_INT_COEFF(int_coeff) |
> + MG_PLL_LF_PROP_COEFF(prop_coeff);
> +
> + pll_state->mg_pll_frac_lock =
> + MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 |
> + MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 |
> + MG_PLL_FRAC_LOCK_LOCKTHRESH(10) |
> + MG_PLL_FRAC_LOCK_DCODITHEREN |
> + MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(feedfwgain);
> + if (use_ssc || m2div_rem > 0)
> + pll_state->mg_pll_frac_lock |=
> + MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN;
> +
> + pll_state->mg_pll_ssc =
> + (use_ssc ? MG_PLL_SSC_EN : 0) |
> + MG_PLL_SSC_TYPE(2) |
> + MG_PLL_SSC_STEPLENGTH(ssc_steplen) |
> + MG_PLL_SSC_STEPNUM(ssc_steplog) |
> + MG_PLL_SSC_FLLEN |
> + MG_PLL_SSC_STEPSIZE(ssc_stepsize);
> +
> + pll_state->mg_pll_tdc_coldst_bias =
> + MG_PLL_TDC_COLDST_COLDSTART |
> + MG_PLL_TDC_COLDST_IREFINT_EN |
> + MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(iref_pu
> lse_w) |
> + MG_PLL_TDC_TDCOVCCORR_EN |
> + MG_PLL_TDC_TDCSEL(3);
> +
> + pll_state->mg_pll_bias =
> + MG_PLL_BIAS_BIAS_GB_SEL(3) |
> + MG_PLL_BIAS_INIT_DCOAMP(0x3F) |
> + MG_PLL_BIAS_BIAS_BONUS(10) |
> + MG_PLL_BIAS_BIASCAL_EN |
> + MG_PLL_BIAS_CTRIM(12) |
> + MG_PLL_BIAS_VREF_RDAC(4) |
> + MG_PLL_BIAS_IREFTRIM(iref_trim);
> +
> + if (refclk_khz == 38400) {
> + pll_state->mg_pll_tdc_coldst_bias_mask =
> + MG_PLL_TDC_COLDST_COLDSTART;
> + pll_state->mg_pll_bias_mask = 0;
> + } else {
> + pll_state->mg_pll_tdc_coldst_bias_mask = -1U;
> + pll_state->mg_pll_bias_mask = -1U;
> + }
>
> - pll_state->mg_pll_tdc_coldst_bias &= pll_state-
> >mg_pll_tdc_coldst_bias_mask;
> - pll_state->mg_pll_bias &= pll_state->mg_pll_bias_mask;
> + pll_state->mg_pll_tdc_coldst_bias &=
> + pll_state->mg_pll_tdc_coldst_bias_mask;
> + pll_state->mg_pll_bias &= pll_state->mg_pll_bias_mask;
> + }
>
> return true;
> }
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^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 10/22] drm/i915/tgl: Add DKL phy pll state calculations
2019-07-13 1:09 [PATCH 00/22] Tiger Lake part 2 Lucas De Marchi
` (8 preceding siblings ...)
2019-07-13 1:09 ` [PATCH 09/22] drm/i915/tgl: re-indent code to prepare for DKL changes Lucas De Marchi
@ 2019-07-13 1:09 ` Lucas De Marchi
2019-07-13 1:09 ` [PATCH 11/22] drm/i915/tgl: start adding the DKL PLLs to use on TC ports Lucas De Marchi
` (17 subsequent siblings)
27 siblings, 0 replies; 64+ messages in thread
From: Lucas De Marchi @ 2019-07-13 1:09 UTC (permalink / raw)
To: intel-gfx
From: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reuse the existing calculate icl_calc_mg_pll_state() function.
Since the pll variables are calculated differently for DKL phy, add
support for the same.
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 59 ++++++++++++++++---
1 file changed, 50 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 7312a47f79ad..0ef14023865b 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2625,7 +2625,8 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
u32 *target_dco_khz,
- struct intel_dpll_hw_state *state)
+ struct intel_dpll_hw_state *state,
+ bool is_dkl)
{
u32 dco_min_freq, dco_max_freq;
int div1_vals[] = {7, 5, 3, 2};
@@ -2647,8 +2648,13 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
continue;
if (div2 >= 2) {
- a_divratio = is_dp ? 10 : 5;
- tlinedrv = 2;
+ if (is_dkl) {
+ a_divratio = 5;
+ tlinedrv = 1;
+ } else {
+ a_divratio = is_dp ? 10 : 5;
+ tlinedrv = 2;
+ }
} else {
a_divratio = 5;
tlinedrv = 0;
@@ -2698,7 +2704,8 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
* adapted to integer-only calculation, that's why it looks so different.
*/
static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
- struct intel_dpll_hw_state *pll_state)
+ struct intel_dpll_hw_state *pll_state,
+ bool is_dkl)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
int refclk_khz = dev_priv->cdclk.hw.ref;
@@ -2715,7 +2722,7 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
memset(pll_state, 0, sizeof(*pll_state));
if (!icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
- pll_state)) {
+ pll_state, is_dkl)) {
DRM_DEBUG_KMS("Failed to find divisors for clock %d\n", clock);
return false;
}
@@ -2723,8 +2730,11 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
m1div = 2;
m2div_int = dco_khz / (refclk_khz * m1div);
if (m2div_int > 255) {
- m1div = 4;
- m2div_int = dco_khz / (refclk_khz * m1div);
+ if (!is_dkl) {
+ m1div = 4;
+ m2div_int = dco_khz / (refclk_khz * m1div);
+ }
+
if (m2div_int > 255) {
DRM_DEBUG_KMS("Failed to find mdiv for clock %d\n",
clock);
@@ -2753,6 +2763,12 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
iref_trim = 28;
iref_pulse_w = 1;
break;
+
+ /*
+ * TODO: spec adds a case for ndiv = 4 when refclk > 80MHz,
+ * however this doesn't seem possible from the input.
+ * See Issue 17526.
+ */
default:
MISSING_CASE(refclk_khz);
return false;
@@ -2805,7 +2821,31 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
ssc_steplog = 4;
/* write pll_state calculations */
- {
+ if (is_dkl) {
+ pll_state->mg_pll_div0 =
+ DKL_PLL_DIV0_INTEG_COEFF(int_coeff) |
+ DKL_PLL_DIV0_PROP_COEFF(prop_coeff) |
+ DKL_PLL_DIV0_FBPREDIV(m1div) |
+ DKL_PLL_DIV0_FBDIV_INT(m2div_int);
+
+ pll_state->mg_pll_div1 =
+ DKL_PLL_DIV1_IREF_TRIM(iref_trim) |
+ DKL_PLL_DIV1_TDC_TARGET_CNT(tdc_targetcnt);
+
+ pll_state->mg_pll_ssc =
+ DKL_PLL_SSC_IREF_NDIV_RATIO(iref_ndiv) |
+ DKL_PLL_SSC_STEP_LEN(ssc_steplen) |
+ DKL_PLL_SSC_STEP_NUM(ssc_steplog) |
+ (use_ssc ? DKL_PLL_SSC_EN : 0);
+
+ pll_state->mg_pll_tdc_coldst_bias =
+ DKL_PLL_TDC_SSC_STEP_SIZE(ssc_stepsize) |
+ DKL_PLL_TDC_FEED_FWD_GAIN(feedfwgain);
+
+ pll_state->mg_pll_bias =
+ (m2div_frac > 0 ? DKL_PLL_BIAS_FRAC_EN_H : 0) |
+ DKL_PLL_BIAS_FBDIV_FRAC(m2div_frac);
+ } else {
pll_state->mg_pll_div0 =
(m2div_rem > 0 ? MG_PLL_DIV0_FRACNEN_H : 0) |
MG_PLL_DIV0_FBDIV_FRAC(m2div_frac) |
@@ -2963,6 +3003,7 @@ static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
struct icl_port_dpll *port_dpll;
enum intel_dpll_id dpll_id;
+ bool is_dkl = INTEL_GEN(dev_priv) >= 12;
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
if (!icl_calc_dpll_state(crtc_state, encoder, &port_dpll->hw_state)) {
@@ -2983,7 +3024,7 @@ static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state,
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
- if (!icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state)) {
+ if (!icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state, is_dkl)) {
DRM_DEBUG_KMS("Could not calculate MG PHY PLL state.\n");
goto err_unreference_tbt_pll;
}
--
2.21.0
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^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 11/22] drm/i915/tgl: start adding the DKL PLLs to use on TC ports
2019-07-13 1:09 [PATCH 00/22] Tiger Lake part 2 Lucas De Marchi
` (9 preceding siblings ...)
2019-07-13 1:09 ` [PATCH 10/22] drm/i915/tgl: Add DKL phy pll state calculations Lucas De Marchi
@ 2019-07-13 1:09 ` Lucas De Marchi
2019-07-13 1:09 ` [PATCH 12/22] drm/i915/tgl: Add support for dkl pll write Lucas De Marchi
` (16 subsequent siblings)
27 siblings, 0 replies; 64+ messages in thread
From: Lucas De Marchi @ 2019-07-13 1:09 UTC (permalink / raw)
To: intel-gfx
The disable function can be the same as for MG phy since the same
registers are used. The others are different as registers change -
prepare for that using an empty dkl_pll_write() to be implemented later.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 98 ++++++++++++++++++-
1 file changed, 97 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 0ef14023865b..c59367ff5b10 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3158,6 +3158,60 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv,
return ret;
}
+static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv,
+ struct intel_shared_dpll *pll,
+ struct intel_dpll_hw_state *hw_state)
+{
+ const enum intel_dpll_id id = pll->info->id;
+ enum tc_port tc_port = icl_pll_id_to_tc_port(id);
+ intel_wakeref_t wakeref;
+ bool ret = false;
+ u32 val;
+
+ wakeref = intel_display_power_get_if_enabled(dev_priv,
+ POWER_DOMAIN_DISPLAY_CORE);
+ if (!wakeref)
+ return false;
+
+ val = I915_READ(MG_PLL_ENABLE(tc_port));
+ if (!(val & PLL_ENABLE))
+ goto out;
+
+ /*
+ * All registers read here have the same HIP_INDEX_REG even though
+ * they are on different building blocks
+ */
+ I915_WRITE(HIP_INDEX_REG(tc_port), 0x2);
+
+ hw_state->mg_refclkin_ctl = I915_READ(DKL_REFCLKIN_CTL(tc_port));
+ hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
+
+ hw_state->mg_clktop2_hsclkctl =
+ I915_READ(DKL_CLKTOP2_HSCLKCTL(tc_port));
+ hw_state->mg_clktop2_hsclkctl &=
+ MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
+ MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
+ MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
+ MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK;
+
+ hw_state->mg_clktop2_coreclkctl1 =
+ I915_READ(DKL_CLKTOP2_CORECLKCTL1(tc_port));
+ hw_state->mg_clktop2_coreclkctl1 &=
+ MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
+
+ hw_state->mg_pll_div0 = I915_READ(DKL_PLL_DIV0(tc_port));
+ hw_state->mg_pll_div1 = I915_READ(DKL_PLL_DIV1(tc_port));
+ hw_state->mg_pll_ssc = I915_READ(DKL_PLL_SSC(tc_port));
+ hw_state->mg_pll_bias = I915_READ(DKL_PLL_BIAS(tc_port));
+ hw_state->mg_pll_tdc_coldst_bias =
+ I915_READ(DKL_PLL_TDC_COLDST_BIAS(tc_port));
+
+ ret = true;
+out:
+ intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
+ return ret;
+}
+
static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *hw_state,
@@ -3282,6 +3336,12 @@ static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
POSTING_READ(MG_PLL_TDC_COLDST_BIAS(tc_port));
}
+static void dkl_pll_write(struct drm_i915_private *dev_priv,
+ struct intel_shared_dpll *pll)
+{
+ /* TODO */
+}
+
static void icl_pll_power_enable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
i915_reg_t enable_reg)
@@ -3389,6 +3449,31 @@ static void mg_pll_enable(struct drm_i915_private *dev_priv,
/* DVFS post sequence would be here. See the comment above. */
}
+static void dkl_pll_enable(struct drm_i915_private *dev_priv,
+ struct intel_shared_dpll *pll)
+{
+ /*
+ * From spec: MG register instances are being used for TypeC in general. The
+ * same MG register instances should be programmed for Dekel PLLs as well
+ */
+ i915_reg_t enable_reg =
+ MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id));
+
+ icl_pll_power_enable(dev_priv, pll, enable_reg);
+
+ dkl_pll_write(dev_priv, pll);
+
+ /*
+ * DVFS pre sequence would be here, but in our driver the cdclk code
+ * paths should already be setting the appropriate voltage, hence we do
+ * nothing here.
+ */
+
+ icl_pll_enable(dev_priv, pll, enable_reg);
+
+ /* DVFS post sequence would be here. See the comment above. */
+}
+
static void icl_pll_disable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
i915_reg_t enable_reg)
@@ -3533,11 +3618,22 @@ static const struct intel_dpll_mgr ehl_pll_mgr = {
.dump_hw_state = icl_dump_hw_state,
};
+static const struct intel_shared_dpll_funcs dkl_pll_funcs = {
+ .enable = dkl_pll_enable,
+ .disable = mg_pll_disable,
+ .get_hw_state = dkl_pll_get_hw_state,
+};
+
static const struct dpll_info tgl_plls[] = {
{ "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
{ "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
{ "TBT PLL", &tbt_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
- /* TODO: Add typeC plls */
+ { "TC PLL 1", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL1, 0 },
+ { "TC PLL 2", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL2, 0 },
+ { "TC PLL 3", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL3, 0 },
+ { "TC PLL 4", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL4, 0 },
+ { "TC PLL 5", &dkl_pll_funcs, DPLL_ID_TGL_MGPLL5, 0 },
+ { "TC PLL 6", &dkl_pll_funcs, DPLL_ID_TGL_MGPLL6, 0 },
{ },
};
--
2.21.0
_______________________________________________
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^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 12/22] drm/i915/tgl: Add support for dkl pll write
2019-07-13 1:09 [PATCH 00/22] Tiger Lake part 2 Lucas De Marchi
` (10 preceding siblings ...)
2019-07-13 1:09 ` [PATCH 11/22] drm/i915/tgl: start adding the DKL PLLs to use on TC ports Lucas De Marchi
@ 2019-07-13 1:09 ` Lucas De Marchi
2019-07-13 1:09 ` [PATCH 13/22] drm/i915/gen12: add support for reading the timestamp frequency Lucas De Marchi
` (15 subsequent siblings)
27 siblings, 0 replies; 64+ messages in thread
From: Lucas De Marchi @ 2019-07-13 1:09 UTC (permalink / raw)
To: intel-gfx
From: Vandita Kulkarni <vandita.kulkarni@intel.com>
Add a new function to write to dkl phy pll registers. As per the
spec all the registers are read modify write.
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 65 ++++++++++++++++++-
1 file changed, 64 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index c59367ff5b10..4d33735eeb65 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3339,7 +3339,70 @@ static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
static void dkl_pll_write(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- /* TODO */
+ struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
+ enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
+ u32 val;
+
+ /*
+ * All registers programmed here have the same HIP_INDEX_REG even
+ * though on different building block
+ */
+ I915_WRITE(HIP_INDEX_REG(tc_port), 0x2);
+
+ /* All the registers are RMW */
+ val = I915_READ(DKL_REFCLKIN_CTL(tc_port));
+ val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK;
+ val |= hw_state->mg_refclkin_ctl;
+ I915_WRITE(DKL_REFCLKIN_CTL(tc_port), val);
+
+ val = I915_READ(DKL_CLKTOP2_CORECLKCTL1(tc_port));
+ val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
+ val |= hw_state->mg_clktop2_coreclkctl1;
+ I915_WRITE(DKL_CLKTOP2_CORECLKCTL1(tc_port), val);
+
+ val = I915_READ(DKL_CLKTOP2_HSCLKCTL(tc_port));
+ val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
+ MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
+ MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
+ MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK);
+ val |= hw_state->mg_clktop2_hsclkctl;
+ I915_WRITE(DKL_CLKTOP2_HSCLKCTL(tc_port), val);
+
+ val = I915_READ(DKL_PLL_DIV0(tc_port));
+ val &= ~(DKL_PLL_DIV0_INTEG_COEFF_MASK |
+ DKL_PLL_DIV0_PROP_COEFF_MASK |
+ DKL_PLL_DIV0_FBPREDIV_MASK |
+ DKL_PLL_DIV0_FBDIV_INT_MASK);
+ val |= hw_state->mg_pll_div0;
+ I915_WRITE(DKL_PLL_DIV0(tc_port), val);
+
+ val = I915_READ(DKL_PLL_DIV1(tc_port));
+ val = ~(DKL_PLL_DIV1_IREF_TRIM_MASK |
+ DKL_PLL_DIV1_TDC_TARGET_CNT_MASK);
+ val |= hw_state->mg_pll_div1;
+ I915_WRITE(DKL_PLL_DIV1(tc_port), val);
+
+ val = I915_READ(DKL_PLL_SSC(tc_port));
+ val &= ~(DKL_PLL_SSC_IREF_NDIV_RATIO_MASK |
+ DKL_PLL_SSC_STEP_LEN_MASK |
+ DKL_PLL_SSC_STEP_NUM_MASK |
+ DKL_PLL_SSC_EN);
+ val |= hw_state->mg_pll_ssc;
+ I915_WRITE(DKL_PLL_SSC(tc_port), val);
+
+ val = I915_READ(DKL_PLL_BIAS(tc_port));
+ val &= ~(DKL_PLL_BIAS_FRAC_EN_H |
+ DKL_PLL_BIAS_FBDIV_FRAC_MASK);
+ val |= hw_state->mg_pll_bias;
+ I915_WRITE(DKL_PLL_BIAS(tc_port), val);
+
+ val = I915_READ(DKL_PLL_TDC_COLDST_BIAS(tc_port));
+ val &= ~(DKL_PLL_TDC_SSC_STEP_SIZE_MASK |
+ DKL_PLL_TDC_FEED_FWD_GAIN_MASK);
+ val |= hw_state->mg_pll_tdc_coldst_bias;
+ I915_WRITE(DKL_PLL_TDC_COLDST_BIAS(tc_port), val);
+
+ POSTING_READ(DKL_PLL_TDC_COLDST_BIAS(tc_port));
}
static void icl_pll_power_enable(struct drm_i915_private *dev_priv,
--
2.21.0
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^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 13/22] drm/i915/gen12: add support for reading the timestamp frequency
2019-07-13 1:09 [PATCH 00/22] Tiger Lake part 2 Lucas De Marchi
` (11 preceding siblings ...)
2019-07-13 1:09 ` [PATCH 12/22] drm/i915/tgl: Add support for dkl pll write Lucas De Marchi
@ 2019-07-13 1:09 ` Lucas De Marchi
2019-07-13 1:09 ` [PATCH 14/22] drm/i915/tgl: allow the reg_read ioctl to read the RCS TIMESTAMP register Lucas De Marchi
` (14 subsequent siblings)
27 siblings, 0 replies; 64+ messages in thread
From: Lucas De Marchi @ 2019-07-13 1:09 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Michel Thierry
From: Michel Thierry <michel.thierry@intel.com>
There are no changes with respect to GEN11, which Paulo wrote.
This gets rid of the "Missing switch case in read_timestamp_frequency"
message at boot for Tiger Lake.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index f99c9fd497b2..a3017d16b7f3 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -716,7 +716,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
}
return freq;
- } else if (INTEL_GEN(dev_priv) <= 11) {
+ } else if (INTEL_GEN(dev_priv) <= 12) {
u32 ctc_reg = I915_READ(CTC_MODE);
u32 freq = 0;
--
2.21.0
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^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 14/22] drm/i915/tgl: allow the reg_read ioctl to read the RCS TIMESTAMP register
2019-07-13 1:09 [PATCH 00/22] Tiger Lake part 2 Lucas De Marchi
` (12 preceding siblings ...)
2019-07-13 1:09 ` [PATCH 13/22] drm/i915/gen12: add support for reading the timestamp frequency Lucas De Marchi
@ 2019-07-13 1:09 ` Lucas De Marchi
2019-07-13 1:09 ` [PATCH 15/22] drm/i915/tgl: Introduce initial Tigerlake Workarounds Lucas De Marchi
` (13 subsequent siblings)
27 siblings, 0 replies; 64+ messages in thread
From: Lucas De Marchi @ 2019-07-13 1:09 UTC (permalink / raw)
To: intel-gfx
From: Jordan Justen <jordan.l.justen@intel.com>
This enables the Mesa driver to advertise support for ARB_timer_query,
and thus an OpenGL version higher than 3.2.
Based on the ICL patch by Paulo Zanoni and CNL patch by Nanley Chery.
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 475ab3d4d91d..2b839acfa0f6 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1776,7 +1776,7 @@ static const struct reg_whitelist {
} reg_read_whitelist[] = { {
.offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
.offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
- .gen_mask = INTEL_GEN_MASK(4, 11),
+ .gen_mask = INTEL_GEN_MASK(4, 12),
.size = 8
} };
--
2.21.0
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^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 15/22] drm/i915/tgl: Introduce initial Tigerlake Workarounds
2019-07-13 1:09 [PATCH 00/22] Tiger Lake part 2 Lucas De Marchi
` (13 preceding siblings ...)
2019-07-13 1:09 ` [PATCH 14/22] drm/i915/tgl: allow the reg_read ioctl to read the RCS TIMESTAMP register Lucas De Marchi
@ 2019-07-13 1:09 ` Lucas De Marchi
2019-07-13 1:09 ` [PATCH 16/22] drm/i915/tgl: Implement Wa_1604555607 Lucas De Marchi
` (12 subsequent siblings)
27 siblings, 0 replies; 64+ messages in thread
From: Lucas De Marchi @ 2019-07-13 1:09 UTC (permalink / raw)
To: intel-gfx; +Cc: Michel Thierry
From: Michel Thierry <michel.thierry@intel.com>
Inherit workarounds from previous platforms that are still valid for
Tigerlake.
WaPipelineFlushCoherentLines:tgl (changed register but has same name)
WaSendPushConstantsFromMMIO:tgl
WaAllowUMDToModifySamplerMode:tgl
WaRsForcewakeAddDelayForAck:tgl
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 2 ++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 40 +++++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 3 ++
drivers/gpu/drm/i915/intel_pm.c | 4 ++-
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
5 files changed, 46 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 9e0992498087..239d2bc41e32 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2045,6 +2045,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
return 0;
switch (INTEL_GEN(engine->i915)) {
+ case 12:
+ return 0;
case 11:
return 0;
case 10:
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3b1fc7c8faa8..ed92738a0735 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -582,6 +582,11 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
}
+static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
+ struct i915_wa_list *wal)
+{
+}
+
static void
__intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
struct i915_wa_list *wal,
@@ -594,7 +599,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
wa_init_start(wal, name, engine->name);
- if (IS_GEN(i915, 11))
+ if (IS_GEN(i915, 12))
+ tgl_ctx_workarounds_init(engine, wal);
+ else if (IS_GEN(i915, 11))
icl_ctx_workarounds_init(engine, wal);
else if (IS_CANNONLAKE(i915))
cnl_ctx_workarounds_init(engine, wal);
@@ -895,10 +902,17 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
GAMT_CHKN_DISABLE_L3_COH_PIPE);
}
+static void
+tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+{
+}
+
static void
gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
- if (IS_GEN(i915, 11))
+ if (IS_GEN(i915, 12))
+ tgl_gt_workarounds_init(i915, wal);
+ else if (IS_GEN(i915, 11))
icl_gt_workarounds_init(i915, wal);
else if (IS_CANNONLAKE(i915))
cnl_gt_workarounds_init(i915, wal);
@@ -1188,6 +1202,17 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
}
}
+static void tgl_whitelist_build(struct intel_engine_cs *engine)
+{
+ struct i915_wa_list *w = &engine->whitelist;
+
+ /* WaSendPushConstantsFromMMIO:tgl */
+ whitelist_reg(w, COMMON_SLICE_CHICKEN2);
+
+ /* WaAllowUMDToModifySamplerMode:tgl */
+ whitelist_reg(w, GEN10_SAMPLER_MODE);
+}
+
void intel_engine_init_whitelist(struct intel_engine_cs *engine)
{
struct drm_i915_private *i915 = engine->i915;
@@ -1195,7 +1220,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
wa_init_start(w, "whitelist", engine->name);
- if (IS_GEN(i915, 11))
+ if (IS_GEN(i915, 12))
+ tgl_whitelist_build(engine);
+ else if (IS_GEN(i915, 11))
icl_whitelist_build(engine);
else if (IS_CANNONLAKE(i915))
cnl_whitelist_build(engine);
@@ -1245,6 +1272,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
+ if (IS_GEN(i915, 12)) {
+ /* WaPipelineFlushCoherentLines:tgl */
+ wa_write_or(wal,
+ GEN12_L3SQCREG2,
+ GEN12_LQSC_FLUSH_COHERENT_LINES);
+ }
+
if (IS_GEN(i915, 11)) {
/* This is not an Wa. Enable for better image quality */
wa_masked_en(wal,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 70872c9391ff..0a2657ce284f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7747,6 +7747,9 @@ enum {
#define GEN8_LQSC_RO_PERF_DIS (1 << 27)
#define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21)
+#define GEN12_L3SQCREG2 _MMIO(0xb104)
+#define GEN12_LQSC_FLUSH_COHERENT_LINES (1 << 24)
+
/* GEN8 chicken */
#define HDC_CHICKEN0 _MMIO(0x7300)
#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 22472f2bd31b..b966c736da69 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9608,7 +9608,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
*/
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_GEN(dev_priv, 11))
+ if (IS_GEN(dev_priv, 12))
+ dev_priv->display.init_clock_gating = nop_init_clock_gating;
+ else if (IS_GEN(dev_priv, 11))
dev_priv->display.init_clock_gating = icl_init_clock_gating;
else if (IS_CANNONLAKE(dev_priv))
dev_priv->display.init_clock_gating = cnl_init_clock_gating;
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 2b839acfa0f6..940445d052a4 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -144,7 +144,7 @@ fw_domain_wait_ack_with_fallback(const struct intel_uncore_forcewake_domain *d,
* the fallback ack.
*
* This workaround is described in HSDES #1604254524 and it's known as:
- * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
+ * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl,tgl
* although the name is a bit misleading.
*/
--
2.21.0
_______________________________________________
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^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH 16/22] drm/i915/tgl: Implement Wa_1604555607
2019-07-13 1:09 [PATCH 00/22] Tiger Lake part 2 Lucas De Marchi
` (14 preceding siblings ...)
2019-07-13 1:09 ` [PATCH 15/22] drm/i915/tgl: Introduce initial Tigerlake Workarounds Lucas De Marchi
@ 2019-07-13 1:09 ` Lucas De Marchi
2019-07-18 6:03 ` Tvrtko Ursulin
2019-07-13 1:09 ` [PATCH 17/22] drm/i915/tgl: Implement Wa_1406941453 Lucas De Marchi
` (11 subsequent siblings)
27 siblings, 1 reply; 64+ messages in thread
From: Lucas De Marchi @ 2019-07-13 1:09 UTC (permalink / raw)
To: intel-gfx; +Cc: Michel Thierry
From: Michel Thierry <michel.thierry@intel.com>
Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
FF_MODE2 is part of the register state context, that's why it is
implemented here.
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++++++
drivers/gpu/drm/i915/i915_reg.h | 5 +++++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index ed92738a0735..347ba16346d3 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -585,6 +585,14 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
+ struct drm_i915_private *dev_priv = engine->i915;
+ u32 val;
+
+ /* Wa_1604555607:tgl */
+ val = I915_READ(FF_MODE2);
+ val &= ~FF_MODE2_TDS_TIMER_MASK;
+ val |= FF_MODE2_TDS_TIMER_128;
+ wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
}
static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0a2657ce284f..d048c349e07e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7789,6 +7789,11 @@ enum {
#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15)
#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7)
+#define FF_MODE2 _MMIO(0x6604)
+#define FF_MODE2_TDS_TIMER_SHIFT (16)
+#define FF_MODE2_TDS_TIMER_128 (4 << FF_MODE2_TDS_TIMER_SHIFT)
+#define FF_MODE2_TDS_TIMER_MASK (0xff << FF_MODE2_TDS_TIMER_SHIFT)
+
/* PCH */
#define PCH_DISPLAY_BASE 0xc0000u
--
2.21.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 16/22] drm/i915/tgl: Implement Wa_1604555607
2019-07-13 1:09 ` [PATCH 16/22] drm/i915/tgl: Implement Wa_1604555607 Lucas De Marchi
@ 2019-07-18 6:03 ` Tvrtko Ursulin
2019-07-19 17:41 ` Lucas De Marchi
0 siblings, 1 reply; 64+ messages in thread
From: Tvrtko Ursulin @ 2019-07-18 6:03 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx
On 13/07/2019 02:09, Lucas De Marchi wrote:
> From: Michel Thierry <michel.thierry@intel.com>
>
> Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
> FF_MODE2 is part of the register state context, that's why it is
> implemented here.
>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++++++
> drivers/gpu/drm/i915/i915_reg.h | 5 +++++
> 2 files changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index ed92738a0735..347ba16346d3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -585,6 +585,14 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> {
> + struct drm_i915_private *dev_priv = engine->i915;
> + u32 val;
> +
> + /* Wa_1604555607:tgl */
> + val = I915_READ(FF_MODE2);
Suggest to switch to uncore mmio and get it from the engine.
Regards,
Tvrtko
P.S. Removed Michel from CC.
> + val &= ~FF_MODE2_TDS_TIMER_MASK;
> + val |= FF_MODE2_TDS_TIMER_128;
> + wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
> }
>
> static void
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0a2657ce284f..d048c349e07e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7789,6 +7789,11 @@ enum {
> #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15)
> #define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7)
>
> +#define FF_MODE2 _MMIO(0x6604)
> +#define FF_MODE2_TDS_TIMER_SHIFT (16)
> +#define FF_MODE2_TDS_TIMER_128 (4 << FF_MODE2_TDS_TIMER_SHIFT)
> +#define FF_MODE2_TDS_TIMER_MASK (0xff << FF_MODE2_TDS_TIMER_SHIFT)
> +
> /* PCH */
>
> #define PCH_DISPLAY_BASE 0xc0000u
>
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^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 16/22] drm/i915/tgl: Implement Wa_1604555607
2019-07-18 6:03 ` Tvrtko Ursulin
@ 2019-07-19 17:41 ` Lucas De Marchi
0 siblings, 0 replies; 64+ messages in thread
From: Lucas De Marchi @ 2019-07-19 17:41 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
On Thu, Jul 18, 2019 at 07:03:26AM +0100, Tvrtko Ursulin wrote:
>
>On 13/07/2019 02:09, Lucas De Marchi wrote:
>>From: Michel Thierry <michel.thierry@intel.com>
>>
>>Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
>>FF_MODE2 is part of the register state context, that's why it is
>>implemented here.
>>
>>Signed-off-by: Michel Thierry <michel.thierry@intel.com>
>>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>---
>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++++++
>> drivers/gpu/drm/i915/i915_reg.h | 5 +++++
>> 2 files changed, 13 insertions(+)
>>
>>diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>index ed92738a0735..347ba16346d3 100644
>>--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>@@ -585,6 +585,14 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>> static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
>> struct i915_wa_list *wal)
>> {
>>+ struct drm_i915_private *dev_priv = engine->i915;
>>+ u32 val;
>>+
>>+ /* Wa_1604555607:tgl */
>>+ val = I915_READ(FF_MODE2);
>
>Suggest to switch to uncore mmio and get it from the engine.
will do for next version
thanks
Lucas De Marchi
>
>Regards,
>
>Tvrtko
>
>P.S. Removed Michel from CC.
>
>>+ val &= ~FF_MODE2_TDS_TIMER_MASK;
>>+ val |= FF_MODE2_TDS_TIMER_128;
>>+ wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
>> }
>> static void
>>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>index 0a2657ce284f..d048c349e07e 100644
>>--- a/drivers/gpu/drm/i915/i915_reg.h
>>+++ b/drivers/gpu/drm/i915/i915_reg.h
>>@@ -7789,6 +7789,11 @@ enum {
>> #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15)
>> #define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7)
>>+#define FF_MODE2 _MMIO(0x6604)
>>+#define FF_MODE2_TDS_TIMER_SHIFT (16)
>>+#define FF_MODE2_TDS_TIMER_128 (4 << FF_MODE2_TDS_TIMER_SHIFT)
>>+#define FF_MODE2_TDS_TIMER_MASK (0xff << FF_MODE2_TDS_TIMER_SHIFT)
>>+
>> /* PCH */
>> #define PCH_DISPLAY_BASE 0xc0000u
>>
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^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 17/22] drm/i915/tgl: Implement Wa_1406941453
2019-07-13 1:09 [PATCH 00/22] Tiger Lake part 2 Lucas De Marchi
` (15 preceding siblings ...)
2019-07-13 1:09 ` [PATCH 16/22] drm/i915/tgl: Implement Wa_1604555607 Lucas De Marchi
@ 2019-07-13 1:09 ` Lucas De Marchi
2019-07-23 16:35 ` Summers, Stuart
2019-07-13 1:09 ` [PATCH 18/22] drm/i915/tgl: Define MOCS entries for Tigerlake Lucas De Marchi
` (10 subsequent siblings)
27 siblings, 1 reply; 64+ messages in thread
From: Lucas De Marchi @ 2019-07-13 1:09 UTC (permalink / raw)
To: intel-gfx; +Cc: Michel Thierry
From: Michel Thierry <michel.thierry@intel.com>
Enable Small PL for power benefit.
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 347ba16346d3..f3367339f445 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1285,6 +1285,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
wa_write_or(wal,
GEN12_L3SQCREG2,
GEN12_LQSC_FLUSH_COHERENT_LINES);
+
+ /* Wa_1406941453:tgl */
+ wa_masked_en(wal,
+ SAMPLER_MODE,
+ SAMPLER_ENABLE_SMALL_PL);
}
if (IS_GEN(i915, 11)) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d048c349e07e..712616fcd6b3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9009,6 +9009,9 @@ enum {
#define GEN9_DG_MIRROR_FIX_ENABLE (1 << 5)
#define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3)
+#define SAMPLER_MODE _MMIO(0xe18c)
+#define SAMPLER_ENABLE_SMALL_PL (1 << 15)
+
#define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
#define FLOW_CONTROL_ENABLE (1 << 15)
#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1 << 8)
--
2.21.0
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^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 17/22] drm/i915/tgl: Implement Wa_1406941453
2019-07-13 1:09 ` [PATCH 17/22] drm/i915/tgl: Implement Wa_1406941453 Lucas De Marchi
@ 2019-07-23 16:35 ` Summers, Stuart
0 siblings, 0 replies; 64+ messages in thread
From: Summers, Stuart @ 2019-07-23 16:35 UTC (permalink / raw)
To: intel-gfx, De Marchi, Lucas; +Cc: Thierry, Michel
[-- Attachment #1.1: Type: text/plain, Size: 1715 bytes --]
On Fri, 2019-07-12 at 18:09 -0700, Lucas De Marchi wrote:
> From: Michel Thierry <michel.thierry@intel.com>
>
> Enable Small PL for power benefit.
>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 347ba16346d3..f3367339f445 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1285,6 +1285,11 @@ rcs_engine_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_list *wal)
> wa_write_or(wal,
> GEN12_L3SQCREG2,
> GEN12_LQSC_FLUSH_COHERENT_LINES);
> +
> + /* Wa_1406941453:tgl */
> + wa_masked_en(wal,
> + SAMPLER_MODE,
> + SAMPLER_ENABLE_SMALL_PL);
> }
>
> if (IS_GEN(i915, 11)) {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index d048c349e07e..712616fcd6b3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9009,6 +9009,9 @@ enum {
> #define GEN9_DG_MIRROR_FIX_ENABLE (1 << 5)
> #define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3)
>
> +#define SAMPLER_MODE _MMIO(0xe18c)
> +#define SAMPLER_ENABLE_SMALL_PL (1 << 15)
> +
> #define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
> #define FLOW_CONTROL_ENABLE (1 << 15)
> #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1 << 8)
[-- Attachment #1.2: smime.p7s --]
[-- Type: application/x-pkcs7-signature, Size: 3270 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
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^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 18/22] drm/i915/tgl: Define MOCS entries for Tigerlake
2019-07-13 1:09 [PATCH 00/22] Tiger Lake part 2 Lucas De Marchi
` (16 preceding siblings ...)
2019-07-13 1:09 ` [PATCH 17/22] drm/i915/tgl: Implement Wa_1406941453 Lucas De Marchi
@ 2019-07-13 1:09 ` Lucas De Marchi
2019-07-18 13:08 ` Ville Syrjälä
2019-07-13 1:09 ` [PATCH 19/22] drm/i915/tgl: Tigerlake only has global MOCS registers Lucas De Marchi
` (9 subsequent siblings)
27 siblings, 1 reply; 64+ messages in thread
From: Lucas De Marchi @ 2019-07-13 1:09 UTC (permalink / raw)
To: intel-gfx; +Cc: Mika Kuoppala
From: Tomasz Lis <tomasz.lis@intel.com>
The MOCS table is published as part of bspec, and versioned. Entries
are supposed to never be modified, but new ones can be added. Adding
entries increases table version. The patch includes version 1 entries.
Two of the 3 legacy entries used for gen9 are no longer expected to work.
Although we are changing the gen11 table, those changes are supposed to
be backward compatible since we are only touching previously undefined
entries.
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 25 ++++++++++++++++++++++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 290a5e9b90b9..259e7bec0a63 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -62,6 +62,10 @@ struct drm_i915_mocs_table {
#define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
/* (e)LLC caching options */
+/*
+ * Note: LE_0_PAGETABLE works only up to Gen11; for newer gens it means
+ * the same as LE_UC
+ */
#define LE_0_PAGETABLE _LE_CACHEABILITY(0)
#define LE_1_UC _LE_CACHEABILITY(1)
#define LE_2_WT _LE_CACHEABILITY(2)
@@ -100,8 +104,9 @@ struct drm_i915_mocs_table {
* of bspec.
*
* Entries not part of the following tables are undefined as far as
- * userspace is concerned and shouldn't be relied upon. For the time
- * being they will be initialized to PTE.
+ * userspace is concerned and shouldn't be relied upon. For Gen < 12
+ * they will be initialized to PTE. Gen >= 12 onwards don't have a setting for
+ * PTE. We use the same value, but that actually means Uncached.
*
* The last two entries are reserved by the hardware. For ICL+ they
* should be initialized according to bspec and never used, for older
@@ -137,11 +142,13 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
};
#define GEN11_MOCS_ENTRIES \
- /* Base - Uncached (Deprecated) */ \
+ /* Gen11: Base - Uncached (Deprecated) */ \
+ /* Gen12+: Base - Error (Reserved for Non-Use) */ \
MOCS_ENTRY(I915_MOCS_UNCACHED, \
LE_1_UC | LE_TC_1_LLC, \
L3_1_UC), \
/* Base - L3 + LeCC:PAT (Deprecated) */ \
+ /* Gen12+: Base - Reserved */ \
MOCS_ENTRY(I915_MOCS_PTE, \
LE_0_PAGETABLE | LE_TC_1_LLC, \
L3_3_WB), \
@@ -233,6 +240,18 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
MOCS_ENTRY(23, \
LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(7), \
L3_3_WB), \
+ /* Gen12+: HW Reserved - HDC:L1 + L3 + LLC */ \
+ MOCS_ENTRY(48, \
+ LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
+ L3_3_WB), \
+ /* Gen12+: HW Reserved - HW Special Case (CCS) */ \
+ MOCS_ENTRY(60, \
+ LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
+ L3_1_UC), \
+ /* Gen12+: HW Reserved - HW Special Case (Displayable) */ \
+ MOCS_ENTRY(61, \
+ LE_1_UC | LE_TC_1_LLC | LE_SCF(1), \
+ L3_3_WB), \
/* HW Reserved - SW program but never use */ \
MOCS_ENTRY(62, \
LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
--
2.21.0
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^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 18/22] drm/i915/tgl: Define MOCS entries for Tigerlake
2019-07-13 1:09 ` [PATCH 18/22] drm/i915/tgl: Define MOCS entries for Tigerlake Lucas De Marchi
@ 2019-07-18 13:08 ` Ville Syrjälä
2019-07-18 17:09 ` Daniele Ceraolo Spurio
0 siblings, 1 reply; 64+ messages in thread
From: Ville Syrjälä @ 2019-07-18 13:08 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, Mika Kuoppala
On Fri, Jul 12, 2019 at 06:09:36PM -0700, Lucas De Marchi wrote:
> From: Tomasz Lis <tomasz.lis@intel.com>
>
> The MOCS table is published as part of bspec, and versioned. Entries
> are supposed to never be modified, but new ones can be added. Adding
> entries increases table version. The patch includes version 1 entries.
>
> Two of the 3 legacy entries used for gen9 are no longer expected to work.
> Although we are changing the gen11 table, those changes are supposed to
> be backward compatible since we are only touching previously undefined
> entries.
>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_mocs.c | 25 ++++++++++++++++++++++---
> 1 file changed, 22 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 290a5e9b90b9..259e7bec0a63 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -62,6 +62,10 @@ struct drm_i915_mocs_table {
> #define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
>
> /* (e)LLC caching options */
> +/*
> + * Note: LE_0_PAGETABLE works only up to Gen11; for newer gens it means
> + * the same as LE_UC
> + */
> #define LE_0_PAGETABLE _LE_CACHEABILITY(0)
> #define LE_1_UC _LE_CACHEABILITY(1)
> #define LE_2_WT _LE_CACHEABILITY(2)
> @@ -100,8 +104,9 @@ struct drm_i915_mocs_table {
> * of bspec.
> *
> * Entries not part of the following tables are undefined as far as
> - * userspace is concerned and shouldn't be relied upon. For the time
> - * being they will be initialized to PTE.
> + * userspace is concerned and shouldn't be relied upon. For Gen < 12
> + * they will be initialized to PTE. Gen >= 12 onwards don't have a setting for
> + * PTE. We use the same value, but that actually means Uncached.
> *
> * The last two entries are reserved by the hardware. For ICL+ they
> * should be initialized according to bspec and never used, for older
> @@ -137,11 +142,13 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
> };
>
> #define GEN11_MOCS_ENTRIES \
> - /* Base - Uncached (Deprecated) */ \
> + /* Gen11: Base - Uncached (Deprecated) */ \
> + /* Gen12+: Base - Error (Reserved for Non-Use) */ \
> MOCS_ENTRY(I915_MOCS_UNCACHED, \
> LE_1_UC | LE_TC_1_LLC, \
> L3_1_UC), \
> /* Base - L3 + LeCC:PAT (Deprecated) */ \
> + /* Gen12+: Base - Reserved */ \
> MOCS_ENTRY(I915_MOCS_PTE, \
> LE_0_PAGETABLE | LE_TC_1_LLC, \
> L3_3_WB), \
> @@ -233,6 +240,18 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
> MOCS_ENTRY(23, \
> LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(7), \
> L3_3_WB), \
> + /* Gen12+: HW Reserved - HDC:L1 + L3 + LLC */ \
Why is this marked as reserved? From the looks of things 48-61 should
just be normal entries that userspace can select to get HDC L1$. And
looks like icl already has that stuff. So someone should probably figure
out if Mesa/etc. can make use of the HDC L1$, and if so we should add
the relevant MOCS entries for icl as well.
> + MOCS_ENTRY(48, \
> + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
> + L3_3_WB), \
> + /* Gen12+: HW Reserved - HW Special Case (CCS) */ \
> + MOCS_ENTRY(60, \
> + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
> + L3_1_UC), \
> + /* Gen12+: HW Reserved - HW Special Case (Displayable) */ \
> + MOCS_ENTRY(61, \
> + LE_1_UC | LE_TC_1_LLC | LE_SCF(1), \
> + L3_3_WB), \
> /* HW Reserved - SW program but never use */ \
> MOCS_ENTRY(62, \
> LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
> --
> 2.21.0
--
Ville Syrjälä
Intel
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 18/22] drm/i915/tgl: Define MOCS entries for Tigerlake
2019-07-18 13:08 ` Ville Syrjälä
@ 2019-07-18 17:09 ` Daniele Ceraolo Spurio
2019-07-18 17:44 ` Ville Syrjälä
2019-07-24 22:32 ` Lucas De Marchi
0 siblings, 2 replies; 64+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-07-18 17:09 UTC (permalink / raw)
To: Ville Syrjälä, Lucas De Marchi; +Cc: intel-gfx, Mika Kuoppala
On 7/18/19 6:08 AM, Ville Syrjälä wrote:
> On Fri, Jul 12, 2019 at 06:09:36PM -0700, Lucas De Marchi wrote:
>> From: Tomasz Lis <tomasz.lis@intel.com>
>>
>> The MOCS table is published as part of bspec, and versioned. Entries
>> are supposed to never be modified, but new ones can be added. Adding
>> entries increases table version. The patch includes version 1 entries.
>>
>> Two of the 3 legacy entries used for gen9 are no longer expected to work.
>> Although we are changing the gen11 table, those changes are supposed to
>> be backward compatible since we are only touching previously undefined
>> entries.
>>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
>> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/intel_mocs.c | 25 ++++++++++++++++++++++---
>> 1 file changed, 22 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
>> index 290a5e9b90b9..259e7bec0a63 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
>> @@ -62,6 +62,10 @@ struct drm_i915_mocs_table {
>> #define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
>>
>> /* (e)LLC caching options */
>> +/*
>> + * Note: LE_0_PAGETABLE works only up to Gen11; for newer gens it means
>> + * the same as LE_UC
>> + */
>> #define LE_0_PAGETABLE _LE_CACHEABILITY(0)
>> #define LE_1_UC _LE_CACHEABILITY(1)
>> #define LE_2_WT _LE_CACHEABILITY(2)
>> @@ -100,8 +104,9 @@ struct drm_i915_mocs_table {
>> * of bspec.
>> *
>> * Entries not part of the following tables are undefined as far as
>> - * userspace is concerned and shouldn't be relied upon. For the time
>> - * being they will be initialized to PTE.
>> + * userspace is concerned and shouldn't be relied upon. For Gen < 12
>> + * they will be initialized to PTE. Gen >= 12 onwards don't have a setting for
>> + * PTE. We use the same value, but that actually means Uncached.
>> *
>> * The last two entries are reserved by the hardware. For ICL+ they
>> * should be initialized according to bspec and never used, for older
>> @@ -137,11 +142,13 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
>> };
>>
>> #define GEN11_MOCS_ENTRIES \
>> - /* Base - Uncached (Deprecated) */ \
>> + /* Gen11: Base - Uncached (Deprecated) */ \
>> + /* Gen12+: Base - Error (Reserved for Non-Use) */ \
>> MOCS_ENTRY(I915_MOCS_UNCACHED, \
>> LE_1_UC | LE_TC_1_LLC, \
>> L3_1_UC), \
>> /* Base - L3 + LeCC:PAT (Deprecated) */ \
>> + /* Gen12+: Base - Reserved */ \
>> MOCS_ENTRY(I915_MOCS_PTE, \
>> LE_0_PAGETABLE | LE_TC_1_LLC, \
>> L3_3_WB), \
>> @@ -233,6 +240,18 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
>> MOCS_ENTRY(23, \
>> LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(7), \
>> L3_3_WB), \
>> + /* Gen12+: HW Reserved - HDC:L1 + L3 + LLC */ \
>
> Why is this marked as reserved? From the looks of things 48-61 should
> just be normal entries that userspace can select to get HDC L1$. And
> looks like icl already has that stuff. So someone should probably figure
> out if Mesa/etc. can make use of the HDC L1$, and if so we should add
> the relevant MOCS entries for icl as well.
Here the reserved terminology is indeed misleading. The 48-59 range is a
"special" range where L1 usage is implicitly enabled by the HW, as there
is no explicit L1 toggle in the MOCS registers. The reserved here means
that the range shouldn't be used for "normal" MOCS settings, but SW can
freely use these entries as needed. Similarly, MOCS 60 and 61 are
reserved for other special purposes, but are still usable by SW. The
only entries SW shouldn't touch are 62 and 63.
Regarding ICL, Gen11 HW doesn't have the capability so no new entries
are required there.
>
>> + MOCS_ENTRY(48, \
>> + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
>> + L3_3_WB), \
>> + /* Gen12+: HW Reserved - HW Special Case (CCS) */ \
The specs have MOCS 49-51 defined as well.
Daniele
>> + MOCS_ENTRY(60, \
>> + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
>> + L3_1_UC), \
>> + /* Gen12+: HW Reserved - HW Special Case (Displayable) */ \
>> + MOCS_ENTRY(61, \
>> + LE_1_UC | LE_TC_1_LLC | LE_SCF(1), \
>> + L3_3_WB), \
>> /* HW Reserved - SW program but never use */ \
>> MOCS_ENTRY(62, \
>> LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
>> --
>> 2.21.0
>
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 18/22] drm/i915/tgl: Define MOCS entries for Tigerlake
2019-07-18 17:09 ` Daniele Ceraolo Spurio
@ 2019-07-18 17:44 ` Ville Syrjälä
2019-07-24 22:32 ` Lucas De Marchi
1 sibling, 0 replies; 64+ messages in thread
From: Ville Syrjälä @ 2019-07-18 17:44 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx, Lucas De Marchi, Mika Kuoppala
On Thu, Jul 18, 2019 at 10:09:27AM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 7/18/19 6:08 AM, Ville Syrjälä wrote:
> > On Fri, Jul 12, 2019 at 06:09:36PM -0700, Lucas De Marchi wrote:
> >> From: Tomasz Lis <tomasz.lis@intel.com>
> >>
> >> The MOCS table is published as part of bspec, and versioned. Entries
> >> are supposed to never be modified, but new ones can be added. Adding
> >> entries increases table version. The patch includes version 1 entries.
> >>
> >> Two of the 3 legacy entries used for gen9 are no longer expected to work.
> >> Although we are changing the gen11 table, those changes are supposed to
> >> be backward compatible since we are only touching previously undefined
> >> entries.
> >>
> >> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> >> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> >> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> >> Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
> >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/gt/intel_mocs.c | 25 ++++++++++++++++++++++---
> >> 1 file changed, 22 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> >> index 290a5e9b90b9..259e7bec0a63 100644
> >> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> >> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> >> @@ -62,6 +62,10 @@ struct drm_i915_mocs_table {
> >> #define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
> >>
> >> /* (e)LLC caching options */
> >> +/*
> >> + * Note: LE_0_PAGETABLE works only up to Gen11; for newer gens it means
> >> + * the same as LE_UC
> >> + */
> >> #define LE_0_PAGETABLE _LE_CACHEABILITY(0)
> >> #define LE_1_UC _LE_CACHEABILITY(1)
> >> #define LE_2_WT _LE_CACHEABILITY(2)
> >> @@ -100,8 +104,9 @@ struct drm_i915_mocs_table {
> >> * of bspec.
> >> *
> >> * Entries not part of the following tables are undefined as far as
> >> - * userspace is concerned and shouldn't be relied upon. For the time
> >> - * being they will be initialized to PTE.
> >> + * userspace is concerned and shouldn't be relied upon. For Gen < 12
> >> + * they will be initialized to PTE. Gen >= 12 onwards don't have a setting for
> >> + * PTE. We use the same value, but that actually means Uncached.
> >> *
> >> * The last two entries are reserved by the hardware. For ICL+ they
> >> * should be initialized according to bspec and never used, for older
> >> @@ -137,11 +142,13 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
> >> };
> >>
> >> #define GEN11_MOCS_ENTRIES \
> >> - /* Base - Uncached (Deprecated) */ \
> >> + /* Gen11: Base - Uncached (Deprecated) */ \
> >> + /* Gen12+: Base - Error (Reserved for Non-Use) */ \
> >> MOCS_ENTRY(I915_MOCS_UNCACHED, \
> >> LE_1_UC | LE_TC_1_LLC, \
> >> L3_1_UC), \
> >> /* Base - L3 + LeCC:PAT (Deprecated) */ \
> >> + /* Gen12+: Base - Reserved */ \
> >> MOCS_ENTRY(I915_MOCS_PTE, \
> >> LE_0_PAGETABLE | LE_TC_1_LLC, \
> >> L3_3_WB), \
> >> @@ -233,6 +240,18 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
> >> MOCS_ENTRY(23, \
> >> LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(7), \
> >> L3_3_WB), \
> >> + /* Gen12+: HW Reserved - HDC:L1 + L3 + LLC */ \
> >
> > Why is this marked as reserved? From the looks of things 48-61 should
> > just be normal entries that userspace can select to get HDC L1$. And
> > looks like icl already has that stuff. So someone should probably figure
> > out if Mesa/etc. can make use of the HDC L1$, and if so we should add
> > the relevant MOCS entries for icl as well.
>
> Here the reserved terminology is indeed misleading. The 48-59 range is a
> "special" range where L1 usage is implicitly enabled by the HW, as there
> is no explicit L1 toggle in the MOCS registers. The reserved here means
> that the range shouldn't be used for "normal" MOCS settings, but SW can
> freely use these entries as needed. Similarly, MOCS 60 and 61 are
> reserved for other special purposes, but are still usable by SW. The
> only entries SW shouldn't touch are 62 and 63.
>
> Regarding ICL, Gen11 HW doesn't have the capability so no new entries
> are required there.
Hmm. The table doesn't list those entries, but HDC_CHICKEN2 seems to be
saying the features is in there. HDC_MODE also talks about HDC L1$.
Confusing.
>
> >
> >> + MOCS_ENTRY(48, \
> >> + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
> >> + L3_3_WB), \
> >> + /* Gen12+: HW Reserved - HW Special Case (CCS) */ \
>
> The specs have MOCS 49-51 defined as well.
>
> Daniele
>
> >> + MOCS_ENTRY(60, \
> >> + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
> >> + L3_1_UC), \
> >> + /* Gen12+: HW Reserved - HW Special Case (Displayable) */ \
> >> + MOCS_ENTRY(61, \
> >> + LE_1_UC | LE_TC_1_LLC | LE_SCF(1), \
> >> + L3_3_WB), \
> >> /* HW Reserved - SW program but never use */ \
> >> MOCS_ENTRY(62, \
> >> LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
> >> --
> >> 2.21.0
> >
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 18/22] drm/i915/tgl: Define MOCS entries for Tigerlake
2019-07-18 17:09 ` Daniele Ceraolo Spurio
2019-07-18 17:44 ` Ville Syrjälä
@ 2019-07-24 22:32 ` Lucas De Marchi
2019-07-25 18:26 ` Lis, Tomasz
1 sibling, 1 reply; 64+ messages in thread
From: Lucas De Marchi @ 2019-07-24 22:32 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx, Mika Kuoppala
On Thu, Jul 18, 2019 at 10:09:27AM -0700, Daniele Ceraolo Spurio wrote:
>
>
>On 7/18/19 6:08 AM, Ville Syrjälä wrote:
>>On Fri, Jul 12, 2019 at 06:09:36PM -0700, Lucas De Marchi wrote:
>>>From: Tomasz Lis <tomasz.lis@intel.com>
>>>
>>>The MOCS table is published as part of bspec, and versioned. Entries
>>>are supposed to never be modified, but new ones can be added. Adding
>>>entries increases table version. The patch includes version 1 entries.
>>>
>>>Two of the 3 legacy entries used for gen9 are no longer expected to work.
>>>Although we are changing the gen11 table, those changes are supposed to
>>>be backward compatible since we are only touching previously undefined
>>>entries.
>>>
>>>Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>>>Cc: Mika Kuoppala <mika.kuoppala@intel.com>
>>>Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>>>Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
>>>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>>---
>>> drivers/gpu/drm/i915/gt/intel_mocs.c | 25 ++++++++++++++++++++++---
>>> 1 file changed, 22 insertions(+), 3 deletions(-)
>>>
>>>diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
>>>index 290a5e9b90b9..259e7bec0a63 100644
>>>--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
>>>+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
>>>@@ -62,6 +62,10 @@ struct drm_i915_mocs_table {
>>> #define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
>>> /* (e)LLC caching options */
>>>+/*
>>>+ * Note: LE_0_PAGETABLE works only up to Gen11; for newer gens it means
>>>+ * the same as LE_UC
>>>+ */
>>> #define LE_0_PAGETABLE _LE_CACHEABILITY(0)
>>> #define LE_1_UC _LE_CACHEABILITY(1)
>>> #define LE_2_WT _LE_CACHEABILITY(2)
>>>@@ -100,8 +104,9 @@ struct drm_i915_mocs_table {
>>> * of bspec.
>>> *
>>> * Entries not part of the following tables are undefined as far as
>>>- * userspace is concerned and shouldn't be relied upon. For the time
>>>- * being they will be initialized to PTE.
>>>+ * userspace is concerned and shouldn't be relied upon. For Gen < 12
>>>+ * they will be initialized to PTE. Gen >= 12 onwards don't have a setting for
>>>+ * PTE. We use the same value, but that actually means Uncached.
>>> *
>>> * The last two entries are reserved by the hardware. For ICL+ they
>>> * should be initialized according to bspec and never used, for older
>>>@@ -137,11 +142,13 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
>>> };
>>> #define GEN11_MOCS_ENTRIES \
>>>- /* Base - Uncached (Deprecated) */ \
>>>+ /* Gen11: Base - Uncached (Deprecated) */ \
>>>+ /* Gen12+: Base - Error (Reserved for Non-Use) */ \
>>> MOCS_ENTRY(I915_MOCS_UNCACHED, \
>>> LE_1_UC | LE_TC_1_LLC, \
>>> L3_1_UC), \
>>> /* Base - L3 + LeCC:PAT (Deprecated) */ \
>>>+ /* Gen12+: Base - Reserved */ \
>>> MOCS_ENTRY(I915_MOCS_PTE, \
>>> LE_0_PAGETABLE | LE_TC_1_LLC, \
>>> L3_3_WB), \
>>>@@ -233,6 +240,18 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
>>> MOCS_ENTRY(23, \
>>> LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(7), \
>>> L3_3_WB), \
>>>+ /* Gen12+: HW Reserved - HDC:L1 + L3 + LLC */ \
>>
>>Why is this marked as reserved? From the looks of things 48-61 should
>>just be normal entries that userspace can select to get HDC L1$. And
>>looks like icl already has that stuff. So someone should probably figure
>>out if Mesa/etc. can make use of the HDC L1$, and if so we should add
>>the relevant MOCS entries for icl as well.
>
>Here the reserved terminology is indeed misleading. The 48-59 range is
>a "special" range where L1 usage is implicitly enabled by the HW, as
>there is no explicit L1 toggle in the MOCS registers. The reserved
>here means that the range shouldn't be used for "normal" MOCS
>settings, but SW can freely use these entries as needed. Similarly,
>MOCS 60 and 61 are reserved for other special purposes, but are still
>usable by SW. The only entries SW shouldn't touch are 62 and 63.
>
>Regarding ICL, Gen11 HW doesn't have the capability so no new entries
>are required there.
>
>>
>>>+ MOCS_ENTRY(48, \
>>>+ LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
>>>+ L3_3_WB), \
>>>+ /* Gen12+: HW Reserved - HW Special Case (CCS) */ \
>
>The specs have MOCS 49-51 defined as well.
humn... it seems they got added later.
I'm not sure anymore if we should update igt so it doesn't expect those
entries to be set to PTE or if we should stop reusing the same table for
ICL and TGL. Spec doesn't mention the compatibility of this table with
gen 11 anymore. Thoughts?
Lucas De Marchi
>
>Daniele
>
>>>+ MOCS_ENTRY(60, \
>>>+ LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
>>>+ L3_1_UC), \
>>>+ /* Gen12+: HW Reserved - HW Special Case (Displayable) */ \
>>>+ MOCS_ENTRY(61, \
>>>+ LE_1_UC | LE_TC_1_LLC | LE_SCF(1), \
>>>+ L3_3_WB), \
>>> /* HW Reserved - SW program but never use */ \
>>> MOCS_ENTRY(62, \
>>> LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
>>>--
>>>2.21.0
>>
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 18/22] drm/i915/tgl: Define MOCS entries for Tigerlake
2019-07-24 22:32 ` Lucas De Marchi
@ 2019-07-25 18:26 ` Lis, Tomasz
0 siblings, 0 replies; 64+ messages in thread
From: Lis, Tomasz @ 2019-07-25 18:26 UTC (permalink / raw)
To: Lucas De Marchi, Daniele Ceraolo Spurio; +Cc: intel-gfx, Mika Kuoppala
On 2019-07-25 00:32, Lucas De Marchi wrote:
> On Thu, Jul 18, 2019 at 10:09:27AM -0700, Daniele Ceraolo Spurio wrote:
>>
>>
>> On 7/18/19 6:08 AM, Ville Syrjälä wrote:
>>> On Fri, Jul 12, 2019 at 06:09:36PM -0700, Lucas De Marchi wrote:
>>>> From: Tomasz Lis <tomasz.lis@intel.com>
>>>>
>>>> The MOCS table is published as part of bspec, and versioned. Entries
>>>> are supposed to never be modified, but new ones can be added. Adding
>>>> entries increases table version. The patch includes version 1 entries.
>>>>
>>>> Two of the 3 legacy entries used for gen9 are no longer expected to
>>>> work.
>>>> Although we are changing the gen11 table, those changes are
>>>> supposed to
>>>> be backward compatible since we are only touching previously undefined
>>>> entries.
>>>>
>>>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>>>> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
>>>> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>>>> Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
>>>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/gt/intel_mocs.c | 25 ++++++++++++++++++++++---
>>>> 1 file changed, 22 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
>>>> b/drivers/gpu/drm/i915/gt/intel_mocs.c
>>>> index 290a5e9b90b9..259e7bec0a63 100644
>>>> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
>>>> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
>>>> @@ -62,6 +62,10 @@ struct drm_i915_mocs_table {
>>>> #define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but
>>>> configured. */
>>>> /* (e)LLC caching options */
>>>> +/*
>>>> + * Note: LE_0_PAGETABLE works only up to Gen11; for newer gens it
>>>> means
>>>> + * the same as LE_UC
>>>> + */
>>>> #define LE_0_PAGETABLE _LE_CACHEABILITY(0)
>>>> #define LE_1_UC _LE_CACHEABILITY(1)
>>>> #define LE_2_WT _LE_CACHEABILITY(2)
>>>> @@ -100,8 +104,9 @@ struct drm_i915_mocs_table {
>>>> * of bspec.
>>>> *
>>>> * Entries not part of the following tables are undefined as far as
>>>> - * userspace is concerned and shouldn't be relied upon. For the time
>>>> - * being they will be initialized to PTE.
>>>> + * userspace is concerned and shouldn't be relied upon. For Gen < 12
>>>> + * they will be initialized to PTE. Gen >= 12 onwards don't have a
>>>> setting for
>>>> + * PTE. We use the same value, but that actually means Uncached.
>>>> *
>>>> * The last two entries are reserved by the hardware. For ICL+ they
>>>> * should be initialized according to bspec and never used, for older
>>>> @@ -137,11 +142,13 @@ static const struct drm_i915_mocs_entry
>>>> broxton_mocs_table[] = {
>>>> };
>>>> #define GEN11_MOCS_ENTRIES \
>>>> - /* Base - Uncached (Deprecated) */ \
>>>> + /* Gen11: Base - Uncached (Deprecated) */ \
>>>> + /* Gen12+: Base - Error (Reserved for Non-Use) */ \
>>>> MOCS_ENTRY(I915_MOCS_UNCACHED, \
>>>> LE_1_UC | LE_TC_1_LLC, \
>>>> L3_1_UC), \
>>>> /* Base - L3 + LeCC:PAT (Deprecated) */ \
>>>> + /* Gen12+: Base - Reserved */ \
>>>> MOCS_ENTRY(I915_MOCS_PTE, \
>>>> LE_0_PAGETABLE | LE_TC_1_LLC, \
>>>> L3_3_WB), \
>>>> @@ -233,6 +240,18 @@ static const struct drm_i915_mocs_entry
>>>> broxton_mocs_table[] = {
>>>> MOCS_ENTRY(23, \
>>>> LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) |
>>>> LE_SCC(7), \
>>>> L3_3_WB), \
>>>> + /* Gen12+: HW Reserved - HDC:L1 + L3 + LLC */ \
>>>
>>> Why is this marked as reserved? From the looks of things 48-61 should
>>> just be normal entries that userspace can select to get HDC L1$. And
>>> looks like icl already has that stuff. So someone should probably
>>> figure
>>> out if Mesa/etc. can make use of the HDC L1$, and if so we should add
>>> the relevant MOCS entries for icl as well.
>>
>> Here the reserved terminology is indeed misleading. The 48-59 range
>> is a "special" range where L1 usage is implicitly enabled by the HW,
>> as there is no explicit L1 toggle in the MOCS registers. The reserved
>> here means that the range shouldn't be used for "normal" MOCS
>> settings, but SW can freely use these entries as needed. Similarly,
>> MOCS 60 and 61 are reserved for other special purposes, but are still
>> usable by SW. The only entries SW shouldn't touch are 62 and 63.
>>
>> Regarding ICL, Gen11 HW doesn't have the capability so no new entries
>> are required there.
It might be a good idea to find a better word for it than "reserved".
Not only for this patch, but to be used everywhere, especially the spec.
But that exceeds the scope of this review.
>>
>>>
>>>> + MOCS_ENTRY(48, \
>>>> + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
>>>> + L3_3_WB), \
>>>> + /* Gen12+: HW Reserved - HW Special Case (CCS) */ \
>>
>> The specs have MOCS 49-51 defined as well.
>
> humn... it seems they got added later.
>
> I'm not sure anymore if we should update igt so it doesn't expect those
> entries to be set to PTE or if we should stop reusing the same table for
> ICL and TGL. Spec doesn't mention the compatibility of this table with
> gen 11 anymore. Thoughts?
>
>
It doesn't sound right to change the implementation decision to keep them
together, only because this allows to keep tests intact.
I don't believe there's a reason to verify undefined entries in IGT.
Sometimes we do want to verify our specific implementation instead of
pure specs compliance; but I don't see a reason for this should be the
case here.
The existing MOCS entries are supposed to be unchangeable (in the boundary
of specific platform). So the chances of having to split the tables in
the future are
low (both tables would have to define V2 entries at same indexes, and define
them differently).
-Tomasz
> Lucas De Marchi
>
>>
>> Daniele
>>
>>>> + MOCS_ENTRY(60, \
>>>> + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
>>>> + L3_1_UC), \
>>>> + /* Gen12+: HW Reserved - HW Special Case (Displayable) */ \
>>>> + MOCS_ENTRY(61, \
>>>> + LE_1_UC | LE_TC_1_LLC | LE_SCF(1), \
>>>> + L3_3_WB), \
>>>> /* HW Reserved - SW program but never use */ \
>>>> MOCS_ENTRY(62, \
>>>> LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
>>>> --
>>>> 2.21.0
>>>
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 19/22] drm/i915/tgl: Tigerlake only has global MOCS registers
2019-07-13 1:09 [PATCH 00/22] Tiger Lake part 2 Lucas De Marchi
` (17 preceding siblings ...)
2019-07-13 1:09 ` [PATCH 18/22] drm/i915/tgl: Define MOCS entries for Tigerlake Lucas De Marchi
@ 2019-07-13 1:09 ` Lucas De Marchi
2019-07-18 17:40 ` Daniele Ceraolo Spurio
2019-07-13 1:09 ` [PATCH 20/22] drm/i915: Move MOCS setup to intel_mocs.c Lucas De Marchi
` (8 subsequent siblings)
27 siblings, 1 reply; 64+ messages in thread
From: Lucas De Marchi @ 2019-07-13 1:09 UTC (permalink / raw)
To: intel-gfx; +Cc: Michel Thierry
From: Michel Thierry <michel.thierry@intel.com>
Until Icelake, each engine had its own set of 64 MOCS registers. In
order to simplify, Tigerlake moves to only 64 Global MOCS registers,
which are no longer part of the engine context. Since these registers
are now global, they also only need to be initialized once.
These new global MOCS registers are located in the same offset of the
render MOCS register from previous platforms.
From Gen12 onwards, MOCS must specify the target cache (3:2) and LRU
management (5:4) fields and cannot be programmed to 'use the value from
Private PAT', because these fields are no longer part of the PPAT. Also
cacheability control (1:0) field has changed, 00 no longer means 'use
controls from page table', but uncacheable (UC).
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Tomasz Lis <tomasz.lis@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt.c | 12 ++++--
drivers/gpu/drm/i915/gt/intel_mocs.c | 47 ++++++++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_mocs.h | 1 +
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_gem.c | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c | 11 ++++--
drivers/gpu/drm/i915/i915_pci.c | 3 +-
drivers/gpu/drm/i915/i915_reg.h | 3 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
9 files changed, 74 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index f7e69db4019d..958edfda2ba2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -80,8 +80,11 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
}
if (INTEL_GEN(i915) >= 8) {
- rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
- intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
+ i915_reg_t fault_reg = (INTEL_GEN(i915) >= 12) ?
+ GEN12_RING_FAULT_REG :
+ GEN8_RING_FAULT_REG;
+ rmw_clear(uncore, fault_reg, RING_FAULT_VALID);
+ intel_uncore_posting_read(uncore, fault_reg);
} else if (INTEL_GEN(i915) >= 6) {
struct intel_engine_cs *engine;
enum intel_engine_id id;
@@ -117,7 +120,10 @@ static void gen6_check_faults(struct intel_gt *gt)
static void gen8_check_faults(struct intel_gt *gt)
{
struct intel_uncore *uncore = gt->uncore;
- u32 fault = intel_uncore_read(uncore, GEN8_RING_FAULT_REG);
+ i915_reg_t fault_reg =
+ (INTEL_GEN(gt->i915) >= 12) ?
+ GEN12_RING_FAULT_REG : GEN8_RING_FAULT_REG;
+ u32 fault = intel_uncore_read(uncore, fault_reg);
if (fault & RING_FAULT_VALID) {
u32 fault_data0, fault_data1;
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 259e7bec0a63..365d8ff11f23 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -365,6 +365,10 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
unsigned int index;
u32 unused_value;
+ /* Platforms with global MOCS do not need per-engine initialization. */
+ if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
+ return;
+
/* Called under a blanket forcewake */
assert_forcewakes_active(uncore, FORCEWAKE_ALL);
@@ -389,6 +393,46 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
unused_value);
}
+/**
+ * intel_mocs_init_global() - program the global mocs registers
+ * gt: pointer to struct intel_gt
+ *
+ * This function initializes the MOCS global registers.
+ */
+void intel_mocs_init_global(struct intel_gt *gt)
+{
+ struct intel_uncore *uncore = gt->uncore;
+ struct drm_i915_mocs_table table;
+ unsigned int index;
+
+ if (!HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
+ return;
+
+ if (!get_mocs_settings(gt, &table))
+ return;
+
+ if (GEM_DEBUG_WARN_ON(table.size > table.n_entries))
+ return;
+
+ for (index = 0; index < table.size; index++)
+ intel_uncore_write(uncore,
+ GEN12_GLOBAL_MOCS(index),
+ table.table[index].control_value);
+
+ /*
+ * Ok, now set the unused entries to uncached. These entries
+ * are officially undefined and no contract for the contents
+ * and settings is given for these entries.
+ *
+ * Entry 0 in the table is uncached - so we are just writing
+ * that value to all the used entries.
+ */
+ for (; index < table.n_entries; index++)
+ intel_uncore_write(uncore,
+ GEN12_GLOBAL_MOCS(index),
+ table.table[0].control_value);
+}
+
/**
* emit_mocs_control_table() - emit the mocs control table
* @rq: Request to set up the MOCS table for.
@@ -592,6 +636,9 @@ int intel_rcs_context_init_mocs(struct i915_request *rq)
struct drm_i915_mocs_table t;
int ret;
+ if (HAS_GLOBAL_MOCS_REGISTERS(rq->i915))
+ return 0;
+
if (get_mocs_settings(rq->engine->gt, &t)) {
/* Program the RCS control registers */
ret = emit_mocs_control_table(rq, &t);
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h b/drivers/gpu/drm/i915/gt/intel_mocs.h
index 8b9813e6f9ac..aa3a2df07c82 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.h
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.h
@@ -56,6 +56,7 @@ struct intel_gt;
int intel_rcs_context_init_mocs(struct i915_request *rq);
void intel_mocs_init_l3cc_table(struct intel_gt *gt);
+void intel_mocs_init_global(struct intel_gt *gt);
void intel_mocs_init_engine(struct intel_engine_cs *engine);
#endif
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 069337f11872..57c05650d3b3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2308,6 +2308,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
+#define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs)
+
#define INTEL_PCH_DEVICE_ID_MASK 0xff80
#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e24955b5ebc2..d23e156f6659 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1254,6 +1254,7 @@ int i915_gem_init_hw(struct drm_i915_private *i915)
goto out;
}
+ intel_mocs_init_global(gt);
intel_mocs_init_l3cc_table(gt);
intel_engines_set_scheduler_caps(i915);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 5489cd879315..ee40c14caa64 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1153,7 +1153,10 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
if (INTEL_GEN(dev_priv) >= 6) {
ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL);
- if (INTEL_GEN(dev_priv) >= 8)
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ ee->fault_reg = I915_READ(GEN12_RING_FAULT_REG);
+ else if (INTEL_GEN(dev_priv) >= 8)
ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);
else
ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine);
@@ -1613,8 +1616,10 @@ static void capture_reg_state(struct i915_gpu_state *error)
if (INTEL_GEN(i915) >= 6) {
error->derrmr = intel_uncore_read(uncore, DERRMR);
- error->error = intel_uncore_read(uncore, ERROR_GEN6);
- error->done_reg = intel_uncore_read(uncore, DONE_REG);
+ if (INTEL_GEN(i915) < 12) {
+ error->error = intel_uncore_read(uncore, ERROR_GEN6);
+ error->done_reg = intel_uncore_read(uncore, DONE_REG);
+ }
}
if (INTEL_GEN(i915) >= 5)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 40076ba431d4..f0e19ef2e71a 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -783,7 +783,8 @@ static const struct intel_device_info intel_elkhartlake_info = {
[TRANSCODER_D] = TRANSCODER_D_OFFSET, \
[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
- }
+ }, \
+ .has_global_mocs = 1
static const struct intel_device_info intel_tigerlake_12_info = {
GEN12_FEATURES,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 712616fcd6b3..6cfcdf6bb1bb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2490,6 +2490,7 @@ enum i915_power_well_id {
#define RENDER_HWS_PGA_GEN7 _MMIO(0x04080)
#define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 * (engine)->hw_id)
#define GEN8_RING_FAULT_REG _MMIO(0x4094)
+#define GEN12_RING_FAULT_REG _MMIO(0xcec4)
#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
#define RING_FAULT_GTTSEL_MASK (1 << 11)
#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
@@ -11362,6 +11363,8 @@ enum skl_power_gate {
#define PMFLUSH_GAPL3UNBLOCK (1 << 21)
#define PMFLUSHDONE_LNEBLK (1 << 22)
+#define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
+
/* gamt regs */
#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 45a9badc9b8e..aea7d143ec47 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -112,6 +112,7 @@ enum intel_ppgtt_type {
func(gpu_reset_clobbers_display); \
func(has_reset_engine); \
func(has_fpga_dbg); \
+ func(has_global_mocs); \
func(has_guc); \
func(has_l3_dpf); \
func(has_llc); \
--
2.21.0
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^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 19/22] drm/i915/tgl: Tigerlake only has global MOCS registers
2019-07-13 1:09 ` [PATCH 19/22] drm/i915/tgl: Tigerlake only has global MOCS registers Lucas De Marchi
@ 2019-07-18 17:40 ` Daniele Ceraolo Spurio
2019-07-19 19:42 ` Lucas De Marchi
0 siblings, 1 reply; 64+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-07-18 17:40 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx; +Cc: Michel Thierry
On 7/12/19 6:09 PM, Lucas De Marchi wrote:
> From: Michel Thierry <michel.thierry@intel.com>
>
> Until Icelake, each engine had its own set of 64 MOCS registers. In
> order to simplify, Tigerlake moves to only 64 Global MOCS registers,
> which are no longer part of the engine context. Since these registers
> are now global, they also only need to be initialized once.
>
> These new global MOCS registers are located in the same offset of the
> render MOCS register from previous platforms.
No, they're not :). They're located in a new range, which overlaps with
the location where the fault register was previously located and that's
why the offset of that one has been changed as well. The code does the
right thing, so only this sentence needs fixing.
the FAULT_TLB_DATA* registers have been moved as well as part of the
re-org, so maybe we can have a patch that just moves all the offsets and
then add the global mocs on top?
>
> From Gen12 onwards, MOCS must specify the target cache (3:2) and LRU
> management (5:4) fields and cannot be programmed to 'use the value from
> Private PAT', because these fields are no longer part of the PPAT. Also
> cacheability control (1:0) field has changed, 00 no longer means 'use
> controls from page table', but uncacheable (UC).
Should we put this as a comment in the code somewhere? Although I'm not
sure we have any use for this info since we copy the table straight from
the specs and we should probably trust it is correct.
Daniele
>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Tomasz Lis <tomasz.lis@intel.com>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 12 ++++--
> drivers/gpu/drm/i915/gt/intel_mocs.c | 47 ++++++++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_mocs.h | 1 +
> drivers/gpu/drm/i915/i915_drv.h | 2 +
> drivers/gpu/drm/i915/i915_gem.c | 1 +
> drivers/gpu/drm/i915/i915_gpu_error.c | 11 ++++--
> drivers/gpu/drm/i915/i915_pci.c | 3 +-
> drivers/gpu/drm/i915/i915_reg.h | 3 ++
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> 9 files changed, 74 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index f7e69db4019d..958edfda2ba2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -80,8 +80,11 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
> }
>
> if (INTEL_GEN(i915) >= 8) {
> - rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
> - intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
> + i915_reg_t fault_reg = (INTEL_GEN(i915) >= 12) ?
> + GEN12_RING_FAULT_REG :
> + GEN8_RING_FAULT_REG;
> + rmw_clear(uncore, fault_reg, RING_FAULT_VALID);
> + intel_uncore_posting_read(uncore, fault_reg);
> } else if (INTEL_GEN(i915) >= 6) {
> struct intel_engine_cs *engine;
> enum intel_engine_id id;
> @@ -117,7 +120,10 @@ static void gen6_check_faults(struct intel_gt *gt)
> static void gen8_check_faults(struct intel_gt *gt)
> {
> struct intel_uncore *uncore = gt->uncore;
> - u32 fault = intel_uncore_read(uncore, GEN8_RING_FAULT_REG);
> + i915_reg_t fault_reg =
> + (INTEL_GEN(gt->i915) >= 12) ?
> + GEN12_RING_FAULT_REG : GEN8_RING_FAULT_REG;
> + u32 fault = intel_uncore_read(uncore, fault_reg);
>
> if (fault & RING_FAULT_VALID) {
> u32 fault_data0, fault_data1;
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 259e7bec0a63..365d8ff11f23 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -365,6 +365,10 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
> unsigned int index;
> u32 unused_value;
>
> + /* Platforms with global MOCS do not need per-engine initialization. */
> + if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
> + return;
> +
> /* Called under a blanket forcewake */
> assert_forcewakes_active(uncore, FORCEWAKE_ALL);
>
> @@ -389,6 +393,46 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
> unused_value);
> }
>
> +/**
> + * intel_mocs_init_global() - program the global mocs registers
> + * gt: pointer to struct intel_gt
> + *
> + * This function initializes the MOCS global registers.
> + */
> +void intel_mocs_init_global(struct intel_gt *gt)
> +{
> + struct intel_uncore *uncore = gt->uncore;
> + struct drm_i915_mocs_table table;
> + unsigned int index;
> +
> + if (!HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
> + return;
> +
> + if (!get_mocs_settings(gt, &table))
> + return;
> +
> + if (GEM_DEBUG_WARN_ON(table.size > table.n_entries))
> + return;
> +
> + for (index = 0; index < table.size; index++)
> + intel_uncore_write(uncore,
> + GEN12_GLOBAL_MOCS(index),
> + table.table[index].control_value);
> +
> + /*
> + * Ok, now set the unused entries to uncached. These entries
> + * are officially undefined and no contract for the contents
> + * and settings is given for these entries.
> + *
> + * Entry 0 in the table is uncached - so we are just writing
> + * that value to all the used entries.
> + */
> + for (; index < table.n_entries; index++)
> + intel_uncore_write(uncore,
> + GEN12_GLOBAL_MOCS(index),
> + table.table[0].control_value);
> +}
> +
> /**
> * emit_mocs_control_table() - emit the mocs control table
> * @rq: Request to set up the MOCS table for.
> @@ -592,6 +636,9 @@ int intel_rcs_context_init_mocs(struct i915_request *rq)
> struct drm_i915_mocs_table t;
> int ret;
>
> + if (HAS_GLOBAL_MOCS_REGISTERS(rq->i915))
> + return 0;
> +
> if (get_mocs_settings(rq->engine->gt, &t)) {
> /* Program the RCS control registers */
> ret = emit_mocs_control_table(rq, &t);
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h b/drivers/gpu/drm/i915/gt/intel_mocs.h
> index 8b9813e6f9ac..aa3a2df07c82 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.h
> @@ -56,6 +56,7 @@ struct intel_gt;
>
> int intel_rcs_context_init_mocs(struct i915_request *rq);
> void intel_mocs_init_l3cc_table(struct intel_gt *gt);
> +void intel_mocs_init_global(struct intel_gt *gt);
> void intel_mocs_init_engine(struct intel_engine_cs *engine);
>
> #endif
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 069337f11872..57c05650d3b3 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2308,6 +2308,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
>
> +#define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs)
> +
> #define INTEL_PCH_DEVICE_ID_MASK 0xff80
> #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
> #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index e24955b5ebc2..d23e156f6659 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1254,6 +1254,7 @@ int i915_gem_init_hw(struct drm_i915_private *i915)
> goto out;
> }
>
> + intel_mocs_init_global(gt);
> intel_mocs_init_l3cc_table(gt);
>
> intel_engines_set_scheduler_caps(i915);
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 5489cd879315..ee40c14caa64 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1153,7 +1153,10 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
>
> if (INTEL_GEN(dev_priv) >= 6) {
> ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL);
> - if (INTEL_GEN(dev_priv) >= 8)
> +
> + if (INTEL_GEN(dev_priv) >= 12)
> + ee->fault_reg = I915_READ(GEN12_RING_FAULT_REG);
> + else if (INTEL_GEN(dev_priv) >= 8)
> ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);
> else
> ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine);
> @@ -1613,8 +1616,10 @@ static void capture_reg_state(struct i915_gpu_state *error)
>
> if (INTEL_GEN(i915) >= 6) {
> error->derrmr = intel_uncore_read(uncore, DERRMR);
> - error->error = intel_uncore_read(uncore, ERROR_GEN6);
> - error->done_reg = intel_uncore_read(uncore, DONE_REG);
> + if (INTEL_GEN(i915) < 12) {
> + error->error = intel_uncore_read(uncore, ERROR_GEN6);
> + error->done_reg = intel_uncore_read(uncore, DONE_REG);
> + }
> }
>
> if (INTEL_GEN(i915) >= 5)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 40076ba431d4..f0e19ef2e71a 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -783,7 +783,8 @@ static const struct intel_device_info intel_elkhartlake_info = {
> [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
> [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
> [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
> - }
> + }, \
> + .has_global_mocs = 1
>
> static const struct intel_device_info intel_tigerlake_12_info = {
> GEN12_FEATURES,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 712616fcd6b3..6cfcdf6bb1bb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2490,6 +2490,7 @@ enum i915_power_well_id {
> #define RENDER_HWS_PGA_GEN7 _MMIO(0x04080)
> #define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 * (engine)->hw_id)
> #define GEN8_RING_FAULT_REG _MMIO(0x4094)
> +#define GEN12_RING_FAULT_REG _MMIO(0xcec4)
> #define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
> #define RING_FAULT_GTTSEL_MASK (1 << 11)
> #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
> @@ -11362,6 +11363,8 @@ enum skl_power_gate {
> #define PMFLUSH_GAPL3UNBLOCK (1 << 21)
> #define PMFLUSHDONE_LNEBLK (1 << 22)
>
> +#define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
> +
> /* gamt regs */
> #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
> #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 45a9badc9b8e..aea7d143ec47 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -112,6 +112,7 @@ enum intel_ppgtt_type {
> func(gpu_reset_clobbers_display); \
> func(has_reset_engine); \
> func(has_fpga_dbg); \
> + func(has_global_mocs); \
> func(has_guc); \
> func(has_l3_dpf); \
> func(has_llc); \
>
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^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 19/22] drm/i915/tgl: Tigerlake only has global MOCS registers
2019-07-18 17:40 ` Daniele Ceraolo Spurio
@ 2019-07-19 19:42 ` Lucas De Marchi
0 siblings, 0 replies; 64+ messages in thread
From: Lucas De Marchi @ 2019-07-19 19:42 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: Michel Thierry, intel-gfx
On Thu, Jul 18, 2019 at 10:40:43AM -0700, Daniele Ceraolo Spurio wrote:
>
>
>On 7/12/19 6:09 PM, Lucas De Marchi wrote:
>>From: Michel Thierry <michel.thierry@intel.com>
>>
>>Until Icelake, each engine had its own set of 64 MOCS registers. In
>>order to simplify, Tigerlake moves to only 64 Global MOCS registers,
>>which are no longer part of the engine context. Since these registers
>>are now global, they also only need to be initialized once.
>>
>>These new global MOCS registers are located in the same offset of the
>>render MOCS register from previous platforms.
>
>No, they're not :). They're located in a new range, which overlaps
>with the location where the fault register was previously located and
>that's why the offset of that one has been changed as well. The code
>does the right thing, so only this sentence needs fixing.
>
>the FAULT_TLB_DATA* registers have been moved as well as part of the
>re-org, so maybe we can have a patch that just moves all the offsets
>and then add the global mocs on top?
yep, makes sense. I will change that in the next version.
>
>>
>> From Gen12 onwards, MOCS must specify the target cache (3:2) and LRU
>>management (5:4) fields and cannot be programmed to 'use the value from
>>Private PAT', because these fields are no longer part of the PPAT. Also
>>cacheability control (1:0) field has changed, 00 no longer means 'use
>>controls from page table', but uncacheable (UC).
>
>Should we put this as a comment in the code somewhere? Although I'm
>not sure we have any use for this info since we copy the table
>straight from the specs and we should probably trust it is correct.
I don't see a value in the comment exactly because of this reason. I
think the one in the commit message is enough.
thanks
Lucas De Marchi
>
>Daniele
>
>>
>>Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>>Cc: Tomasz Lis <tomasz.lis@intel.com>
>>Signed-off-by: Michel Thierry <michel.thierry@intel.com>
>>Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>---
>> drivers/gpu/drm/i915/gt/intel_gt.c | 12 ++++--
>> drivers/gpu/drm/i915/gt/intel_mocs.c | 47 ++++++++++++++++++++++++
>> drivers/gpu/drm/i915/gt/intel_mocs.h | 1 +
>> drivers/gpu/drm/i915/i915_drv.h | 2 +
>> drivers/gpu/drm/i915/i915_gem.c | 1 +
>> drivers/gpu/drm/i915/i915_gpu_error.c | 11 ++++--
>> drivers/gpu/drm/i915/i915_pci.c | 3 +-
>> drivers/gpu/drm/i915/i915_reg.h | 3 ++
>> drivers/gpu/drm/i915/intel_device_info.h | 1 +
>> 9 files changed, 74 insertions(+), 7 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
>>index f7e69db4019d..958edfda2ba2 100644
>>--- a/drivers/gpu/drm/i915/gt/intel_gt.c
>>+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
>>@@ -80,8 +80,11 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
>> }
>> if (INTEL_GEN(i915) >= 8) {
>>- rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
>>- intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
>>+ i915_reg_t fault_reg = (INTEL_GEN(i915) >= 12) ?
>>+ GEN12_RING_FAULT_REG :
>>+ GEN8_RING_FAULT_REG;
>>+ rmw_clear(uncore, fault_reg, RING_FAULT_VALID);
>>+ intel_uncore_posting_read(uncore, fault_reg);
>> } else if (INTEL_GEN(i915) >= 6) {
>> struct intel_engine_cs *engine;
>> enum intel_engine_id id;
>>@@ -117,7 +120,10 @@ static void gen6_check_faults(struct intel_gt *gt)
>> static void gen8_check_faults(struct intel_gt *gt)
>> {
>> struct intel_uncore *uncore = gt->uncore;
>>- u32 fault = intel_uncore_read(uncore, GEN8_RING_FAULT_REG);
>>+ i915_reg_t fault_reg =
>>+ (INTEL_GEN(gt->i915) >= 12) ?
>>+ GEN12_RING_FAULT_REG : GEN8_RING_FAULT_REG;
>>+ u32 fault = intel_uncore_read(uncore, fault_reg);
>> if (fault & RING_FAULT_VALID) {
>> u32 fault_data0, fault_data1;
>>diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
>>index 259e7bec0a63..365d8ff11f23 100644
>>--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
>>+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
>>@@ -365,6 +365,10 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
>> unsigned int index;
>> u32 unused_value;
>>+ /* Platforms with global MOCS do not need per-engine initialization. */
>>+ if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
>>+ return;
>>+
>> /* Called under a blanket forcewake */
>> assert_forcewakes_active(uncore, FORCEWAKE_ALL);
>>@@ -389,6 +393,46 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
>> unused_value);
>> }
>>+/**
>>+ * intel_mocs_init_global() - program the global mocs registers
>>+ * gt: pointer to struct intel_gt
>>+ *
>>+ * This function initializes the MOCS global registers.
>>+ */
>>+void intel_mocs_init_global(struct intel_gt *gt)
>>+{
>>+ struct intel_uncore *uncore = gt->uncore;
>>+ struct drm_i915_mocs_table table;
>>+ unsigned int index;
>>+
>>+ if (!HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
>>+ return;
>>+
>>+ if (!get_mocs_settings(gt, &table))
>>+ return;
>>+
>>+ if (GEM_DEBUG_WARN_ON(table.size > table.n_entries))
>>+ return;
>>+
>>+ for (index = 0; index < table.size; index++)
>>+ intel_uncore_write(uncore,
>>+ GEN12_GLOBAL_MOCS(index),
>>+ table.table[index].control_value);
>>+
>>+ /*
>>+ * Ok, now set the unused entries to uncached. These entries
>>+ * are officially undefined and no contract for the contents
>>+ * and settings is given for these entries.
>>+ *
>>+ * Entry 0 in the table is uncached - so we are just writing
>>+ * that value to all the used entries.
>>+ */
>>+ for (; index < table.n_entries; index++)
>>+ intel_uncore_write(uncore,
>>+ GEN12_GLOBAL_MOCS(index),
>>+ table.table[0].control_value);
>>+}
>>+
>> /**
>> * emit_mocs_control_table() - emit the mocs control table
>> * @rq: Request to set up the MOCS table for.
>>@@ -592,6 +636,9 @@ int intel_rcs_context_init_mocs(struct i915_request *rq)
>> struct drm_i915_mocs_table t;
>> int ret;
>>+ if (HAS_GLOBAL_MOCS_REGISTERS(rq->i915))
>>+ return 0;
>>+
>> if (get_mocs_settings(rq->engine->gt, &t)) {
>> /* Program the RCS control registers */
>> ret = emit_mocs_control_table(rq, &t);
>>diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h b/drivers/gpu/drm/i915/gt/intel_mocs.h
>>index 8b9813e6f9ac..aa3a2df07c82 100644
>>--- a/drivers/gpu/drm/i915/gt/intel_mocs.h
>>+++ b/drivers/gpu/drm/i915/gt/intel_mocs.h
>>@@ -56,6 +56,7 @@ struct intel_gt;
>> int intel_rcs_context_init_mocs(struct i915_request *rq);
>> void intel_mocs_init_l3cc_table(struct intel_gt *gt);
>>+void intel_mocs_init_global(struct intel_gt *gt);
>> void intel_mocs_init_engine(struct intel_engine_cs *engine);
>> #endif
>>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>index 069337f11872..57c05650d3b3 100644
>>--- a/drivers/gpu/drm/i915/i915_drv.h
>>+++ b/drivers/gpu/drm/i915/i915_drv.h
>>@@ -2308,6 +2308,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>> #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
>>+#define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs)
>>+
>> #define INTEL_PCH_DEVICE_ID_MASK 0xff80
>> #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
>> #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
>>diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
>>index e24955b5ebc2..d23e156f6659 100644
>>--- a/drivers/gpu/drm/i915/i915_gem.c
>>+++ b/drivers/gpu/drm/i915/i915_gem.c
>>@@ -1254,6 +1254,7 @@ int i915_gem_init_hw(struct drm_i915_private *i915)
>> goto out;
>> }
>>+ intel_mocs_init_global(gt);
>> intel_mocs_init_l3cc_table(gt);
>> intel_engines_set_scheduler_caps(i915);
>>diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
>>index 5489cd879315..ee40c14caa64 100644
>>--- a/drivers/gpu/drm/i915/i915_gpu_error.c
>>+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
>>@@ -1153,7 +1153,10 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
>> if (INTEL_GEN(dev_priv) >= 6) {
>> ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL);
>>- if (INTEL_GEN(dev_priv) >= 8)
>>+
>>+ if (INTEL_GEN(dev_priv) >= 12)
>>+ ee->fault_reg = I915_READ(GEN12_RING_FAULT_REG);
>>+ else if (INTEL_GEN(dev_priv) >= 8)
>> ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);
>> else
>> ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine);
>>@@ -1613,8 +1616,10 @@ static void capture_reg_state(struct i915_gpu_state *error)
>> if (INTEL_GEN(i915) >= 6) {
>> error->derrmr = intel_uncore_read(uncore, DERRMR);
>>- error->error = intel_uncore_read(uncore, ERROR_GEN6);
>>- error->done_reg = intel_uncore_read(uncore, DONE_REG);
>>+ if (INTEL_GEN(i915) < 12) {
>>+ error->error = intel_uncore_read(uncore, ERROR_GEN6);
>>+ error->done_reg = intel_uncore_read(uncore, DONE_REG);
>>+ }
>> }
>> if (INTEL_GEN(i915) >= 5)
>>diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>>index 40076ba431d4..f0e19ef2e71a 100644
>>--- a/drivers/gpu/drm/i915/i915_pci.c
>>+++ b/drivers/gpu/drm/i915/i915_pci.c
>>@@ -783,7 +783,8 @@ static const struct intel_device_info intel_elkhartlake_info = {
>> [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
>> [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
>> [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
>>- }
>>+ }, \
>>+ .has_global_mocs = 1
>> static const struct intel_device_info intel_tigerlake_12_info = {
>> GEN12_FEATURES,
>>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>index 712616fcd6b3..6cfcdf6bb1bb 100644
>>--- a/drivers/gpu/drm/i915/i915_reg.h
>>+++ b/drivers/gpu/drm/i915/i915_reg.h
>>@@ -2490,6 +2490,7 @@ enum i915_power_well_id {
>> #define RENDER_HWS_PGA_GEN7 _MMIO(0x04080)
>> #define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 * (engine)->hw_id)
>> #define GEN8_RING_FAULT_REG _MMIO(0x4094)
>>+#define GEN12_RING_FAULT_REG _MMIO(0xcec4)
>> #define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
>> #define RING_FAULT_GTTSEL_MASK (1 << 11)
>> #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
>>@@ -11362,6 +11363,8 @@ enum skl_power_gate {
>> #define PMFLUSH_GAPL3UNBLOCK (1 << 21)
>> #define PMFLUSHDONE_LNEBLK (1 << 22)
>>+#define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
>>+
>> /* gamt regs */
>> #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
>> #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
>>diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>>index 45a9badc9b8e..aea7d143ec47 100644
>>--- a/drivers/gpu/drm/i915/intel_device_info.h
>>+++ b/drivers/gpu/drm/i915/intel_device_info.h
>>@@ -112,6 +112,7 @@ enum intel_ppgtt_type {
>> func(gpu_reset_clobbers_display); \
>> func(has_reset_engine); \
>> func(has_fpga_dbg); \
>>+ func(has_global_mocs); \
>> func(has_guc); \
>> func(has_l3_dpf); \
>> func(has_llc); \
>>
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^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 20/22] drm/i915: Move MOCS setup to intel_mocs.c
2019-07-13 1:09 [PATCH 00/22] Tiger Lake part 2 Lucas De Marchi
` (18 preceding siblings ...)
2019-07-13 1:09 ` [PATCH 19/22] drm/i915/tgl: Tigerlake only has global MOCS registers Lucas De Marchi
@ 2019-07-13 1:09 ` Lucas De Marchi
2019-07-23 16:30 ` Summers, Stuart
2019-07-13 1:09 ` [PATCH 21/22] drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers Lucas De Marchi
` (7 subsequent siblings)
27 siblings, 1 reply; 64+ messages in thread
From: Lucas De Marchi @ 2019-07-13 1:09 UTC (permalink / raw)
To: intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Hide the details of MOCS setup from i915_gem by moving both current calls
into one in intel_mocs_init.
Cc: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 15 +++++++++++----
drivers/gpu/drm/i915/gt/intel_mocs.h | 3 +--
drivers/gpu/drm/i915/i915_gem.c | 3 +--
3 files changed, 13 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 365d8ff11f23..5cd18768b5df 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -399,14 +399,13 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
*
* This function initializes the MOCS global registers.
*/
-void intel_mocs_init_global(struct intel_gt *gt)
+static void intel_mocs_init_global(struct intel_gt *gt)
{
struct intel_uncore *uncore = gt->uncore;
struct drm_i915_mocs_table table;
unsigned int index;
- if (!HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
- return;
+ GEM_BUG_ON(!HAS_GLOBAL_MOCS_REGISTERS(gt->i915));
if (!get_mocs_settings(gt, &table))
return;
@@ -575,7 +574,7 @@ static int emit_mocs_l3cc_table(struct i915_request *rq,
*
* Return: Nothing.
*/
-void intel_mocs_init_l3cc_table(struct intel_gt *gt)
+static void intel_mocs_init_l3cc_table(struct intel_gt *gt)
{
struct intel_uncore *uncore = gt->uncore;
struct drm_i915_mocs_table table;
@@ -653,3 +652,11 @@ int intel_rcs_context_init_mocs(struct i915_request *rq)
return 0;
}
+
+void intel_mocs_init(struct intel_gt *gt)
+{
+ intel_mocs_init_l3cc_table(gt);
+
+ if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
+ intel_mocs_init_global(gt);
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h b/drivers/gpu/drm/i915/gt/intel_mocs.h
index aa3a2df07c82..2c5cbf213819 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.h
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.h
@@ -55,8 +55,7 @@ struct intel_engine_cs;
struct intel_gt;
int intel_rcs_context_init_mocs(struct i915_request *rq);
-void intel_mocs_init_l3cc_table(struct intel_gt *gt);
-void intel_mocs_init_global(struct intel_gt *gt);
+void intel_mocs_init(struct intel_gt *gt);
void intel_mocs_init_engine(struct intel_engine_cs *engine);
#endif
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d23e156f6659..7980ee9bf8a8 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1254,8 +1254,7 @@ int i915_gem_init_hw(struct drm_i915_private *i915)
goto out;
}
- intel_mocs_init_global(gt);
- intel_mocs_init_l3cc_table(gt);
+ intel_mocs_init(gt);
intel_engines_set_scheduler_caps(i915);
--
2.21.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 20/22] drm/i915: Move MOCS setup to intel_mocs.c
2019-07-13 1:09 ` [PATCH 20/22] drm/i915: Move MOCS setup to intel_mocs.c Lucas De Marchi
@ 2019-07-23 16:30 ` Summers, Stuart
0 siblings, 0 replies; 64+ messages in thread
From: Summers, Stuart @ 2019-07-23 16:30 UTC (permalink / raw)
To: intel-gfx, De Marchi, Lucas
[-- Attachment #1.1: Type: text/plain, Size: 3193 bytes --]
On Fri, 2019-07-12 at 18:09 -0700, Lucas De Marchi wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Hide the details of MOCS setup from i915_gem by moving both current
> calls
> into one in intel_mocs_init.
>
> Cc: Stuart Summers <stuart.summers@intel.com>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_mocs.c | 15 +++++++++++----
> drivers/gpu/drm/i915/gt/intel_mocs.h | 3 +--
> drivers/gpu/drm/i915/i915_gem.c | 3 +--
> 3 files changed, 13 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
> b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 365d8ff11f23..5cd18768b5df 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -399,14 +399,13 @@ void intel_mocs_init_engine(struct
> intel_engine_cs *engine)
> *
> * This function initializes the MOCS global registers.
> */
> -void intel_mocs_init_global(struct intel_gt *gt)
> +static void intel_mocs_init_global(struct intel_gt *gt)
> {
> struct intel_uncore *uncore = gt->uncore;
> struct drm_i915_mocs_table table;
> unsigned int index;
>
> - if (!HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
> - return;
> + GEM_BUG_ON(!HAS_GLOBAL_MOCS_REGISTERS(gt->i915));
>
> if (!get_mocs_settings(gt, &table))
> return;
> @@ -575,7 +574,7 @@ static int emit_mocs_l3cc_table(struct
> i915_request *rq,
> *
> * Return: Nothing.
> */
> -void intel_mocs_init_l3cc_table(struct intel_gt *gt)
> +static void intel_mocs_init_l3cc_table(struct intel_gt *gt)
> {
> struct intel_uncore *uncore = gt->uncore;
> struct drm_i915_mocs_table table;
> @@ -653,3 +652,11 @@ int intel_rcs_context_init_mocs(struct
> i915_request *rq)
>
> return 0;
> }
> +
> +void intel_mocs_init(struct intel_gt *gt)
> +{
> + intel_mocs_init_l3cc_table(gt);
> +
> + if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
> + intel_mocs_init_global(gt);
> +}
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h
> b/drivers/gpu/drm/i915/gt/intel_mocs.h
> index aa3a2df07c82..2c5cbf213819 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.h
> @@ -55,8 +55,7 @@ struct intel_engine_cs;
> struct intel_gt;
>
> int intel_rcs_context_init_mocs(struct i915_request *rq);
> -void intel_mocs_init_l3cc_table(struct intel_gt *gt);
> -void intel_mocs_init_global(struct intel_gt *gt);
> +void intel_mocs_init(struct intel_gt *gt);
> void intel_mocs_init_engine(struct intel_engine_cs *engine);
>
> #endif
> diff --git a/drivers/gpu/drm/i915/i915_gem.c
> b/drivers/gpu/drm/i915/i915_gem.c
> index d23e156f6659..7980ee9bf8a8 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1254,8 +1254,7 @@ int i915_gem_init_hw(struct drm_i915_private
> *i915)
> goto out;
> }
>
> - intel_mocs_init_global(gt);
> - intel_mocs_init_l3cc_table(gt);
> + intel_mocs_init(gt);
>
> intel_engines_set_scheduler_caps(i915);
>
[-- Attachment #1.2: smime.p7s --]
[-- Type: application/x-pkcs7-signature, Size: 3270 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 21/22] drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers
2019-07-13 1:09 [PATCH 00/22] Tiger Lake part 2 Lucas De Marchi
` (19 preceding siblings ...)
2019-07-13 1:09 ` [PATCH 20/22] drm/i915: Move MOCS setup to intel_mocs.c Lucas De Marchi
@ 2019-07-13 1:09 ` Lucas De Marchi
2019-07-18 5:47 ` Anshuman Gupta
2019-07-13 1:09 ` [PATCH 22/22] drm/i915/mst: Do not hardcoded the crtcs that encoder can connect Lucas De Marchi
` (6 subsequent siblings)
27 siblings, 1 reply; 64+ messages in thread
From: Lucas De Marchi @ 2019-07-13 1:09 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
Tiger Lask has a new register offset for DC5 and DC6 residency counters.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 21 +++++++++++++--------
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index a1843e3de6d7..4b12b5588dd6 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2465,6 +2465,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
intel_wakeref_t wakeref;
struct intel_csr *csr;
+ i915_reg_t dc5_reg, dc6_reg = {};
if (!HAS_CSR(dev_priv))
return -ENODEV;
@@ -2482,15 +2483,19 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
CSR_VERSION_MINOR(csr->version));
- if (WARN_ON(INTEL_GEN(dev_priv) > 11))
- goto out;
+ if (INTEL_GEN(dev_priv) >= 12) {
+ dc5_reg = TGL_CSR_DC5_RES_COUNT;
+ dc6_reg = TGL_CSR_DC6_RES_COUNT;
+ } else {
+ dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
+ SKL_CSR_DC3_DC5_COUNT;
+ if (!IS_GEN9_LP(dev_priv))
+ dc6_reg = SKL_CSR_DC5_DC6_COUNT;
+ }
- seq_printf(m, "DC3 -> DC5 count: %d\n",
- I915_READ(IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
- SKL_CSR_DC3_DC5_COUNT));
- if (!IS_GEN9_LP(dev_priv))
- seq_printf(m, "DC5 -> DC6 count: %d\n",
- I915_READ(SKL_CSR_DC5_DC6_COUNT));
+ seq_printf(m, "DC3 -> DC5 count: %d\n", I915_READ(dc5_reg));
+ if (dc6_reg.reg)
+ seq_printf(m, "DC5 -> DC6 count: %d\n", I915_READ(dc6_reg));
out:
seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6cfcdf6bb1bb..5e3434cdd1e8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7269,6 +7269,8 @@ enum {
#define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
#define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
#define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
+#define TGL_CSR_DC5_RES_COUNT _MMIO(0x101084)
+#define TGL_CSR_DC6_RES_COUNT _MMIO(0x101088)
/* interrupts */
#define DE_MASTER_IRQ_CONTROL (1 << 31)
--
2.21.0
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 21/22] drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers
2019-07-13 1:09 ` [PATCH 21/22] drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers Lucas De Marchi
@ 2019-07-18 5:47 ` Anshuman Gupta
2019-07-19 15:58 ` Atwood, Matthew S
2019-07-19 18:39 ` Lucas De Marchi
0 siblings, 2 replies; 64+ messages in thread
From: Anshuman Gupta @ 2019-07-18 5:47 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On 2019-07-12 at 18:09:39 -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
>
> Tiger Lask has a new register offset for DC5 and DC6 residency counters.
>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 21 +++++++++++++--------
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> 2 files changed, 15 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index a1843e3de6d7..4b12b5588dd6 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2465,6 +2465,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> intel_wakeref_t wakeref;
> struct intel_csr *csr;
> + i915_reg_t dc5_reg, dc6_reg = {};
>
> if (!HAS_CSR(dev_priv))
> return -ENODEV;
> @@ -2482,15 +2483,19 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
> seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
> CSR_VERSION_MINOR(csr->version));
>
> - if (WARN_ON(INTEL_GEN(dev_priv) > 11))
> - goto out;
> + if (INTEL_GEN(dev_priv) >= 12) {
> + dc5_reg = TGL_CSR_DC5_RES_COUNT;
> + dc6_reg = TGL_CSR_DC6_RES_COUNT;
> + } else {
> + dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
> + SKL_CSR_DC3_DC5_COUNT;
> + if (!IS_GEN9_LP(dev_priv))
> + dc6_reg = SKL_CSR_DC5_DC6_COUNT;
> + }
>
> - seq_printf(m, "DC3 -> DC5 count: %d\n",
> - I915_READ(IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
> - SKL_CSR_DC3_DC5_COUNT));
> - if (!IS_GEN9_LP(dev_priv))
> - seq_printf(m, "DC5 -> DC6 count: %d\n",
> - I915_READ(SKL_CSR_DC5_DC6_COUNT));
> + seq_printf(m, "DC3 -> DC5 count: %d\n", I915_READ(dc5_reg));
> + if (dc6_reg.reg)
> + seq_printf(m, "DC5 -> DC6 count: %d\n", I915_READ(dc6_reg));
>
> out:
> seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6cfcdf6bb1bb..5e3434cdd1e8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7269,6 +7269,8 @@ enum {
> #define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
> #define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
> #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
> +#define TGL_CSR_DC5_RES_COUNT _MMIO(0x101084)
> +#define TGL_CSR_DC6_RES_COUNT _MMIO(0x101088)
CSR memory ranges from 0x80000 till 0x8ffff
These DMC_DEBUG regisers are not are not CSR register.
It would make sense to rename the macro.
>
> /* interrupts */
> #define DE_MASTER_IRQ_CONTROL (1 << 31)
> --
> 2.21.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 21/22] drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers
2019-07-18 5:47 ` Anshuman Gupta
@ 2019-07-19 15:58 ` Atwood, Matthew S
2019-07-19 18:39 ` Lucas De Marchi
1 sibling, 0 replies; 64+ messages in thread
From: Atwood, Matthew S @ 2019-07-19 15:58 UTC (permalink / raw)
To: Gupta, Anshuman, De Marchi, Lucas; +Cc: intel-gfx
On Thu, 2019-07-18 at 11:17 +0530, Anshuman Gupta wrote:
> On 2019-07-12 at 18:09:39 -0700, Lucas De Marchi wrote:
> > From: José Roberto de Souza <jose.souza@intel.com>
> >
> > Tiger Lask has a new register offset for DC5 and DC6 residency
> > counters.
nit: Tiger Lake
> >
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 21 +++++++++++++--------
> > drivers/gpu/drm/i915/i915_reg.h | 2 ++
> > 2 files changed, 15 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index a1843e3de6d7..4b12b5588dd6 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -2465,6 +2465,7 @@ static int i915_dmc_info(struct seq_file *m,
> > void *unused)
> > struct drm_i915_private *dev_priv = node_to_i915(m->private);
> > intel_wakeref_t wakeref;
> > struct intel_csr *csr;
> > + i915_reg_t dc5_reg, dc6_reg = {};
> >
> > if (!HAS_CSR(dev_priv))
> > return -ENODEV;
> > @@ -2482,15 +2483,19 @@ static int i915_dmc_info(struct seq_file
> > *m, void *unused)
> > seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr-
> > >version),
> > CSR_VERSION_MINOR(csr->version));
> >
> > - if (WARN_ON(INTEL_GEN(dev_priv) > 11))
> > - goto out;
> > + if (INTEL_GEN(dev_priv) >= 12) {
> > + dc5_reg = TGL_CSR_DC5_RES_COUNT;
> > + dc6_reg = TGL_CSR_DC6_RES_COUNT;
> > + } else {
> > + dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT
> > :
> > + SKL_CSR_DC3_DC5_COUNT;
> > + if (!IS_GEN9_LP(dev_priv))
> > + dc6_reg = SKL_CSR_DC5_DC6_COUNT;
> > + }
> >
> > - seq_printf(m, "DC3 -> DC5 count: %d\n",
> > - I915_READ(IS_BROXTON(dev_priv) ?
> > BXT_CSR_DC3_DC5_COUNT :
> > - SKL_CSR_DC3_DC5_COU
> > NT));
> > - if (!IS_GEN9_LP(dev_priv))
> > - seq_printf(m, "DC5 -> DC6 count: %d\n",
> > - I915_READ(SKL_CSR_DC5_DC6_COUNT));
> > + seq_printf(m, "DC3 -> DC5 count: %d\n", I915_READ(dc5_reg));
> > + if (dc6_reg.reg)
> > + seq_printf(m, "DC5 -> DC6 count: %d\n",
> > I915_READ(dc6_reg));
> >
> > out:
> > seq_printf(m, "program base: 0x%08x\n",
> > I915_READ(CSR_PROGRAM(0)));
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 6cfcdf6bb1bb..5e3434cdd1e8 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7269,6 +7269,8 @@ enum {
> > #define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
> > #define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
> > #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
> > +#define TGL_CSR_DC5_RES_COUNT _MMIO(0x101084)
> > +#define TGL_CSR_DC6_RES_COUNT _MMIO(0x101088)
>
> CSR memory ranges from 0x80000 till 0x8ffff
> These DMC_DEBUG regisers are not are not CSR register.
> It would make sense to rename the macro.
> >
> > /* interrupts */
> > #define DE_MASTER_IRQ_CONTROL (1 << 31)
> > --
> > 2.21.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 21/22] drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers
2019-07-18 5:47 ` Anshuman Gupta
2019-07-19 15:58 ` Atwood, Matthew S
@ 2019-07-19 18:39 ` Lucas De Marchi
2019-07-22 7:41 ` Anshuman Gupta
1 sibling, 1 reply; 64+ messages in thread
From: Lucas De Marchi @ 2019-07-19 18:39 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
On Thu, Jul 18, 2019 at 11:17:03AM +0530, Anshuman Gupta wrote:
>On 2019-07-12 at 18:09:39 -0700, Lucas De Marchi wrote:
>> From: José Roberto de Souza <jose.souza@intel.com>
>>
>> Tiger Lask has a new register offset for DC5 and DC6 residency counters.
>>
>> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_debugfs.c | 21 +++++++++++++--------
>> drivers/gpu/drm/i915/i915_reg.h | 2 ++
>> 2 files changed, 15 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>> index a1843e3de6d7..4b12b5588dd6 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -2465,6 +2465,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>> struct drm_i915_private *dev_priv = node_to_i915(m->private);
>> intel_wakeref_t wakeref;
>> struct intel_csr *csr;
>> + i915_reg_t dc5_reg, dc6_reg = {};
>>
>> if (!HAS_CSR(dev_priv))
>> return -ENODEV;
>> @@ -2482,15 +2483,19 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>> seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
>> CSR_VERSION_MINOR(csr->version));
>>
>> - if (WARN_ON(INTEL_GEN(dev_priv) > 11))
>> - goto out;
>> + if (INTEL_GEN(dev_priv) >= 12) {
>> + dc5_reg = TGL_CSR_DC5_RES_COUNT;
>> + dc6_reg = TGL_CSR_DC6_RES_COUNT;
>> + } else {
>> + dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
>> + SKL_CSR_DC3_DC5_COUNT;
>> + if (!IS_GEN9_LP(dev_priv))
>> + dc6_reg = SKL_CSR_DC5_DC6_COUNT;
>> + }
>>
>> - seq_printf(m, "DC3 -> DC5 count: %d\n",
>> - I915_READ(IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
>> - SKL_CSR_DC3_DC5_COUNT));
>> - if (!IS_GEN9_LP(dev_priv))
>> - seq_printf(m, "DC5 -> DC6 count: %d\n",
>> - I915_READ(SKL_CSR_DC5_DC6_COUNT));
>> + seq_printf(m, "DC3 -> DC5 count: %d\n", I915_READ(dc5_reg));
>> + if (dc6_reg.reg)
>> + seq_printf(m, "DC5 -> DC6 count: %d\n", I915_READ(dc6_reg));
>>
>> out:
>> seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 6cfcdf6bb1bb..5e3434cdd1e8 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -7269,6 +7269,8 @@ enum {
>> #define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
>> #define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
>> #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
>> +#define TGL_CSR_DC5_RES_COUNT _MMIO(0x101084)
>> +#define TGL_CSR_DC6_RES_COUNT _MMIO(0x101088)
>CSR memory ranges from 0x80000 till 0x8ffff
>These DMC_DEBUG regisers are not are not CSR register.
>It would make sense to rename the macro.
True.
TGL_DMC_DEBUG_DC5_COUNT and TGL_DMC_DEBUG_DC6_COUNT sounds good?
Lucas De Marchi
>>
>> /* interrupts */
>> #define DE_MASTER_IRQ_CONTROL (1 << 31)
>> --
>> 2.21.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 21/22] drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers
2019-07-19 18:39 ` Lucas De Marchi
@ 2019-07-22 7:41 ` Anshuman Gupta
2019-07-22 17:40 ` Lucas De Marchi
0 siblings, 1 reply; 64+ messages in thread
From: Anshuman Gupta @ 2019-07-22 7:41 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On 2019-07-19 at 11:39:54 -0700, Lucas De Marchi wrote:
> On Thu, Jul 18, 2019 at 11:17:03AM +0530, Anshuman Gupta wrote:
> >On 2019-07-12 at 18:09:39 -0700, Lucas De Marchi wrote:
> >>From: José Roberto de Souza <jose.souza@intel.com>
> >>
> >>Tiger Lask has a new register offset for DC5 and DC6 residency counters.
> >>
> >>Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> >>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> >>---
> >> drivers/gpu/drm/i915/i915_debugfs.c | 21 +++++++++++++--------
> >> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> >> 2 files changed, 15 insertions(+), 8 deletions(-)
> >>
> >>diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> >>index a1843e3de6d7..4b12b5588dd6 100644
> >>--- a/drivers/gpu/drm/i915/i915_debugfs.c
> >>+++ b/drivers/gpu/drm/i915/i915_debugfs.c
> >>@@ -2465,6 +2465,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
> >> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> >> intel_wakeref_t wakeref;
> >> struct intel_csr *csr;
> >>+ i915_reg_t dc5_reg, dc6_reg = {};
> >>
> >> if (!HAS_CSR(dev_priv))
> >> return -ENODEV;
> >>@@ -2482,15 +2483,19 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
> >> seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
> >> CSR_VERSION_MINOR(csr->version));
> >>
> >>- if (WARN_ON(INTEL_GEN(dev_priv) > 11))
> >>- goto out;
> >>+ if (INTEL_GEN(dev_priv) >= 12) {
Below DMC debug registers offsets are specific to TGL,
So it would make sense to add IS_TIGERLAKE condition?
> >>+ dc5_reg = TGL_CSR_DC5_RES_COUNT;
> >>+ dc6_reg = TGL_CSR_DC6_RES_COUNT;
> >>+ } else {
> >>+ dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
> >>+ SKL_CSR_DC3_DC5_COUNT;
> >>+ if (!IS_GEN9_LP(dev_priv))
> >>+ dc6_reg = SKL_CSR_DC5_DC6_COUNT;
> >>+ }
> >>
> >>- seq_printf(m, "DC3 -> DC5 count: %d\n",
> >>- I915_READ(IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
> >>- SKL_CSR_DC3_DC5_COUNT));
> >>- if (!IS_GEN9_LP(dev_priv))
> >>- seq_printf(m, "DC5 -> DC6 count: %d\n",
> >>- I915_READ(SKL_CSR_DC5_DC6_COUNT));
> >>+ seq_printf(m, "DC3 -> DC5 count: %d\n", I915_READ(dc5_reg));
> >>+ if (dc6_reg.reg)
> >>+ seq_printf(m, "DC5 -> DC6 count: %d\n", I915_READ(dc6_reg));
> >>
> >> out:
> >> seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
> >>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >>index 6cfcdf6bb1bb..5e3434cdd1e8 100644
> >>--- a/drivers/gpu/drm/i915/i915_reg.h
> >>+++ b/drivers/gpu/drm/i915/i915_reg.h
> >>@@ -7269,6 +7269,8 @@ enum {
> >> #define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
> >> #define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
> >> #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
> >>+#define TGL_CSR_DC5_RES_COUNT _MMIO(0x101084)
> >>+#define TGL_CSR_DC6_RES_COUNT _MMIO(0x101088)
> >CSR memory ranges from 0x80000 till 0x8ffff
> >These DMC_DEBUG regisers are not are not CSR register.
> >It would make sense to rename the macro.
>
> True.
>
> TGL_DMC_DEBUG_DC5_COUNT and TGL_DMC_DEBUG_DC6_COUNT sounds good?
yes!
>
> Lucas De Marchi
>
> >>
> >> /* interrupts */
> >> #define DE_MASTER_IRQ_CONTROL (1 << 31)
> >>--
> >>2.21.0
> >>
> >>_______________________________________________
> >>Intel-gfx mailing list
> >>Intel-gfx@lists.freedesktop.org
> >>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH 21/22] drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers
2019-07-22 7:41 ` Anshuman Gupta
@ 2019-07-22 17:40 ` Lucas De Marchi
0 siblings, 0 replies; 64+ messages in thread
From: Lucas De Marchi @ 2019-07-22 17:40 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
On Mon, Jul 22, 2019 at 01:11:40PM +0530, Anshuman Gupta wrote:
>On 2019-07-19 at 11:39:54 -0700, Lucas De Marchi wrote:
>> On Thu, Jul 18, 2019 at 11:17:03AM +0530, Anshuman Gupta wrote:
>> >On 2019-07-12 at 18:09:39 -0700, Lucas De Marchi wrote:
>> >>From: José Roberto de Souza <jose.souza@intel.com>
>> >>
>> >>Tiger Lask has a new register offset for DC5 and DC6 residency counters.
>> >>
>> >>Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>> >>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> >>---
>> >> drivers/gpu/drm/i915/i915_debugfs.c | 21 +++++++++++++--------
>> >> drivers/gpu/drm/i915/i915_reg.h | 2 ++
>> >> 2 files changed, 15 insertions(+), 8 deletions(-)
>> >>
>> >>diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>> >>index a1843e3de6d7..4b12b5588dd6 100644
>> >>--- a/drivers/gpu/drm/i915/i915_debugfs.c
>> >>+++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> >>@@ -2465,6 +2465,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>> >> struct drm_i915_private *dev_priv = node_to_i915(m->private);
>> >> intel_wakeref_t wakeref;
>> >> struct intel_csr *csr;
>> >>+ i915_reg_t dc5_reg, dc6_reg = {};
>> >>
>> >> if (!HAS_CSR(dev_priv))
>> >> return -ENODEV;
>> >>@@ -2482,15 +2483,19 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>> >> seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
>> >> CSR_VERSION_MINOR(csr->version));
>> >>
>> >>- if (WARN_ON(INTEL_GEN(dev_priv) > 11))
>> >>- goto out;
>> >>+ if (INTEL_GEN(dev_priv) >= 12) {
>Below DMC debug registers offsets are specific to TGL,
>So it would make sense to add IS_TIGERLAKE condition?
I think we can leave it with gen >= 12 and change it when/if the next
platform change that.
>> >>+ dc5_reg = TGL_CSR_DC5_RES_COUNT;
>> >>+ dc6_reg = TGL_CSR_DC6_RES_COUNT;
>> >>+ } else {
>> >>+ dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
>> >>+ SKL_CSR_DC3_DC5_COUNT;
>> >>+ if (!IS_GEN9_LP(dev_priv))
>> >>+ dc6_reg = SKL_CSR_DC5_DC6_COUNT;
>> >>+ }
>> >>
>> >>- seq_printf(m, "DC3 -> DC5 count: %d\n",
>> >>- I915_READ(IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
>> >>- SKL_CSR_DC3_DC5_COUNT));
>> >>- if (!IS_GEN9_LP(dev_priv))
>> >>- seq_printf(m, "DC5 -> DC6 count: %d\n",
>> >>- I915_READ(SKL_CSR_DC5_DC6_COUNT));
>> >>+ seq_printf(m, "DC3 -> DC5 count: %d\n", I915_READ(dc5_reg));
>> >>+ if (dc6_reg.reg)
>> >>+ seq_printf(m, "DC5 -> DC6 count: %d\n", I915_READ(dc6_reg));
>> >>
>> >> out:
>> >> seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
>> >>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> >>index 6cfcdf6bb1bb..5e3434cdd1e8 100644
>> >>--- a/drivers/gpu/drm/i915/i915_reg.h
>> >>+++ b/drivers/gpu/drm/i915/i915_reg.h
>> >>@@ -7269,6 +7269,8 @@ enum {
>> >> #define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
>> >> #define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
>> >> #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
>> >>+#define TGL_CSR_DC5_RES_COUNT _MMIO(0x101084)
>> >>+#define TGL_CSR_DC6_RES_COUNT _MMIO(0x101088)
>> >CSR memory ranges from 0x80000 till 0x8ffff
>> >These DMC_DEBUG regisers are not are not CSR register.
>> >It would make sense to rename the macro.
>>
>> True.
>>
>> TGL_DMC_DEBUG_DC5_COUNT and TGL_DMC_DEBUG_DC6_COUNT sounds good?
>yes!
thanks, I'll send an updated version.
Lucas De Marchi
>>
>> Lucas De Marchi
>>
>> >>
>> >> /* interrupts */
>> >> #define DE_MASTER_IRQ_CONTROL (1 << 31)
>> >>--
>> >>2.21.0
>> >>
>> >>_______________________________________________
>> >>Intel-gfx mailing list
>> >>Intel-gfx@lists.freedesktop.org
>> >>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH 22/22] drm/i915/mst: Do not hardcoded the crtcs that encoder can connect
2019-07-13 1:09 [PATCH 00/22] Tiger Lake part 2 Lucas De Marchi
` (20 preceding siblings ...)
2019-07-13 1:09 ` [PATCH 21/22] drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers Lucas De Marchi
@ 2019-07-13 1:09 ` Lucas De Marchi
2019-07-18 13:10 ` Ville Syrjälä
2019-07-13 1:19 ` ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake part 2 Patchwork
` (5 subsequent siblings)
27 siblings, 1 reply; 64+ messages in thread
From: Lucas De Marchi @ 2019-07-13 1:09 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
Tiger Lake has up to 4 pipes so the mask would need to be 0xf instead of
0x7. Do not hardcode the mask so it allows the fake MST encoders to
connect to all pipes no matter how many the platform has.
Iterating over all pipes to keep consistent with intel_ddi_init().
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 60652ebbdf61..1b79b6befa92 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -586,6 +586,8 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum
struct intel_dp_mst_encoder *intel_mst;
struct intel_encoder *intel_encoder;
struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ enum pipe pipe_iter;
intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL);
@@ -602,8 +604,9 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum
intel_encoder->type = INTEL_OUTPUT_DP_MST;
intel_encoder->power_domain = intel_dig_port->base.power_domain;
intel_encoder->port = intel_dig_port->base.port;
- intel_encoder->crtc_mask = 0x7;
intel_encoder->cloneable = 0;
+ for_each_pipe(dev_priv, pipe_iter)
+ intel_encoder->crtc_mask |= BIT(pipe_iter);
intel_encoder->compute_config = intel_dp_mst_compute_config;
intel_encoder->disable = intel_mst_disable_dp;
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH 22/22] drm/i915/mst: Do not hardcoded the crtcs that encoder can connect
2019-07-13 1:09 ` [PATCH 22/22] drm/i915/mst: Do not hardcoded the crtcs that encoder can connect Lucas De Marchi
@ 2019-07-18 13:10 ` Ville Syrjälä
2019-08-15 17:41 ` James Ausmus
0 siblings, 1 reply; 64+ messages in thread
From: Ville Syrjälä @ 2019-07-18 13:10 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Fri, Jul 12, 2019 at 06:09:40PM -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
>
> Tiger Lake has up to 4 pipes so the mask would need to be 0xf instead of
> 0x7. Do not hardcode the mask so it allows the fake MST encoders to
> connect to all pipes no matter how many the platform has.
>
> Iterating over all pipes to keep consistent with intel_ddi_init().
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 60652ebbdf61..1b79b6befa92 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -586,6 +586,8 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum
> struct intel_dp_mst_encoder *intel_mst;
> struct intel_encoder *intel_encoder;
> struct drm_device *dev = intel_dig_port->base.base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + enum pipe pipe_iter;
>
> intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL);
>
> @@ -602,8 +604,9 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum
> intel_encoder->type = INTEL_OUTPUT_DP_MST;
> intel_encoder->power_domain = intel_dig_port->base.power_domain;
> intel_encoder->port = intel_dig_port->base.port;
> - intel_encoder->crtc_mask = 0x7;
> intel_encoder->cloneable = 0;
> + for_each_pipe(dev_priv, pipe_iter)
> + intel_encoder->crtc_mask |= BIT(pipe_iter);
https://patchwork.freedesktop.org/patch/316555/?series=63399&rev=1
>
> intel_encoder->compute_config = intel_dp_mst_compute_config;
> intel_encoder->disable = intel_mst_disable_dp;
> --
> 2.21.0
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH 22/22] drm/i915/mst: Do not hardcoded the crtcs that encoder can connect
2019-07-18 13:10 ` Ville Syrjälä
@ 2019-08-15 17:41 ` James Ausmus
0 siblings, 0 replies; 64+ messages in thread
From: James Ausmus @ 2019-08-15 17:41 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, Lucas De Marchi
On Thu, Jul 18, 2019 at 04:10:13PM +0300, Ville Syrjälä wrote:
> On Fri, Jul 12, 2019 at 06:09:40PM -0700, Lucas De Marchi wrote:
> > From: José Roberto de Souza <jose.souza@intel.com>
> >
> > Tiger Lake has up to 4 pipes so the mask would need to be 0xf instead of
> > 0x7. Do not hardcode the mask so it allows the fake MST encoders to
> > connect to all pipes no matter how many the platform has.
> >
> > Iterating over all pipes to keep consistent with intel_ddi_init().
> >
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 ++++-
> > 1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index 60652ebbdf61..1b79b6befa92 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -586,6 +586,8 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum
> > struct intel_dp_mst_encoder *intel_mst;
> > struct intel_encoder *intel_encoder;
> > struct drm_device *dev = intel_dig_port->base.base.dev;
> > + struct drm_i915_private *dev_priv = to_i915(dev);
> > + enum pipe pipe_iter;
> >
> > intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL);
> >
> > @@ -602,8 +604,9 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum
> > intel_encoder->type = INTEL_OUTPUT_DP_MST;
> > intel_encoder->power_domain = intel_dig_port->base.power_domain;
> > intel_encoder->port = intel_dig_port->base.port;
> > - intel_encoder->crtc_mask = 0x7;
> > intel_encoder->cloneable = 0;
> > + for_each_pipe(dev_priv, pipe_iter)
> > + intel_encoder->crtc_mask |= BIT(pipe_iter);
>
> https://patchwork.freedesktop.org/patch/316555/?series=63399&rev=1
Would it make sense to bring this patch in for now for TGL MST, until
that larger series can land?
-James
>
> >
> > intel_encoder->compute_config = intel_dp_mst_compute_config;
> > intel_encoder->disable = intel_mst_disable_dp;
> > --
> > 2.21.0
>
> --
> Ville Syrjälä
> Intel
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake part 2
2019-07-13 1:09 [PATCH 00/22] Tiger Lake part 2 Lucas De Marchi
` (21 preceding siblings ...)
2019-07-13 1:09 ` [PATCH 22/22] drm/i915/mst: Do not hardcoded the crtcs that encoder can connect Lucas De Marchi
@ 2019-07-13 1:19 ` Patchwork
2019-07-13 1:38 ` ✓ Fi.CI.BAT: success " Patchwork
` (4 subsequent siblings)
27 siblings, 0 replies; 64+ messages in thread
From: Patchwork @ 2019-07-13 1:19 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Tiger Lake part 2
URL : https://patchwork.freedesktop.org/series/63670/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4f24138130a1 drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
05104c3c0561 drm/i915/tgl: select correct bit for port select
e617f60b4405 drm/i915/tgl: update ddi/tc clock_off bits
-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tc_port' - possible side-effects?
#24: FILE: drivers/gpu/drm/i915/i915_reg.h:9752:
+#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \
+ (tc_port) + 12 : \
+ (tc_port) - PORT_TC4 + 21))
total: 0 errors, 0 warnings, 1 checks, 11 lines checked
57a1c831349d drm/i915/tgl: Add hpd interrupt handling
f2dae71692e9 drm/i915/tgl: Update north display hotplug detection to TGL connections
53ccf63d0767 drm/i915/tgl: handle DP aux interrupts
09bbb93143b0 drm/i915/dmc: Load DMC on TGL
68948c4cd8c6 drm/i915/tgl: Add DKL phy pll registers
eb6e1fade3e4 drm/i915/tgl: re-indent code to prepare for DKL changes
2ab94df17776 drm/i915/tgl: Add DKL phy pll state calculations
3b65df033d2d drm/i915/tgl: start adding the DKL PLLs to use on TC ports
afc14ee9b29d drm/i915/tgl: Add support for dkl pll write
75c99ba6ce4d drm/i915/gen12: add support for reading the timestamp frequency
208c82065cfd drm/i915/tgl: allow the reg_read ioctl to read the RCS TIMESTAMP register
86ca705881e4 drm/i915/tgl: Introduce initial Tigerlake Workarounds
4a3b203f6670 drm/i915/tgl: Implement Wa_1604555607
b7e6d7545812 drm/i915/tgl: Implement Wa_1406941453
155c1076b200 drm/i915/tgl: Define MOCS entries for Tigerlake
f0efc64bb91a drm/i915/tgl: Tigerlake only has global MOCS registers
5bc6743823d3 drm/i915: Move MOCS setup to intel_mocs.c
224b62268855 drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers
a093f7155e48 drm/i915/mst: Do not hardcoded the crtcs that encoder can connect
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* ✓ Fi.CI.BAT: success for Tiger Lake part 2
2019-07-13 1:09 [PATCH 00/22] Tiger Lake part 2 Lucas De Marchi
` (22 preceding siblings ...)
2019-07-13 1:19 ` ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake part 2 Patchwork
@ 2019-07-13 1:38 ` Patchwork
2019-07-14 20:26 ` ✗ Fi.CI.IGT: failure " Patchwork
` (3 subsequent siblings)
27 siblings, 0 replies; 64+ messages in thread
From: Patchwork @ 2019-07-13 1:38 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Tiger Lake part 2
URL : https://patchwork.freedesktop.org/series/63670/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6480 -> Patchwork_13653
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/
Known issues
------------
Here are the changes found in Patchwork_13653 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@prime_vgem@basic-fence-flip:
- fi-ilk-650: [PASS][1] -> [DMESG-WARN][2] ([fdo#106387]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/fi-ilk-650/igt@prime_vgem@basic-fence-flip.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/fi-ilk-650/igt@prime_vgem@basic-fence-flip.html
#### Possible fixes ####
* {igt@gem_ctx_switch@legacy-render}:
- fi-icl-u3: [INCOMPLETE][3] ([fdo#107713]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/fi-icl-u3/igt@gem_ctx_switch@legacy-render.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/fi-icl-u3/igt@gem_ctx_switch@legacy-render.html
* igt@i915_module_load@reload:
- fi-blb-e6850: [INCOMPLETE][5] ([fdo#107718]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/fi-blb-e6850/igt@i915_module_load@reload.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/fi-blb-e6850/igt@i915_module_load@reload.html
* igt@i915_selftest@live_contexts:
- fi-skl-iommu: [INCOMPLETE][7] ([fdo#111050]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/fi-skl-iommu/igt@i915_selftest@live_contexts.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/fi-skl-iommu/igt@i915_selftest@live_contexts.html
* igt@kms_chamelium@hdmi-edid-read:
- {fi-icl-u4}: [FAIL][9] ([fdo#111045] / [fdo#111046 ]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/fi-icl-u4/igt@kms_chamelium@hdmi-edid-read.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/fi-icl-u4/igt@kms_chamelium@hdmi-edid-read.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046
[fdo#111050]: https://bugs.freedesktop.org/show_bug.cgi?id=111050
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
Participating hosts (53 -> 45)
------------------------------
Additional (2): fi-apl-guc fi-cml-u
Missing (10): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-icl-y fi-icl-dsi fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_6480 -> Patchwork_13653
CI_DRM_6480: a4856ee98f5d0058656d4fd8efb4ffa433bdfaa4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5096: bb4d55a02dd3e1971f2c091a13b6bd7f0b496e40 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13653: a093f7155e489ec00adfe2f0a8fcf4e5776c2586 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a093f7155e48 drm/i915/mst: Do not hardcoded the crtcs that encoder can connect
224b62268855 drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers
5bc6743823d3 drm/i915: Move MOCS setup to intel_mocs.c
f0efc64bb91a drm/i915/tgl: Tigerlake only has global MOCS registers
155c1076b200 drm/i915/tgl: Define MOCS entries for Tigerlake
b7e6d7545812 drm/i915/tgl: Implement Wa_1406941453
4a3b203f6670 drm/i915/tgl: Implement Wa_1604555607
86ca705881e4 drm/i915/tgl: Introduce initial Tigerlake Workarounds
208c82065cfd drm/i915/tgl: allow the reg_read ioctl to read the RCS TIMESTAMP register
75c99ba6ce4d drm/i915/gen12: add support for reading the timestamp frequency
afc14ee9b29d drm/i915/tgl: Add support for dkl pll write
3b65df033d2d drm/i915/tgl: start adding the DKL PLLs to use on TC ports
2ab94df17776 drm/i915/tgl: Add DKL phy pll state calculations
eb6e1fade3e4 drm/i915/tgl: re-indent code to prepare for DKL changes
68948c4cd8c6 drm/i915/tgl: Add DKL phy pll registers
09bbb93143b0 drm/i915/dmc: Load DMC on TGL
53ccf63d0767 drm/i915/tgl: handle DP aux interrupts
f2dae71692e9 drm/i915/tgl: Update north display hotplug detection to TGL connections
57a1c831349d drm/i915/tgl: Add hpd interrupt handling
e617f60b4405 drm/i915/tgl: update ddi/tc clock_off bits
05104c3c0561 drm/i915/tgl: select correct bit for port select
4f24138130a1 drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* ✗ Fi.CI.IGT: failure for Tiger Lake part 2
2019-07-13 1:09 [PATCH 00/22] Tiger Lake part 2 Lucas De Marchi
` (23 preceding siblings ...)
2019-07-13 1:38 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-07-14 20:26 ` Patchwork
2019-07-15 22:32 ` ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake part 2 (rev2) Patchwork
` (2 subsequent siblings)
27 siblings, 0 replies; 64+ messages in thread
From: Patchwork @ 2019-07-14 20:26 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Tiger Lake part 2
URL : https://patchwork.freedesktop.org/series/63670/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6480_full -> Patchwork_13653_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_13653_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_13653_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_13653_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_mocs_settings@mocs-isolation-blt:
- shard-iclb: NOTRUN -> [FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-iclb1/igt@gem_mocs_settings@mocs-isolation-blt.html
* igt@gem_mocs_settings@mocs-reset-ctx-render:
- shard-iclb: [PASS][2] -> [FAIL][3] +17 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-iclb8/igt@gem_mocs_settings@mocs-reset-ctx-render.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-iclb3/igt@gem_mocs_settings@mocs-reset-ctx-render.html
Known issues
------------
Here are the changes found in Patchwork_13653_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@system-suspend-modeset:
- shard-iclb: [PASS][4] -> [INCOMPLETE][5] ([fdo#107713] / [fdo#108840])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-iclb4/igt@i915_pm_rpm@system-suspend-modeset.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-iclb4/igt@i915_pm_rpm@system-suspend-modeset.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-hsw: [PASS][6] -> [FAIL][7] ([fdo#105767])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-hsw5/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-hsw1/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
* igt@kms_flip@flip-vs-suspend:
- shard-skl: [PASS][8] -> [INCOMPLETE][9] ([fdo#109507])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-skl7/igt@kms_flip@flip-vs-suspend.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-skl1/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-kbl: [PASS][10] -> [DMESG-WARN][11] ([fdo#108566]) +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip@plain-flip-ts-check-interruptible:
- shard-skl: [PASS][12] -> [FAIL][13] ([fdo#100368])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-skl4/igt@kms_flip@plain-flip-ts-check-interruptible.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-skl1/igt@kms_flip@plain-flip-ts-check-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-msflip-blt:
- shard-iclb: [PASS][14] -> [FAIL][15] ([fdo#103167]) +3 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-msflip-blt.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@psr-suspend:
- shard-skl: [PASS][16] -> [INCOMPLETE][17] ([fdo#104108] / [fdo#106978])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-skl10/igt@kms_frontbuffer_tracking@psr-suspend.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-skl7/igt@kms_frontbuffer_tracking@psr-suspend.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][18] -> [FAIL][19] ([fdo#108145] / [fdo#110403])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_plane_scaling@pipe-b-scaler-with-rotation:
- shard-glk: [PASS][20] -> [DMESG-WARN][21] ([fdo#105763] / [fdo#106538])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-glk2/igt@kms_plane_scaling@pipe-b-scaler-with-rotation.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-glk5/igt@kms_plane_scaling@pipe-b-scaler-with-rotation.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: [PASS][22] -> [SKIP][23] ([fdo#109441]) +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-iclb2/igt@kms_psr@psr2_suspend.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-iclb7/igt@kms_psr@psr2_suspend.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-apl: [PASS][24] -> [DMESG-WARN][25] ([fdo#108566]) +2 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-apl8/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-apl3/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* igt@tools_test@tools_test:
- shard-apl: [PASS][26] -> [SKIP][27] ([fdo#109271])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-apl7/igt@tools_test@tools_test.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-apl3/igt@tools_test@tools_test.html
#### Possible fixes ####
* igt@i915_pm_backlight@fade_with_suspend:
- shard-iclb: [INCOMPLETE][28] ([fdo#107713] / [fdo#107820]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-iclb5/igt@i915_pm_backlight@fade_with_suspend.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-iclb5/igt@i915_pm_backlight@fade_with_suspend.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [DMESG-WARN][30] ([fdo#108566]) -> [PASS][31] +2 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-apl7/igt@i915_suspend@sysfs-reader.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-apl4/igt@i915_suspend@sysfs-reader.html
* igt@kms_busy@extended-modeset-hang-newfb-render-c:
- shard-kbl: [DMESG-WARN][32] ([fdo#103313] / [fdo#103558] / [fdo#105602] / [fdo#110222]) -> [PASS][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-kbl1/igt@kms_busy@extended-modeset-hang-newfb-render-c.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-kbl4/igt@kms_busy@extended-modeset-hang-newfb-render-c.html
* igt@kms_cursor_crc@pipe-b-cursor-alpha-transparent:
- shard-snb: [SKIP][34] ([fdo#109271]) -> [PASS][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-snb6/igt@kms_cursor_crc@pipe-b-cursor-alpha-transparent.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-snb1/igt@kms_cursor_crc@pipe-b-cursor-alpha-transparent.html
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-ytiled:
- shard-skl: [FAIL][36] ([fdo#103184] / [fdo#103232] / [fdo#108145]) -> [PASS][37]
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-skl8/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-ytiled.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-skl10/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-ytiled.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: [FAIL][38] ([fdo#105363]) -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [FAIL][40] ([fdo#105363]) -> [PASS][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-skl10/igt@kms_flip@flip-vs-expired-vblank.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-skl10/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-suspend:
- shard-kbl: [DMESG-WARN][42] ([fdo#103558] / [fdo#105602] / [fdo#108566]) -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-kbl1/igt@kms_flip@flip-vs-suspend.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-kbl4/igt@kms_flip@flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
- shard-iclb: [FAIL][44] ([fdo#103167]) -> [PASS][45] +3 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_pipe_crc_basic@bad-source:
- shard-kbl: [DMESG-WARN][46] ([fdo#103558] / [fdo#105602]) -> [PASS][47] +11 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-kbl1/igt@kms_pipe_crc_basic@bad-source.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-kbl4/igt@kms_pipe_crc_basic@bad-source.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][48] ([fdo#108145]) -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [SKIP][50] ([fdo#109642] / [fdo#111068]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-iclb7/igt@kms_psr2_su@frontbuffer.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][52] ([fdo#109441]) -> [PASS][53] +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-iclb7/igt@kms_psr@psr2_no_drrs.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
* igt@perf_pmu@rc6:
- shard-kbl: [SKIP][54] ([fdo#109271]) -> [PASS][55]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-kbl7/igt@perf_pmu@rc6.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-kbl4/igt@perf_pmu@rc6.html
#### Warnings ####
* igt@kms_atomic_transition@4x-modeset-transitions:
- shard-kbl: [SKIP][56] ([fdo#105602] / [fdo#109271] / [fdo#109278]) -> [SKIP][57] ([fdo#109271] / [fdo#109278]) +1 similar issue
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-kbl1/igt@kms_atomic_transition@4x-modeset-transitions.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-kbl4/igt@kms_atomic_transition@4x-modeset-transitions.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-skl: [FAIL][58] ([fdo#108040]) -> [FAIL][59] ([fdo#103167])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-skl8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-skl10/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render:
- shard-kbl: [SKIP][60] ([fdo#105602] / [fdo#109271]) -> [SKIP][61] ([fdo#109271]) +10 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-kbl1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-kbl4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt:
- shard-skl: [FAIL][62] ([fdo#103167]) -> [FAIL][63] ([fdo#108040])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6480/shard-skl8/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/shard-skl10/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt.html
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103313]: https://bugs.freedesktop.org/show_bug.cgi?id=103313
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
[fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
[fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107820]: https://bugs.freedesktop.org/show_bug.cgi?id=107820
[fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110222]: https://bugs.freedesktop.org/show_bug.cgi?id=110222
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_6480 -> Patchwork_13653
CI_DRM_6480: a4856ee98f5d0058656d4fd8efb4ffa433bdfaa4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5096: bb4d55a02dd3e1971f2c091a13b6bd7f0b496e40 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13653: a093f7155e489ec00adfe2f0a8fcf4e5776c2586 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13653/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake part 2 (rev2)
2019-07-13 1:09 [PATCH 00/22] Tiger Lake part 2 Lucas De Marchi
` (24 preceding siblings ...)
2019-07-14 20:26 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2019-07-15 22:32 ` Patchwork
2019-07-15 22:55 ` ✓ Fi.CI.BAT: success " Patchwork
2019-07-16 0:02 ` ✗ Fi.CI.IGT: failure " Patchwork
27 siblings, 0 replies; 64+ messages in thread
From: Patchwork @ 2019-07-15 22:32 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Tiger Lake part 2 (rev2)
URL : https://patchwork.freedesktop.org/series/63670/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1399f5e0e588 drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
7aeb531f6973 drm/i915/tgl: select correct bit for port select
61df67c27f47 drm/i915/tgl: update ddi/tc clock_off bits
-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tc_port' - possible side-effects?
#24: FILE: drivers/gpu/drm/i915/i915_reg.h:9742:
+#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \
+ (tc_port) + 12 : \
+ (tc_port) - PORT_TC4 + 21))
total: 0 errors, 0 warnings, 1 checks, 11 lines checked
545774fac0b1 drm/i915/tgl: Add hpd interrupt handling
89b636156020 drm/i915/tgl: Update north display hotplug detection to TGL connections
b77732b3475a drm/i915/tgl: handle DP aux interrupts
d79bc42ba14e drm/i915/dmc: Load DMC on TGL
eba607ec684f drm/i915/tgl: Add DKL phy pll registers
bed7e1bf70ee drm/i915/tgl: re-indent code to prepare for DKL changes
fde555890199 drm/i915/tgl: Add DKL phy pll state calculations
21a4942ecadc drm/i915/tgl: start adding the DKL PLLs to use on TC ports
cf9e40f919cc drm/i915/tgl: Add support for dkl pll write
8839cfd99330 drm/i915/gen12: add support for reading the timestamp frequency
94f4cd6f0993 drm/i915/tgl: allow the reg_read ioctl to read the RCS TIMESTAMP register
c961a0a0ef25 drm/i915/tgl: Introduce initial Tigerlake Workarounds
e141194e47b0 drm/i915/tgl: Implement Wa_1604555607
21e1d03a7fc9 drm/i915/tgl: Implement Wa_1406941453
622babc7ad99 drm/i915/tgl: Define MOCS entries for Tigerlake
bbe66a71b6b7 drm/i915/tgl: Tigerlake only has global MOCS registers
2d16249077a4 drm/i915: Move MOCS setup to intel_mocs.c
f844f9561a03 drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers
261c7e151c10 drm/i915/mst: Do not hardcoded the crtcs that encoder can connect
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* ✓ Fi.CI.BAT: success for Tiger Lake part 2 (rev2)
2019-07-13 1:09 [PATCH 00/22] Tiger Lake part 2 Lucas De Marchi
` (25 preceding siblings ...)
2019-07-15 22:32 ` ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake part 2 (rev2) Patchwork
@ 2019-07-15 22:55 ` Patchwork
2019-07-16 0:02 ` ✗ Fi.CI.IGT: failure " Patchwork
27 siblings, 0 replies; 64+ messages in thread
From: Patchwork @ 2019-07-15 22:55 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Tiger Lake part 2 (rev2)
URL : https://patchwork.freedesktop.org/series/63670/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6488 -> Patchwork_13661
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_13661:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_hangcheck:
- {fi-icl-u4}: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
Known issues
------------
Here are the changes found in Patchwork_13661 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fence@basic-wait-default:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/fi-icl-u3/igt@gem_exec_fence@basic-wait-default.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/fi-icl-u3/igt@gem_exec_fence@basic-wait-default.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][5] -> [INCOMPLETE][6] ([fdo#107718])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
* igt@i915_selftest@live_contexts:
- fi-skl-iommu: [PASS][7] -> [INCOMPLETE][8] ([fdo#111050])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/fi-skl-iommu/igt@i915_selftest@live_contexts.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/fi-skl-iommu/igt@i915_selftest@live_contexts.html
#### Possible fixes ####
* igt@gem_ctx_exec@basic:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/fi-icl-u3/igt@gem_ctx_exec@basic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/fi-icl-u3/igt@gem_ctx_exec@basic.html
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [DMESG-FAIL][11] ([fdo#111108]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
* igt@kms_chamelium@dp-crc-fast:
- fi-icl-u2: [FAIL][13] ([fdo#109635 ]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html
- fi-cml-u2: [FAIL][15] ([fdo#110627]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html
* igt@prime_vgem@basic-fence-flip:
- fi-ilk-650: [DMESG-WARN][17] ([fdo#106387]) -> [PASS][18] +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/fi-ilk-650/igt@prime_vgem@basic-fence-flip.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/fi-ilk-650/igt@prime_vgem@basic-fence-flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#110627]: https://bugs.freedesktop.org/show_bug.cgi?id=110627
[fdo#111050]: https://bugs.freedesktop.org/show_bug.cgi?id=111050
[fdo#111108]: https://bugs.freedesktop.org/show_bug.cgi?id=111108
[fdo#111115]: https://bugs.freedesktop.org/show_bug.cgi?id=111115
Participating hosts (54 -> 47)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_6488 -> Patchwork_13661
CI_DRM_6488: bbf4d95db6732b16547dc9d849701ccf4189aa0d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5098: 41ff022b62b45a5b84504daa3537fa1b295b97c9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13661: 261c7e151c1048692404d5a3e3e5fc0fdb7a038c @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
261c7e151c10 drm/i915/mst: Do not hardcoded the crtcs that encoder can connect
f844f9561a03 drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers
2d16249077a4 drm/i915: Move MOCS setup to intel_mocs.c
bbe66a71b6b7 drm/i915/tgl: Tigerlake only has global MOCS registers
622babc7ad99 drm/i915/tgl: Define MOCS entries for Tigerlake
21e1d03a7fc9 drm/i915/tgl: Implement Wa_1406941453
e141194e47b0 drm/i915/tgl: Implement Wa_1604555607
c961a0a0ef25 drm/i915/tgl: Introduce initial Tigerlake Workarounds
94f4cd6f0993 drm/i915/tgl: allow the reg_read ioctl to read the RCS TIMESTAMP register
8839cfd99330 drm/i915/gen12: add support for reading the timestamp frequency
cf9e40f919cc drm/i915/tgl: Add support for dkl pll write
21a4942ecadc drm/i915/tgl: start adding the DKL PLLs to use on TC ports
fde555890199 drm/i915/tgl: Add DKL phy pll state calculations
bed7e1bf70ee drm/i915/tgl: re-indent code to prepare for DKL changes
eba607ec684f drm/i915/tgl: Add DKL phy pll registers
d79bc42ba14e drm/i915/dmc: Load DMC on TGL
b77732b3475a drm/i915/tgl: handle DP aux interrupts
89b636156020 drm/i915/tgl: Update north display hotplug detection to TGL connections
545774fac0b1 drm/i915/tgl: Add hpd interrupt handling
61df67c27f47 drm/i915/tgl: update ddi/tc clock_off bits
7aeb531f6973 drm/i915/tgl: select correct bit for port select
1399f5e0e588 drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 64+ messages in thread* ✗ Fi.CI.IGT: failure for Tiger Lake part 2 (rev2)
2019-07-13 1:09 [PATCH 00/22] Tiger Lake part 2 Lucas De Marchi
` (26 preceding siblings ...)
2019-07-15 22:55 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-07-16 0:02 ` Patchwork
27 siblings, 0 replies; 64+ messages in thread
From: Patchwork @ 2019-07-16 0:02 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Tiger Lake part 2 (rev2)
URL : https://patchwork.freedesktop.org/series/63670/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6488_full -> Patchwork_13661_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_13661_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_13661_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_13661_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_mocs_settings@mocs-reset-ctx-render:
- shard-iclb: [PASS][1] -> [FAIL][2] +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/shard-iclb2/igt@gem_mocs_settings@mocs-reset-ctx-render.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/shard-iclb3/igt@gem_mocs_settings@mocs-reset-ctx-render.html
Known issues
------------
Here are the changes found in Patchwork_13661_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_tiled_swapping@non-threaded:
- shard-iclb: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] / [fdo#108686])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/shard-iclb8/igt@gem_tiled_swapping@non-threaded.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/shard-iclb4/igt@gem_tiled_swapping@non-threaded.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip@plain-flip-ts-check-interruptible:
- shard-glk: [PASS][7] -> [FAIL][8] ([fdo#100368])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/shard-glk1/igt@kms_flip@plain-flip-ts-check-interruptible.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/shard-glk8/igt@kms_flip@plain-flip-ts-check-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc:
- shard-skl: [PASS][9] -> [FAIL][10] ([fdo#108040])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/shard-skl4/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/shard-skl5/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103166])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/shard-iclb1/igt@kms_plane_lowres@pipe-a-tiling-x.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/shard-iclb4/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr@no_drrs:
- shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#108341])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/shard-iclb4/igt@kms_psr@no_drrs.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/shard-iclb1/igt@kms_psr@no_drrs.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/shard-iclb8/igt@kms_psr@psr2_sprite_plane_move.html
#### Possible fixes ####
* igt@gem_eio@in-flight-suspend:
- shard-snb: [DMESG-WARN][21] ([fdo#102365]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/shard-snb5/igt@gem_eio@in-flight-suspend.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/shard-snb6/igt@gem_eio@in-flight-suspend.html
* igt@i915_pm_backlight@fade_with_suspend:
- shard-skl: [INCOMPLETE][23] ([fdo#104108]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/shard-skl9/igt@i915_pm_backlight@fade_with_suspend.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/shard-skl2/igt@i915_pm_backlight@fade_with_suspend.html
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-kbl: [SKIP][25] ([fdo#109271]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/shard-kbl2/igt@i915_pm_rc6_residency@rc6-accuracy.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/shard-kbl7/igt@i915_pm_rc6_residency@rc6-accuracy.html
* igt@i915_pm_rpm@debugfs-read:
- shard-skl: [INCOMPLETE][27] ([fdo#107807]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/shard-skl3/igt@i915_pm_rpm@debugfs-read.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/shard-skl1/igt@i915_pm_rpm@debugfs-read.html
* igt@kms_cursor_crc@pipe-b-cursor-64x64-offscreen:
- shard-glk: [INCOMPLETE][29] ([fdo#103359] / [k.org#198133]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/shard-glk2/igt@kms_cursor_crc@pipe-b-cursor-64x64-offscreen.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/shard-glk9/igt@kms_cursor_crc@pipe-b-cursor-64x64-offscreen.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-wc-untiled:
- shard-skl: [FAIL][31] ([fdo#103184] / [fdo#103232]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/shard-skl5/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-untiled.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/shard-skl4/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-untiled.html
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-untiled:
- shard-skl: [FAIL][33] ([fdo#103184] / [fdo#103232] / [fdo#108472]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/shard-skl7/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-untiled.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/shard-skl8/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-untiled.html
* igt@kms_draw_crc@fill-fb:
- shard-skl: [FAIL][35] ([fdo#103184]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/shard-skl5/igt@kms_draw_crc@fill-fb.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/shard-skl4/igt@kms_draw_crc@fill-fb.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [FAIL][37] ([fdo#105363]) -> [PASS][38] +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/shard-skl10/igt@kms_flip@flip-vs-expired-vblank.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/shard-skl10/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-skl: [INCOMPLETE][39] ([fdo#109507]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/shard-skl4/igt@kms_flip@flip-vs-suspend-interruptible.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/shard-skl5/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip@plain-flip-ts-check-interruptible:
- shard-skl: [FAIL][41] ([fdo#100368]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/shard-skl5/igt@kms_flip@plain-flip-ts-check-interruptible.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/shard-skl5/igt@kms_flip@plain-flip-ts-check-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt:
- shard-iclb: [FAIL][43] ([fdo#103167]) -> [PASS][44] +4 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt:
- shard-skl: [FAIL][45] ([fdo#108040]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/shard-skl7/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/shard-skl8/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render:
- shard-skl: [FAIL][47] ([fdo#103167]) -> [PASS][48] +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/shard-skl8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: [DMESG-WARN][49] ([fdo#108566]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/shard-apl5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][51] ([fdo#108145]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][53] ([fdo#108145] / [fdo#110403]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_cursor_mmap_gtt:
- shard-iclb: [SKIP][55] ([fdo#109441]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/shard-iclb5/igt@kms_psr@psr2_cursor_mmap_gtt.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_gtt.html
* igt@kms_setmode@basic:
- shard-kbl: [FAIL][57] ([fdo#99912]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6488/shard-kbl7/igt@kms_setmode@basic.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/shard-kbl6/igt@kms_setmode@basic.html
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#102365]: https://bugs.freedesktop.org/show_bug.cgi?id=102365
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
[fdo#108472]: https://bugs.freedesktop.org/show_bug.cgi?id=108472
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_6488 -> Patchwork_13661
CI_DRM_6488: bbf4d95db6732b16547dc9d849701ccf4189aa0d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5098: 41ff022b62b45a5b84504daa3537fa1b295b97c9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13661: 261c7e151c1048692404d5a3e3e5fc0fdb7a038c @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13661/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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