From: Andrew Murray <andrew.murray@arm.com> To: Mathieu Poirier <mathieu.poirier@linaro.org>, Suzuki K Poulose <suzuki.poulose@arm.com>, Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: linux-arm-kernel@lists.infradead.org, Mike Leach <mike.leach@linaro.org>, Sudeep Holla <sudeep.holla@arm.com>, Leo Yan <leo.yan@linaro.org>, Al.Grant@arm.com, coresight@lists.linaro.org, stable@vger.kernel.org Subject: [PATCH v4 2/6] coresight: etm4x: use explicit barriers on enable/disable Date: Tue, 30 Jul 2019 13:51:53 +0100 [thread overview] Message-ID: <20190730125157.884-3-andrew.murray@arm.com> (raw) In-Reply-To: <20190730125157.884-1-andrew.murray@arm.com> Synchronization is recommended before disabling the trace registers to prevent any start or stop points being speculative at the point of disabling the unit (section 7.3.77 of ARM IHI 0064D). Synchronization is also recommended after programming the trace registers to ensure all updates are committed prior to normal code resuming (section 4.3.7 of ARM IHI 0064D). Let's ensure these syncronization points are present in the code and clearly commented. Note that we could rely on the barriers in CS_LOCK and coresight_disclaim_device_unlocked or the context switch to user space - however coresight may be of use in the kernel. On armv8 the mb macro is defined as dsb(sy) - Given that the etm4x is only used on armv8 let's directly use dsb(sy) instead of mb(). This removes some ambiguity and makes it easier to correlate the code with the TRM. Signed-off-by: Andrew Murray <andrew.murray@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> CC: stable@vger.kernel.org --- drivers/hwtracing/coresight/coresight-etm4x.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 7ad15651e069..ec9468880c71 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -188,6 +188,13 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) dev_err(etm_dev, "timeout while waiting for Idle Trace Status\n"); + /* + * As recommended by section 4.3.7 ("Synchronization when using the + * memory-mapped interface") of ARM IHI 0064D + */ + dsb(sy); + isb(); + done: CS_LOCK(drvdata->base); @@ -453,8 +460,12 @@ static void etm4_disable_hw(void *info) /* EN, bit[0] Trace unit enable bit */ control &= ~0x1; - /* make sure everything completes before disabling */ - mb(); + /* + * Make sure everything completes before disabling, as recommended + * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register, + * SSTATUS") of ARM IHI 0064D + */ + dsb(sy); isb(); writel_relaxed(control, drvdata->base + TRCPRGCTLR); -- 2.21.0
WARNING: multiple messages have this Message-ID (diff)
From: Andrew Murray <andrew.murray@arm.com> To: Mathieu Poirier <mathieu.poirier@linaro.org>, Suzuki K Poulose <suzuki.poulose@arm.com>, Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Al.Grant@arm.com, coresight@lists.linaro.org, Leo Yan <leo.yan@linaro.org>, stable@vger.kernel.org, Sudeep Holla <sudeep.holla@arm.com>, linux-arm-kernel@lists.infradead.org, Mike Leach <mike.leach@linaro.org> Subject: [PATCH v4 2/6] coresight: etm4x: use explicit barriers on enable/disable Date: Tue, 30 Jul 2019 13:51:53 +0100 [thread overview] Message-ID: <20190730125157.884-3-andrew.murray@arm.com> (raw) In-Reply-To: <20190730125157.884-1-andrew.murray@arm.com> Synchronization is recommended before disabling the trace registers to prevent any start or stop points being speculative at the point of disabling the unit (section 7.3.77 of ARM IHI 0064D). Synchronization is also recommended after programming the trace registers to ensure all updates are committed prior to normal code resuming (section 4.3.7 of ARM IHI 0064D). Let's ensure these syncronization points are present in the code and clearly commented. Note that we could rely on the barriers in CS_LOCK and coresight_disclaim_device_unlocked or the context switch to user space - however coresight may be of use in the kernel. On armv8 the mb macro is defined as dsb(sy) - Given that the etm4x is only used on armv8 let's directly use dsb(sy) instead of mb(). This removes some ambiguity and makes it easier to correlate the code with the TRM. Signed-off-by: Andrew Murray <andrew.murray@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> CC: stable@vger.kernel.org --- drivers/hwtracing/coresight/coresight-etm4x.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 7ad15651e069..ec9468880c71 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -188,6 +188,13 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) dev_err(etm_dev, "timeout while waiting for Idle Trace Status\n"); + /* + * As recommended by section 4.3.7 ("Synchronization when using the + * memory-mapped interface") of ARM IHI 0064D + */ + dsb(sy); + isb(); + done: CS_LOCK(drvdata->base); @@ -453,8 +460,12 @@ static void etm4_disable_hw(void *info) /* EN, bit[0] Trace unit enable bit */ control &= ~0x1; - /* make sure everything completes before disabling */ - mb(); + /* + * Make sure everything completes before disabling, as recommended + * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register, + * SSTATUS") of ARM IHI 0064D + */ + dsb(sy); isb(); writel_relaxed(control, drvdata->base + TRCPRGCTLR); -- 2.21.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-07-30 12:52 UTC|newest] Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-07-30 12:51 [PATCH v4 0/6] coresight: etm4x: save/restore ETMv4 context across CPU low power states Andrew Murray 2019-07-30 12:51 ` [PATCH v4 1/6] coresight: etm4x: remove superfluous setting of os_unlock Andrew Murray 2019-07-30 12:51 ` Andrew Murray [this message] 2019-07-30 12:51 ` [PATCH v4 2/6] coresight: etm4x: use explicit barriers on enable/disable Andrew Murray 2019-08-01 13:31 ` Sasha Levin 2019-08-01 14:48 ` Mathieu Poirier 2019-08-01 14:48 ` Mathieu Poirier 2019-08-02 18:08 ` Sasha Levin 2019-07-30 12:51 ` [PATCH v4 3/6] coresight: etm4x: use module_param instead of module_param_named Andrew Murray 2019-08-02 10:23 ` Suzuki K Poulose 2019-07-30 12:51 ` [PATCH v4 4/6] coresight: etm4x: improve clarity of etm4_os_unlock comment Andrew Murray 2019-07-30 12:51 ` [PATCH v4 5/6] coresight: etm4x: save/restore state across CPU low power states Andrew Murray 2019-07-30 21:16 ` Mathieu Poirier 2019-07-30 21:45 ` Andrew Murray 2019-07-31 8:16 ` Mike Leach 2019-07-31 9:45 ` Andrew Murray 2019-08-02 10:54 ` Suzuki K Poulose 2019-08-14 9:12 ` Andrew Murray 2019-07-30 12:51 ` [PATCH v4 6/6] dt-bindings: arm: coresight: Add support for coresight-needs-save-restore Andrew Murray 2019-08-02 10:40 ` Suzuki K Poulose 2019-08-02 14:37 ` Andrew Murray 2019-08-04 13:13 ` Mathieu Poirier 2019-08-14 10:01 ` Andrew Murray 2019-08-14 11:06 ` Mike Leach 2019-08-14 12:35 ` Suzuki K Poulose 2019-08-14 12:49 ` Andrew Murray 2019-08-14 14:20 ` Mike Leach 2019-07-30 20:12 ` [PATCH v4 0/6] coresight: etm4x: save/restore ETMv4 context across CPU low power states Mathieu Poirier 2019-07-30 21:46 ` Andrew Murray
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