* [PATCH v3 1/9] drm/i915/tgl: Add DC3CO required register and bits
2019-07-30 13:50 [PATCH v3 0/9] DC3CO Support for TGL Anshuman Gupta
@ 2019-07-30 13:50 ` Anshuman Gupta
2019-08-01 4:23 ` Animesh Manna
2019-07-30 13:50 ` [PATCH v3 2/9] drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask Anshuman Gupta
` (10 subsequent siblings)
11 siblings, 1 reply; 16+ messages in thread
From: Anshuman Gupta @ 2019-07-30 13:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Deak, jani.nikula, Nikula, Manna
Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.
Cc: Nikula, Jani <jani.nikula@intel.com>
Cc: Deak, Imre <imre.deak@intel.com>
Cc: Manna, Animesh <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d2b76121d863..d42e95da5b14 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4195,6 +4195,7 @@ enum {
#define _VTOTAL_A 0x6000c
#define _VBLANK_A 0x60010
#define _VSYNC_A 0x60014
+#define _EXITLINE_A 0x60018
#define _PIPEASRC 0x6001c
#define _BCLRPAT_A 0x60020
#define _VSYNCSHIFT_A 0x60028
@@ -4241,11 +4242,16 @@ enum {
#define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A)
#define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A)
#define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A)
+#define EXITLINE(trans) _MMIO_TRANS2(trans, _EXITLINE_A)
#define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A)
#define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
#define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
#define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
+#define EXITLINE_ENABLE (1 << 31)
+#define EXITLINE_MASK (0x1fff)
+#define EXITLINE_SHIFT 0
+
/* HSW+ eDP PSR registers */
#define HSW_EDP_PSR_BASE 0x64800
#define BDW_EDP_PSR_BASE 0x6f800
@@ -9996,6 +10002,8 @@ enum skl_power_gate {
/* GEN9 DC */
#define DC_STATE_EN _MMIO(0x45504)
#define DC_STATE_DISABLE 0
+#define DC_STATE_EN_DC3CO (1 << 30)
+#define DC_STATE_DC3CO_STATUS (1 << 29)
#define DC_STATE_EN_UPTO_DC5 (1 << 0)
#define DC_STATE_EN_DC9 (1 << 3)
#define DC_STATE_EN_UPTO_DC6 (2 << 0)
--
2.21.0
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^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v3 1/9] drm/i915/tgl: Add DC3CO required register and bits
2019-07-30 13:50 ` [PATCH v3 1/9] drm/i915/tgl: Add DC3CO required register and bits Anshuman Gupta
@ 2019-08-01 4:23 ` Animesh Manna
0 siblings, 0 replies; 16+ messages in thread
From: Animesh Manna @ 2019-08-01 4:23 UTC (permalink / raw)
To: Anshuman Gupta, intel-gfx; +Cc: jani.nikula
On 7/30/2019 7:20 PM, Anshuman Gupta wrote:
> Adding following definition to i915_reg.h
> 1. DC_STATE_EN register DC3CO bit fields and masks.
> 2. Transcoder EXITLINE register and its bit fields and mask.
>
> Cc: Nikula, Jani <jani.nikula@intel.com>
> Cc: Deak, Imre <imre.deak@intel.com>
> Cc: Manna, Animesh <animesh.manna@intel.com>
Should be like below,
Cc: Animesh Manna <animesh.manna@intel.com>
Need change everywhere in this patch series for all.
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d2b76121d863..d42e95da5b14 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4195,6 +4195,7 @@ enum {
> #define _VTOTAL_A 0x6000c
> #define _VBLANK_A 0x60010
> #define _VSYNC_A 0x60014
> +#define _EXITLINE_A 0x60018
> #define _PIPEASRC 0x6001c
> #define _BCLRPAT_A 0x60020
> #define _VSYNCSHIFT_A 0x60028
> @@ -4241,11 +4242,16 @@ enum {
> #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A)
> #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A)
> #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A)
> +#define EXITLINE(trans) _MMIO_TRANS2(trans, _EXITLINE_A)
> #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A)
> #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
> #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
> #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
>
> +#define EXITLINE_ENABLE (1 << 31)
> +#define EXITLINE_MASK (0x1fff)
> +#define EXITLINE_SHIFT 0
> +
> /* HSW+ eDP PSR registers */
> #define HSW_EDP_PSR_BASE 0x64800
> #define BDW_EDP_PSR_BASE 0x6f800
> @@ -9996,6 +10002,8 @@ enum skl_power_gate {
> /* GEN9 DC */
> #define DC_STATE_EN _MMIO(0x45504)
> #define DC_STATE_DISABLE 0
> +#define DC_STATE_EN_DC3CO (1 << 30)
> +#define DC_STATE_DC3CO_STATUS (1 << 29)
Need extra space.
Regards,
Animesh
> #define DC_STATE_EN_UPTO_DC5 (1 << 0)
> #define DC_STATE_EN_DC9 (1 << 3)
> #define DC_STATE_EN_UPTO_DC6 (2 << 0)
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^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 2/9] drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
2019-07-30 13:50 [PATCH v3 0/9] DC3CO Support for TGL Anshuman Gupta
2019-07-30 13:50 ` [PATCH v3 1/9] drm/i915/tgl: Add DC3CO required register and bits Anshuman Gupta
@ 2019-07-30 13:50 ` Anshuman Gupta
2019-08-01 4:35 ` Animesh Manna
2019-07-30 13:50 ` [PATCH v3 3/9] drm/i915/tgl: Add power well to enable DC3CO state Anshuman Gupta
` (9 subsequent siblings)
11 siblings, 1 reply; 16+ messages in thread
From: Anshuman Gupta @ 2019-07-30 13:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Deak, jani.nikula, Nikula, Manna
Enables dc3co state in enable_dc module param
and adds dc3co enable mask to allowed_dc_mask and gen9_dc_mask.
Cc: Nikula, Jani <jani.nikula@intel.com>
Cc: Deak, Imre <imre.deak@intel.com>
Cc: Manna, Animesh <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 13 +++++++++++--
drivers/gpu/drm/i915/i915_params.c | 3 ++-
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index dd2a50b8ba0a..d9585d08e081 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -717,6 +717,10 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
u32 mask;
mask = DC_STATE_EN_UPTO_DC5;
+
+ if (INTEL_GEN(dev_priv) == 12)
+ mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
+ | DC_STATE_EN_DC9;
if (INTEL_GEN(dev_priv) >= 11)
mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
else if (IS_GEN9_LP(dev_priv))
@@ -3946,7 +3950,10 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
int requested_dc;
int max_dc;
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (INTEL_GEN(dev_priv) == 12) {
+ max_dc = 3;
+ mask = DC_STATE_EN_DC9;
+ } else if (INTEL_GEN(dev_priv) >= 11) {
max_dc = 2;
/*
* DC9 has a separate HW flow from the rest of the DC states,
@@ -3972,7 +3979,7 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
requested_dc = enable_dc;
} else if (enable_dc == -1) {
requested_dc = max_dc;
- } else if (enable_dc > max_dc && enable_dc <= 2) {
+ } else if (enable_dc > max_dc && enable_dc <= 3) {
DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
enable_dc, max_dc);
requested_dc = max_dc;
@@ -3981,6 +3988,8 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
requested_dc = max_dc;
}
+ if (requested_dc > 2)
+ mask |= DC_STATE_EN_DC3CO;
if (requested_dc > 1)
mask |= DC_STATE_EN_UPTO_DC6;
if (requested_dc > 0)
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 296452f9efe4..7a46dc957660 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -46,7 +46,8 @@ i915_param_named(modeset, int, 0400,
i915_param_named_unsafe(enable_dc, int, 0400,
"Enable power-saving display C-states. "
- "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6)");
+ "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6; "
+ "3=up to DC6 with DC3CO)");
i915_param_named_unsafe(enable_fbc, int, 0600,
"Enable frame buffer compression for power savings "
--
2.21.0
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^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v3 2/9] drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
2019-07-30 13:50 ` [PATCH v3 2/9] drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask Anshuman Gupta
@ 2019-08-01 4:35 ` Animesh Manna
0 siblings, 0 replies; 16+ messages in thread
From: Animesh Manna @ 2019-08-01 4:35 UTC (permalink / raw)
To: Anshuman Gupta, intel-gfx; +Cc: jani.nikula
Hi,
On 7/30/2019 7:20 PM, Anshuman Gupta wrote:
> diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
> index 296452f9efe4..7a46dc957660 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -46,7 +46,8 @@ i915_param_named(modeset, int, 0400,
>
> i915_param_named_unsafe(enable_dc, int, 0400,
> "Enable power-saving display C-states. "
> - "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6)");
> + "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6; "
> + "3=up to DC6 with DC3CO)");
What about DC3co with DC5? User do not an option to enable DC3co with
upto DC5 enabled.
Regards,
Animesh
>
> i915_param_named_unsafe(enable_fbc, int, 0600,
> "Enable frame buffer compression for power savings "
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^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 3/9] drm/i915/tgl: Add power well to enable DC3CO state
2019-07-30 13:50 [PATCH v3 0/9] DC3CO Support for TGL Anshuman Gupta
2019-07-30 13:50 ` [PATCH v3 1/9] drm/i915/tgl: Add DC3CO required register and bits Anshuman Gupta
2019-07-30 13:50 ` [PATCH v3 2/9] drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask Anshuman Gupta
@ 2019-07-30 13:50 ` Anshuman Gupta
2019-07-30 13:50 ` [PATCH v3 4/9] drm/i915/tgl: mutual exclusive handling for DC3CO and DC5/6 Anshuman Gupta
` (8 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Anshuman Gupta @ 2019-07-30 13:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Deak, jani.nikula, Vivi, Nikula, Manna
"DC3CO Off" power well inherits its power domains from
"DC Off" power well, these power domains will disallow
DC3CO when any external displays are connected and at
time of modeset and aux programming.
Renaming "DC Off" power well to "DC5 Off" power well.
v2: commit log improvement.
v3: Used intel_wait_for_register to wait for DC3CO exit. [Imre]
Used gen9_set_dc_state() to allow/disallow DC3CO. [Imre]
Moved transcoder psr2 exit line enablement from tgl_allow_dc3co()
to a appropriate place haswell_crtc_enable(). [Imre]
Changed the DC3CO power well enabled call back logic as
recommended in review comments. [Imre]
v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
Cc: Nikula, Jani <jani.nikula@intel.com>
Cc: Deak, Imre <imre.deak@intel.com>
Cc: Manna, Animesh <animesh.manna@intel.com>
Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
.../drm/i915/display/intel_display_power.c | 72 ++++++++++++++++++-
1 file changed, 71 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index d9585d08e081..1d2aced7f0e7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -791,6 +791,30 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
dev_priv->csr.dc_state = val & mask;
}
+static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
+{
+ gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
+}
+
+static void tgl_disallow_dc3co(struct drm_i915_private *dev_priv)
+{
+ u32 val;
+
+ val = I915_READ(DC_STATE_EN);
+ val &= ~DC_STATE_DC3CO_STATUS;
+ I915_WRITE(DC_STATE_EN, val);
+ gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ /*
+ * Delay of 200us DC3CO Exit time B.Spec 49196
+ * Every time it is not necessary that DC3CO exit will completed,
+ * when we disallow DC3CO.
+ * It might not have got chance to enter DC3CO earlier.
+ */
+ if (wait_for_us(I915_READ(DC_STATE_EN) &
+ DC_STATE_DC3CO_STATUS, 200))
+ DRM_INFO("Timed out waiting for dc3co exit\n");
+}
+
void bxt_enable_dc9(struct drm_i915_private *dev_priv)
{
assert_can_enable_dc9(dev_priv);
@@ -1007,6 +1031,33 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
gen9_enable_dc5(dev_priv);
}
+static void tgl_dc3co_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ tgl_disallow_dc3co(dev_priv);
+}
+
+static void tgl_dc3co_power_well_disable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ if (WARN_ON(!dev_priv->psr.sink_psr2_support))
+ return;
+
+ if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)
+ tgl_allow_dc3co(dev_priv);
+}
+
+static bool tgl_dc3co_power_well_enabled(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ /*
+ * Checking alone DC_STATE_EN is not enough as DC5 power well also
+ * allow/disallow DC3CO to make sure both are not enabled at same time
+ */
+ return ((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
+ (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
+}
+
static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
@@ -2611,6 +2662,12 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
BIT_ULL(POWER_DOMAIN_INIT))
+#define TGL_DISPLAY_DC3CO_OFF_POWER_DOMAINS ( \
+ TGL_PW_2_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
#define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
TGL_PW_2_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_MODESET) | \
@@ -2715,6 +2772,13 @@ static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
.is_enabled = gen9_dc_off_power_well_enabled,
};
+static const struct i915_power_well_ops tgl_dc3co_power_well_ops = {
+ .sync_hw = i9xx_power_well_sync_hw_noop,
+ .enable = tgl_dc3co_power_well_enable,
+ .disable = tgl_dc3co_power_well_disable,
+ .is_enabled = tgl_dc3co_power_well_enabled,
+};
+
static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
.enable = bxt_dpio_cmn_power_well_enable,
@@ -3626,11 +3690,17 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
},
{
- .name = "DC off",
+ .name = "DC5 off",
.domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
.id = DISP_PW_ID_NONE,
},
+ {
+ .name = "DC3CO off",
+ .domains = TGL_DISPLAY_DC3CO_OFF_POWER_DOMAINS,
+ .ops = &tgl_dc3co_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ },
{
.name = "power well 2",
.domains = TGL_PW_2_POWER_DOMAINS,
--
2.21.0
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 4/9] drm/i915/tgl: mutual exclusive handling for DC3CO and DC5/6
2019-07-30 13:50 [PATCH v3 0/9] DC3CO Support for TGL Anshuman Gupta
` (2 preceding siblings ...)
2019-07-30 13:50 ` [PATCH v3 3/9] drm/i915/tgl: Add power well to enable DC3CO state Anshuman Gupta
@ 2019-07-30 13:50 ` Anshuman Gupta
2019-07-30 13:50 ` [PATCH v3 5/9] drm/i915/tgl: Add helper function to prefer dc3co over dc5 Anshuman Gupta
` (7 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Anshuman Gupta @ 2019-07-30 13:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Deak, jani.nikula, Vivi, Nikula, Manna
As per B.Specs DC5 and DC6 not allowed when DC3CO is enabled
and DC3CO should be enabled only during VIDEO playback.
Which essentially means both can DC5 and DC3CO can not be
enabled at same time, it makes DC3CO and DC5 mutual exclusive.
Cc: Nikula, Jani <jani.nikula@intel.com>
Cc: Deak, Imre <imre.deak@intel.com>
Cc: Manna, Animesh <animesh.manna@intel.com>
Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 1d2aced7f0e7..64bf61a8b427 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1001,6 +1001,10 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ /* DC3CO and DC5/6 are mutually exclusive */
+ if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)
+ tgl_allow_dc3co(dev_priv);
+
dev_priv->display.get_cdclk(dev_priv, &cdclk_state);
/* Can't read out voltage_level so can't use intel_cdclk_changed() */
WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state));
@@ -1025,6 +1029,10 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
if (!dev_priv->csr.dmc_payload)
return;
+ /* DC3CO and DC5/6 are mutually exclusive */
+ if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)
+ tgl_disallow_dc3co(dev_priv);
+
if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
skl_enable_dc6(dev_priv);
else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
--
2.21.0
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 5/9] drm/i915/tgl: Add helper function to prefer dc3co over dc5
2019-07-30 13:50 [PATCH v3 0/9] DC3CO Support for TGL Anshuman Gupta
` (3 preceding siblings ...)
2019-07-30 13:50 ` [PATCH v3 4/9] drm/i915/tgl: mutual exclusive handling for DC3CO and DC5/6 Anshuman Gupta
@ 2019-07-30 13:50 ` Anshuman Gupta
2019-07-30 13:50 ` [PATCH v3 6/9] drm/i915/tgl: Add VIDEO power domain Anshuman Gupta
` (6 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Anshuman Gupta @ 2019-07-30 13:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Deak, jani.nikula, Nikula, Manna
If it is only edp display connected and it has psr2 capability,
then set prefer_dc3co flag to true, which will be used to
switch to dc3co. It also will be used to program DC3CO PSR2
transcoder early exitline event.
TODO: B. Specs says dc3co should be allow only in video playback
case, currently driver doesn't differentiate between video playback
and a normal flip.
User space will be the best to judge if it is VPB case
otherwise we need to have that intelligence in driver.
Cc: Nikula, Jani <jani.nikula@intel.com>
Cc: Deak, Imre <imre.deak@intel.com>
Cc: Manna, Animesh <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
.../drm/i915/display/intel_display_power.c | 96 +++++++++++++++++++
.../drm/i915/display/intel_display_power.h | 5 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 2 +-
drivers/gpu/drm/i915/intel_pm.h | 2 +
6 files changed, 110 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 51e4f6798a6b..34a1867cd803 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6448,6 +6448,9 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
if (WARN_ON(intel_crtc->active))
return;
+ /* Enable PSR2 transcoder exit line */
+ if (pipe_config->has_psr2 && dev_priv->csr.prefer_dc3co)
+ tgl_enable_psr2_transcoder_exitline(pipe_config);
intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
@@ -13686,6 +13689,8 @@ static int intel_atomic_check(struct drm_device *dev,
"[modeset]" : "[fastset]");
}
+ tgl_prefer_dc3co_over_dc5_check(dev_priv, state);
+
return 0;
fail:
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 64bf61a8b427..c44b3c54cbcb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -18,6 +18,7 @@
#include "intel_hotplug.h"
#include "intel_sideband.h"
#include "intel_tc.h"
+#include "intel_pm.h"
bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
enum i915_power_well_id power_well_id);
@@ -791,6 +792,101 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
dev_priv->csr.dc_state = val & mask;
}
+void tgl_enable_psr2_transcoder_exitline(struct intel_crtc_state *cstate)
+{
+ u32 linetime_us, val, exit_scanlines;
+ u32 crtc_vdisplay = cstate->base.adjusted_mode.crtc_vdisplay;
+ struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
+
+ if (WARN_ON(cstate->cpu_transcoder != TRANSCODER_A))
+ return;
+
+ linetime_us = fixed16_to_u32_round_up(intel_get_linetime_us(cstate));
+ if (WARN_ON(!linetime_us))
+ return;
+ /*
+ * DC3CO Exit time 200us B.Spec 49196
+ * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
+ * Exit line event need to program above calculated scan lines before
+ * next VBLANK.
+ */
+ exit_scanlines = DIV_ROUND_UP(200, linetime_us) + 1;
+ if (WARN_ON(exit_scanlines > crtc_vdisplay))
+ return;
+
+ exit_scanlines = crtc_vdisplay - exit_scanlines;
+ exit_scanlines <<= EXITLINE_SHIFT;
+ val = I915_READ(EXITLINE(cstate->cpu_transcoder));
+ val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
+ val |= exit_scanlines;
+ val |= EXITLINE_ENABLE;
+ I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
+}
+
+static bool tgl_is_only_edp_connected(struct intel_crtc_state *crtc_state)
+{
+ struct drm_atomic_state *state = crtc_state->base.state;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_connector *connector, *edp_connector = NULL;
+ struct drm_connector_state *connector_state;
+ int i;
+
+ for_each_new_connector_in_state(state, connector, connector_state, i) {
+ if (connector_state->crtc != &crtc->base)
+ continue;
+
+ if (connector->status == connector_status_connected &&
+ connector->connector_type != DRM_MODE_CONNECTOR_eDP)
+ return false;
+ else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP &&
+ connector->status == connector_status_connected)
+ edp_connector = connector;
+ }
+
+ if (edp_connector)
+ return true;
+
+ return false;
+}
+
+/*
+ * tgl_prefer_dc3co_over_dc5_check check whether it is worth to choose
+ * DC3CO over DC5. Currently it just check crtc psr2 capebilty and only
+ * edp display should be connected.
+ * TODO: Prefer DC3CO over DC5 only in video playback.
+ */
+void tgl_prefer_dc3co_over_dc5_check(struct drm_i915_private *dev_priv,
+ struct intel_atomic_state *state)
+{
+ struct intel_crtc_state *crtc_state;
+ struct intel_crtc *crtc;
+ int i;
+
+ dev_priv->csr.prefer_dc3co = false;
+
+ if (!IS_TIGERLAKE(dev_priv))
+ return;
+
+ if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
+ return;
+
+ for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
+ if (!crtc_state->has_psr2 && crtc_state->base.active) {
+ dev_priv->csr.prefer_dc3co = false;
+ return;
+ } else if (crtc_state->has_psr2) {
+ if (tgl_is_only_edp_connected(crtc_state) &&
+ crtc_state->base.active) {
+ dev_priv->csr.prefer_dc3co = true;
+ continue;
+ } else {
+ dev_priv->csr.prefer_dc3co = false;
+ return;
+ }
+ }
+ }
+}
+
static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
{
gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index e4d2c1ba24b0..7a61cab1eb31 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -12,6 +12,8 @@
struct drm_i915_private;
struct intel_encoder;
+struct intel_crtc_state;
+struct intel_atomic_state;
enum intel_display_power_domain {
POWER_DOMAIN_DISPLAY_CORE,
@@ -253,6 +255,9 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv);
void hsw_disable_pc8(struct drm_i915_private *dev_priv);
void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
+void tgl_prefer_dc3co_over_dc5_check(struct drm_i915_private *dev_priv,
+ struct intel_atomic_state *state);
+void tgl_enable_psr2_transcoder_exitline(struct intel_crtc_state *cstate);
const char *
intel_display_power_domain_str(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 59d4a1146039..04e454e51a5e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -360,6 +360,7 @@ struct intel_csr {
u32 dc_state;
u32 allowed_dc_mask;
intel_wakeref_t wakeref;
+ bool prefer_dc3co;
};
enum i915_cache_level {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 30399b245f07..78bf1070dc33 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4583,7 +4583,7 @@ skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency,
return ret;
}
-static uint_fixed_16_16_t
+uint_fixed_16_16_t
intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
{
u32 pixel_rate;
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index e3573e1e16e3..454e92c06dff 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -8,6 +8,7 @@
#include <linux/types.h>
+#include "i915_drv.h"
#include "i915_reg.h"
struct drm_device;
@@ -76,6 +77,7 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv, i915_reg_t reg);
u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, i915_reg_t reg);
u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
+uint_fixed_16_16_t intel_get_linetime_us(const struct intel_crtc_state *cstate);
unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
--
2.21.0
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 6/9] drm/i915/tgl: Add VIDEO power domain
2019-07-30 13:50 [PATCH v3 0/9] DC3CO Support for TGL Anshuman Gupta
` (4 preceding siblings ...)
2019-07-30 13:50 ` [PATCH v3 5/9] drm/i915/tgl: Add helper function to prefer dc3co over dc5 Anshuman Gupta
@ 2019-07-30 13:50 ` Anshuman Gupta
2019-07-30 13:50 ` [PATCH v3 7/9] drm/i915/tgl: DC3CO PSR2 helper Anshuman Gupta
` (5 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Anshuman Gupta @ 2019-07-30 13:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Deak, jani.nikula, Nikula, Manna
POWER_DOMAIN_VIDEO is a hook to "DC5 Off" power well,
which can disallow DC5/6 and allow DC3CO.
It will be used when there will be PSR2 idle frame while active
video playback.
Cc: Nikula, Jani <jani.nikula@intel.com>
Cc: Deak, Imre <imre.deak@intel.com>
Cc: Manna, Animesh <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 3 +++
drivers/gpu/drm/i915/display/intel_display_power.h | 1 +
drivers/gpu/drm/i915/i915_drv.h | 6 ++++++
3 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index c44b3c54cbcb..24df21e86a38 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -122,6 +122,8 @@ intel_display_power_domain_str(struct drm_i915_private *i915,
return "VGA";
case POWER_DOMAIN_AUDIO:
return "AUDIO";
+ case POWER_DOMAIN_VIDEO:
+ return "VIDEO";
case POWER_DOMAIN_AUX_A:
return "AUX_A";
case POWER_DOMAIN_AUX_B:
@@ -2774,6 +2776,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
#define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
TGL_PW_2_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_VIDEO) | \
BIT_ULL(POWER_DOMAIN_MODESET) | \
BIT_ULL(POWER_DOMAIN_AUX_A) | \
BIT_ULL(POWER_DOMAIN_INIT))
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 7a61cab1eb31..1dd221c4bee1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -66,6 +66,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_OTHER,
POWER_DOMAIN_VGA,
POWER_DOMAIN_AUDIO,
+ POWER_DOMAIN_VIDEO,
POWER_DOMAIN_AUX_A,
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_AUX_C,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 04e454e51a5e..8b7dbaa91a0d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -361,6 +361,12 @@ struct intel_csr {
u32 allowed_dc_mask;
intel_wakeref_t wakeref;
bool prefer_dc3co;
+ intel_wakeref_t dc5_wakeref;
+ /*
+ * Mutex to protect dc5_wakeref which make maintain proper
+ * power domain reference count of POWER_DOMAIN_VIDEO
+ */
+ struct mutex dc5_mutex;
};
enum i915_cache_level {
--
2.21.0
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 7/9] drm/i915/tgl: DC3CO PSR2 helper
2019-07-30 13:50 [PATCH v3 0/9] DC3CO Support for TGL Anshuman Gupta
` (5 preceding siblings ...)
2019-07-30 13:50 ` [PATCH v3 6/9] drm/i915/tgl: Add VIDEO power domain Anshuman Gupta
@ 2019-07-30 13:50 ` Anshuman Gupta
2019-07-31 7:11 ` kbuild test robot
2019-07-30 13:50 ` [PATCH v3 8/9] drm/i915/tgl: switch between dc3co and dc5 based on display idleness Anshuman Gupta
` (4 subsequent siblings)
11 siblings, 1 reply; 16+ messages in thread
From: Anshuman Gupta @ 2019-07-30 13:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Deak, jani.nikula, Nikula, Souza, Manna
Add dc3co helper functions to enable/disable psr2 deep sleep.
Disallow DC3CO state before PSR2 exit, it essentially does
that by putting a reference to POWER_DOMAIN_VIDEO before
PSR2 exit.
Cc: Nikula, Jani <jani.nikula@intel.com>
Cc: Deak, Imre <imre.deak@intel.com>
Cc: Manna, Animesh <animesh.manna@intel.com>
Cc: Souza, Jose <jose.souza@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 44 ++++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_psr.h | 2 ++
2 files changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 69d908e6a050..12765b1f9e33 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -533,6 +533,49 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
I915_WRITE(EDP_PSR2_CTL, val);
}
+void tgl_psr2_deep_sleep_disable(struct drm_i915_private *dev_priv)
+{
+ u32 val;
+ int idle_frames = 0;
+
+ idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT;
+ val = I915_READ(EDP_PSR2_CTL);
+ val &= ~EDP_PSR2_IDLE_FRAME_MASK;
+ val |= idle_frames;
+ I915_WRITE(EDP_PSR2_CTL, val);
+}
+
+void tgl_psr2_deep_sleep_enable(struct drm_i915_private *dev_priv)
+{
+ u32 val;
+ int idle_frames;
+
+ /*
+ * Let's use 6 as the minimum to cover all known cases including the
+ * off-by-one issue that HW has in some cases.
+ */
+ idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
+ idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
+ idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT;
+ val = I915_READ(EDP_PSR2_CTL);
+ val &= ~EDP_PSR2_IDLE_FRAME_MASK;
+ val |= idle_frames;
+ I915_WRITE(EDP_PSR2_CTL, val);
+}
+
+void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv)
+{
+ intel_wakeref_t wakeref __maybe_unused;
+
+ /* Before PSR2 exit disallow dc3co*/
+ mutex_lock(&dev_priv->csr.dc5_mutex);
+ wakeref = fetch_and_zero(&dev_priv->csr.dc5_wakeref);
+ if (wakeref)
+ intel_display_power_put(dev_priv, POWER_DOMAIN_VIDEO,
+ dev_priv->csr.dc5_wakeref);
+ mutex_unlock(&dev_priv->csr.dc5_mutex);
+}
+
static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state)
{
@@ -789,6 +832,7 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
}
if (dev_priv->psr.psr2_enabled) {
+ tgl_disallow_dc3co_on_psr2_exit(dev_priv);
val = I915_READ(EDP_PSR2_CTL);
WARN_ON(!(val & EDP_PSR2_ENABLE));
I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index dc818826f36d..6fb4c385489c 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -36,5 +36,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp);
int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
u32 *out_value);
bool intel_psr_enabled(struct intel_dp *intel_dp);
+void tgl_psr2_deep_sleep_disable(struct drm_i915_private *dev_priv);
+void tgl_psr2_deep_sleep_enable(struct drm_i915_private *dev_priv);
#endif /* __INTEL_PSR_H__ */
--
2.21.0
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^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v3 7/9] drm/i915/tgl: DC3CO PSR2 helper
2019-07-30 13:50 ` [PATCH v3 7/9] drm/i915/tgl: DC3CO PSR2 helper Anshuman Gupta
@ 2019-07-31 7:11 ` kbuild test robot
0 siblings, 0 replies; 16+ messages in thread
From: kbuild test robot @ 2019-07-31 7:11 UTC (permalink / raw)
To: Anshuman Gupta
Cc: jani.nikula, intel-gfx, Souza, Manna, Deak, kbuild-all, Nikula
Hi Anshuman,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[cannot apply to v5.3-rc2 next-20190730]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Anshuman-Gupta/DC3CO-Support-for-TGL/20190731-014749
base: git://anongit.freedesktop.org/drm-intel for-linux-next
reproduce:
# apt-get install sparse
# sparse version: v0.6.1-rc1-7-g2b96cd8-dirty
make ARCH=x86_64 allmodconfig
make C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__'
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
sparse warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/i915/display/intel_psr.c:566:6: sparse: sparse: symbol 'tgl_disallow_dc3co_on_psr2_exit' was not declared. Should it be static?
Please review and possibly fold the followup patch.
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 8/9] drm/i915/tgl: switch between dc3co and dc5 based on display idleness
2019-07-30 13:50 [PATCH v3 0/9] DC3CO Support for TGL Anshuman Gupta
` (6 preceding siblings ...)
2019-07-30 13:50 ` [PATCH v3 7/9] drm/i915/tgl: DC3CO PSR2 helper Anshuman Gupta
@ 2019-07-30 13:50 ` Anshuman Gupta
2019-07-30 13:50 ` [PATCH v3 9/9] drm/i915/tgl: Add DC3CO counter in i915_dmc_info Anshuman Gupta
` (3 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Anshuman Gupta @ 2019-07-30 13:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Deak, jani.nikula, Nikula, Manna
DC5 and DC6 not allowed when DC3CO feature is enabled.
DC5 and DC6 saves more power, but can't be entered during video
playback because there are not enough idle frames in a row to meet
most PSR2 panel deep sleep entry requirement typically 4 frames.
Hence switch to DC3CO when there is an update to display and switch
back to DC5 when display is idle. It is safer to allow DC5 after 6
idle frame, as PSR2 requires minimum 6 idle frame.
v2: calculated s/w state to switch over dc3co when there is an
update. [Imre]
used cancel_delayed_work_sync() in order to avoid any race
with already scheduled delayed work. [Imre]
v3: cancel_delayed_work_sync() may blocked the commit work.
Hence dropping it, dc5_idle_thread() checks the valid wakeref before
putting the reference count, which avoids any chances of dropping
a zero wakeref. [Imre (IRC)]
Cc: Nikula, Jani <jani.nikula@intel.com>
Cc: Deak, Imre <imre.deak@intel.com>
Cc: Manna, Animesh <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 4 ++
.../drm/i915/display/intel_display_power.c | 72 +++++++++++++++++++
.../drm/i915/display/intel_display_power.h | 5 ++
drivers/gpu/drm/i915/i915_drv.h | 1 +
4 files changed, 82 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 34a1867cd803..e8cc98757880 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14083,6 +14083,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
}
+
+ tgl_switch_to_dc3co_after_flip(dev_priv);
intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
/*
@@ -16157,6 +16159,7 @@ int intel_modeset_init(struct drm_device *dev)
init_llist_head(&dev_priv->atomic_helper.free_list);
INIT_WORK(&dev_priv->atomic_helper.free_work,
intel_atomic_helper_free_state_worker);
+ INIT_DELAYED_WORK(&dev_priv->csr.idle_work, intel_dc5_idle_thread);
intel_init_quirks(dev_priv);
@@ -17100,6 +17103,7 @@ void intel_modeset_driver_remove(struct drm_device *dev)
flush_workqueue(dev_priv->modeset_wq);
flush_work(&dev_priv->atomic_helper.free_work);
+ flush_delayed_work(&dev_priv->csr.idle_work);
WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
/*
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 24df21e86a38..c44bef4b907d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -19,6 +19,7 @@
#include "intel_sideband.h"
#include "intel_tc.h"
#include "intel_pm.h"
+#include "intel_psr.h"
bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
enum i915_power_well_id power_well_id);
@@ -825,6 +826,41 @@ void tgl_enable_psr2_transcoder_exitline(struct intel_crtc_state *cstate)
I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
}
+void tgl_switch_to_dc3co_after_flip(struct drm_i915_private *dev_priv)
+{
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *cstate;
+ u32 delay;
+
+ /* PSR2 is enabled and only edp is connected */
+ if (dev_priv->csr.prefer_dc3co && dev_priv->psr.psr2_enabled &&
+ dev_priv->psr.enabled) {
+ /*
+ * As every flip go through intel_atomic_commit, so tracking a
+ * atomic commit will be a hint for idle frames.
+ * Delayed work for 6 idle frames will be enough to allow dc6
+ * over dc3co for deepest power savings.
+ * At every atomic commit cancel the delayed work first,
+ * when delayed scheduled that means display has been idle
+ * for the 6 idle frame.
+ */
+ cancel_delayed_work(&dev_priv->csr.idle_work);
+ mutex_lock(&dev_priv->csr.dc5_mutex);
+ if (!dev_priv->csr.dc5_wakeref) {
+ dev_priv->csr.dc5_wakeref =
+ intel_display_power_get(dev_priv, POWER_DOMAIN_VIDEO);
+ tgl_psr2_deep_sleep_disable(dev_priv);
+ }
+ mutex_unlock(&dev_priv->csr.dc5_mutex);
+ crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
+ cstate = to_intel_crtc_state(crtc->base.state);
+
+ delay = DC5_REQ_IDLE_FRAMES * intel_get_frame_time_us(cstate);
+ schedule_delayed_work(&dev_priv->csr.idle_work,
+ usecs_to_jiffies(delay));
+ }
+}
+
static bool tgl_is_only_edp_connected(struct intel_crtc_state *crtc_state)
{
struct drm_atomic_state *state = crtc_state->base.state;
@@ -889,6 +925,20 @@ void tgl_prefer_dc3co_over_dc5_check(struct drm_i915_private *dev_priv,
}
}
+void intel_dc5_idle_thread(struct work_struct *work)
+{
+ intel_wakeref_t wakeref __maybe_unused;
+ struct drm_i915_private *dev_priv =
+ container_of(work, typeof(*dev_priv), csr.idle_work.work);
+
+ mutex_lock(&dev_priv->csr.dc5_mutex);
+ wakeref = fetch_and_zero(&dev_priv->csr.dc5_wakeref);
+ if (wakeref)
+ intel_display_power_put(dev_priv, POWER_DOMAIN_VIDEO, wakeref);
+ tgl_psr2_deep_sleep_enable(dev_priv);
+ mutex_unlock(&dev_priv->csr.dc5_mutex);
+}
+
static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
{
gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
@@ -1164,6 +1214,27 @@ static bool tgl_dc3co_power_well_enabled(struct drm_i915_private *dev_priv,
(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
}
+u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate)
+{
+ u32 pixel_rate, crtc_htotal, crtc_vtotal;
+ uint_fixed_16_16_t frametime_us;
+
+ if (!cstate || !cstate->base.active)
+ return 0;
+
+ pixel_rate = cstate->pixel_rate;
+
+ if (WARN_ON(pixel_rate == 0))
+ return 0;
+
+ crtc_htotal = cstate->base.adjusted_mode.crtc_htotal;
+ crtc_vtotal = cstate->base.adjusted_mode.crtc_vtotal;
+ frametime_us = div_fixed16(crtc_htotal * crtc_vtotal * 1000,
+ pixel_rate);
+
+ return fixed16_to_u32_round_up(frametime_us);
+}
+
static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
@@ -4234,6 +4305,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
BUILD_BUG_ON(POWER_DOMAIN_NUM > 64);
mutex_init(&power_domains->lock);
+ mutex_init(&dev_priv->csr.dc5_mutex);
INIT_DELAYED_WORK(&power_domains->async_put_work,
intel_display_power_put_async_work);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 1dd221c4bee1..43fb4bebba95 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -10,6 +10,8 @@
#include "intel_runtime_pm.h"
#include "i915_reg.h"
+#define DC5_REQ_IDLE_FRAMES 6
+
struct drm_i915_private;
struct intel_encoder;
struct intel_crtc_state;
@@ -237,6 +239,8 @@ struct i915_power_domains {
void skl_enable_dc6(struct drm_i915_private *dev_priv);
void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
+void intel_dc5_idle_thread(struct work_struct *work);
+u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate);
void bxt_enable_dc9(struct drm_i915_private *dev_priv);
void bxt_disable_dc9(struct drm_i915_private *dev_priv);
void gen9_enable_dc5(struct drm_i915_private *dev_priv);
@@ -259,6 +263,7 @@ void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
void tgl_prefer_dc3co_over_dc5_check(struct drm_i915_private *dev_priv,
struct intel_atomic_state *state);
void tgl_enable_psr2_transcoder_exitline(struct intel_crtc_state *cstate);
+void tgl_switch_to_dc3co_after_flip(struct drm_i915_private *dev_priv);
const char *
intel_display_power_domain_str(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8b7dbaa91a0d..0e07338de6db 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -359,6 +359,7 @@ struct intel_csr {
u32 mmiodata[20];
u32 dc_state;
u32 allowed_dc_mask;
+ struct delayed_work idle_work;
intel_wakeref_t wakeref;
bool prefer_dc3co;
intel_wakeref_t dc5_wakeref;
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v3 9/9] drm/i915/tgl: Add DC3CO counter in i915_dmc_info
2019-07-30 13:50 [PATCH v3 0/9] DC3CO Support for TGL Anshuman Gupta
` (7 preceding siblings ...)
2019-07-30 13:50 ` [PATCH v3 8/9] drm/i915/tgl: switch between dc3co and dc5 based on display idleness Anshuman Gupta
@ 2019-07-30 13:50 ` Anshuman Gupta
2019-07-30 14:23 ` ✗ Fi.CI.SPARSE: warning for DC3CO Support for TGL Patchwork
` (2 subsequent siblings)
11 siblings, 0 replies; 16+ messages in thread
From: Anshuman Gupta @ 2019-07-30 13:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Deak, jani.nikula, Nikula, Manna
Adding DC3CO counter in i915_dmc_info debugfs will be
useful for DC3CO validation.
DMC firmware uses DMC_DEBUG3 register as DC3CO counter
register on TGL, as per B.Specs DMC_DEBUG3 is general
purpose register.
Cc: Nikula, Jani <jani.nikula@intel.com>
Cc: Deak, Imre <imre.deak@intel.com>
Cc: Manna, Animesh <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 9 ++++++++-
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 24787bb48c9f..5a677d73b488 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2482,9 +2482,16 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
CSR_VERSION_MINOR(csr->version));
- if (WARN_ON(INTEL_GEN(dev_priv) > 11))
+ if (WARN_ON(INTEL_GEN(dev_priv) > 12))
goto out;
+ /*
+ * B.Spes specify that DMC_DEBUG3 is general debug register
+ * DMC folks uses this register for DC3CO counter for TGL
+ */
+ if (IS_TIGERLAKE(dev_priv))
+ seq_printf(m, "DC3CO count: %d\n", I915_READ(DMC_DEBUG3));
+
seq_printf(m, "DC3 -> DC5 count: %d\n",
I915_READ(IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
SKL_CSR_DC3_DC5_COUNT));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d42e95da5b14..cbcda37c29e4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7275,6 +7275,9 @@ enum {
#define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
#define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
+/* DMC DEBUG COUNTERS for TGL*/
+#define DMC_DEBUG3 _MMIO(0x101090) /*DC3CO debug counter*/
+
/* interrupts */
#define DE_MASTER_IRQ_CONTROL (1 << 31)
#define DE_SPRITEB_FLIP_DONE (1 << 29)
--
2.21.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread* ✗ Fi.CI.SPARSE: warning for DC3CO Support for TGL.
2019-07-30 13:50 [PATCH v3 0/9] DC3CO Support for TGL Anshuman Gupta
` (8 preceding siblings ...)
2019-07-30 13:50 ` [PATCH v3 9/9] drm/i915/tgl: Add DC3CO counter in i915_dmc_info Anshuman Gupta
@ 2019-07-30 14:23 ` Patchwork
2019-07-30 14:41 ` ✓ Fi.CI.BAT: success " Patchwork
2019-07-31 0:37 ` ✓ Fi.CI.IGT: " Patchwork
11 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2019-07-30 14:23 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
== Series Details ==
Series: DC3CO Support for TGL.
URL : https://patchwork.freedesktop.org/series/64436/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/tgl: Add DC3CO required register and bits
Okay!
Commit: drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
Okay!
Commit: drm/i915/tgl: Add power well to enable DC3CO state
Okay!
Commit: drm/i915/tgl: mutual exclusive handling for DC3CO and DC5/6
Okay!
Commit: drm/i915/tgl: Add helper function to prefer dc3co over dc5
Okay!
Commit: drm/i915/tgl: Add VIDEO power domain
Okay!
Commit: drm/i915/tgl: DC3CO PSR2 helper
+drivers/gpu/drm/i915/display/intel_psr.c:557:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_psr.c:558:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_psr.c:558:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_psr.c:566:6: warning: symbol 'tgl_disallow_dc3co_on_psr2_exit' was not declared. Should it be static?
Commit: drm/i915/tgl: switch between dc3co and dc5 based on display idleness
Okay!
Commit: drm/i915/tgl: Add DC3CO counter in i915_dmc_info
Okay!
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread* ✓ Fi.CI.BAT: success for DC3CO Support for TGL.
2019-07-30 13:50 [PATCH v3 0/9] DC3CO Support for TGL Anshuman Gupta
` (9 preceding siblings ...)
2019-07-30 14:23 ` ✗ Fi.CI.SPARSE: warning for DC3CO Support for TGL Patchwork
@ 2019-07-30 14:41 ` Patchwork
2019-07-31 0:37 ` ✓ Fi.CI.IGT: " Patchwork
11 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2019-07-30 14:41 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
== Series Details ==
Series: DC3CO Support for TGL.
URL : https://patchwork.freedesktop.org/series/64436/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6581 -> Patchwork_13801
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/
Known issues
------------
Here are the changes found in Patchwork_13801 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@gem_ctx_create@basic-files:
- {fi-icl-guc}: [INCOMPLETE][1] ([fdo#107713] / [fdo#109100]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/fi-icl-guc/igt@gem_ctx_create@basic-files.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/fi-icl-guc/igt@gem_ctx_create@basic-files.html
- fi-cml-u: [INCOMPLETE][3] ([fdo#110566]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/fi-cml-u/igt@gem_ctx_create@basic-files.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/fi-cml-u/igt@gem_ctx_create@basic-files.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: [INCOMPLETE][5] ([fdo#107718]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/fi-blb-e6850/igt@gem_exec_suspend@basic-s4-devices.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/fi-blb-e6850/igt@gem_exec_suspend@basic-s4-devices.html
* igt@i915_pm_rpm@module-reload:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/fi-icl-u3/igt@i915_pm_rpm@module-reload.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/fi-icl-u3/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live_reset:
- fi-icl-u2: [INCOMPLETE][9] ([fdo#107713]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/fi-icl-u2/igt@i915_selftest@live_reset.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/fi-icl-u2/igt@i915_selftest@live_reset.html
* igt@kms_chamelium@dp-edid-read:
- fi-cml-u2: [FAIL][11] ([fdo#106766]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/fi-cml-u2/igt@kms_chamelium@dp-edid-read.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/fi-cml-u2/igt@kms_chamelium@dp-edid-read.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][13] ([fdo#109485]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106766]: https://bugs.freedesktop.org/show_bug.cgi?id=106766
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
Participating hosts (55 -> 46)
------------------------------
Missing (9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-pnv-d510 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6581 -> Patchwork_13801
CI-20190529: 20190529
CI_DRM_6581: 53dee2a1faf99813437ddda7cf25a9adec5b01ce @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5115: 21be7a02ac8a8ff46b561c36a69e4dd5a0c2938b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13801: ca56010d7bee670d96e2f28da6075e1c597c795a @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
ca56010d7bee drm/i915/tgl: Add DC3CO counter in i915_dmc_info
461b05f267fa drm/i915/tgl: switch between dc3co and dc5 based on display idleness
5fc1f386cf41 drm/i915/tgl: DC3CO PSR2 helper
9adfc45ac7c2 drm/i915/tgl: Add VIDEO power domain
73880539ec99 drm/i915/tgl: Add helper function to prefer dc3co over dc5
b6e116dd1fab drm/i915/tgl: mutual exclusive handling for DC3CO and DC5/6
2125b106d92d drm/i915/tgl: Add power well to enable DC3CO state
eea9809c6185 drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
04c4a10612d6 drm/i915/tgl: Add DC3CO required register and bits
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread* ✓ Fi.CI.IGT: success for DC3CO Support for TGL.
2019-07-30 13:50 [PATCH v3 0/9] DC3CO Support for TGL Anshuman Gupta
` (10 preceding siblings ...)
2019-07-30 14:41 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-07-31 0:37 ` Patchwork
11 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2019-07-31 0:37 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
== Series Details ==
Series: DC3CO Support for TGL.
URL : https://patchwork.freedesktop.org/series/64436/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6581_full -> Patchwork_13801_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_13801_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110854])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/shard-iclb4/igt@gem_exec_balancer@smoke.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/shard-iclb7/igt@gem_exec_balancer@smoke.html
* igt@i915_pm_backlight@fade_with_suspend:
- shard-skl: [PASS][3] -> [INCOMPLETE][4] ([fdo#104108]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/shard-skl5/igt@i915_pm_backlight@fade_with_suspend.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/shard-skl3/igt@i915_pm_backlight@fade_with_suspend.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [PASS][5] -> [INCOMPLETE][6] ([fdo#103927])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/shard-apl5/igt@i915_suspend@sysfs-reader.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/shard-apl6/igt@i915_suspend@sysfs-reader.html
* igt@kms_busy@extended-modeset-hang-oldfb-render-c:
- shard-iclb: [PASS][7] -> [INCOMPLETE][8] ([fdo#107713])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/shard-iclb1/igt@kms_busy@extended-modeset-hang-oldfb-render-c.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/shard-iclb7/igt@kms_busy@extended-modeset-hang-oldfb-render-c.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-skl: [PASS][9] -> [INCOMPLETE][10] ([fdo#110741])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/shard-skl5/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/shard-skl6/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_cursor_crc@pipe-c-cursor-64x21-random:
- shard-hsw: [PASS][11] -> [INCOMPLETE][12] ([fdo#103540])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/shard-hsw1/igt@kms_cursor_crc@pipe-c-cursor-64x21-random.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/shard-hsw8/igt@kms_cursor_crc@pipe-c-cursor-64x21-random.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: [PASS][13] -> [FAIL][14] ([fdo#105363])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/shard-glk5/igt@kms_flip@flip-vs-expired-vblank.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/shard-glk8/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [PASS][15] -> [FAIL][16] ([fdo#105363])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite:
- shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +3 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [PASS][19] -> [DMESG-WARN][20] ([fdo#108566]) +2 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/shard-apl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([fdo#108566]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/shard-kbl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [fdo#110403])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109441]) +2 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/shard-iclb4/igt@kms_psr@psr2_cursor_plane_move.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][27] -> [FAIL][28] ([fdo#99912])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/shard-apl1/igt@kms_setmode@basic.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/shard-apl6/igt@kms_setmode@basic.html
#### Possible fixes ####
* igt@gem_softpin@noreloc-s3:
- shard-skl: [INCOMPLETE][29] ([fdo#104108]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/shard-skl7/igt@gem_softpin@noreloc-s3.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/shard-skl3/igt@gem_softpin@noreloc-s3.html
* igt@gem_tiled_swapping@non-threaded:
- shard-apl: [DMESG-WARN][31] ([fdo#108686]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/shard-apl8/igt@gem_tiled_swapping@non-threaded.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/shard-apl5/igt@gem_tiled_swapping@non-threaded.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [DMESG-WARN][33] ([fdo#108566]) -> [PASS][34] +5 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/shard-apl1/igt@gem_workarounds@suspend-resume-context.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/shard-apl8/igt@gem_workarounds@suspend-resume-context.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [DMESG-WARN][35] ([fdo#108566]) -> [PASS][36] +6 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/shard-kbl3/igt@gem_workarounds@suspend-resume-fd.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/shard-kbl7/igt@gem_workarounds@suspend-resume-fd.html
* igt@kms_cursor_crc@pipe-c-cursor-alpha-opaque:
- shard-kbl: [FAIL][37] ([fdo#103232]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/shard-kbl7/igt@kms_cursor_crc@pipe-c-cursor-alpha-opaque.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-alpha-opaque.html
* igt@kms_draw_crc@draw-method-xrgb8888-blt-untiled:
- shard-skl: [FAIL][39] ([fdo#103184] / [fdo#103232] / [fdo#108472]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/shard-skl8/igt@kms_draw_crc@draw-method-xrgb8888-blt-untiled.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/shard-skl3/igt@kms_draw_crc@draw-method-xrgb8888-blt-untiled.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [FAIL][41] ([fdo#105363]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/shard-skl8/igt@kms_flip@flip-vs-expired-vblank.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-suspend:
- shard-skl: [INCOMPLETE][43] ([fdo#109507]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/shard-skl7/igt@kms_flip@flip-vs-suspend.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/shard-skl8/igt@kms_flip@flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-iclb: [FAIL][45] ([fdo#103167]) -> [PASS][46] +3 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-snb: [DMESG-WARN][47] ([fdo#102365]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/shard-snb1/igt@kms_frontbuffer_tracking@fbc-suspend.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/shard-snb5/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt:
- shard-skl: [FAIL][49] ([fdo#103167]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/shard-skl8/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/shard-skl2/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [FAIL][51] ([fdo#108145]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [FAIL][53] ([fdo#103166]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-y.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][55] ([fdo#109441]) -> [PASS][56] +2 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/shard-iclb8/igt@kms_psr@psr2_sprite_plane_move.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_psr@suspend:
- shard-skl: [INCOMPLETE][57] ([fdo#108972]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/shard-skl2/igt@kms_psr@suspend.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/shard-skl7/igt@kms_psr@suspend.html
* igt@tools_test@tools_test:
- shard-iclb: [SKIP][59] ([fdo#109352]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6581/shard-iclb6/igt@tools_test@tools_test.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/shard-iclb1/igt@tools_test@tools_test.html
[fdo#102365]: https://bugs.freedesktop.org/show_bug.cgi?id=102365
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108472]: https://bugs.freedesktop.org/show_bug.cgi?id=108472
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#108972]: https://bugs.freedesktop.org/show_bug.cgi?id=108972
[fdo#109352]: https://bugs.freedesktop.org/show_bug.cgi?id=109352
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#110741]: https://bugs.freedesktop.org/show_bug.cgi?id=110741
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6581 -> Patchwork_13801
CI-20190529: 20190529
CI_DRM_6581: 53dee2a1faf99813437ddda7cf25a9adec5b01ce @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5115: 21be7a02ac8a8ff46b561c36a69e4dd5a0c2938b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13801: ca56010d7bee670d96e2f28da6075e1c597c795a @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13801/
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Intel-gfx@lists.freedesktop.org
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