From: "André Roth" <neolynx@gmail.com> To: linux-omap@vger.kernel.org Cc: Nishanth Menon <nm@ti.com>, Kevin Hilman <khilman@ti.com>, Thara Gopinath <thara@ti.com>, Shweta Gulati <shweta.gulati@ti.com>, linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/3] OMAP3: PM: Set/clear T2 bit for Smartreflex on TWL Date: Thu, 1 Aug 2019 03:28:21 +0200 [thread overview] Message-ID: <20190801012823.28730-2-neolynx@gmail.com> (raw) In-Reply-To: <20190801012823.28730-1-neolynx@gmail.com> From: Thara Gopinath <thara@ti.com> Voltage control on TWL can be done using VMODE/I2C1/I2C_SR. Since almost all platforms use I2C_SR on omap3, omap3_twl_init by default expects that OMAP's I2C_SR is plugged in to TWL's I2C and calls omap3_twl_set_sr_bit. On platforms where I2C_SR is not connected, the board files are expected to call omap3_twl_set_sr_bit(false) to ensure that I2C_SR path is not set for voltage control and prevent the default behavior of omap3_twl_init. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Thara Gopinath <thara@ti.com> Signed-off-by: Shweta Gulati <shweta.gulati@ti.com> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Kevin Hilman <khilman@ti.com> --- arch/arm/mach-omap2/omap_twl.c | 60 ++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c index 6787f1e72c6b..1dae906128c2 100644 --- a/arch/arm/mach-omap2/omap_twl.c +++ b/arch/arm/mach-omap2/omap_twl.c @@ -43,8 +43,15 @@ static bool is_offset_valid; static u8 smps_offset; +/* + * Flag to ensure Smartreflex bit in TWL + * being cleared in board file is not overwritten. + */ +static bool __initdata twl_sr_enable_autoinit; +#define TWL4030_DCDC_GLOBAL_CFG 0x06 #define REG_SMPS_OFFSET 0xE0 +#define SMARTREFLEX_ENABLE BIT(3) static unsigned long twl4030_vsel_to_uv(const u8 vsel) { @@ -241,6 +248,18 @@ int __init omap3_twl_init(void) if (!cpu_is_omap34xx()) return -ENODEV; + /* + * The smartreflex bit on twl4030 specifies if the setting of voltage + * is done over the I2C_SR path. Since this setting is independent of + * the actual usage of smartreflex AVS module, we enable TWL SR bit + * by default irrespective of whether smartreflex AVS module is enabled + * on the OMAP side or not. This is because without this bit enabled, + * the voltage scaling through vp forceupdate/bypass mechanism of + * voltage scaling will not function on TWL over I2C_SR. + */ + if (!twl_sr_enable_autoinit) + omap3_twl_set_sr_bit(true); + voltdm = voltdm_lookup("mpu_iva"); omap_voltage_register_pmic(voltdm, &omap3_mpu_pmic); @@ -249,3 +268,44 @@ int __init omap3_twl_init(void) return 0; } + +/** + * omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL + * @enable: enable SR mode in twl or not + * + * If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure + * voltage scaling through OMAP SR works. Else, the smartreflex bit + * on twl4030 is cleared as there are platforms which use OMAP3 and T2 but + * use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct + * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages, + * in those scenarios this bit is to be cleared (enable = false). + * + * Returns 0 on sucess, error is returned if I2C read/write fails. + */ +int __init omap3_twl_set_sr_bit(bool enable) +{ + u8 temp; + int ret; + if (twl_sr_enable_autoinit) + pr_warning("%s: unexpected multiple calls\n", __func__); + + ret = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &temp, + TWL4030_DCDC_GLOBAL_CFG); + if (ret) + goto err; + + if (enable) + temp |= SMARTREFLEX_ENABLE; + else + temp &= ~SMARTREFLEX_ENABLE; + + ret = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, temp, + TWL4030_DCDC_GLOBAL_CFG); + if (!ret) { + twl_sr_enable_autoinit = true; + return 0; + } +err: + pr_err("%s: Error access to TWL4030 (%d)\n", __func__, ret); + return ret; +} -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: "André Roth" <neolynx@gmail.com> To: linux-omap@vger.kernel.org Cc: Nishanth Menon <nm@ti.com>, Kevin Hilman <khilman@ti.com>, Thara Gopinath <thara@ti.com>, Shweta Gulati <shweta.gulati@ti.com>, linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/3] OMAP3: PM: Set/clear T2 bit for Smartreflex on TWL Date: Thu, 1 Aug 2019 03:28:21 +0200 [thread overview] Message-ID: <20190801012823.28730-2-neolynx@gmail.com> (raw) In-Reply-To: <20190801012823.28730-1-neolynx@gmail.com> From: Thara Gopinath <thara@ti.com> Voltage control on TWL can be done using VMODE/I2C1/I2C_SR. Since almost all platforms use I2C_SR on omap3, omap3_twl_init by default expects that OMAP's I2C_SR is plugged in to TWL's I2C and calls omap3_twl_set_sr_bit. On platforms where I2C_SR is not connected, the board files are expected to call omap3_twl_set_sr_bit(false) to ensure that I2C_SR path is not set for voltage control and prevent the default behavior of omap3_twl_init. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Thara Gopinath <thara@ti.com> Signed-off-by: Shweta Gulati <shweta.gulati@ti.com> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Kevin Hilman <khilman@ti.com> --- arch/arm/mach-omap2/omap_twl.c | 60 ++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c index 6787f1e72c6b..1dae906128c2 100644 --- a/arch/arm/mach-omap2/omap_twl.c +++ b/arch/arm/mach-omap2/omap_twl.c @@ -43,8 +43,15 @@ static bool is_offset_valid; static u8 smps_offset; +/* + * Flag to ensure Smartreflex bit in TWL + * being cleared in board file is not overwritten. + */ +static bool __initdata twl_sr_enable_autoinit; +#define TWL4030_DCDC_GLOBAL_CFG 0x06 #define REG_SMPS_OFFSET 0xE0 +#define SMARTREFLEX_ENABLE BIT(3) static unsigned long twl4030_vsel_to_uv(const u8 vsel) { @@ -241,6 +248,18 @@ int __init omap3_twl_init(void) if (!cpu_is_omap34xx()) return -ENODEV; + /* + * The smartreflex bit on twl4030 specifies if the setting of voltage + * is done over the I2C_SR path. Since this setting is independent of + * the actual usage of smartreflex AVS module, we enable TWL SR bit + * by default irrespective of whether smartreflex AVS module is enabled + * on the OMAP side or not. This is because without this bit enabled, + * the voltage scaling through vp forceupdate/bypass mechanism of + * voltage scaling will not function on TWL over I2C_SR. + */ + if (!twl_sr_enable_autoinit) + omap3_twl_set_sr_bit(true); + voltdm = voltdm_lookup("mpu_iva"); omap_voltage_register_pmic(voltdm, &omap3_mpu_pmic); @@ -249,3 +268,44 @@ int __init omap3_twl_init(void) return 0; } + +/** + * omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL + * @enable: enable SR mode in twl or not + * + * If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure + * voltage scaling through OMAP SR works. Else, the smartreflex bit + * on twl4030 is cleared as there are platforms which use OMAP3 and T2 but + * use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct + * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages, + * in those scenarios this bit is to be cleared (enable = false). + * + * Returns 0 on sucess, error is returned if I2C read/write fails. + */ +int __init omap3_twl_set_sr_bit(bool enable) +{ + u8 temp; + int ret; + if (twl_sr_enable_autoinit) + pr_warning("%s: unexpected multiple calls\n", __func__); + + ret = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &temp, + TWL4030_DCDC_GLOBAL_CFG); + if (ret) + goto err; + + if (enable) + temp |= SMARTREFLEX_ENABLE; + else + temp &= ~SMARTREFLEX_ENABLE; + + ret = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, temp, + TWL4030_DCDC_GLOBAL_CFG); + if (!ret) { + twl_sr_enable_autoinit = true; + return 0; + } +err: + pr_err("%s: Error access to TWL4030 (%d)\n", __func__, ret); + return ret; +} -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next parent reply other threads:[~2019-08-01 1:28 UTC|newest] Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top [not found] <20190801012823.28730-1-neolynx@gmail.com> 2019-08-01 1:28 ` André Roth [this message] 2019-08-01 1:28 ` [PATCH 1/3] OMAP3: PM: Set/clear T2 bit for Smartreflex on TWL André Roth 2019-09-12 18:59 ` Adam Ford 2019-09-12 21:09 ` Tony Lindgren 2019-09-13 15:11 ` Adam Ford [not found] ` <CAHCN7x+nD0J6KZYtfH+0ApQTPO5byO2obMkUwc9Uf4WubyRbTw@mail.gmail.com> [not found] ` <C04F49BA-1229-4E96-9FCF-4FC662D1DB11@goldelico.com> [not found] ` <CAHCN7x+Ye6sB_YqO0sAX1OJDw64B-qGS3pL545v3Xk5z914cwQ@mail.gmail.com> [not found] ` <0C1EF64E-B33C-4BFA-A7D3-471DD1B9EE86@goldelico.com> [not found] ` <515048DE-138D-4400-8168-F2B7D61F1005@goldelico.com> [not found] ` <CAHCN7xLPCX9rZ0+7KVBiA_bgZ6tg6VeCXqD-UXu+6iwpFMPVrA@mail.gmail.com> [not found] ` <7B3D1D77-3E8C-444F-90B9-6DF2641178B8@goldelico.com> [not found] ` <CAHCN7xLW58ggx3CpVL=HdCVHWo6D-MCTB91A_9rtSRoZQ+xJuQ@mail.gmail.com> 2019-09-07 7:37 ` [Letux-kernel] [RFC PATCH 0/3] Enable 1GHz support on omap36xx H. Nikolaus Schaller 2019-09-09 14:26 ` Adam Ford 2019-09-09 14:56 ` H. Nikolaus Schaller 2019-09-09 16:20 ` Adam Ford 2019-09-09 16:32 ` Adam Ford 2019-09-09 16:32 ` Tony Lindgren 2019-09-09 16:38 ` Adam Ford 2019-09-09 17:03 ` H. Nikolaus Schaller 2019-09-09 16:54 ` H. Nikolaus Schaller 2019-09-09 18:11 ` H. Nikolaus Schaller 2019-09-09 19:13 ` Adam Ford 2019-09-10 16:59 ` H. Nikolaus Schaller 2019-09-10 16:59 ` H. Nikolaus Schaller 2019-09-10 18:30 ` Adam Ford 2019-09-10 18:51 ` H. Nikolaus Schaller 2019-09-10 18:51 ` H. Nikolaus Schaller 2019-09-10 19:26 ` H. Nikolaus Schaller 2019-09-10 19:26 ` H. Nikolaus Schaller 2019-09-10 19:36 ` Adam Ford 2019-09-10 19:55 ` H. Nikolaus Schaller 2019-09-10 19:55 ` H. Nikolaus Schaller 2019-09-10 20:06 ` Adam Ford 2019-09-11 0:24 ` Adam Ford 2019-09-11 0:41 ` Adam Ford 2019-09-11 5:13 ` H. Nikolaus Schaller 2019-09-11 5:13 ` H. Nikolaus Schaller 2019-09-11 6:03 ` H. Nikolaus Schaller 2019-09-11 6:03 ` H. Nikolaus Schaller 2019-09-11 6:49 ` H. Nikolaus Schaller 2019-09-11 6:49 ` H. Nikolaus Schaller 2019-09-11 12:43 ` Adam Ford 2019-09-11 15:46 ` H. Nikolaus Schaller 2019-09-11 15:46 ` H. Nikolaus Schaller 2019-09-11 15:56 ` Adam Ford 2019-09-11 16:01 ` H. Nikolaus Schaller 2019-09-11 16:01 ` H. Nikolaus Schaller 2019-09-11 17:43 ` H. Nikolaus Schaller 2019-09-11 17:43 ` H. Nikolaus Schaller 2019-09-11 17:49 ` Adam Ford 2019-09-12 13:58 ` Adam Ford 2019-09-12 18:52 ` Adam Ford [not found] <20190801010450.27863-1-neolynx@gmail.com> 2019-08-01 1:04 ` [PATCH 1/3] OMAP3: PM: Set/clear T2 bit for Smartreflex on TWL André Roth
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