* [PATCH 01/39] drm/i915/tgl: do not use DDIC
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-16 8:04 ` [PATCH 02/39] drm/i915/psr: Make PSR registers relative to transcoders Lucas De Marchi
` (41 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx
On both A0 and A2 machines DDIC is not working. VBT reports the port as
being present. In BIOS configuration it seems to be disabled and can't
be enabled.
The symptom we have is while enabling the combo phy, PORT_COMP_DW*
return 0xFFFFFFFF, which is invalid per register definition.
During initialization we check what phys are not yet enabled by reading
PHY_MISC_C and try to enable it by toggling the "DE to IO Comp Pwr Down"
bit. But after that any read to the PORT_COMP_DW* returns invalid
results. To me it looks like it's powered down and we can't bring it up.
This papers over the following warnings:
[56997.634353] Missing case (val == 4294967295)
[56997.639241] WARNING: CPU: 5 PID: 768 at drivers/gpu/drm/i915/display/intel_combo_phy.c:54 cnl_get_procmon_ref_values+0xc9/0xf0 [i915]
[56997.639808] Modules linked in: i915(+) prime_numbers x86_pkg_temp_thermal coretemp kvm_intel kvm irqbypass crct10dif_pclmul crc32_pclmul ghash_clmulni_intel e1000e [last unloaded: prime_numbers]
[56997.639808] CPU: 5 PID: 768 Comm: insmod Tainted: G U W 5.2.0-demarchi+ #65
[56997.639808] Hardware name: Intel Corporation Tiger Lake Client Platform/TigerLake U DDR4 SODIMM RVP, BIOS TGLSFWI1.R00.2252.A03.1906270154 06/27/2019
[56997.639808] RIP: 0010:cnl_get_procmon_ref_values+0xc9/0xf0 [i915]
[56997.639808] Code: 2c a0 85 c9 74 e0 81 f9 00 00 00 01 75 09 48 c7 c0 0c a4 2c a0 eb cf 48 c7 c6 3c 3a 31 a0 48 c7 c7 40 3a 31 a0 e8 6b 4d ea e0 <0f> 0b 48 c7 c0 00 a4 2c a0 eb b1 48 c7 c0 24 a4 2
c a0 eb a8 e8 be
[56997.639808] RSP: 0018:ffffc9000068f8a8 EFLAGS: 00010286
[56997.639808] RAX: 0000000000000000 RBX: ffff88848fa90000 RCX: 0000000000000000
[56997.639808] RDX: ffff8884a08b5ef8 RSI: ffff8884a08a6658 RDI: 00000000ffffffff
[56997.639808] RBP: 0000000000000002 R08: 0000000000000000 R09: 0000000000000000
[56997.639808] R10: 0000000000000000 R11: 0000000000000000 R12: ffff88848fa90000
[56997.639808] R13: 0000000000000000 R14: 0000000000000002 R15: 0006c00000162000
[56997.639808] FS: 00007f61ca3d12c0(0000) GS:ffff8884a0880000(0000) knlGS:0000000000000000
[56997.639808] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[56997.639808] CR2: 00007f71be6a92c0 CR3: 0000000494750006 CR4: 0000000000760ee0
[56997.639808] PKRU: 55555554
[56997.639808] Call Trace:
[56997.639808] cnl_verify_procmon_ref_values+0x36/0xf0 [i915]
[56997.639808] ? rcu_read_lock_sched_held+0x6f/0x80
[56997.639808] ? gen11_fwtable_read32+0x257/0x290 [i915]
[56997.639808] icl_combo_phy_verify_state.part.0+0x22/0xa0 [i915]
[56997.639808] intel_combo_phy_init+0x17e/0x3e0 [i915]
[56997.639808] ? icl_display_core_init+0x2c/0x1a0 [i915]
[56997.639808] ? _raw_spin_unlock_irqrestore+0x4c/0x60
[56997.639808] icl_display_core_init+0x34/0x1a0 [i915]
[56997.639808] intel_power_domains_init_hw+0x200/0x570 [i915]
[56997.639808] i915_driver_probe+0x103b/0x17e0 [i915]
[56997.639808] ? printk+0x53/0x6a
[56997.639808] i915_pci_probe+0x3b/0x190 [i915]
Feedback from people responsible for VBT:
We got a confirmation that DDI-C is not pinned out in the
packaging/disabled, probably this is the reason the Combo PHY C
registers are not accessible. Once the spec is updated, we will remap
DDI-C to No Display type and will hide configuration of DDI-C, so that
it is not configurable by the user.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5b733e38eae3..6c6a5a5f41bb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6683,7 +6683,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
if (phy == PHY_NONE)
return false;
- if (IS_ELKHARTLAKE(dev_priv) || INTEL_GEN(dev_priv) >= 12)
+ if (IS_ELKHARTLAKE(dev_priv))
return phy <= PHY_C;
if (INTEL_GEN(dev_priv) >= 11)
@@ -15317,7 +15317,6 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
/* TODO: initialize TC ports as well */
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
- intel_ddi_init(dev_priv, PORT_C);
icl_dsi_init(dev_priv);
} else if (IS_ELKHARTLAKE(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 02/39] drm/i915/psr: Make PSR registers relative to transcoders
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
2019-08-16 8:04 ` [PATCH 01/39] drm/i915/tgl: do not use DDIC Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-16 8:04 ` [PATCH 03/39] drm/i915: Add transcoder restriction to PSR2 Lucas De Marchi
` (40 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan
From: José Roberto de Souza <jose.souza@intel.com>
PSR registers are a mess, some have the full address while others just
have the additional offset from psr_mmio_base.
For BDW+ psr_mmio_base is nothing more than TRANSCODER_EDP_OFFSET +
0x800 and using it makes more difficult for people with an PSR
register address or PSR register name from from BSpec as i915 also
don't match the BSpec names.
For HSW psr_mmio_base is _DDI_BUF_CTL_A + 0x800 and PSR registers are
only available in DDIA.
Other reason to make relative to transcoder is that since BDW every
transcoder have PSR registers, so in theory it should be possible to
have PSR enabled in a non-eDP transcoder.
So for BDW+ we can use _TRANS2() to get the register offset of any
PSR register in any transcoder while for HSW we have _HSW_PSR_ADJ
that will calculate the register offset for the single PSR instance,
noting that we are already guarded about trying to enable PSR in other
port than DDIA on HSW by the 'if (dig_port->base.port != PORT_A)' in
intel_psr_compute_config(), this check should only be valid for HSW
and will be changed in future.
PSR2 registers and PSR_EVENT was added after Haswell so that is why
_PSR_ADJ() is not used in some macros.
The only registers that can not be relative to transcoder are
PSR_IMR and PSR_IIR that are not relative to anything, so keeping it
hardcoded.
Also removing BDW_EDP_PSR_BASE from GVT because it is not used as it
is the only PSR register that GVT have.
v5:
- Macros changed to be more explicit about HSW (Dhinakaran)
- Squashed with the patch that added the tran parameter to the
macros (Dhinakaran)
v6:
- Checking for interruption errors after module reload in the
transcoder that will be used (Dhinakaran)
- Using lowercase to the registers offsets
v7:
- Removing IS_HASWELL() from registers macros(Jani)
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 104 +++++++++++++----------
drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 18 ++--
drivers/gpu/drm/i915/i915_drv.h | 5 +-
drivers/gpu/drm/i915/i915_reg.h | 57 +++++++++----
5 files changed, 113 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index ad7044ea1efe..795e25d45357 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -390,7 +390,7 @@ static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
BUILD_BUG_ON(sizeof(aux_msg) > 20);
for (i = 0; i < sizeof(aux_msg); i += 4)
- I915_WRITE(EDP_PSR_AUX_DATA(i >> 2),
+ I915_WRITE(EDP_PSR_AUX_DATA(dev_priv->psr.transcoder, i >> 2),
intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
@@ -401,7 +401,7 @@ static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
/* Select only valid bits for SRD_AUX_CTL */
aux_ctl &= psr_aux_mask;
- I915_WRITE(EDP_PSR_AUX_CTL, aux_ctl);
+ I915_WRITE(EDP_PSR_AUX_CTL(dev_priv->psr.transcoder), aux_ctl);
}
static void intel_psr_enable_sink(struct intel_dp *intel_dp)
@@ -491,8 +491,9 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
if (INTEL_GEN(dev_priv) >= 8)
val |= EDP_PSR_CRC_ENABLE;
- val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK;
- I915_WRITE(EDP_PSR_CTL, val);
+ val |= (I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder)) &
+ EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK);
+ I915_WRITE(EDP_PSR_CTL(dev_priv->psr.transcoder), val);
}
static void hsw_activate_psr2(struct intel_dp *intel_dp)
@@ -528,9 +529,9 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
* PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is
* recommending keep this bit unset while PSR2 is enabled.
*/
- I915_WRITE(EDP_PSR_CTL, 0);
+ I915_WRITE(EDP_PSR_CTL(dev_priv->psr.transcoder), 0);
- I915_WRITE(EDP_PSR2_CTL, val);
+ I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val);
}
static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
@@ -606,10 +607,9 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
/*
* HSW spec explicitly says PSR is tied to port A.
- * BDW+ platforms with DDI implementation of PSR have different
- * PSR registers per transcoder and we only implement transcoder EDP
- * ones. Since by Display design transcoder EDP is tied to port A
- * we can safely escape based on the port A.
+ * BDW+ platforms have a instance of PSR registers per transcoder but
+ * for now it only supports one instance of PSR, so lets keep it
+ * hardcoded to PORT_A
*/
if (dig_port->base.port != PORT_A) {
DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
@@ -649,8 +649,8 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
if (INTEL_GEN(dev_priv) >= 9)
- WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
- WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
+ WARN_ON(I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)) & EDP_PSR2_ENABLE);
+ WARN_ON(I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder)) & EDP_PSR_ENABLE);
WARN_ON(dev_priv->psr.active);
lockdep_assert_held(&dev_priv->psr.lock);
@@ -720,19 +720,37 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
if (INTEL_GEN(dev_priv) < 11)
mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
- I915_WRITE(EDP_PSR_DEBUG, mask);
+ I915_WRITE(EDP_PSR_DEBUG(dev_priv->psr.transcoder), mask);
}
static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state)
{
struct intel_dp *intel_dp = dev_priv->psr.dp;
+ u32 val;
WARN_ON(dev_priv->psr.enabled);
dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state);
dev_priv->psr.busy_frontbuffer_bits = 0;
dev_priv->psr.pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
+ dev_priv->psr.transcoder = crtc_state->cpu_transcoder;
+
+ /*
+ * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
+ * will still keep the error set even after the reset done in the
+ * irq_preinstall and irq_uninstall hooks.
+ * And enabling in this situation cause the screen to freeze in the
+ * first time that PSR HW tries to activate so lets keep PSR disabled
+ * to avoid any rendering problems.
+ */
+ val = I915_READ(EDP_PSR_IIR);
+ val &= EDP_PSR_ERROR(edp_psr_shift(dev_priv->psr.transcoder));
+ if (val) {
+ dev_priv->psr.sink_not_reliable = true;
+ DRM_DEBUG_KMS("PSR interruption error set, not enabling PSR\n");
+ return;
+ }
DRM_DEBUG_KMS("Enabling PSR%s\n",
dev_priv->psr.psr2_enabled ? "2" : "1");
@@ -782,20 +800,27 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
u32 val;
if (!dev_priv->psr.active) {
- if (INTEL_GEN(dev_priv) >= 9)
- WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
- WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
+ if (INTEL_GEN(dev_priv) >= 9) {
+ val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder));
+ WARN_ON(val & EDP_PSR2_ENABLE);
+ }
+
+ val = I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder));
+ WARN_ON(val & EDP_PSR_ENABLE);
+
return;
}
if (dev_priv->psr.psr2_enabled) {
- val = I915_READ(EDP_PSR2_CTL);
+ val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder));
WARN_ON(!(val & EDP_PSR2_ENABLE));
- I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
+ val &= ~EDP_PSR2_ENABLE;
+ I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val);
} else {
- val = I915_READ(EDP_PSR_CTL);
+ val = I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder));
WARN_ON(!(val & EDP_PSR_ENABLE));
- I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
+ val &= ~EDP_PSR_ENABLE;
+ I915_WRITE(EDP_PSR_CTL(dev_priv->psr.transcoder), val);
}
dev_priv->psr.active = false;
}
@@ -817,10 +842,10 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
intel_psr_exit(dev_priv);
if (dev_priv->psr.psr2_enabled) {
- psr_status = EDP_PSR2_STATUS;
+ psr_status = EDP_PSR2_STATUS(dev_priv->psr.transcoder);
psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
} else {
- psr_status = EDP_PSR_STATUS;
+ psr_status = EDP_PSR_STATUS(dev_priv->psr.transcoder);
psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
}
@@ -963,7 +988,8 @@ int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
* defensive enough to cover everything.
*/
- return __intel_wait_for_register(&dev_priv->uncore, EDP_PSR_STATUS,
+ return __intel_wait_for_register(&dev_priv->uncore,
+ EDP_PSR_STATUS(dev_priv->psr.transcoder),
EDP_PSR_STATUS_STATE_MASK,
EDP_PSR_STATUS_STATE_IDLE, 2, 50,
out_value);
@@ -979,10 +1005,10 @@ static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv)
return false;
if (dev_priv->psr.psr2_enabled) {
- reg = EDP_PSR2_STATUS;
+ reg = EDP_PSR2_STATUS(dev_priv->psr.transcoder);
mask = EDP_PSR2_STATUS_STATE_MASK;
} else {
- reg = EDP_PSR_STATUS;
+ reg = EDP_PSR_STATUS(dev_priv->psr.transcoder);
mask = EDP_PSR_STATUS_STATE_MASK;
}
@@ -1208,36 +1234,24 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
*/
void intel_psr_init(struct drm_i915_private *dev_priv)
{
- u32 val;
-
if (!HAS_PSR(dev_priv))
return;
- dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
- HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;
-
if (!dev_priv->psr.sink_support)
return;
+ if (IS_HASWELL(dev_priv))
+ /*
+ * HSW don't have PSR registers on the same space as transcoder
+ * so set this to a value that when subtract to the register
+ * in transcoder space results in the right offset for HSW
+ */
+ dev_priv->hsw_psr_mmio_adjust = _SRD_CTL_EDP - _HSW_EDP_PSR_BASE;
+
if (i915_modparams.enable_psr == -1)
if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable)
i915_modparams.enable_psr = 0;
- /*
- * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
- * will still keep the error set even after the reset done in the
- * irq_preinstall and irq_uninstall hooks.
- * And enabling in this situation cause the screen to freeze in the
- * first time that PSR HW tries to activate so lets keep PSR disabled
- * to avoid any rendering problems.
- */
- val = I915_READ(EDP_PSR_IIR);
- val &= EDP_PSR_ERROR(edp_psr_shift(TRANSCODER_EDP));
- if (val) {
- DRM_DEBUG_KMS("PSR interruption error set\n");
- dev_priv->psr.sink_not_reliable = true;
- }
-
/* Set link_standby x link_off defaults */
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
/* HSW and BDW require workarounds that we don't implement. */
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 25f78196b964..45a9124e53b6 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2796,7 +2796,7 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
MMIO_D(WM_MISC, D_BDW);
- MMIO_D(_MMIO(BDW_EDP_PSR_BASE), D_BDW);
+ MMIO_D(_MMIO(_SRD_CTL_EDP), D_BDW);
MMIO_D(_MMIO(0x6671c), D_BDW_PLUS);
MMIO_D(_MMIO(0x66c00), D_BDW_PLUS);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index ef4f84e060ee..ce3e0f0de148 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2136,7 +2136,7 @@ psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
"BUF_ON",
"TG_ON"
};
- val = I915_READ(EDP_PSR2_STATUS);
+ val = I915_READ(EDP_PSR2_STATUS(dev_priv->psr.transcoder));
status_val = (val & EDP_PSR2_STATUS_STATE_MASK) >>
EDP_PSR2_STATUS_STATE_SHIFT;
if (status_val < ARRAY_SIZE(live_status))
@@ -2152,7 +2152,7 @@ psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
"SRDOFFACK",
"SRDENT_ON",
};
- val = I915_READ(EDP_PSR_STATUS);
+ val = I915_READ(EDP_PSR_STATUS(dev_priv->psr.transcoder));
status_val = (val & EDP_PSR_STATUS_STATE_MASK) >>
EDP_PSR_STATUS_STATE_SHIFT;
if (status_val < ARRAY_SIZE(live_status))
@@ -2195,10 +2195,10 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
goto unlock;
if (psr->psr2_enabled) {
- val = I915_READ(EDP_PSR2_CTL);
+ val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder));
enabled = val & EDP_PSR2_ENABLE;
} else {
- val = I915_READ(EDP_PSR_CTL);
+ val = I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder));
enabled = val & EDP_PSR_ENABLE;
}
seq_printf(m, "Source PSR ctl: %s [0x%08x]\n",
@@ -2211,7 +2211,8 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
* SKL+ Perf counter is reset to 0 everytime DC state is entered
*/
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
- val = I915_READ(EDP_PSR_PERF_CNT) & EDP_PSR_PERF_CNT_MASK;
+ val = I915_READ(EDP_PSR_PERF_CNT(dev_priv->psr.transcoder));
+ val &= EDP_PSR_PERF_CNT_MASK;
seq_printf(m, "Performance counter: %u\n", val);
}
@@ -2229,8 +2230,11 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
* Reading all 3 registers before hand to minimize crossing a
* frame boundary between register reads
*/
- for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3)
- su_frames_val[frame / 3] = I915_READ(PSR2_SU_STATUS(frame));
+ for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) {
+ val = I915_READ(PSR2_SU_STATUS(dev_priv->psr.transcoder,
+ frame));
+ su_frames_val[frame / 3] = val;
+ }
seq_puts(m, "Frame:\tPSR2 SU blocks:\n");
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c4406a60f3e4..8d57e9680c99 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -478,6 +478,7 @@ struct i915_psr {
bool enabled;
struct intel_dp *dp;
enum pipe pipe;
+ enum transcoder transcoder;
bool active;
struct work_struct work;
unsigned busy_frontbuffer_bits;
@@ -1391,11 +1392,11 @@ struct drm_i915_private {
*/
u32 gpio_mmio_base;
+ u32 hsw_psr_mmio_adjust;
+
/* MMIO base address for MIPI regs */
u32 mipi_mmio_base;
- u32 psr_mmio_base;
-
u32 pps_mmio_base;
wait_queue_head_t gmbus_wait_queue;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2b7ccebf6550..7da44ae86320 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4250,10 +4250,17 @@ enum {
#define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
#define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
-/* HSW+ eDP PSR registers */
-#define HSW_EDP_PSR_BASE 0x64800
-#define BDW_EDP_PSR_BASE 0x6f800
-#define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0)
+/*
+ * HSW+ eDP PSR registers
+ *
+ * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one
+ * instance of it
+ */
+#define _HSW_EDP_PSR_BASE 0x64800
+#define _SRD_CTL_A 0x60800
+#define _SRD_CTL_EDP 0x6f800
+#define _PSR_ADJ(tran, reg) (_TRANS2(tran, reg) - dev_priv->hsw_psr_mmio_adjust)
+#define EDP_PSR_CTL(tran) _MMIO(_PSR_ADJ(tran, _SRD_CTL_A))
#define EDP_PSR_ENABLE (1 << 31)
#define BDW_PSR_SINGLE_FRAME (1 << 30)
#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29) /* SW can't modify */
@@ -4290,16 +4297,22 @@ enum {
#define EDP_PSR_TRANSCODER_A_SHIFT 8
#define EDP_PSR_TRANSCODER_EDP_SHIFT 0
-#define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10)
+#define _SRD_AUX_CTL_A 0x60810
+#define _SRD_AUX_CTL_EDP 0x6f810
+#define EDP_PSR_AUX_CTL(tran) _MMIO(_PSR_ADJ(tran, _SRD_AUX_CTL_A))
#define EDP_PSR_AUX_CTL_TIME_OUT_MASK (3 << 26)
#define EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
#define EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16)
#define EDP_PSR_AUX_CTL_ERROR_INTERRUPT (1 << 11)
#define EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff)
-#define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
+#define _SRD_AUX_DATA_A 0x60814
+#define _SRD_AUX_DATA_EDP 0x6f814
+#define EDP_PSR_AUX_DATA(tran, i) _MMIO(_PSR_ADJ(tran, _SRD_AUX_DATA_A) + (i) + 4) /* 5 registers */
-#define EDP_PSR_STATUS _MMIO(dev_priv->psr_mmio_base + 0x40)
+#define _SRD_STATUS_A 0x60840
+#define _SRD_STATUS_EDP 0x6f840
+#define EDP_PSR_STATUS(tran) _MMIO(_PSR_ADJ(tran, _SRD_STATUS_A))
#define EDP_PSR_STATUS_STATE_MASK (7 << 29)
#define EDP_PSR_STATUS_STATE_SHIFT 29
#define EDP_PSR_STATUS_STATE_IDLE (0 << 29)
@@ -4324,10 +4337,15 @@ enum {
#define EDP_PSR_STATUS_SENDING_TP1 (1 << 4)
#define EDP_PSR_STATUS_IDLE_MASK 0xf
-#define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44)
+#define _SRD_PERF_CNT_A 0x60844
+#define _SRD_PERF_CNT_EDP 0x6f844
+#define EDP_PSR_PERF_CNT(tran) _MMIO(_PSR_ADJ(tran, _SRD_PERF_CNT_A))
#define EDP_PSR_PERF_CNT_MASK 0xffffff
-#define EDP_PSR_DEBUG _MMIO(dev_priv->psr_mmio_base + 0x60) /* PSR_MASK on SKL+ */
+/* PSR_MASK on SKL+ */
+#define _SRD_DEBUG_A 0x60860
+#define _SRD_DEBUG_EDP 0x6f860
+#define EDP_PSR_DEBUG(tran) _MMIO(_PSR_ADJ(tran, _SRD_DEBUG_A))
#define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28)
#define EDP_PSR_DEBUG_MASK_LPSP (1 << 27)
#define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26)
@@ -4335,7 +4353,9 @@ enum {
#define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */
#define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */
-#define EDP_PSR2_CTL _MMIO(0x6f900)
+#define _PSR2_CTL_A 0x60900
+#define _PSR2_CTL_EDP 0x6f900
+#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A)
#define EDP_PSR2_ENABLE (1 << 31)
#define EDP_SU_TRACK_ENABLE (1 << 30)
#define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */
@@ -4357,8 +4377,8 @@ enum {
#define _PSR_EVENT_TRANS_B 0x61848
#define _PSR_EVENT_TRANS_C 0x62848
#define _PSR_EVENT_TRANS_D 0x63848
-#define _PSR_EVENT_TRANS_EDP 0x6F848
-#define PSR_EVENT(trans) _MMIO_TRANS2(trans, _PSR_EVENT_TRANS_A)
+#define _PSR_EVENT_TRANS_EDP 0x6f848
+#define PSR_EVENT(tran) _MMIO_TRANS2(tran, _PSR_EVENT_TRANS_A)
#define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17)
#define PSR_EVENT_PSR2_DISABLED (1 << 16)
#define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15)
@@ -4376,15 +4396,16 @@ enum {
#define PSR_EVENT_LPSP_MODE_EXIT (1 << 1)
#define PSR_EVENT_PSR_DISABLE (1 << 0)
-#define EDP_PSR2_STATUS _MMIO(0x6f940)
+#define _PSR2_STATUS_A 0x60940
+#define _PSR2_STATUS_EDP 0x6f940
+#define EDP_PSR2_STATUS(tran) _MMIO_TRANS2(tran, _PSR2_STATUS_A)
#define EDP_PSR2_STATUS_STATE_MASK (0xf << 28)
#define EDP_PSR2_STATUS_STATE_SHIFT 28
-#define _PSR2_SU_STATUS_0 0x6F914
-#define _PSR2_SU_STATUS_1 0x6F918
-#define _PSR2_SU_STATUS_2 0x6F91C
-#define _PSR2_SU_STATUS(index) _MMIO(_PICK_EVEN((index), _PSR2_SU_STATUS_0, _PSR2_SU_STATUS_1))
-#define PSR2_SU_STATUS(frame) (_PSR2_SU_STATUS((frame) / 3))
+#define _PSR2_SU_STATUS_A 0x60914
+#define _PSR2_SU_STATUS_EDP 0x6f914
+#define _PSR2_SU_STATUS(tran, index) _MMIO(_TRANS2(tran, _PSR2_SU_STATUS_A) + (index) * 4)
+#define PSR2_SU_STATUS(tran, frame) (_PSR2_SU_STATUS(tran, (frame) / 3))
#define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10)
#define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
#define PSR2_SU_STATUS_FRAMES 8
--
2.21.0
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 03/39] drm/i915: Add transcoder restriction to PSR2
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
2019-08-16 8:04 ` [PATCH 01/39] drm/i915/tgl: do not use DDIC Lucas De Marchi
2019-08-16 8:04 ` [PATCH 02/39] drm/i915/psr: Make PSR registers relative to transcoders Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-16 8:04 ` [PATCH 04/39] drm/i915: Do not unmask PSR interruption in IRQ postinstall Lucas De Marchi
` (39 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan
From: José Roberto de Souza <jose.souza@intel.com>
According to PSR2_CTL definition on BSpec there is only one instance
of PSR2_CTL also ICL display overview state that PSR2 is only
supported in EDP transcoder, so now that is possible to have PSR in
any transcoder lets add this hardware restriction.
BSpec: 7713
BSpec: 20584
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 795e25d45357..d4d2f1f272fe 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -545,6 +545,11 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
if (!dev_priv->psr.sink_psr2_support)
return false;
+ if (crtc_state->cpu_transcoder != TRANSCODER_EDP) {
+ DRM_DEBUG_KMS("PSR2 is only supported in EDP transcoder\n");
+ return false;
+ }
+
/*
* DSC and PSR2 cannot be enabled simultaneously. If a requested
* resolution requires DSC to be enabled, priority is given to DSC
--
2.21.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 04/39] drm/i915: Do not unmask PSR interruption in IRQ postinstall
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (2 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 03/39] drm/i915: Add transcoder restriction to PSR2 Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-16 8:04 ` [PATCH 05/39] drm/i915/psr: Only handle interruptions of the transcoder in use Lucas De Marchi
` (38 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan
From: José Roberto de Souza <jose.souza@intel.com>
No need to unmask PSR interrutpion if PSR is not enabled, better move
the call to intel_psr_enable_source().
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 4 +++-
drivers/gpu/drm/i915/display/intel_psr.h | 1 -
drivers/gpu/drm/i915/i915_irq.c | 2 --
3 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index d4d2f1f272fe..633ab23674bc 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -105,7 +105,7 @@ static int edp_psr_shift(enum transcoder cpu_transcoder)
}
}
-void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug)
+static void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug)
{
u32 debug_mask, mask;
enum transcoder cpu_transcoder;
@@ -726,6 +726,8 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
I915_WRITE(EDP_PSR_DEBUG(dev_priv->psr.transcoder), mask);
+
+ intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
}
static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index dc818826f36d..46e4de8b8cd5 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -30,7 +30,6 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
void intel_psr_init(struct drm_i915_private *dev_priv);
void intel_psr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state);
-void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug);
void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
void intel_psr_short_pulse(struct intel_dp *intel_dp);
int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 37e3dd3c1a9d..77391d8325bf 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3684,7 +3684,6 @@ static void ironlake_irq_postinstall(struct drm_i915_private *dev_priv)
if (IS_HASWELL(dev_priv)) {
gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
- intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
display_mask |= DE_EDP_PSR_INT_HSW;
}
@@ -3795,7 +3794,6 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
- intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
for_each_pipe(dev_priv, pipe) {
dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
--
2.21.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 05/39] drm/i915/psr: Only handle interruptions of the transcoder in use
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (3 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 04/39] drm/i915: Do not unmask PSR interruption in IRQ postinstall Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-16 8:04 ` [PATCH 06/39] drm/i915/bdw+: Enable PSR in any eDP port Lucas De Marchi
` (37 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan
From: José Roberto de Souza <jose.souza@intel.com>
It was enabling and checking PSR interruptions in every transcoder
while it should keep the interruptions on the non-used transcoders
masked.
This also already prepares for future when more the one PSR instance
will be allowed.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 140 +++++++++--------------
drivers/gpu/drm/i915/i915_reg.h | 12 +-
2 files changed, 58 insertions(+), 94 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 633ab23674bc..36bdc16fb43b 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -88,48 +88,23 @@ static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
}
}
-static int edp_psr_shift(enum transcoder cpu_transcoder)
+static void intel_psr_irq_control(struct drm_i915_private *dev_priv)
{
- switch (cpu_transcoder) {
- case TRANSCODER_A:
- return EDP_PSR_TRANSCODER_A_SHIFT;
- case TRANSCODER_B:
- return EDP_PSR_TRANSCODER_B_SHIFT;
- case TRANSCODER_C:
- return EDP_PSR_TRANSCODER_C_SHIFT;
- default:
- MISSING_CASE(cpu_transcoder);
- /* fallthrough */
- case TRANSCODER_EDP:
- return EDP_PSR_TRANSCODER_EDP_SHIFT;
- }
-}
+ enum transcoder trans = dev_priv->psr.transcoder;
+ u32 val, mask;
-static void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug)
-{
- u32 debug_mask, mask;
- enum transcoder cpu_transcoder;
- u32 transcoders = BIT(TRANSCODER_EDP);
-
- if (INTEL_GEN(dev_priv) >= 8)
- transcoders |= BIT(TRANSCODER_A) |
- BIT(TRANSCODER_B) |
- BIT(TRANSCODER_C);
-
- debug_mask = 0;
- mask = 0;
- for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
- int shift = edp_psr_shift(cpu_transcoder);
-
- mask |= EDP_PSR_ERROR(shift);
- debug_mask |= EDP_PSR_POST_EXIT(shift) |
- EDP_PSR_PRE_ENTRY(shift);
- }
+ mask = EDP_PSR_ERROR(trans);
+ if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ)
+ mask |= EDP_PSR_POST_EXIT(trans) | EDP_PSR_PRE_ENTRY(trans);
- if (debug & I915_PSR_DEBUG_IRQ)
- mask |= debug_mask;
-
- I915_WRITE(EDP_PSR_IMR, ~mask);
+ /*
+ * TODO: when handling multiple PSR instances a global spinlock will be
+ * needed to synchronize the value of shared register
+ */
+ val = I915_READ(EDP_PSR_IMR);
+ val &= ~EDP_PSR_TRANS_MASK(trans);
+ val |= ~mask;
+ I915_WRITE(EDP_PSR_IMR, val);
}
static void psr_event_print(u32 val, bool psr2_enabled)
@@ -171,63 +146,54 @@ static void psr_event_print(u32 val, bool psr2_enabled)
void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
{
- u32 transcoders = BIT(TRANSCODER_EDP);
- enum transcoder cpu_transcoder;
+ enum transcoder cpu_transcoder = dev_priv->psr.transcoder;
ktime_t time_ns = ktime_get();
- u32 mask = 0;
- if (INTEL_GEN(dev_priv) >= 8)
- transcoders |= BIT(TRANSCODER_A) |
- BIT(TRANSCODER_B) |
- BIT(TRANSCODER_C);
+ if (psr_iir & EDP_PSR_ERROR(cpu_transcoder)) {
+ u32 val;
- for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
- int shift = edp_psr_shift(cpu_transcoder);
+ DRM_WARN("[transcoder %s] PSR aux error\n",
+ transcoder_name(cpu_transcoder));
- if (psr_iir & EDP_PSR_ERROR(shift)) {
- DRM_WARN("[transcoder %s] PSR aux error\n",
- transcoder_name(cpu_transcoder));
+ dev_priv->psr.irq_aux_error = true;
- dev_priv->psr.irq_aux_error = true;
+ /*
+ * If this interruption is not masked it will keep
+ * interrupting so fast that it prevents the scheduled
+ * work to run.
+ * Also after a PSR error, we don't want to arm PSR
+ * again so we don't care about unmask the interruption
+ * or unset irq_aux_error.
+ *
+ * TODO: when handling multiple PSR instances a global spinlock
+ * will be needed to synchronize the value of shared register
+ */
+ val = I915_READ(EDP_PSR_IMR);
+ val |= EDP_PSR_ERROR(cpu_transcoder);
+ I915_WRITE(EDP_PSR_IMR, val);
- /*
- * If this interruption is not masked it will keep
- * interrupting so fast that it prevents the scheduled
- * work to run.
- * Also after a PSR error, we don't want to arm PSR
- * again so we don't care about unmask the interruption
- * or unset irq_aux_error.
- */
- mask |= EDP_PSR_ERROR(shift);
- }
+ schedule_work(&dev_priv->psr.work);
+ }
- if (psr_iir & EDP_PSR_PRE_ENTRY(shift)) {
- dev_priv->psr.last_entry_attempt = time_ns;
- DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
- transcoder_name(cpu_transcoder));
- }
+ if (psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder)) {
+ dev_priv->psr.last_entry_attempt = time_ns;
+ DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
+ transcoder_name(cpu_transcoder));
+ }
- if (psr_iir & EDP_PSR_POST_EXIT(shift)) {
- dev_priv->psr.last_exit = time_ns;
- DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
- transcoder_name(cpu_transcoder));
+ if (psr_iir & EDP_PSR_POST_EXIT(cpu_transcoder)) {
+ dev_priv->psr.last_exit = time_ns;
+ DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
+ transcoder_name(cpu_transcoder));
- if (INTEL_GEN(dev_priv) >= 9) {
- u32 val = I915_READ(PSR_EVENT(cpu_transcoder));
- bool psr2_enabled = dev_priv->psr.psr2_enabled;
+ if (INTEL_GEN(dev_priv) >= 9) {
+ u32 val = I915_READ(PSR_EVENT(cpu_transcoder));
+ bool psr2_enabled = dev_priv->psr.psr2_enabled;
- I915_WRITE(PSR_EVENT(cpu_transcoder), val);
- psr_event_print(val, psr2_enabled);
- }
+ I915_WRITE(PSR_EVENT(cpu_transcoder), val);
+ psr_event_print(val, psr2_enabled);
}
}
-
- if (mask) {
- mask |= I915_READ(EDP_PSR_IMR);
- I915_WRITE(EDP_PSR_IMR, mask);
-
- schedule_work(&dev_priv->psr.work);
- }
}
static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
@@ -727,7 +693,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
I915_WRITE(EDP_PSR_DEBUG(dev_priv->psr.transcoder), mask);
- intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
+ intel_psr_irq_control(dev_priv);
}
static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
@@ -752,7 +718,7 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
* to avoid any rendering problems.
*/
val = I915_READ(EDP_PSR_IIR);
- val &= EDP_PSR_ERROR(edp_psr_shift(dev_priv->psr.transcoder));
+ val &= EDP_PSR_ERROR(dev_priv->psr.transcoder);
if (val) {
dev_priv->psr.sink_not_reliable = true;
DRM_DEBUG_KMS("PSR interruption error set, not enabling PSR\n");
@@ -1100,7 +1066,7 @@ int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 val)
old_mode = dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK;
dev_priv->psr.debug = val;
- intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
+ intel_psr_irq_control(dev_priv);
mutex_unlock(&dev_priv->psr.lock);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7da44ae86320..029904e81891 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4289,13 +4289,11 @@ enum {
/* Bspec claims those aren't shifted but stay at 0x64800 */
#define EDP_PSR_IMR _MMIO(0x64834)
#define EDP_PSR_IIR _MMIO(0x64838)
-#define EDP_PSR_ERROR(shift) (1 << ((shift) + 2))
-#define EDP_PSR_POST_EXIT(shift) (1 << ((shift) + 1))
-#define EDP_PSR_PRE_ENTRY(shift) (1 << (shift))
-#define EDP_PSR_TRANSCODER_C_SHIFT 24
-#define EDP_PSR_TRANSCODER_B_SHIFT 16
-#define EDP_PSR_TRANSCODER_A_SHIFT 8
-#define EDP_PSR_TRANSCODER_EDP_SHIFT 0
+#define _EDP_PSR_TRANS_SHIFT(trans) (trans == TRANSCODER_EDP ? 0 : (trans + 1) * 8)
+#define EDP_PSR_TRANS_MASK(trans) (0x7 << _EDP_PSR_TRANS_SHIFT(trans))
+#define EDP_PSR_ERROR(trans) (0x4 << _EDP_PSR_TRANS_SHIFT(trans))
+#define EDP_PSR_POST_EXIT(trans) (0x2 << _EDP_PSR_TRANS_SHIFT(trans))
+#define EDP_PSR_PRE_ENTRY(trans) (0x1 << _EDP_PSR_TRANS_SHIFT(trans))
#define _SRD_AUX_CTL_A 0x60810
#define _SRD_AUX_CTL_EDP 0x6f810
--
2.21.0
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^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 06/39] drm/i915/bdw+: Enable PSR in any eDP port
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (4 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 05/39] drm/i915/psr: Only handle interruptions of the transcoder in use Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-22 16:20 ` Gupta, Anshuman
2019-08-16 8:04 ` [PATCH 07/39] drm/i915: Guard and warn if more than one eDP panel is present Lucas De Marchi
` (36 subsequent siblings)
42 siblings, 1 reply; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan
From: José Roberto de Souza <jose.souza@intel.com>
From BDW+ the PSR registers moved from DDIA to transcoder, so any port
with a eDP panel connected can have PSR, so lets remove this limitation.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 36bdc16fb43b..6eedd8281e72 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -578,11 +578,10 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
/*
* HSW spec explicitly says PSR is tied to port A.
- * BDW+ platforms have a instance of PSR registers per transcoder but
- * for now it only supports one instance of PSR, so lets keep it
- * hardcoded to PORT_A
+ * BDW+ platforms with DDI implementation of PSR have different
+ * PSR registers per transcoder.
*/
- if (dig_port->base.port != PORT_A) {
+ if (IS_HASWELL(dev_priv) && dig_port->base.port != PORT_A) {
DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
return;
}
--
2.21.0
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^ permalink raw reply related [flat|nested] 58+ messages in thread* Re: [PATCH 06/39] drm/i915/bdw+: Enable PSR in any eDP port
2019-08-16 8:04 ` [PATCH 06/39] drm/i915/bdw+: Enable PSR in any eDP port Lucas De Marchi
@ 2019-08-22 16:20 ` Gupta, Anshuman
2019-08-22 16:42 ` Gupta, Anshuman
0 siblings, 1 reply; 58+ messages in thread
From: Gupta, Anshuman @ 2019-08-22 16:20 UTC (permalink / raw)
To: intel-gfx
Verified from B.Specs:7723 and B.Spec:8041
On 8/16/2019 1:34 PM, Lucas De Marchi wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
>
> From BDW+ the PSR registers moved from DDIA to transcoder, so any port
> with a eDP panel connected can have PSR, so lets remove this limitation.
>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 7 +++----
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 36bdc16fb43b..6eedd8281e72 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -578,11 +578,10 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
>
> /*
> * HSW spec explicitly says PSR is tied to port A.
> - * BDW+ platforms have a instance of PSR registers per transcoder but
> - * for now it only supports one instance of PSR, so lets keep it
> - * hardcoded to PORT_A
> + * BDW+ platforms with DDI implementation of PSR have different
> + * PSR registers per transcoder.
> */
> - if (dig_port->base.port != PORT_A) {
> + if (IS_HASWELL(dev_priv) && dig_port->base.port != PORT_A) {
> DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
> return;
> }
>
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^ permalink raw reply [flat|nested] 58+ messages in thread* Re: [PATCH 06/39] drm/i915/bdw+: Enable PSR in any eDP port
2019-08-22 16:20 ` Gupta, Anshuman
@ 2019-08-22 16:42 ` Gupta, Anshuman
0 siblings, 0 replies; 58+ messages in thread
From: Gupta, Anshuman @ 2019-08-22 16:42 UTC (permalink / raw)
To: intel-gfx, Lucas De Marchi; +Cc: Dhinakaran Pandiyan
On 8/22/2019 9:50 PM, Gupta, Anshuman wrote:
> Verified from B.Specs:7723 and B.Spec:8041
>
> On 8/16/2019 1:34 PM, Lucas De Marchi wrote:
>> From: José Roberto de Souza <jose.souza@intel.com>
>>
>> From BDW+ the PSR registers moved from DDIA to transcoder, so any port
>> with a eDP panel connected can have PSR, so lets remove this limitation.
>>
>> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_psr.c | 7 +++----
>> 1 file changed, 3 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
>> b/drivers/gpu/drm/i915/display/intel_psr.c
>> index 36bdc16fb43b..6eedd8281e72 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -578,11 +578,10 @@ void intel_psr_compute_config(struct intel_dp
>> *intel_dp,
>> /*
>> * HSW spec explicitly says PSR is tied to port A.
>> - * BDW+ platforms have a instance of PSR registers per transcoder
>> but
>> - * for now it only supports one instance of PSR, so lets keep it
>> - * hardcoded to PORT_A
>> + * BDW+ platforms with DDI implementation of PSR have different
>> + * PSR registers per transcoder.
>> */
>> - if (dig_port->base.port != PORT_A) {
>> + if (IS_HASWELL(dev_priv) && dig_port->base.port != PORT_A) {
>> DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
>> return;
>> }
>>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH 07/39] drm/i915: Guard and warn if more than one eDP panel is present
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (5 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 06/39] drm/i915/bdw+: Enable PSR in any eDP port Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-16 8:04 ` [PATCH 08/39] drm/i915/tgl: Change PSR2 transcoder restriction Lucas De Marchi
` (35 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan
From: José Roberto de Souza <jose.souza@intel.com>
Now that is allowed to have PSR enabled in any port from BDW+, lets
guard intel_psr_init_dpcd() against multiple eDP panels and warn about
it.
For now we will keep just one instance of PSR.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 6eedd8281e72..01070eb67571 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -249,6 +249,11 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv =
to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
+ if (dev_priv->psr.dp) {
+ DRM_WARN("More than one eDP panel found, PSR support should be extend\n");
+ return;
+ }
+
drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
sizeof(intel_dp->psr_dpcd));
@@ -271,7 +276,6 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
dev_priv->psr.sink_sync_latency =
intel_dp_get_sink_sync_latency(intel_dp);
- WARN_ON(dev_priv->psr.dp);
dev_priv->psr.dp = intel_dp;
if (INTEL_GEN(dev_priv) >= 9 &&
--
2.21.0
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^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 08/39] drm/i915/tgl: Change PSR2 transcoder restriction
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (6 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 07/39] drm/i915: Guard and warn if more than one eDP panel is present Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-16 21:28 ` Lucas De Marchi
2019-08-16 8:04 ` [PATCH 09/39] drm/i915: Do not read PSR2 register in transcoders without PSR2 Lucas De Marchi
` (34 subsequent siblings)
42 siblings, 1 reply; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan
From: José Roberto de Souza <jose.souza@intel.com>
Tiger Lake has eDP-capable transcoders rather than a transcoder
dedicated to eDP. Transcoder A is the one where we have PSR2.
Actually transcoder B also supports PSR2 but only with software
tracking that is not implemented.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 01070eb67571..1d36d7be015d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -511,12 +511,19 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
int crtc_hdisplay = crtc_state->base.adjusted_mode.crtc_hdisplay;
int crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay;
int psr_max_h = 0, psr_max_v = 0;
+ enum transcoder supported;
if (!dev_priv->psr.sink_psr2_support)
return false;
- if (crtc_state->cpu_transcoder != TRANSCODER_EDP) {
- DRM_DEBUG_KMS("PSR2 is only supported in EDP transcoder\n");
+ /*
+ * TODO: PSR2 is also supported in TRANSCODER_B on TGL+ but it requires
+ * software tracking
+ */
+ supported = INTEL_GEN(dev_priv) >= 12 ? TRANSCODER_A : TRANSCODER_EDP;
+ if (crtc_state->cpu_transcoder != supported) {
+ DRM_DEBUG_KMS("PSR2 not supported in transcoder %s\n",
+ transcoder_name(supported));
return false;
}
--
2.21.0
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^ permalink raw reply related [flat|nested] 58+ messages in thread* Re: [PATCH 08/39] drm/i915/tgl: Change PSR2 transcoder restriction
2019-08-16 8:04 ` [PATCH 08/39] drm/i915/tgl: Change PSR2 transcoder restriction Lucas De Marchi
@ 2019-08-16 21:28 ` Lucas De Marchi
2019-08-16 21:59 ` Souza, Jose
0 siblings, 1 reply; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 21:28 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: Intel Graphics, Dhinakaran Pandiyan
On Fri, Aug 16, 2019 at 1:05 AM Lucas De Marchi
<lucas.demarchi@intel.com> wrote:
>
> From: José Roberto de Souza <jose.souza@intel.com>
>
> Tiger Lake has eDP-capable transcoders rather than a transcoder
> dedicated to eDP. Transcoder A is the one where we have PSR2.
> Actually transcoder B also supports PSR2 but only with software
> tracking that is not implemented.
>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 01070eb67571..1d36d7be015d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -511,12 +511,19 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> int crtc_hdisplay = crtc_state->base.adjusted_mode.crtc_hdisplay;
> int crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay;
> int psr_max_h = 0, psr_max_v = 0;
> + enum transcoder supported;
>
> if (!dev_priv->psr.sink_psr2_support)
> return false;
>
> - if (crtc_state->cpu_transcoder != TRANSCODER_EDP) {
> - DRM_DEBUG_KMS("PSR2 is only supported in EDP transcoder\n");
> + /*
> + * TODO: PSR2 is also supported in TRANSCODER_B on TGL+ but it requires
> + * software tracking
> + */
where is this coming from? spec 49180 says: "Only transcoder A supports PSR2."
Could this patch be squashed in "drm/i915: Add transcoder restriction
to PSR2" so we just add the restriction
for any platform at the same time?
Lucas De Marchi
> + supported = INTEL_GEN(dev_priv) >= 12 ? TRANSCODER_A : TRANSCODER_EDP;
> + if (crtc_state->cpu_transcoder != supported) {
> + DRM_DEBUG_KMS("PSR2 not supported in transcoder %s\n",
> + transcoder_name(supported));
> return false;
> }
>
> --
> 2.21.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Lucas De Marchi
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^ permalink raw reply [flat|nested] 58+ messages in thread* Re: [PATCH 08/39] drm/i915/tgl: Change PSR2 transcoder restriction
2019-08-16 21:28 ` Lucas De Marchi
@ 2019-08-16 21:59 ` Souza, Jose
0 siblings, 0 replies; 58+ messages in thread
From: Souza, Jose @ 2019-08-16 21:59 UTC (permalink / raw)
To: lucas.de.marchi, De Marchi, Lucas; +Cc: intel-gfx, Pandiyan, Dhinakaran
On Fri, 2019-08-16 at 14:28 -0700, Lucas De Marchi wrote:
> On Fri, Aug 16, 2019 at 1:05 AM Lucas De Marchi
> <lucas.demarchi@intel.com> wrote:
> > From: José Roberto de Souza <jose.souza@intel.com>
> >
> > Tiger Lake has eDP-capable transcoders rather than a transcoder
> > dedicated to eDP. Transcoder A is the one where we have PSR2.
> > Actually transcoder B also supports PSR2 but only with software
> > tracking that is not implemented.
> >
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_psr.c | 11 +++++++++--
> > 1 file changed, 9 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 01070eb67571..1d36d7be015d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -511,12 +511,19 @@ static bool intel_psr2_config_valid(struct
> > intel_dp *intel_dp,
> > int crtc_hdisplay = crtc_state-
> > >base.adjusted_mode.crtc_hdisplay;
> > int crtc_vdisplay = crtc_state-
> > >base.adjusted_mode.crtc_vdisplay;
> > int psr_max_h = 0, psr_max_v = 0;
> > + enum transcoder supported;
> >
> > if (!dev_priv->psr.sink_psr2_support)
> > return false;
> >
> > - if (crtc_state->cpu_transcoder != TRANSCODER_EDP) {
> > - DRM_DEBUG_KMS("PSR2 is only supported in EDP
> > transcoder\n");
> > + /*
> > + * TODO: PSR2 is also supported in TRANSCODER_B on TGL+ but
> > it requires
> > + * software tracking
> > + */
>
> where is this coming from? spec 49180 says: "Only transcoder A
> supports PSR2."
BSpec: 49274
Selective Update on second eDP
But or I misread or the platforms changed, TGL do not support PSR2 on
transcoder B even using manual tracking.
>
> Could this patch be squashed in "drm/i915: Add transcoder restriction
> to PSR2" so we just add the restriction
> for any platform at the same time?
Yes it now can be squashed, it was not before because I was trying to
upstream "drm/i915: Add transcoder restriction to PSR2" before TGL was
public.
I will fix both
Thanks
>
> Lucas De Marchi
>
> > + supported = INTEL_GEN(dev_priv) >= 12 ? TRANSCODER_A :
> > TRANSCODER_EDP;
> > + if (crtc_state->cpu_transcoder != supported) {
> > + DRM_DEBUG_KMS("PSR2 not supported in transcoder
> > %s\n",
> > + transcoder_name(supported));
> > return false;
> > }
> >
> > --
> > 2.21.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
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^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH 09/39] drm/i915: Do not read PSR2 register in transcoders without PSR2
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (7 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 08/39] drm/i915/tgl: Change PSR2 transcoder restriction Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-16 8:04 ` [PATCH 10/39] drm/i915/tgl: PSR link standby is not supported anymore Lucas De Marchi
` (33 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
This fix unclaimed access warnings:
[ 245.525788] ------------[ cut here ]------------
[ 245.525884] Unclaimed read from register 0x62900
[ 245.526154] WARNING: CPU: 0 PID: 1234 at drivers/gpu/drm/i915/intel_uncore.c:1100 __unclaimed_reg_debug+0x40/0x50 [i915]
[ 245.526160] Modules linked in: i915 x86_pkg_temp_thermal ax88179_178a coretemp usbnet crct10dif_pclmul mii crc32_pclmul ghash_clmulni_intel e1000e [last unloaded: i915]
[ 245.526191] CPU: 0 PID: 1234 Comm: kms_fullmodeset Not tainted 5.1.0-rc6+ #915
[ 245.526197] Hardware name: Intel Corporation Tiger Lake Client Platform/TigerLake U DDR4 SODIMM RVP, BIOS TGLSFWR1.D00.2081.A10.1904182155 04/18/2019
[ 245.526273] RIP: 0010:__unclaimed_reg_debug+0x40/0x50 [i915]
[ 245.526281] Code: 74 05 5b 5d 41 5c c3 45 84 e4 48 c7 c0 76 97 21 a0 48 c7 c6 6c 97 21 a0 89 ea 48 0f 44 f0 48 c7 c7 7f 97 21 a0 e8 4f 1e fe e0 <0f> 0b 83 2d 6f d9 1c 00 01 5b 5d 41 5c c3 66 90 41 57 41 56 41 55
[ 245.526288] RSP: 0018:ffffc900006bf7d8 EFLAGS: 00010086
[ 245.526297] RAX: 0000000000000000 RBX: 0000000000000000 RCX: 0000000000000000
[ 245.526304] RDX: 0000000000000007 RSI: 0000000000000000 RDI: 00000000ffffffff
[ 245.526310] RBP: 0000000000061900 R08: 0000000000000000 R09: 0000000000000001
[ 245.526317] R10: 0000000000000006 R11: 0000000000000000 R12: 0000000000000001
[ 245.526324] R13: 0000000000000000 R14: ffff8882914f0d58 R15: 0000000000000206
[ 245.526332] FS: 00007fed2a3c39c0(0000) GS:ffff8882a8600000(0000) knlGS:0000000000000000
[ 245.526340] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 245.526347] CR2: 00007fed28dff000 CR3: 00000002a086c006 CR4: 0000000000760ef0
[ 245.526354] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
[ 245.526361] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
[ 245.526367] PKRU: 55555554
[ 245.526373] Call Trace:
[ 245.526454] gen11_fwtable_read32+0x219/0x250 [i915]
[ 245.526576] intel_psr_activate+0x57/0x400 [i915]
[ 245.526697] intel_psr_enable_locked+0x367/0x4b0 [i915]
[ 245.526828] intel_psr_enable+0xa4/0xd0 [i915]
[ 245.526946] intel_enable_ddi+0x127/0x2f0 [i915]
[ 245.527075] intel_encoders_enable.isra.79+0x62/0x90 [i915]
[ 245.527202] haswell_crtc_enable+0x2a2/0x850 [i915]
[ 245.527337] intel_update_crtc+0x51/0x360 [i915]
[ 245.527466] skl_update_crtcs+0x26c/0x300 [i915]
[ 245.527603] intel_atomic_commit_tail+0x3e5/0x13c0 [i915]
[ 245.527757] intel_atomic_commit+0x24d/0x2d0 [i915]
[ 245.527782] drm_atomic_helper_set_config+0x7b/0x90
[ 245.527799] drm_mode_setcrtc+0x1b4/0x6f0
[ 245.527856] ? drm_mode_getcrtc+0x180/0x180
[ 245.527867] drm_ioctl_kernel+0xad/0xf0
[ 245.527886] drm_ioctl+0x2f4/0x3b0
[ 245.527902] ? drm_mode_getcrtc+0x180/0x180
[ 245.527935] ? rcu_read_lock_sched_held+0x6f/0x80
[ 245.527956] do_vfs_ioctl+0xa0/0x6d0
[ 245.527970] ? __task_pid_nr_ns+0xb6/0x200
[ 245.527991] ksys_ioctl+0x35/0x70
[ 245.528009] __x64_sys_ioctl+0x11/0x20
[ 245.528020] do_syscall_64+0x55/0x180
[ 245.528034] entry_SYSCALL_64_after_hwframe+0x49/0xbe
[ 245.528042] RIP: 0033:0x7fed2cc7c3c7
[ 245.528050] Code: 00 00 90 48 8b 05 c9 3a 0d 00 64 c7 00 26 00 00 00 48 c7 c0 ff ff ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 b8 10 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 99 3a 0d 00 f7 d8 64 89 01 48
[ 245.528057] RSP: 002b:00007ffe36944378 EFLAGS: 00000246 ORIG_RAX: 0000000000000010
[ 245.528067] RAX: ffffffffffffffda RBX: 00007ffe369443b0 RCX: 00007fed2cc7c3c7
[ 245.528074] RDX: 00007ffe369443b0 RSI: 00000000c06864a2 RDI: 0000000000000003
[ 245.528081] RBP: 00007ffe369443b0 R08: 0000000000000000 R09: 0000564c0173ae98
[ 245.528088] R10: 0000564c0173aeb8 R11: 0000000000000246 R12: 00000000c06864a2
[ 245.528095] R13: 0000000000000003 R14: 0000000000000000 R15: 0000000000000000
[ 245.528128] irq event stamp: 140866
[ 245.528138] hardirqs last enabled at (140865): [<ffffffff819a63dc>] _raw_spin_unlock_irqrestore+0x4c/0x60
[ 245.528148] hardirqs last disabled at (140866): [<ffffffff819a624d>] _raw_spin_lock_irqsave+0xd/0x50
[ 245.528158] softirqs last enabled at (140860): [<ffffffff81c0038c>] __do_softirq+0x38c/0x499
[ 245.528170] softirqs last disabled at (140853): [<ffffffff810b4a09>] irq_exit+0xa9/0xc0
[ 245.528247] WARNING: CPU: 0 PID: 1234 at drivers/gpu/drm/i915/intel_uncore.c:1100 __unclaimed_reg_debug+0x40/0x50 [i915]
[ 245.528254] ---[ end trace 366069676e98a410 ]---
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 29 ++++++++++++++++--------
1 file changed, 19 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 1d36d7be015d..7e0b370183ad 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -504,6 +504,19 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val);
}
+static bool
+_trans_support_psr2(struct drm_i915_private *dev_priv, enum transcoder trans)
+{
+ /*
+ * TODO: PSR2 is also supported in TRANSCODER_B on TGL+ but it requires
+ * software tracking
+ */
+ if (INTEL_GEN(dev_priv) >= 12)
+ return trans == TRANSCODER_A;
+ else
+ return trans == TRANSCODER_EDP;
+}
+
static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state)
{
@@ -511,19 +524,13 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
int crtc_hdisplay = crtc_state->base.adjusted_mode.crtc_hdisplay;
int crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay;
int psr_max_h = 0, psr_max_v = 0;
- enum transcoder supported;
if (!dev_priv->psr.sink_psr2_support)
return false;
- /*
- * TODO: PSR2 is also supported in TRANSCODER_B on TGL+ but it requires
- * software tracking
- */
- supported = INTEL_GEN(dev_priv) >= 12 ? TRANSCODER_A : TRANSCODER_EDP;
- if (crtc_state->cpu_transcoder != supported) {
+ if (!_trans_support_psr2(dev_priv, crtc_state->cpu_transcoder)) {
DRM_DEBUG_KMS("PSR2 not supported in transcoder %s\n",
- transcoder_name(supported));
+ transcoder_name(crtc_state->cpu_transcoder));
return false;
}
@@ -629,7 +636,8 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- if (INTEL_GEN(dev_priv) >= 9)
+ if (INTEL_GEN(dev_priv) >= 9 &&
+ _trans_support_psr2(dev_priv, dev_priv->psr.transcoder))
WARN_ON(I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)) & EDP_PSR2_ENABLE);
WARN_ON(I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder)) & EDP_PSR_ENABLE);
WARN_ON(dev_priv->psr.active);
@@ -783,7 +791,8 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
u32 val;
if (!dev_priv->psr.active) {
- if (INTEL_GEN(dev_priv) >= 9) {
+ if (INTEL_GEN(dev_priv) >= 9 &&
+ _trans_support_psr2(dev_priv, dev_priv->psr.transcoder)) {
val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder));
WARN_ON(val & EDP_PSR2_ENABLE);
}
--
2.21.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 10/39] drm/i915/tgl: PSR link standby is not supported anymore
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (8 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 09/39] drm/i915: Do not read PSR2 register in transcoders without PSR2 Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-22 9:54 ` Gupta, Anshuman
2019-08-16 8:04 ` [PATCH 11/39] drm/i915/tgl: Access the right register when handling PSR interruptions Lucas De Marchi
` (32 subsequent siblings)
42 siblings, 1 reply; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
According to BSpc if link standby is set on TGL+, PSR will not be
enabled. Vendors should not use panels that requires link standby and
even if they do, panel should assert a PSR error that will cause PSR to
be disabled.
BSpec: 50434
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 7e0b370183ad..4cde1b75f901 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1248,8 +1248,8 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
/* HSW and BDW require workarounds that we don't implement. */
dev_priv->psr.link_standby = false;
- else
- /* For new platforms let's respect VBT back again */
+ else if (INTEL_GEN(dev_priv) < 12)
+ /* For new platforms up to TGL let's respect VBT back again */
dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
INIT_WORK(&dev_priv->psr.work, intel_psr_work);
--
2.21.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 58+ messages in thread* Re: [PATCH 10/39] drm/i915/tgl: PSR link standby is not supported anymore
2019-08-16 8:04 ` [PATCH 10/39] drm/i915/tgl: PSR link standby is not supported anymore Lucas De Marchi
@ 2019-08-22 9:54 ` Gupta, Anshuman
0 siblings, 0 replies; 58+ messages in thread
From: Gupta, Anshuman @ 2019-08-22 9:54 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx
Verified with respect two B.Spces: 50434 and eDP specs DPCD – Sink
"Device PSR Configuration Field" 00170h address.
Looks Good to me.
On 8/16/2019 1:34 PM, Lucas De Marchi wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
>
> According to BSpc if link standby is set on TGL+, PSR will not be
> enabled. Vendors should not use panels that requires link standby and
> even if they do, panel should assert a PSR error that will cause PSR to
> be disabled.
>
> BSpec: 50434
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 7e0b370183ad..4cde1b75f901 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1248,8 +1248,8 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> /* HSW and BDW require workarounds that we don't implement. */
> dev_priv->psr.link_standby = false;
> - else
> - /* For new platforms let's respect VBT back again */
> + else if (INTEL_GEN(dev_priv) < 12)
> + /* For new platforms up to TGL let's respect VBT back again */
> dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
>
> INIT_WORK(&dev_priv->psr.work, intel_psr_work);
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH 11/39] drm/i915/tgl: Access the right register when handling PSR interruptions
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (9 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 10/39] drm/i915/tgl: PSR link standby is not supported anymore Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-16 8:04 ` [PATCH 12/39] drm/i915/tgl: Add maximum resolution supported by PSR2 HW Lucas De Marchi
` (31 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan
From: José Roberto de Souza <jose.souza@intel.com>
For older gens PSR IIR and IMR had a fixed address that was not
relative to anything, but from TGL those registers moved to each
transcoder offset.
So here adding a new macro and a new PSR irq handler with the
transcoder parameter.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 63 ++++++++++++++++++------
drivers/gpu/drm/i915/display/intel_psr.h | 1 +
drivers/gpu/drm/i915/i915_irq.c | 52 ++++++++++++++++---
drivers/gpu/drm/i915/i915_reg.h | 10 +++-
4 files changed, 105 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 4cde1b75f901..894c1709e332 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -91,20 +91,33 @@ static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
static void intel_psr_irq_control(struct drm_i915_private *dev_priv)
{
enum transcoder trans = dev_priv->psr.transcoder;
- u32 val, mask;
+ u32 psr_error, psr_entry, psr_exit, mask, val;
+ i915_reg_t mask_reg;
+
+ if (INTEL_GEN(dev_priv) >= 12) {
+ psr_error = TRANS_PSR_ERROR;
+ psr_entry = TRANS_PSR_PRE_ENTRY;
+ psr_exit = TRANS_PSR_POST_EXIT;
+ mask_reg = TRANS_PSR_IMR(trans);
+ } else {
+ psr_error = EDP_PSR_ERROR(trans);
+ psr_entry = EDP_PSR_PRE_ENTRY(trans);
+ psr_exit = EDP_PSR_POST_EXIT(trans);
+ mask_reg = EDP_PSR_IMR;
+ }
- mask = EDP_PSR_ERROR(trans);
+ mask = psr_error;
if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ)
- mask |= EDP_PSR_POST_EXIT(trans) | EDP_PSR_PRE_ENTRY(trans);
+ mask |= psr_exit | psr_entry;
/*
* TODO: when handling multiple PSR instances a global spinlock will be
* needed to synchronize the value of shared register
*/
- val = I915_READ(EDP_PSR_IMR);
- val &= ~EDP_PSR_TRANS_MASK(trans);
+ val = I915_READ(mask_reg);
+ val &= ~(psr_error | psr_entry | psr_exit);
val |= ~mask;
- I915_WRITE(EDP_PSR_IMR, val);
+ I915_WRITE(mask_reg, val);
}
static void psr_event_print(u32 val, bool psr2_enabled)
@@ -147,9 +160,21 @@ static void psr_event_print(u32 val, bool psr2_enabled)
void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
{
enum transcoder cpu_transcoder = dev_priv->psr.transcoder;
+ u32 psr_error, psr_entry, psr_exit;
ktime_t time_ns = ktime_get();
- if (psr_iir & EDP_PSR_ERROR(cpu_transcoder)) {
+ if (INTEL_GEN(dev_priv) >= 12) {
+ psr_error = TRANS_PSR_ERROR;
+ psr_entry = TRANS_PSR_PRE_ENTRY;
+ psr_exit = TRANS_PSR_POST_EXIT;
+ } else {
+ psr_error = EDP_PSR_ERROR(cpu_transcoder);
+ psr_entry = EDP_PSR_PRE_ENTRY(cpu_transcoder);
+ psr_exit = EDP_PSR_POST_EXIT(cpu_transcoder);
+ }
+
+ if (psr_iir & psr_error) {
+ i915_reg_t mask_reg;
u32 val;
DRM_WARN("[transcoder %s] PSR aux error\n",
@@ -168,20 +193,25 @@ void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
* TODO: when handling multiple PSR instances a global spinlock
* will be needed to synchronize the value of shared register
*/
- val = I915_READ(EDP_PSR_IMR);
- val |= EDP_PSR_ERROR(cpu_transcoder);
- I915_WRITE(EDP_PSR_IMR, val);
+ if (INTEL_GEN(dev_priv) >= 12)
+ mask_reg = TRANS_PSR_IMR(cpu_transcoder);
+ else
+ mask_reg = EDP_PSR_IMR;
+
+ val = I915_READ(mask_reg);
+ val |= psr_error;
+ I915_WRITE(mask_reg, val);
schedule_work(&dev_priv->psr.work);
}
- if (psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder)) {
+ if (psr_iir & psr_entry) {
dev_priv->psr.last_entry_attempt = time_ns;
DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
transcoder_name(cpu_transcoder));
}
- if (psr_iir & EDP_PSR_POST_EXIT(cpu_transcoder)) {
+ if (psr_iir & psr_exit) {
dev_priv->psr.last_exit = time_ns;
DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
transcoder_name(cpu_transcoder));
@@ -735,8 +765,13 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
* first time that PSR HW tries to activate so lets keep PSR disabled
* to avoid any rendering problems.
*/
- val = I915_READ(EDP_PSR_IIR);
- val &= EDP_PSR_ERROR(dev_priv->psr.transcoder);
+ if (INTEL_GEN(dev_priv) >= 12) {
+ val = I915_READ(TRANS_PSR_IIR(dev_priv->psr.transcoder));
+ val &= TRANS_PSR_ERROR;
+ } else {
+ val = I915_READ(EDP_PSR_IIR);
+ val &= EDP_PSR_ERROR(dev_priv->psr.transcoder);
+ }
if (val) {
dev_priv->psr.sink_not_reliable = true;
DRM_DEBUG_KMS("PSR interruption error set, not enabling PSR\n");
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 46e4de8b8cd5..6570a23a68b2 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -6,6 +6,7 @@
#ifndef __INTEL_PSR_H__
#define __INTEL_PSR_H__
+#include "intel_display.h"
#include "intel_frontbuffer.h"
struct drm_i915_private;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 77391d8325bf..6024a6ef1c76 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2655,11 +2655,22 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
}
if (iir & GEN8_DE_EDP_PSR) {
- u32 psr_iir = I915_READ(EDP_PSR_IIR);
+ u32 psr_iir;
+
+ if (INTEL_GEN(dev_priv) >= 12) {
+ enum transcoder trans = dev_priv->psr.transcoder;
+
+ psr_iir = I915_READ(TRANS_PSR_IIR(trans));
+ I915_WRITE(TRANS_PSR_IIR(trans), psr_iir);
+ } else {
+ psr_iir = I915_READ(EDP_PSR_IIR);
+ I915_WRITE(EDP_PSR_IIR, psr_iir);
+ }
+
+ if (psr_iir)
+ found = true;
intel_psr_irq_handler(dev_priv, psr_iir);
- I915_WRITE(EDP_PSR_IIR, psr_iir);
- found = true;
}
if (!found)
@@ -3279,8 +3290,23 @@ static void gen11_irq_reset(struct drm_i915_private *dev_priv)
intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);
- intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
- intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
+ if (INTEL_GEN(dev_priv) >= 12) {
+ enum transcoder trans;
+
+ for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) {
+ enum intel_display_power_domain domain;
+
+ domain = POWER_DOMAIN_TRANSCODER(trans);
+ if (!intel_display_power_is_enabled(dev_priv, domain))
+ continue;
+
+ intel_uncore_write(uncore, TRANS_PSR_IMR(trans), 0xffffffff);
+ intel_uncore_write(uncore, TRANS_PSR_IIR(trans), 0xffffffff);
+ }
+ } else {
+ intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
+ intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
+ }
for_each_pipe(dev_priv, pipe)
if (intel_display_power_is_enabled(dev_priv,
@@ -3793,7 +3819,21 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
else if (IS_BROADWELL(dev_priv))
de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
- gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
+ if (INTEL_GEN(dev_priv) >= 12) {
+ enum transcoder trans;
+
+ for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) {
+ enum intel_display_power_domain domain;
+
+ domain = POWER_DOMAIN_TRANSCODER(trans);
+ if (!intel_display_power_is_enabled(dev_priv, domain))
+ continue;
+
+ gen3_assert_iir_is_zero(uncore, TRANS_PSR_IIR(trans));
+ }
+ } else {
+ gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
+ }
for_each_pipe(dev_priv, pipe) {
dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 029904e81891..095dd27044c0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4286,7 +4286,7 @@ enum {
#define EDP_PSR_TP1_TIME_0us (3 << 4)
#define EDP_PSR_IDLE_FRAME_SHIFT 0
-/* Bspec claims those aren't shifted but stay at 0x64800 */
+/* Bspec claims those aren't shifted but stay at 0x64800 until TGL */
#define EDP_PSR_IMR _MMIO(0x64834)
#define EDP_PSR_IIR _MMIO(0x64838)
#define _EDP_PSR_TRANS_SHIFT(trans) (trans == TRANSCODER_EDP ? 0 : (trans + 1) * 8)
@@ -4295,6 +4295,14 @@ enum {
#define EDP_PSR_POST_EXIT(trans) (0x2 << _EDP_PSR_TRANS_SHIFT(trans))
#define EDP_PSR_PRE_ENTRY(trans) (0x1 << _EDP_PSR_TRANS_SHIFT(trans))
+#define _PSR_IMR_A 0x60814
+#define _PSR_IIR_A 0x60818
+#define TRANS_PSR_IMR(tran) _MMIO_TRANS2(tran, _PSR_IMR_A) /* TGL+ */
+#define TRANS_PSR_IIR(tran) _MMIO_TRANS2(tran, _PSR_IIR_A) /* TGL+ */
+#define TRANS_PSR_ERROR (1 << 2)
+#define TRANS_PSR_POST_EXIT (1 << 1)
+#define TRANS_PSR_PRE_ENTRY (1 << 0)
+
#define _SRD_AUX_CTL_A 0x60810
#define _SRD_AUX_CTL_EDP 0x6f810
#define EDP_PSR_AUX_CTL(tran) _MMIO(_PSR_ADJ(tran, _SRD_AUX_CTL_A))
--
2.21.0
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^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 12/39] drm/i915/tgl: Add maximum resolution supported by PSR2 HW
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (10 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 11/39] drm/i915/tgl: Access the right register when handling PSR interruptions Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-22 16:46 ` Gupta, Anshuman
2019-08-16 8:04 ` [PATCH 13/39] drm/i915/mst: Do not hardcoded the crtcs that encoder can connect Lucas De Marchi
` (30 subsequent siblings)
42 siblings, 1 reply; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan
From: José Roberto de Souza <jose.souza@intel.com>
TGL PSR2 HW supports a bigger resolution, so lets add it
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 894c1709e332..33936fdd8851 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -574,7 +574,10 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
return false;
}
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 12) {
+ psr_max_h = 5120;
+ psr_max_v = 3200;
+ } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
psr_max_h = 4096;
psr_max_v = 2304;
} else if (IS_GEN(dev_priv, 9)) {
--
2.21.0
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^ permalink raw reply related [flat|nested] 58+ messages in thread* Re: [PATCH 12/39] drm/i915/tgl: Add maximum resolution supported by PSR2 HW
2019-08-16 8:04 ` [PATCH 12/39] drm/i915/tgl: Add maximum resolution supported by PSR2 HW Lucas De Marchi
@ 2019-08-22 16:46 ` Gupta, Anshuman
0 siblings, 0 replies; 58+ messages in thread
From: Gupta, Anshuman @ 2019-08-22 16:46 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx; +Cc: Dhinakaran Pandiyan
On 8/16/2019 1:34 PM, Lucas De Marchi wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
>
> TGL PSR2 HW supports a bigger resolution, so lets add it
>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 894c1709e332..33936fdd8851 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -574,7 +574,10 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> return false;
> }
>
> - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 12) {
> + psr_max_h = 5120;
> + psr_max_v = 3200;
B.Specs 49199 only talks about PSR2 maximum pipe horizontal active size
5120 pixels, from where we got the max vertical size.
> + } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
> psr_max_h = 4096;
> psr_max_v = 2304;
> } else if (IS_GEN(dev_priv, 9)) {
>
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^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH 13/39] drm/i915/mst: Do not hardcoded the crtcs that encoder can connect
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (11 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 12/39] drm/i915/tgl: Add maximum resolution supported by PSR2 HW Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-16 8:04 ` [PATCH 14/39] drm/i915: Add for_each_new_intel_connector_in_state() Lucas De Marchi
` (29 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
Tiger Lake has up to 4 pipes so the mask would need to be 0xf instead of
0x7. Do not hardcode the mask so it allows the fake MST encoders to
connect to all pipes no matter how many the platform has.
Iterating over all pipes to keep consistent with intel_ddi_init().
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index b1a3df185f4c..7138785daf15 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -586,6 +586,8 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum
struct intel_dp_mst_encoder *intel_mst;
struct intel_encoder *intel_encoder;
struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ enum pipe pipe_iter;
intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL);
@@ -602,8 +604,9 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum
intel_encoder->type = INTEL_OUTPUT_DP_MST;
intel_encoder->power_domain = intel_dig_port->base.power_domain;
intel_encoder->port = intel_dig_port->base.port;
- intel_encoder->crtc_mask = 0x7;
intel_encoder->cloneable = 0;
+ for_each_pipe(dev_priv, pipe_iter)
+ intel_encoder->crtc_mask |= BIT(pipe_iter);
intel_encoder->compute_config = intel_dp_mst_compute_config;
intel_encoder->disable = intel_mst_disable_dp;
--
2.21.0
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^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 14/39] drm/i915: Add for_each_new_intel_connector_in_state()
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (12 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 13/39] drm/i915/mst: Do not hardcoded the crtcs that encoder can connect Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-22 12:55 ` Maarten Lankhorst
2019-08-16 8:04 ` [PATCH 15/39] drm: Add for_each_oldnew_intel_crtc_in_state_reverse() Lucas De Marchi
` (28 subsequent siblings)
42 siblings, 1 reply; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
The same macro as for_each_new_connector_in_state() but it uses
intel/i915 types instead of the drm ones.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index e57e6969051d..fd3043e77b50 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -411,6 +411,14 @@ enum phy_fia {
(__i)++) \
for_each_if(crtc)
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->base.num_connector; \
+ (__i)++) \
+ for_each_if ((__state)->base.connectors[__i].ptr && \
+ ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+ (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
+
void intel_link_compute_m_n(u16 bpp, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
--
2.21.0
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^ permalink raw reply related [flat|nested] 58+ messages in thread* Re: [PATCH 14/39] drm/i915: Add for_each_new_intel_connector_in_state()
2019-08-16 8:04 ` [PATCH 14/39] drm/i915: Add for_each_new_intel_connector_in_state() Lucas De Marchi
@ 2019-08-22 12:55 ` Maarten Lankhorst
0 siblings, 0 replies; 58+ messages in thread
From: Maarten Lankhorst @ 2019-08-22 12:55 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx
Op 16-08-2019 om 10:04 schreef Lucas De Marchi:
> From: José Roberto de Souza <jose.souza@intel.com>
>
> The same macro as for_each_new_connector_in_state() but it uses
> intel/i915 types instead of the drm ones.
>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.h | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index e57e6969051d..fd3043e77b50 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -411,6 +411,14 @@ enum phy_fia {
> (__i)++) \
> for_each_if(crtc)
>
> +#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
> + for ((__i) = 0; \
> + (__i) < (__state)->base.num_connector; \
> + (__i)++) \
> + for_each_if ((__state)->base.connectors[__i].ptr && \
> + ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
> + (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
> +
> void intel_link_compute_m_n(u16 bpp, int nlanes,
> int pixel_clock, int link_clock,
> struct intel_link_m_n *m_n,
Hey,
This is slightly invalid, as intel_tv_connector_state doesn't subclass intel_digital_connector_state, it subclasses drm_connector_state directly.
I would at least fix intel_tv.c to take a intel_digital_connector_state as base class.
With that patch as prerequisite:
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH 15/39] drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (13 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 14/39] drm/i915: Add for_each_new_intel_connector_in_state() Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-16 8:04 ` [PATCH 16/39] drm/i915: Disable pipes in reverse order Lucas De Marchi
` (27 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
Same as for_each_oldnew_intel_crtc_in_state() but iterates in reverse
order.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index fd3043e77b50..c0197380a871 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -411,6 +411,7 @@ enum phy_fia {
(__i)++) \
for_each_if(crtc)
+
#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
for ((__i) = 0; \
(__i) < (__state)->base.num_connector; \
@@ -419,6 +420,15 @@ enum phy_fia {
((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
(new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+ for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
+ (__i) >= 0 && \
+ ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+ (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+ (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+ (__i)--) \
+ for_each_if(crtc)
+
void intel_link_compute_m_n(u16 bpp, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
--
2.21.0
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^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 16/39] drm/i915: Disable pipes in reverse order
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (14 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 15/39] drm: Add for_each_oldnew_intel_crtc_in_state_reverse() Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-16 8:04 ` [PATCH 17/39] drm/i915/tgl: Select master transcoder in DP MST Lucas De Marchi
` (26 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
Disable CRTC/pipes in reverse order because some features (MST in
TGL+) requires master and slave relationship between pipes, so it
should always pick the lowest pipe as master as it will be enabled
first and disable in the reverse order so the master will be the last
one to be disabled.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6c6a5a5f41bb..72c41d3affb1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13924,7 +13924,15 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (state->modeset)
wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
- for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+ /*
+ * Disable CRTC/pipes in reverse order because some features(MST in
+ * TGL+) requires master and slave relationship between pipes, so it
+ * should always pick the lowest pipe as master as it will be enabled
+ * first and disable in the reverse order so the master will be the
+ * last one to be disabled.
+ */
+ for_each_oldnew_intel_crtc_in_state_reverse(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
if (needs_modeset(new_crtc_state) ||
new_crtc_state->update_pipe) {
--
2.21.0
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^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 17/39] drm/i915/tgl: Select master transcoder in DP MST
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (15 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 16/39] drm/i915: Disable pipes in reverse order Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-16 8:04 ` [PATCH 18/39] drm/i915/tgl: Introduce initial Tiger Lake workarounds Lucas De Marchi
` (25 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
On TGL the blending of all the streams have moved from DDI to
transcoder, so now every transcoder working over the same MST port must
send its stream to a master transcoder and master will send to DDI
respecting the time slots.
So here it is picking the lowest pipe/transcoder as it will be
enabled first and disabled last.
BSpec: 50493
BSpec: 49190
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 17 ++
drivers/gpu/drm/i915/display/intel_display.c | 15 ++
drivers/gpu/drm/i915/display/intel_display.h | 3 +
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 159 +++++++++++++++++-
drivers/gpu/drm/i915/display/intel_dp_mst.h | 2 +
drivers/gpu/drm/i915/i915_reg.h | 3 +
7 files changed, 199 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 647ba5140656..c26dee8521f6 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1840,6 +1840,12 @@ void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
temp |= TRANS_DDI_MODE_SELECT_DP_MST;
temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
+
+ if (INTEL_GEN(dev_priv) >= 12) {
+ enum transcoder master = crtc_state->mst_master_trans;
+
+ temp |= TRANS_DDI_MST_TRANSPORT_SELECT_DPTP(master);
+ }
} else {
temp |= TRANS_DDI_MODE_SELECT_DP_SST;
temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
@@ -3863,6 +3869,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
break;
}
+ pipe_config->mst_master_trans = TRANSCODER_INVALID;
+
switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
case TRANS_DDI_MODE_SELECT_HDMI:
pipe_config->has_hdmi_sink = true;
@@ -3898,6 +3906,13 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
pipe_config->lane_count =
((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
+
+ if (INTEL_GEN(dev_priv) >= 12) {
+ temp = temp & TRANS_DDI_MST_TRANSPORT_SELECT_MASK;
+ temp = temp >> TRANS_DDI_MST_TRANSPORT_SELECT_SHIFT;
+ pipe_config->mst_master_trans = temp;
+ }
+
intel_dp_get_m_n(intel_crtc, pipe_config);
break;
default:
@@ -4000,6 +4015,8 @@ static int intel_ddi_compute_config(struct intel_encoder *encoder,
intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
+ pipe_config->mst_master_trans = TRANSCODER_INVALID;
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 72c41d3affb1..81c1d359edb2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -47,6 +47,7 @@
#include "display/intel_crt.h"
#include "display/intel_ddi.h"
#include "display/intel_dp.h"
+#include "display/intel_dp_mst.h"
#include "display/intel_dsi.h"
#include "display/intel_dvo.h"
#include "display/intel_gmbus.h"
@@ -12154,6 +12155,14 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
+ if (INTEL_GEN(dev_priv) >= 12 &&
+ intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) {
+ enum transcoder master = pipe_config->mst_master_trans;
+
+ DRM_DEBUG_KMS("master mst cpu_transcoder: %s\n",
+ transcoder_name(master));
+ }
+
dump_planes:
if (!state)
return;
@@ -12837,6 +12846,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_INFOFRAME(hdmi);
PIPE_CONF_CHECK_INFOFRAME(drm);
+ PIPE_CONF_CHECK_I(mst_master_trans);
+
#undef PIPE_CONF_CHECK_X
#undef PIPE_CONF_CHECK_I
#undef PIPE_CONF_CHECK_BOOL
@@ -13613,6 +13624,10 @@ static int intel_atomic_check(struct drm_device *dev,
int ret, i;
bool any_ms = state->cdclk.force_min_cdclk_changed;
+ ret = intel_dp_mst_atomic_add_affected_crtcs(state);
+ if (ret)
+ return ret;
+
/* Catch I915_MODE_FLAG_INHERITED */
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index c0197380a871..459b341796bd 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -91,6 +91,8 @@ enum pipe {
#define pipe_name(p) ((p) + 'A')
enum transcoder {
+ TRANSCODER_INVALID = -1,
+
/*
* The following transcoders have a 1:1 transcoder -> pipe mapping,
* keep their values fixed: the code assumes that TRANSCODER_A=0, the
@@ -132,6 +134,7 @@ static inline const char *transcoder_name(enum transcoder transcoder)
return "DSI A";
case TRANSCODER_DSI_C:
return "DSI C";
+ case TRANSCODER_INVALID:
default:
return "<invalid>";
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index a88ec9aa9ca0..54d1053ff6d0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -983,6 +983,9 @@ struct intel_crtc_state {
/* Forward Error correction State */
bool fec_enable;
+
+ /* Master transcoder for all streams, only used on TGL+ */
+ enum transcoder mst_master_trans;
};
struct intel_crtc {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 7138785daf15..75c9db85f2b0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -87,6 +87,50 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
return 0;
}
+/*
+ * Iterate over all the CRTCs and return the transcoder of the lowest CRTC that
+ * share the same MST connector.
+ */
+static enum transcoder
+mst_compute_master_trans(struct drm_atomic_state *state,
+ struct drm_connector *mst_conn)
+{
+ struct intel_connector *intel_mst_conn = to_intel_connector(mst_conn);
+ struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
+ struct drm_i915_private *dev_priv = to_i915(state->dev);
+ struct intel_crtc_state *intel_crtc_state;
+ struct intel_crtc *intel_crtc;
+ int i;
+
+ if (INTEL_GEN(dev_priv) < 12)
+ return TRANSCODER_INVALID;
+
+ /* Iterate from the lowest to the highest pipe */
+ for_each_new_intel_crtc_in_state(intel_state, intel_crtc, intel_crtc_state, i) {
+ struct intel_digital_connector_state *intel_conn_state;
+ struct intel_connector *intel_conn;
+ int j;
+
+ if (!intel_crtc_state->base.active)
+ continue;
+
+ for_each_new_intel_connector_in_state(intel_state, intel_conn,
+ intel_conn_state, j) {
+ /* Only care about connectors of this CRTC */
+ if (intel_conn_state->base.crtc !=
+ intel_crtc_state->base.crtc)
+ continue;
+
+ if (intel_conn->mst_port != intel_mst_conn->mst_port)
+ continue;
+
+ return intel_crtc_state->cpu_transcoder;
+ }
+ }
+
+ return TRANSCODER_INVALID;
+}
+
static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
@@ -94,14 +138,15 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
struct intel_dp *intel_dp = &intel_mst->primary->dp;
- struct intel_connector *connector =
- to_intel_connector(conn_state->connector);
+ struct drm_connector *connector = conn_state->connector;
+ struct intel_connector *intel_connector = to_intel_connector(connector);
struct intel_digital_connector_state *intel_conn_state =
to_intel_digital_connector_state(conn_state);
const struct drm_display_mode *adjusted_mode =
&pipe_config->base.adjusted_mode;
- void *port = connector->port;
+ void *port = intel_connector->port;
struct link_config_limits limits;
+ enum transcoder master;
int ret;
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
@@ -146,6 +191,51 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
+ master = mst_compute_master_trans(conn_state->state, connector);
+ pipe_config->mst_master_trans = master;
+
+ return 0;
+}
+
+static int
+intel_dp_mst_master_trans_check(struct drm_connector *conn,
+ struct drm_connector_state *new_conn_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(conn->dev);
+ struct drm_atomic_state *state = new_conn_state->state;
+ struct drm_connector_state *old_conn_state =
+ drm_atomic_get_old_connector_state(state, conn);
+ struct drm_crtc *new_crtc = new_conn_state->crtc;
+ struct drm_crtc *old_crtc = old_conn_state->crtc;
+ enum transcoder old_master_trans = TRANSCODER_INVALID;
+ enum transcoder new_master_trans = TRANSCODER_INVALID;
+ struct drm_crtc_state *new_crtc_state, *old_crtc_state;
+
+ if (INTEL_GEN(dev_priv) < 12)
+ return 0;
+
+ if (old_crtc) {
+ struct intel_crtc_state *intel_crtc_state;
+
+ old_crtc_state = drm_atomic_get_new_crtc_state(state, old_crtc);
+ intel_crtc_state = to_intel_crtc_state(old_crtc_state);
+ old_master_trans = intel_crtc_state->mst_master_trans;
+ }
+
+ if (new_crtc) {
+ struct intel_crtc_state *intel_crtc_state;
+
+ new_crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc);
+ intel_crtc_state = to_intel_crtc_state(new_crtc_state);
+ new_master_trans = mst_compute_master_trans(state, conn);
+ }
+
+ if (old_crtc && old_master_trans != new_master_trans)
+ old_crtc_state->mode_changed = true;
+
+ if (new_crtc && old_master_trans != new_master_trans)
+ new_crtc_state->mode_changed = true;
+
return 0;
}
@@ -168,6 +258,10 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
if (ret)
return ret;
+ ret = intel_dp_mst_master_trans_check(connector, new_conn_state);
+ if (ret)
+ return ret;
+
if (!old_conn_state->crtc)
return 0;
@@ -672,3 +766,62 @@ intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port)
drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr);
/* encoders will get killed by normal cleanup */
}
+
+/**
+ * intel_dp_mst_atomic_add_affected_crtcs - Add all CRTCs that share the MST
+ * stream with the CRTCs in the current atomic state.
+ * @state: state to add CRTCs
+ *
+ * It is needed add the CRTCs trigger a call to atomic_check() to
+ * every connector attached to the CRTC in case a new master transcoder will
+ * be needed.
+ */
+int intel_dp_mst_atomic_add_affected_crtcs(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_digital_connector_state *intel_conn_state;
+ struct drm_device *dev = state->base.dev;
+ struct intel_connector *intel_conn;
+ int i;
+
+ if (INTEL_GEN(dev_priv) < 12)
+ return 0;
+
+ for_each_new_intel_connector_in_state(state, intel_conn, intel_conn_state, i) {
+ struct drm_connector_list_iter conn_list_iter;
+ struct drm_connector *conn_iter;
+
+ if (!intel_conn->mst_port)
+ continue;
+
+ drm_connector_list_iter_begin(dev, &conn_list_iter);
+ drm_for_each_connector_iter(conn_iter, &conn_list_iter) {
+ struct drm_connector_state *conn_iter_state;
+ struct intel_connector *intel_conn_iter;
+ struct drm_crtc_state *crtc_state;
+
+ intel_conn_iter = to_intel_connector(conn_iter);
+
+ if (intel_conn_iter->mst_port != intel_conn->mst_port)
+ continue;
+
+ conn_iter_state = drm_atomic_get_connector_state(&state->base, conn_iter);
+ if (IS_ERR(conn_iter_state)) {
+ drm_connector_list_iter_end(&conn_list_iter);
+ return PTR_ERR(conn_iter_state);
+ }
+ if (!conn_iter_state->crtc)
+ continue;
+
+ crtc_state = drm_atomic_get_crtc_state(&state->base,
+ conn_iter_state->crtc);
+ if (IS_ERR(crtc_state)) {
+ drm_connector_list_iter_end(&conn_list_iter);
+ return PTR_ERR(crtc_state);
+ }
+ }
+ drm_connector_list_iter_end(&conn_list_iter);
+ }
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.h b/drivers/gpu/drm/i915/display/intel_dp_mst.h
index f660ad80db04..173598aa81d2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.h
@@ -6,10 +6,12 @@
#ifndef __INTEL_DP_MST_H__
#define __INTEL_DP_MST_H__
+struct intel_atomic_state;
struct intel_digital_port;
int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
+int intel_dp_mst_atomic_add_affected_crtcs(struct intel_atomic_state *state);
int intel_dp_mst_encoder_active_links(struct intel_digital_port *intel_dig_port);
#endif /* __INTEL_DP_MST_H__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 095dd27044c0..c836af0b8231 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9480,6 +9480,9 @@ enum skl_power_gate {
#define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
#define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
#define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
+#define TRANS_DDI_MST_TRANSPORT_SELECT_SHIFT 10 /* TGL+ */
+#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK (0x3 << 10)
+#define TRANS_DDI_MST_TRANSPORT_SELECT_DPTP(trans) ((trans) << 10)
#define TRANS_DDI_HDCP_SIGNALLING (1 << 9)
#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
--
2.21.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 18/39] drm/i915/tgl: Introduce initial Tiger Lake workarounds
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (16 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 17/39] drm/i915/tgl: Select master transcoder in DP MST Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-16 8:04 ` [PATCH 19/39] drm/i915/tgl: Implement Wa_1406941453 Lucas De Marchi
` (24 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx
Add empty workaround hooks for Tiger Lake. The workarounds will be added
on separate patches. We were already applying
WaRsForcewakeAddDelayForAck, which is indeed still valid, so also update
the comment.
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 26 ++++++++++++++++++---
drivers/gpu/drm/i915/intel_pm.c | 4 +++-
3 files changed, 27 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index a5d9b902d6e3..fafae7c7af0d 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2079,6 +2079,7 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
return 0;
switch (INTEL_GEN(engine->i915)) {
+ case 12:
case 11:
return 0;
case 10:
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 704ace01e7f5..126ab3667919 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -569,6 +569,11 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
}
+static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
+ struct i915_wa_list *wal)
+{
+}
+
static void
__intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
struct i915_wa_list *wal,
@@ -581,7 +586,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
wa_init_start(wal, name, engine->name);
- if (IS_GEN(i915, 11))
+ if (IS_GEN(i915, 12))
+ tgl_ctx_workarounds_init(engine, wal);
+ else if (IS_GEN(i915, 11))
icl_ctx_workarounds_init(engine, wal);
else if (IS_CANNONLAKE(i915))
cnl_ctx_workarounds_init(engine, wal);
@@ -890,10 +897,17 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
GAMT_CHKN_DISABLE_L3_COH_PIPE);
}
+static void
+tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+{
+}
+
static void
gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
- if (IS_GEN(i915, 11))
+ if (IS_GEN(i915, 12))
+ tgl_gt_workarounds_init(i915, wal);
+ else if (IS_GEN(i915, 11))
icl_gt_workarounds_init(i915, wal);
else if (IS_CANNONLAKE(i915))
cnl_gt_workarounds_init(i915, wal);
@@ -1183,6 +1197,10 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
}
}
+static void tgl_whitelist_build(struct intel_engine_cs *engine)
+{
+}
+
void intel_engine_init_whitelist(struct intel_engine_cs *engine)
{
struct drm_i915_private *i915 = engine->i915;
@@ -1190,7 +1208,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
wa_init_start(w, "whitelist", engine->name);
- if (IS_GEN(i915, 11))
+ if (IS_GEN(i915, 12))
+ tgl_whitelist_build(engine);
+ else if (IS_GEN(i915, 11))
icl_whitelist_build(engine);
else if (IS_CANNONLAKE(i915))
cnl_whitelist_build(engine);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index aca676e79948..75ee027abb80 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9597,7 +9597,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
*/
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_GEN(dev_priv, 11))
+ if (IS_GEN(dev_priv, 12))
+ dev_priv->display.init_clock_gating = nop_init_clock_gating;
+ else if (IS_GEN(dev_priv, 11))
dev_priv->display.init_clock_gating = icl_init_clock_gating;
else if (IS_CANNONLAKE(dev_priv))
dev_priv->display.init_clock_gating = cnl_init_clock_gating;
--
2.21.0
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 19/39] drm/i915/tgl: Implement Wa_1406941453
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (17 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 18/39] drm/i915/tgl: Introduce initial Tiger Lake workarounds Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-16 8:04 ` [PATCH 20/39] drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating Lucas De Marchi
` (23 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx; +Cc: Michel Thierry
From: Michel Thierry <michel.thierry@intel.com>
Enable Small PL for power benefit.
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 126ab3667919..b58e1e6e610f 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1260,6 +1260,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
+ if (IS_GEN(i915, 12)) {
+ /* Wa_1406941453:tgl */
+ wa_masked_en(wal,
+ SAMPLER_MODE,
+ SAMPLER_ENABLE_SMALL_PL);
+ }
+
if (IS_GEN(i915, 11)) {
/* This is not an Wa. Enable for better image quality */
wa_masked_en(wal,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c836af0b8231..10e6c47c4149 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9027,6 +9027,9 @@ enum {
#define GEN9_DG_MIRROR_FIX_ENABLE (1 << 5)
#define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3)
+#define SAMPLER_MODE _MMIO(0xe18c)
+#define SAMPLER_ENABLE_SMALL_PL (1 << 15)
+
#define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
#define FLOW_CONTROL_ENABLE (1 << 15)
#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1 << 8)
--
2.21.0
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 20/39] drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (18 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 19/39] drm/i915/tgl: Implement Wa_1406941453 Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-16 8:04 ` [PATCH 21/39] drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards Lucas De Marchi
` (22 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx; +Cc: Michel Thierry
From: Michel Thierry <michel.thierry@intel.com>
HCP/MFX power gating is disabled by default, turn it on for the vd units
available. User space will also issue a MI_FORCE_WAKEUP properly to
wake up proper subwell.
During driver load, init_clock_gating happens after device_info_init_mmio
read the vdbox disable fuse register, so only present vd units will have
these enabled.
BSpec: 14214
HSDES: 1209977827
Cc: Tony Ye <tony.ye@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
drivers/gpu/drm/i915/intel_pm.c | 17 ++++++++++++++++-
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 10e6c47c4149..a64b1c4cd7bf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8682,6 +8682,10 @@ enum {
#define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0)
#define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1)
+#define POWERGATE_ENABLE _MMIO(0xa210)
+#define VDN_HCP_POWERGATE_ENABLE(n) BIT(((n) * 2) + 3)
+#define VDN_MFX_POWERGATE_ENABLE(n) BIT(((n) * 2) + 4)
+
#define GTFIFODBG _MMIO(0x120000)
#define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20)
#define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 75ee027abb80..604c53793726 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9078,6 +9078,21 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
_MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE));
}
+static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+ u32 vd_pg_enable = 0;
+ unsigned int i;
+
+ /* This is not a WA. Enable VD HCP & MFX_ENC powergate */
+ for (i = 0; i < I915_MAX_VCS; i++) {
+ if (HAS_ENGINE(dev_priv, _VCS(i)))
+ vd_pg_enable |= VDN_HCP_POWERGATE_ENABLE(i) |
+ VDN_MFX_POWERGATE_ENABLE(i);
+ }
+ I915_WRITE(POWERGATE_ENABLE,
+ I915_READ(POWERGATE_ENABLE) | vd_pg_enable);
+}
+
static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
{
if (!HAS_PCH_CNP(dev_priv))
@@ -9598,7 +9613,7 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
if (IS_GEN(dev_priv, 12))
- dev_priv->display.init_clock_gating = nop_init_clock_gating;
+ dev_priv->display.init_clock_gating = tgl_init_clock_gating;
else if (IS_GEN(dev_priv, 11))
dev_priv->display.init_clock_gating = icl_init_clock_gating;
else if (IS_CANNONLAKE(dev_priv))
--
2.21.0
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 21/39] drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (19 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 20/39] drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-16 8:04 ` [PATCH 22/39] drm/i915/tgl: implement WaProgramMgsrForCorrectSliceSpecificMmioReads Lucas De Marchi
` (21 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx; +Cc: Michel Thierry
From: Michel Thierry <michel.thierry@intel.com>
Workaround no longer needed (plus L3_LRA_1_GPGPU doesn't exist).
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index fcf05c213b0a..536eadf095fe 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2012,7 +2012,7 @@ static void gtt_write_workarounds(struct intel_gt *gt)
intel_uncore_write(uncore,
GEN8_L3_LRA_1_GPGPU,
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
- else if (INTEL_GEN(i915) >= 9)
+ else if (INTEL_GEN(i915) >= 9 && INTEL_GEN(i915) <= 11)
intel_uncore_write(uncore,
GEN8_L3_LRA_1_GPGPU,
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
--
2.21.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 22/39] drm/i915/tgl: implement WaProgramMgsrForCorrectSliceSpecificMmioReads
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (20 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 21/39] drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-16 8:04 ` [PATCH 23/39] drm/i915/tgl: Register state context definition for Gen12 Lucas De Marchi
` (20 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx
From my tests this workaround is needed otherwise we read the wrong
number of slices later on. It's sent as a FIXME since I couldn't find
any documentation saying this applies to TGL. Fix the following warning:
[ 82.905527] WARN_ON_ONCE((mcr & mcr_slice_subslice_mask) != default_mcr_s_ss_
select)
[ 82.905618] WARNING: CPU: 3 PID: 1118 at drivers/gpu/drm/i915/intel_engine_cs
.c:927 intel_engine_get_instdone+0x4c4/0x530 [i915]
[ 82.905629] Modules linked in: i915
[ 82.905642] CPU: 3 PID: 1118 Comm: cat Tainted: G U W 4.17.0-rc7
-demarchi+ #7
[ 82.905653] Hardware name: Bochs Bochs, BIOS Bochs 01/01/2007
[ 82.905711] RIP: 0010:intel_engine_get_instdone+0x4c4/0x530 [i915]
[ 82.905722] RSP: 0018:ffffb5a381317be8 EFLAGS: 00010092
[ 82.905734] RAX: 0000000000000048 RBX: 0000000008000000 RCX: ffffffff9165c748
[ 82.905745] RDX: 0000000000000001 RSI: 0000000000000086 RDI: 0000000000000087
[ 82.905756] RBP: 0000000000000001 R08: 297463656c65735f R09: 00000000000003c2
[ 82.905768] R10: 5f746c7561666564 R11: 73735f735f72636d R12: 0000000000000000
[ 82.905779] R13: 0000000000000000 R14: ffff98b598a00000 R15: 0000000000000000
[ 82.905791] FS: 00007f6e6fa5e500(0000) GS:ffff98b5bfb80000(0000) knlGS:00000
00000000000
[ 82.905802] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 82.905813] CR2: 00007f6e6fa3b000 CR3: 0000000232606000 CR4: 00000000000006e0
[ 82.905824] Call Trace:
[ 82.905883] i915_hangcheck_info+0xf7/0x3d0 [i915]
[ 82.905898] seq_read+0x15b/0x440
[ 82.905911] ? __handle_mm_fault+0xaf9/0x1270
[ 82.905923] full_proxy_read+0x53/0x80
[ 82.905936] __vfs_read+0x26/0x140
[ 82.905949] vfs_read+0x8a/0x140
[ 82.905961] ksys_read+0x3f/0xa0
[ 82.905974] do_syscall_64+0x5b/0x160
[ 82.905986] entry_SYSCALL_64_after_hwframe+0x44/0xa9
[ 82.905998] RIP: 0033:0x7f6e6f585701
[ 82.906009] RSP: 002b:00007ffff94652e8 EFLAGS: 00000246 ORIG_RAX: 00000000000
CC: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b58e1e6e610f..a227a0272f3c 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -768,7 +768,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
* by default, to make sure we correctly read certain registers
* later on (in the range 0xB100 - 0xB3FF).
*
- * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
+ * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl,tgl
* Before any MMIO read into slice/subslice specific registers, MCR
* packet control register needs to be programmed to point to any
* enabled s/ss pair. Otherwise, incorrect values will be returned.
@@ -900,6 +900,7 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
static void
tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
+ wa_init_mcr(i915, wal);
}
static void
--
2.21.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 23/39] drm/i915/tgl: Register state context definition for Gen12
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (21 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 22/39] drm/i915/tgl: implement WaProgramMgsrForCorrectSliceSpecificMmioReads Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-16 8:04 ` [PATCH 24/39] drm/i915/tgl: move DP_TP_* to transcoder Lucas De Marchi
` (19 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx; +Cc: Michel Thierry
From: Michel Thierry <michel.thierry@intel.com>
Gen12 has subtle changes in the reg state context offsets (some fields
are gone, some are in a different location), compared to previous Gens.
The simplest approach seems to be keeping Gen12 (and future platform)
changes apart from the previous gens, while keeping the registers that
are contiguous in functions we can reuse.
v2: 'gen8' prefix in the legacy function (Michal)
v3: Rebase (clear save-inhibit bit).
v4: Group some registers into functions (helps to catch any changes in
the gen8 path), fix length of first LRI for non-rcs to include the semaphore
token, skip the GEN12_CTX_LRI_HEADER_2 that is always empty for now (Daniele)
v5: Rebase! ctx->ppgtt is no more (Lucas)
Bspec: 20202
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 156 +++++++++++++++++-------
drivers/gpu/drm/i915/gt/intel_lrc.h | 2 +
drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 30 ++++-
3 files changed, 143 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index fafae7c7af0d..35a5ad575e12 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2999,28 +2999,12 @@ static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
return indirect_ctx_offset;
}
-static void execlists_init_reg_state(u32 *regs,
- struct intel_context *ce,
- struct intel_engine_cs *engine,
- struct intel_ring *ring)
+static void init_common_reg_state(u32 *regs,
+ struct intel_engine_cs *engine,
+ struct intel_ring *ring)
{
- struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ce->vm);
- bool rcs = engine->class == RENDER_CLASS;
u32 base = engine->mmio_base;
- /*
- * A context is actually a big batch buffer with several
- * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
- * values we are setting here are only for the first context restore:
- * on a subsequent save, the GPU will recreate this batchbuffer with new
- * values (including all the missing MI_LOAD_REGISTER_IMM commands that
- * we are not initializing here).
- *
- * Must keep consistent with virtual_update_register_offsets().
- */
- regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
- MI_LRI_FORCE_POSTED;
-
CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(base),
_MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) |
_MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH));
@@ -3037,38 +3021,44 @@ static void execlists_init_reg_state(u32 *regs,
CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0);
CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0);
CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT);
- CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0);
- CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0);
- CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0);
- if (rcs) {
- struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
-
- CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0);
- CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET,
- RING_INDIRECT_CTX_OFFSET(base), 0);
- if (wa_ctx->indirect_ctx.size) {
- u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
+}
- regs[CTX_RCS_INDIRECT_CTX + 1] =
- (ggtt_offset + wa_ctx->indirect_ctx.offset) |
- (wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
+static void init_wa_bb_reg_state(u32 *regs,
+ struct intel_engine_cs *engine,
+ u32 pos_bb_per_ctx)
+{
+ struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
+ u32 base = engine->mmio_base;
+ u32 pos_indirect_ctx = pos_bb_per_ctx + 2;
+ u32 pos_indirect_ctx_offset = pos_indirect_ctx + 2;
- regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] =
- intel_lr_indirect_ctx_offset(engine) << 6;
- }
+ GEM_BUG_ON(engine->id != RCS0);
+ CTX_REG(regs, pos_indirect_ctx, RING_INDIRECT_CTX(base), 0);
+ CTX_REG(regs, pos_indirect_ctx_offset,
+ RING_INDIRECT_CTX_OFFSET(base), 0);
+ if (wa_ctx->indirect_ctx.size) {
+ u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
- CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0);
- if (wa_ctx->per_ctx.size) {
- u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
+ regs[pos_indirect_ctx + 1] =
+ (ggtt_offset + wa_ctx->indirect_ctx.offset) |
+ (wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
- regs[CTX_BB_PER_CTX_PTR + 1] =
- (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
- }
+ regs[pos_indirect_ctx_offset + 1] =
+ intel_lr_indirect_ctx_offset(engine) << 6;
}
- regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
+ CTX_REG(regs, pos_bb_per_ctx, RING_BB_PER_CTX_PTR(base), 0);
+ if (wa_ctx->per_ctx.size) {
+ u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
- CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0);
+ regs[pos_bb_per_ctx + 1] =
+ (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
+ }
+}
+
+static void init_ppgtt_reg_state(u32 *regs, u32 base,
+ struct i915_ppgtt *ppgtt)
+{
/* PDP values well be assigned later if needed */
CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(base, 3), 0);
CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(base, 3), 0);
@@ -3091,6 +3081,32 @@ static void execlists_init_reg_state(u32 *regs,
ASSIGN_CTX_PDP(ppgtt, regs, 1);
ASSIGN_CTX_PDP(ppgtt, regs, 0);
}
+}
+
+static void gen8_init_reg_state(u32 *regs,
+ struct intel_context *ce,
+ struct intel_engine_cs *engine,
+ struct intel_ring *ring)
+{
+ struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ce->vm);
+ bool rcs = engine->class == RENDER_CLASS;
+ u32 base = engine->mmio_base;
+
+ regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
+ MI_LRI_FORCE_POSTED;
+
+ init_common_reg_state(regs, engine, ring);
+ CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0);
+ CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0);
+ CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0);
+ if (rcs)
+ init_wa_bb_reg_state(regs, engine, CTX_BB_PER_CTX_PTR);
+
+ regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
+
+ CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0);
+
+ init_ppgtt_reg_state(regs, base, ppgtt);
if (rcs) {
regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
@@ -3102,6 +3118,58 @@ static void execlists_init_reg_state(u32 *regs,
regs[CTX_END] |= BIT(0);
}
+static void gen12_init_reg_state(u32 *regs,
+ struct intel_context *ce,
+ struct intel_engine_cs *engine,
+ struct intel_ring *ring)
+{
+ struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ce->vm);
+ bool rcs = engine->class == RENDER_CLASS;
+ u32 base = engine->mmio_base;
+
+ GEM_DEBUG_EXEC(DRM_INFO_ONCE("Using GEN12 Register State Context\n"));
+
+ regs[GEN12_CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(13) |
+ MI_LRI_FORCE_POSTED;
+
+ init_common_reg_state(regs, engine, ring);
+ if (rcs)
+ init_wa_bb_reg_state(regs, engine, GEN12_CTX_BB_PER_CTX_PTR);
+
+ regs[GEN12_CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) |
+ MI_LRI_FORCE_POSTED;
+
+ CTX_REG(regs, GEN12_CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0);
+
+ init_ppgtt_reg_state(regs, base, ppgtt);
+
+ if (rcs) {
+ regs[GEN12_CTX_LRI_HEADER_3] = MI_LOAD_REGISTER_IMM(1);
+ CTX_REG(regs, GEN12_CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
+ 0);
+
+ /* TODO: oa_init_reg_state ? */
+ }
+}
+
+static void execlists_init_reg_state(u32 *regs,
+ struct intel_context *ce,
+ struct intel_engine_cs *engine,
+ struct intel_ring *ring)
+{
+ /* A context is actually a big batch buffer with several
+ * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
+ * values we are setting here are only for the first context restore:
+ * on a subsequent save, the GPU will recreate this batchbuffer with new
+ * values (including all the missing MI_LOAD_REGISTER_IMM commands that
+ * we are not initializing here).
+ */
+ if (INTEL_GEN(engine->i915) >= 12)
+ gen12_init_reg_state(regs, ce, engine, ring);
+ else
+ gen8_init_reg_state(regs, ce, engine, ring);
+}
+
static int
populate_lr_context(struct intel_context *ce,
struct drm_i915_gem_object *ctx_obj,
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h b/drivers/gpu/drm/i915/gt/intel_lrc.h
index c2bba82bcc16..69285d354d9b 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
@@ -49,6 +49,8 @@ struct intel_engine_cs;
#define EL_CTRL_LOAD (1 << 0)
+#define GEN12_ENGINE_SEMAPHORE_TOKEN(engine) _MMIO((engine)->mmio_base + 0x2b4)
+
/* The docs specify that the write pointer wraps around after 5h, "After status
* is written out to the last available status QW at offset 5h, this pointer
* wraps to 0."
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
index 6bf34738b4e5..915824ebaf17 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
@@ -9,7 +9,7 @@
#include <linux/types.h>
-/* GEN8+ Reg State Context */
+/* GEN8 to GEN11 Reg State Context */
#define CTX_LRI_HEADER_0 0x01
#define CTX_CONTEXT_CONTROL 0x02
#define CTX_RING_HEAD 0x04
@@ -39,6 +39,34 @@
#define CTX_R_PWR_CLK_STATE 0x42
#define CTX_END 0x44
+/* GEN12+ Reg State Context */
+#define GEN12_CTX_LRI_HEADER_0 CTX_LRI_HEADER_0
+#define GEN12_CTX_CONTEXT_CONTROL CTX_CONTEXT_CONTROL
+#define GEN12_CTX_RING_HEAD CTX_RING_HEAD
+#define GEN12_CTX_RING_TAIL CTX_RING_TAIL
+#define GEN12_CTX_RING_BUFFER_START CTX_RING_BUFFER_START
+#define GEN12_CTX_RING_BUFFER_CONTROL CTX_RING_BUFFER_CONTROL
+#define GEN12_CTX_BB_HEAD_U CTX_BB_HEAD_U
+#define GEN12_CTX_BB_HEAD_L CTX_BB_HEAD_L
+#define GEN12_CTX_BB_STATE CTX_BB_STATE
+#define GEN12_CTX_BB_PER_CTX_PTR 0x12
+#define GEN12_CTX_RCS_INDIRECT_CTX 0x14
+#define GEN12_CTX_RCS_INDIRECT_CTX_OFFSET 0x16
+#define GEN12_CTX_LRI_HEADER_1 CTX_LRI_HEADER_1
+#define GEN12_CTX_CTX_TIMESTAMP CTX_CTX_TIMESTAMP
+#define GEN12_CTX_PDP3_UDW CTX_PDP3_UDW
+#define GEN12_CTX_PDP3_LDW CTX_PDP3_LDW
+#define GEN12_CTX_PDP2_UDW CTX_PDP2_UDW
+#define GEN12_CTX_PDP2_LDW CTX_PDP2_LDW
+#define GEN12_CTX_PDP1_UDW CTX_PDP1_UDW
+#define GEN12_CTX_PDP1_LDW CTX_PDP1_LDW
+#define GEN12_CTX_PDP0_UDW CTX_PDP0_UDW
+#define GEN12_CTX_PDP0_LDW CTX_PDP0_LDW
+#define GEN12_CTX_LRI_HEADER_2 0x34
+#define GEN12_CTX_LRI_HEADER_3 0x41
+#define GEN12_CTX_R_PWR_CLK_STATE 0x42
+#define GEN12_CTX_GPGPU_CSR_BASE_ADDRESS 0x44
+
#define CTX_REG(reg_state, pos, reg, val) do { \
u32 *reg_state__ = (reg_state); \
const u32 pos__ = (pos); \
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 24/39] drm/i915/tgl: move DP_TP_* to transcoder
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (22 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 23/39] drm/i915/tgl: Register state context definition for Gen12 Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-16 8:04 ` [PATCH 25/39] drm/i915/tgl: Implement TGL DisplayPort training sequence Lucas De Marchi
` (18 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx
Gen 12 onwards moves the DP_TP_* registers to be transcoder-based rather
than port-based. This add the new register address and changes the
functions that are used with DDI on gen 12 to use the new registers. On
MST the master transcoder is the one to be used.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 42 ++++++++----
.../drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 66 +++++++++++++++++--
drivers/gpu/drm/i915/display/intel_dp.h | 9 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 20 ++++--
drivers/gpu/drm/i915/i915_reg.h | 4 ++
6 files changed, 119 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index c26dee8521f6..17d49c77faa0 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3135,17 +3135,22 @@ static void intel_ddi_enable_fec(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
enum port port = encoder->port;
+ i915_reg_t ctl, status;
u32 val;
if (!crtc_state->fec_enable)
return;
- val = I915_READ(DP_TP_CTL(port));
+ ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
+ status = intel_dp_tp_status_reg(dev_priv, cpu_transcoder, port);
+
+ val = I915_READ(ctl);
val |= DP_TP_CTL_FEC_ENABLE;
- I915_WRITE(DP_TP_CTL(port), val);
+ I915_WRITE(ctl, val);
- if (intel_wait_for_register(&dev_priv->uncore, DP_TP_STATUS(port),
+ if (intel_wait_for_register(&dev_priv->uncore, status,
DP_TP_STATUS_FEC_ENABLE_LIVE,
DP_TP_STATUS_FEC_ENABLE_LIVE,
1))
@@ -3156,16 +3161,19 @@ static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
enum port port = encoder->port;
+ i915_reg_t ctl;
u32 val;
if (!crtc_state->fec_enable)
return;
- val = I915_READ(DP_TP_CTL(port));
+ ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
+ val = I915_READ(ctl);
val &= ~DP_TP_CTL_FEC_ENABLE;
- I915_WRITE(DP_TP_CTL(port), val);
- POSTING_READ(DP_TP_CTL(port));
+ I915_WRITE(ctl, val);
+ POSTING_READ(ctl);
}
static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
@@ -3327,7 +3335,9 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
enum port port = encoder->port;
+ i915_reg_t ctl;
bool wait = false;
u32 val;
@@ -3338,10 +3348,11 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
wait = true;
}
- val = I915_READ(DP_TP_CTL(port));
+ ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
+ val = I915_READ(ctl);
val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
val |= DP_TP_CTL_LINK_TRAIN_PAT1;
- I915_WRITE(DP_TP_CTL(port), val);
+ I915_WRITE(ctl, val);
/* Disable FEC in DP Sink */
intel_ddi_disable_fec_state(encoder, crtc_state);
@@ -3766,10 +3777,13 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv =
to_i915(intel_dig_port->base.base.dev);
enum port port = intel_dig_port->base.port;
+ i915_reg_t ctl;
u32 val;
bool wait = false;
+ enum transcoder cpu_transcoder = intel_dp_get_transcoder(intel_dp);
- if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
+ ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
+ if (I915_READ(ctl) & DP_TP_CTL_ENABLE) {
val = I915_READ(DDI_BUF_CTL(port));
if (val & DDI_BUF_CTL_ENABLE) {
val &= ~DDI_BUF_CTL_ENABLE;
@@ -3777,11 +3791,11 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
wait = true;
}
- val = I915_READ(DP_TP_CTL(port));
+ val = I915_READ(ctl);
val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
val |= DP_TP_CTL_LINK_TRAIN_PAT1;
- I915_WRITE(DP_TP_CTL(port), val);
- POSTING_READ(DP_TP_CTL(port));
+ I915_WRITE(ctl, val);
+ POSTING_READ(ctl);
if (wait)
intel_wait_ddi_buf_idle(dev_priv, port);
@@ -3796,8 +3810,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
}
- I915_WRITE(DP_TP_CTL(port), val);
- POSTING_READ(DP_TP_CTL(port));
+ I915_WRITE(ctl, val);
+ POSTING_READ(ctl);
intel_dp->DP |= DDI_BUF_CTL_ENABLE;
I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 54d1053ff6d0..caf5e2b50c0c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1213,6 +1213,7 @@ struct intel_dp {
bool can_mst; /* this port supports mst */
bool is_mst;
int active_mst_links;
+ enum transcoder mst_master_trans; /* Only valid on TGL+ */
/* connector directly attached - won't be use for modeset in mst world */
struct intel_connector *attached_connector;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4884c87c8ed7..ebfcf183c7f1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3206,6 +3206,51 @@ static void chv_post_disable_dp(struct intel_encoder *encoder,
vlv_dpio_put(dev_priv);
}
+i915_reg_t intel_dp_tp_ctl_reg(const struct drm_i915_private *dev_priv,
+ enum transcoder cpu_transcoder,
+ enum port port)
+{
+ if (INTEL_GEN(dev_priv) >= 12) {
+ WARN_ON(cpu_transcoder == TRANSCODER_INVALID);
+ return TGL_DP_TP_CTL(cpu_transcoder);
+ } else {
+ return DP_TP_CTL(port);
+ }
+}
+
+i915_reg_t intel_dp_tp_status_reg(const struct drm_i915_private *dev_priv,
+ enum transcoder cpu_transcoder,
+ enum port port)
+{
+ if (INTEL_GEN(dev_priv) >= 12) {
+ WARN_ON(cpu_transcoder == TRANSCODER_INVALID);
+ return TGL_DP_TP_STATUS(cpu_transcoder);
+ } else {
+ return DP_TP_STATUS(port);
+ }
+}
+
+/*
+ * Return the transcoder that this intel_dp port is driven.
+ * When in MST mode it will return the master transcoder of the MST so do not
+ * use it when reading or writing registers in the slave transcoders.
+ */
+enum transcoder intel_dp_get_transcoder(struct intel_dp *intel_dp)
+{
+ struct intel_connector *connector;
+ struct drm_connector_state *conn_state;
+ struct intel_crtc_state *crtc_state;
+
+ if (intel_dp->is_mst)
+ return intel_dp->mst_master_trans;
+
+ connector = intel_dp->attached_connector;
+ conn_state = connector->base.state;
+ crtc_state = to_intel_crtc_state(conn_state->crtc->state);
+
+ return crtc_state->cpu_transcoder;
+}
+
static void
_intel_dp_set_link_train(struct intel_dp *intel_dp,
u32 *DP,
@@ -3221,8 +3266,13 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
dp_train_pat & train_pat_mask);
if (HAS_DDI(dev_priv)) {
- u32 temp = I915_READ(DP_TP_CTL(port));
+ enum transcoder cpu_transcoder;
+ i915_reg_t ctl;
+ u32 temp;
+ cpu_transcoder = intel_dp_get_transcoder(intel_dp);
+ ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
+ temp = I915_READ(ctl);
if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
else
@@ -3247,7 +3297,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
break;
}
- I915_WRITE(DP_TP_CTL(port), temp);
+ I915_WRITE(ctl, temp);
} else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
(HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
@@ -3940,15 +3990,21 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
enum port port = intel_dig_port->base.port;
+ enum transcoder cpu_transcoder;
+ i915_reg_t ctl, status;
u32 val;
if (!HAS_DDI(dev_priv))
return;
- val = I915_READ(DP_TP_CTL(port));
+ cpu_transcoder = intel_dp_get_transcoder(intel_dp);
+ ctl = intel_dp_tp_ctl_reg(dev_priv, cpu_transcoder, port);
+ status = intel_dp_tp_status_reg(dev_priv, cpu_transcoder, port);
+
+ val = I915_READ(ctl);
val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
val |= DP_TP_CTL_LINK_TRAIN_IDLE;
- I915_WRITE(DP_TP_CTL(port), val);
+ I915_WRITE(ctl, val);
/*
* On PORT_A we can have only eDP in SST mode. There the only reason
@@ -3960,7 +4016,7 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
if (port == PORT_A)
return;
- if (intel_wait_for_register(&dev_priv->uncore, DP_TP_STATUS(port),
+ if (intel_wait_for_register(&dev_priv->uncore, status,
DP_TP_STATUS_IDLE_DONE,
DP_TP_STATUS_IDLE_DONE,
1))
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 657bbb1f5ed0..107129b5d9a3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -11,6 +11,7 @@
#include <drm/i915_drm.h>
#include "i915_reg.h"
+#include "intel_display.h"
enum pipe;
struct drm_connector_state;
@@ -113,6 +114,14 @@ int intel_dp_link_required(int pixel_clock, int bpp);
int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
bool intel_digital_port_connected(struct intel_encoder *encoder);
+i915_reg_t intel_dp_tp_ctl_reg(const struct drm_i915_private *dev_priv,
+ enum transcoder cpu_transcoder,
+ enum port port);
+i915_reg_t intel_dp_tp_status_reg(const struct drm_i915_private *dev_priv,
+ enum transcoder cpu_transcoder,
+ enum port port);
+enum transcoder intel_dp_get_transcoder(struct intel_dp *intel_dp);
+
static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
{
return ~((1 << lane_count) - 1) & 0xf;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 75c9db85f2b0..7c14c349f666 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -354,9 +354,11 @@ static void intel_mst_pre_pll_enable_dp(struct intel_encoder *encoder,
struct intel_digital_port *intel_dig_port = intel_mst->primary;
struct intel_dp *intel_dp = &intel_dig_port->dp;
- if (intel_dp->active_mst_links == 0)
+ if (intel_dp->active_mst_links == 0) {
+ intel_dp->mst_master_trans = pipe_config->mst_master_trans;
intel_dig_port->base.pre_pll_enable(&intel_dig_port->base,
pipe_config, NULL);
+ }
}
static void intel_mst_post_pll_disable_dp(struct intel_encoder *encoder,
@@ -384,6 +386,7 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
enum port port = intel_dig_port->base.port;
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
+ i915_reg_t status;
int ret;
u32 temp;
@@ -412,8 +415,12 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
DRM_ERROR("failed to allocate vcpi\n");
intel_dp->active_mst_links++;
- temp = I915_READ(DP_TP_STATUS(port));
- I915_WRITE(DP_TP_STATUS(port), temp);
+
+ status = intel_dp_tp_status_reg(dev_priv,
+ pipe_config->mst_master_trans,
+ port);
+ temp = I915_READ(status);
+ I915_WRITE(status, temp);
ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr);
@@ -429,11 +436,16 @@ static void intel_mst_enable_dp(struct intel_encoder *encoder,
struct intel_dp *intel_dp = &intel_dig_port->dp;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = intel_dig_port->base.port;
+ i915_reg_t status;
DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
+ status = intel_dp_tp_status_reg(dev_priv,
+ pipe_config->mst_master_trans,
+ port);
+
if (intel_wait_for_register(&dev_priv->uncore,
- DP_TP_STATUS(port),
+ status,
DP_TP_STATUS_ACT_SENT,
DP_TP_STATUS_ACT_SENT,
1))
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a64b1c4cd7bf..eca8295aba9e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9517,7 +9517,9 @@ enum skl_power_gate {
/* DisplayPort Transport Control */
#define _DP_TP_CTL_A 0x64040
#define _DP_TP_CTL_B 0x64140
+#define _TGL_DP_TP_CTL_A 0x60540
#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
+#define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A)
#define DP_TP_CTL_ENABLE (1 << 31)
#define DP_TP_CTL_FEC_ENABLE (1 << 30)
#define DP_TP_CTL_MODE_SST (0 << 27)
@@ -9537,7 +9539,9 @@ enum skl_power_gate {
/* DisplayPort Transport Status */
#define _DP_TP_STATUS_A 0x64044
#define _DP_TP_STATUS_B 0x64144
+#define _TGL_DP_TP_STATUS_A 0x60544
#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
+#define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A)
#define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28)
#define DP_TP_STATUS_IDLE_DONE (1 << 25)
#define DP_TP_STATUS_ACT_SENT (1 << 24)
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 25/39] drm/i915/tgl: Implement TGL DisplayPort training sequence
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (23 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 24/39] drm/i915/tgl: move DP_TP_* to transcoder Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-19 14:21 ` Maarten Lankhorst
2019-08-16 8:04 ` [PATCH 26/39] HACK: drm/i915/tgl: Gen12 render context size Lucas De Marchi
` (17 subsequent siblings)
42 siblings, 1 reply; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
On TGL some registers moved from DDI to transcoder and the
DisplayPort training sequence has a separate BSpec page.
I started adding 'ifs' to the original intel_ddi_pre_enable_dp() but
it was becoming really hard to follow, so a new and cleaner function
for TGL was added with comments of all steps. It's similar to ICL, but
different enough to deserve a new function
The rest of DisplayPort enable and the whole disable sequences
remained the same.
BSpec: 49190
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 134 ++++++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_dp.c | 8 +-
2 files changed, 134 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 17d49c77faa0..5d971e9d0459 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1761,7 +1761,14 @@ void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
}
-void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
+/*
+ * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
+ *
+ * Only intended to be used by intel_ddi_enable_transcoder_func() and
+ * intel_ddi_config_transcoder_func().
+ */
+static u32
+intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
@@ -1851,6 +1858,33 @@ void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
}
+ return temp;
+}
+
+void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 temp;
+
+ temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
+ I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
+}
+
+/*
+ * Same as intel_ddi_enable_transcoder_func() but it do not set the enable bit
+ */
+static void
+intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 temp;
+
+ temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
+ temp &= ~TRANS_DDI_FUNC_ENABLE;
I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
}
@@ -3176,9 +3210,89 @@ static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
POSTING_READ(ctl);
}
-static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
+static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+ struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+ bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
+ int level = intel_ddi_dp_level(intel_dp);
+
+ intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
+ crtc_state->lane_count, is_mst);
+
+ /* 1.a got on intel_atomic_commit_tail() */
+
+ /* 2. */
+ intel_edp_panel_on(intel_dp);
+
+ /*
+ * 1.b, 3. and 4. is done by before this functions by
+ * haswell_crtc_enable()->intel_encoders_pre_pll_enable() and
+ * haswell_crtc_enable()->intel_enable_shared_dpll()
+ */
+
+ /* 5. */
+ if (!intel_phy_is_tc(dev_priv, phy) ||
+ dig_port->tc_mode != TC_PORT_TBT_ALT)
+ intel_display_power_get(dev_priv,
+ dig_port->ddi_io_power_domain);
+
+ /* 6. */
+ icl_program_mg_dp_mode(dig_port);
+
+ /*
+ * 7.a - Steps in this function that should only be executed over MST
+ * master as MST encoders will only be executed on MST master as MST
+ * encoder have have it's own pre_enable() hook
+ */
+ intel_ddi_enable_pipe_clock(crtc_state);
+
+ /* 7.b */
+ intel_ddi_config_transcoder_func(crtc_state);
+
+ /* 7.d */
+ icl_disable_phy_clock_gating(dig_port);
+
+ /* 7.e */
+ icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
+ encoder->type);
+
+ /* 7.f */
+ if (intel_phy_is_combo(dev_priv, phy)) {
+ bool lane_reversal =
+ dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
+
+ intel_combo_phy_power_up_lanes(dev_priv, phy, false,
+ crtc_state->lane_count,
+ lane_reversal);
+ }
+
+ /* 7.g */
+ intel_ddi_init_dp_buf_reg(encoder);
+
+ if (!is_mst)
+ intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+
+ /* 7.c, 7.h, 7.i, 7.j */
+ intel_dp_start_link_train(intel_dp);
+
+ /* 7.k */
+ intel_dp_stop_link_train(intel_dp);
+
+ /* 7.l */
+ intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
+ true);
+ intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
+ intel_dsc_enable(encoder, crtc_state);
+}
+
+static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
{
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -3244,6 +3358,18 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
intel_dsc_enable(encoder, crtc_state);
}
+static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ tgl_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
+ else
+ hsw_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
+}
+
static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index ebfcf183c7f1..1a8e041a5c43 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4007,13 +4007,13 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
I915_WRITE(ctl, val);
/*
- * On PORT_A we can have only eDP in SST mode. There the only reason
- * we need to set idle transmission mode is to work around a HW issue
- * where we enable the pipe while not in idle link-training mode.
+ * Until TGL on PORT_A we can have only eDP in SST mode. There the only
+ * reason we need to set idle transmission mode is to work around a HW
+ * issue where we enable the pipe while not in idle link-training mode.
* In this case there is requirement to wait for a minimum number of
* idle patterns to be sent.
*/
- if (port == PORT_A)
+ if (port == PORT_A && INTEL_GEN(dev_priv) < 12)
return;
if (intel_wait_for_register(&dev_priv->uncore, status,
--
2.21.0
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^ permalink raw reply related [flat|nested] 58+ messages in thread* Re: [PATCH 25/39] drm/i915/tgl: Implement TGL DisplayPort training sequence
2019-08-16 8:04 ` [PATCH 25/39] drm/i915/tgl: Implement TGL DisplayPort training sequence Lucas De Marchi
@ 2019-08-19 14:21 ` Maarten Lankhorst
2019-08-19 21:26 ` Souza, Jose
0 siblings, 1 reply; 58+ messages in thread
From: Maarten Lankhorst @ 2019-08-19 14:21 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx
Op 16-08-2019 om 10:04 schreef Lucas De Marchi:
> From: José Roberto de Souza <jose.souza@intel.com>
>
> On TGL some registers moved from DDI to transcoder and the
> DisplayPort training sequence has a separate BSpec page.
>
> I started adding 'ifs' to the original intel_ddi_pre_enable_dp() but
> it was becoming really hard to follow, so a new and cleaner function
> for TGL was added with comments of all steps. It's similar to ICL, but
> different enough to deserve a new function
>
> The rest of DisplayPort enable and the whole disable sequences
> remained the same.
>
> BSpec: 49190
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 134 ++++++++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_dp.c | 8 +-
> 2 files changed, 134 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 17d49c77faa0..5d971e9d0459 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1761,7 +1761,14 @@ void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
> I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
> }
>
> -void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
> +/*
> + * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
> + *
> + * Only intended to be used by intel_ddi_enable_transcoder_func() and
> + * intel_ddi_config_transcoder_func().
> + */
> +static u32
> +intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
> @@ -1851,6 +1858,33 @@ void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
> temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
> }
>
> + return temp;
> +}
> +
> +void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + u32 temp;
> +
> + temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
> + I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
> +}
> +
> +/*
> + * Same as intel_ddi_enable_transcoder_func() but it do not set the enable bit
> + */
> +static void
> +intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + u32 temp;
> +
> + temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
> + temp &= ~TRANS_DDI_FUNC_ENABLE;
> I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
> }
>
> @@ -3176,9 +3210,89 @@ static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
> POSTING_READ(ctl);
> }
>
> -static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> - const struct intel_crtc_state *crtc_state,
> - const struct drm_connector_state *conn_state)
> +static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + const struct drm_connector_state *conn_state)
> +{
> + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> + struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
> + bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
> + int level = intel_ddi_dp_level(intel_dp);
> +
> + intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
> + crtc_state->lane_count, is_mst);
> +
> + /* 1.a got on intel_atomic_commit_tail() */
> +
> + /* 2. */
> + intel_edp_panel_on(intel_dp);
> +
> + /*
> + * 1.b, 3. and 4. is done by before this functions by
> + * haswell_crtc_enable()->intel_encoders_pre_pll_enable() and
> + * haswell_crtc_enable()->intel_enable_shared_dpll()
> + */
> +
> + /* 5. */
> + if (!intel_phy_is_tc(dev_priv, phy) ||
> + dig_port->tc_mode != TC_PORT_TBT_ALT)
> + intel_display_power_get(dev_priv,
> + dig_port->ddi_io_power_domain);
> +
> + /* 6. */
> + icl_program_mg_dp_mode(dig_port);
> +
> + /*
> + * 7.a - Steps in this function that should only be executed over MST
> + * master as MST encoders will only be executed on MST master as MST
> + * encoder have have it's own pre_enable() hook
> + */
> + intel_ddi_enable_pipe_clock(crtc_state);
> +
> + /* 7.b */
> + intel_ddi_config_transcoder_func(crtc_state);
> +
> + /* 7.d */
> + icl_disable_phy_clock_gating(dig_port);
> +
> + /* 7.e */
> + icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
> + encoder->type);
> +
> + /* 7.f */
> + if (intel_phy_is_combo(dev_priv, phy)) {
> + bool lane_reversal =
> + dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> +
> + intel_combo_phy_power_up_lanes(dev_priv, phy, false,
> + crtc_state->lane_count,
> + lane_reversal);
> + }
> +
> + /* 7.g */
> + intel_ddi_init_dp_buf_reg(encoder);
> +
> + if (!is_mst)
> + intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> +
> + /* 7.c, 7.h, 7.i, 7.j */
> + intel_dp_start_link_train(intel_dp);
> +
> + /* 7.k */
> + intel_dp_stop_link_train(intel_dp);
> +
> + /* 7.l */
> + intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
> + true);
> + intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
See "DDI FEC" in bspec.
intel_dp_sink_set_fec_ready() needs to be called before link training,
intel_ddi_enable_fec() after.
Presumably this is the same for DSC.
> + intel_dsc_enable(encoder, crtc_state);
> +}
> +
> +static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + const struct drm_connector_state *conn_state)
> {
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> @@ -3244,6 +3358,18 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> intel_dsc_enable(encoder, crtc_state);
> }
>
> +static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + const struct drm_connector_state *conn_state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> + if (INTEL_GEN(dev_priv) >= 12)
> + tgl_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
> + else
> + hsw_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
> +}
> +
> static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state)
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index ebfcf183c7f1..1a8e041a5c43 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4007,13 +4007,13 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
> I915_WRITE(ctl, val);
>
> /*
> - * On PORT_A we can have only eDP in SST mode. There the only reason
> - * we need to set idle transmission mode is to work around a HW issue
> - * where we enable the pipe while not in idle link-training mode.
> + * Until TGL on PORT_A we can have only eDP in SST mode. There the only
> + * reason we need to set idle transmission mode is to work around a HW
> + * issue where we enable the pipe while not in idle link-training mode.
> * In this case there is requirement to wait for a minimum number of
> * idle patterns to be sent.
> */
> - if (port == PORT_A)
> + if (port == PORT_A && INTEL_GEN(dev_priv) < 12)
> return;
>
> if (intel_wait_for_register(&dev_priv->uncore, status,
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^ permalink raw reply [flat|nested] 58+ messages in thread* Re: [PATCH 25/39] drm/i915/tgl: Implement TGL DisplayPort training sequence
2019-08-19 14:21 ` Maarten Lankhorst
@ 2019-08-19 21:26 ` Souza, Jose
0 siblings, 0 replies; 58+ messages in thread
From: Souza, Jose @ 2019-08-19 21:26 UTC (permalink / raw)
To: maarten.lankhorst, intel-gfx, De Marchi, Lucas
On Mon, 2019-08-19 at 16:21 +0200, Maarten Lankhorst wrote:
> Op 16-08-2019 om 10:04 schreef Lucas De Marchi:
> > From: José Roberto de Souza <jose.souza@intel.com>
> >
> > On TGL some registers moved from DDI to transcoder and the
> > DisplayPort training sequence has a separate BSpec page.
> >
> > I started adding 'ifs' to the original intel_ddi_pre_enable_dp()
> > but
> > it was becoming really hard to follow, so a new and cleaner
> > function
> > for TGL was added with comments of all steps. It's similar to ICL,
> > but
> > different enough to deserve a new function
> >
> > The rest of DisplayPort enable and the whole disable sequences
> > remained the same.
> >
> > BSpec: 49190
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 134
> > ++++++++++++++++++++++-
> > drivers/gpu/drm/i915/display/intel_dp.c | 8 +-
> > 2 files changed, 134 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 17d49c77faa0..5d971e9d0459 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -1761,7 +1761,14 @@ void intel_ddi_set_vc_payload_alloc(const
> > struct intel_crtc_state *crtc_state,
> > I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
> > }
> >
> > -void intel_ddi_enable_transcoder_func(const struct
> > intel_crtc_state *crtc_state)
> > +/*
> > + * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
> > + *
> > + * Only intended to be used by intel_ddi_enable_transcoder_func()
> > and
> > + * intel_ddi_config_transcoder_func().
> > + */
> > +static u32
> > +intel_ddi_transcoder_func_reg_val_get(const struct
> > intel_crtc_state *crtc_state)
> > {
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > struct intel_encoder *encoder =
> > intel_ddi_get_crtc_encoder(crtc);
> > @@ -1851,6 +1858,33 @@ void intel_ddi_enable_transcoder_func(const
> > struct intel_crtc_state *crtc_state)
> > temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
> > }
> >
> > + return temp;
> > +}
> > +
> > +void intel_ddi_enable_transcoder_func(const struct
> > intel_crtc_state *crtc_state)
> > +{
> > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > + u32 temp;
> > +
> > + temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
> > + I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
> > +}
> > +
> > +/*
> > + * Same as intel_ddi_enable_transcoder_func() but it do not set
> > the enable bit
> > + */
> > +static void
> > +intel_ddi_config_transcoder_func(const struct intel_crtc_state
> > *crtc_state)
> > +{
> > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > + u32 temp;
> > +
> > + temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
> > + temp &= ~TRANS_DDI_FUNC_ENABLE;
> > I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
> > }
> >
> > @@ -3176,9 +3210,89 @@ static void
> > intel_ddi_disable_fec_state(struct intel_encoder *encoder,
> > POSTING_READ(ctl);
> > }
> >
> > -static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> > - const struct intel_crtc_state
> > *crtc_state,
> > - const struct drm_connector_state
> > *conn_state)
> > +static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
> > + const struct intel_crtc_state
> > *crtc_state,
> > + const struct drm_connector_state
> > *conn_state)
> > +{
> > + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> > + struct intel_digital_port *dig_port = enc_to_dig_port(&encoder-
> > >base);
> > + bool is_mst = intel_crtc_has_type(crtc_state,
> > INTEL_OUTPUT_DP_MST);
> > + int level = intel_ddi_dp_level(intel_dp);
> > +
> > + intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
> > + crtc_state->lane_count, is_mst);
> > +
> > + /* 1.a got on intel_atomic_commit_tail() */
> > +
> > + /* 2. */
> > + intel_edp_panel_on(intel_dp);
> > +
> > + /*
> > + * 1.b, 3. and 4. is done by before this functions by
> > + * haswell_crtc_enable()->intel_encoders_pre_pll_enable() and
> > + * haswell_crtc_enable()->intel_enable_shared_dpll()
> > + */
> > +
> > + /* 5. */
> > + if (!intel_phy_is_tc(dev_priv, phy) ||
> > + dig_port->tc_mode != TC_PORT_TBT_ALT)
> > + intel_display_power_get(dev_priv,
> > + dig_port->ddi_io_power_domain);
> > +
> > + /* 6. */
> > + icl_program_mg_dp_mode(dig_port);
> > +
> > + /*
> > + * 7.a - Steps in this function that should only be executed
> > over MST
> > + * master as MST encoders will only be executed on MST master
> > as MST
> > + * encoder have have it's own pre_enable() hook
> > + */
> > + intel_ddi_enable_pipe_clock(crtc_state);
> > +
> > + /* 7.b */
> > + intel_ddi_config_transcoder_func(crtc_state);
> > +
> > + /* 7.d */
> > + icl_disable_phy_clock_gating(dig_port);
> > +
> > + /* 7.e */
> > + icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
> > + encoder->type);
> > +
> > + /* 7.f */
> > + if (intel_phy_is_combo(dev_priv, phy)) {
> > + bool lane_reversal =
> > + dig_port->saved_port_bits &
> > DDI_BUF_PORT_REVERSAL;
> > +
> > + intel_combo_phy_power_up_lanes(dev_priv, phy, false,
> > + crtc_state->lane_count,
> > + lane_reversal);
> > + }
> > +
> > + /* 7.g */
> > + intel_ddi_init_dp_buf_reg(encoder);
> > +
> > + if (!is_mst)
> > + intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> > +
> > + /* 7.c, 7.h, 7.i, 7.j */
> > + intel_dp_start_link_train(intel_dp);
> > +
> > + /* 7.k */
> > + intel_dp_stop_link_train(intel_dp);
> > +
> > + /* 7.l */
> > + intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
> > + true);
> > + intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
> See "DDI FEC" in bspec.
>
> intel_dp_sink_set_fec_ready() needs to be called before link
> training,
> intel_ddi_enable_fec() after.
Thanks for finding it
>
> Presumably this is the same for DSC.
Will try to clarify it before send the fixed version.
Thanks again
>
> > + intel_dsc_enable(encoder, crtc_state);
> > +}
> > +
> > +static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder,
> > + const struct intel_crtc_state
> > *crtc_state,
> > + const struct drm_connector_state
> > *conn_state)
> > {
> > struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > @@ -3244,6 +3358,18 @@ static void intel_ddi_pre_enable_dp(struct
> > intel_encoder *encoder,
> > intel_dsc_enable(encoder, crtc_state);
> > }
> >
> > +static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> > + const struct intel_crtc_state
> > *crtc_state,
> > + const struct drm_connector_state
> > *conn_state)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +
> > + if (INTEL_GEN(dev_priv) >= 12)
> > + tgl_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
> > + else
> > + hsw_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
> > +}
> > +
> > static void intel_ddi_pre_enable_hdmi(struct intel_encoder
> > *encoder,
> > const struct intel_crtc_state
> > *crtc_state,
> > const struct drm_connector_state
> > *conn_state)
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index ebfcf183c7f1..1a8e041a5c43 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -4007,13 +4007,13 @@ void intel_dp_set_idle_link_train(struct
> > intel_dp *intel_dp)
> > I915_WRITE(ctl, val);
> >
> > /*
> > - * On PORT_A we can have only eDP in SST mode. There the only
> > reason
> > - * we need to set idle transmission mode is to work around a HW
> > issue
> > - * where we enable the pipe while not in idle link-training
> > mode.
> > + * Until TGL on PORT_A we can have only eDP in SST mode. There
> > the only
> > + * reason we need to set idle transmission mode is to work
> > around a HW
> > + * issue where we enable the pipe while not in idle link-
> > training mode.
> > * In this case there is requirement to wait for a minimum
> > number of
> > * idle patterns to be sent.
> > */
> > - if (port == PORT_A)
> > + if (port == PORT_A && INTEL_GEN(dev_priv) < 12)
> > return;
> >
> > if (intel_wait_for_register(&dev_priv->uncore, status,
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH 26/39] HACK: drm/i915/tgl: Gen12 render context size
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (24 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 25/39] drm/i915/tgl: Implement TGL DisplayPort training sequence Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-16 8:04 ` [PATCH 27/39] drm/i915/tgl: add Gen12 default indirect ctx offset Lucas De Marchi
` (16 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Re-use Gen11 context size for now.
[ Lucas: add HACK since this is a temporary patch that needs to be
confirmed: we need to check BSpec 46255 and recompute ]
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index d20750e420c0..d398d80d4a0d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -164,6 +164,7 @@ u32 intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
default:
MISSING_CASE(INTEL_GEN(dev_priv));
return DEFAULT_LR_CONTEXT_RENDER_SIZE;
+ case 12:
case 11:
return GEN11_LR_CONTEXT_RENDER_SIZE;
case 10:
--
2.21.0
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^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 27/39] drm/i915/tgl: add Gen12 default indirect ctx offset
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (25 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 26/39] HACK: drm/i915/tgl: Gen12 render context size Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-16 8:04 ` [PATCH 28/39] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID Lucas De Marchi
` (15 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Gen12 uses a new indirect ctx offset.
Bspec: 11740
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++++
drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 35a5ad575e12..aa69e434aa03 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2978,6 +2978,10 @@ static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
default:
MISSING_CASE(INTEL_GEN(engine->i915));
/* fall through */
+ case 12:
+ indirect_ctx_offset =
+ GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
+ break;
case 11:
indirect_ctx_offset =
GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
index 915824ebaf17..b7695b96e484 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
@@ -92,5 +92,6 @@
#define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
#define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x19
#define GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x1A
+#define GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0xD
#endif /* _INTEL_LRC_REG_H_ */
--
2.21.0
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^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 28/39] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (26 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 27/39] drm/i915/tgl: add Gen12 default indirect ctx offset Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-16 8:04 ` [PATCH 29/39] drm/i915/tgl: Report valid VDBoxes with SFC capability Lucas De Marchi
` (14 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Like Gen11, Gen12 has 11 available bits for the ctx id field. However,
the last value (0x7FF) is reserved to indicate "invalid context", so
we need to reduce the maximum number of contexts by 1 compared to Gen11.
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 +++-
drivers/gpu/drm/i915/i915_drv.h | 2 ++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index a6b0cb714292..c44b346633ad 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -173,7 +173,9 @@ static inline int new_hw_id(struct drm_i915_private *i915, gfp_t gfp)
lockdep_assert_held(&i915->contexts.mutex);
- if (INTEL_GEN(i915) >= 11)
+ if (INTEL_GEN(i915) >= 12)
+ max = GEN12_MAX_CONTEXT_HW_ID;
+ else if (INTEL_GEN(i915) >= 11)
max = GEN11_MAX_CONTEXT_HW_ID;
else if (USES_GUC_SUBMISSION(i915))
/*
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8d57e9680c99..49c8b49d0e1e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1604,6 +1604,8 @@ struct drm_i915_private {
#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
#define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
#define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
+/* in Gen12 ID 0x7FF is reserved to indicate "invalid context" */
+#define GEN12_MAX_CONTEXT_HW_ID (GEN11_MAX_CONTEXT_HW_ID - 1)
struct list_head hw_id_list;
} contexts;
--
2.21.0
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^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 29/39] drm/i915/tgl: Report valid VDBoxes with SFC capability
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (27 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 28/39] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-16 8:04 ` [PATCH 30/39] drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap Lucas De Marchi
` (13 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx; +Cc: Michel Thierry
From: Michel Thierry <michel.thierry@intel.com>
In Gen11, only even numbered "logical" VDBoxes are hooked up to a SFC
(Scaler & Format Converter) unit. This is not the case in Tigerlake,
where each VDBox can access a SFC.
We will use this information to decide when the SFC units need to be reset
and also pass it to the almighty GuC.
BSpec: 21771
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/intel_device_info.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index f99c9fd497b2..2a39b52c3582 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -1022,8 +1022,9 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
/*
* In Gen11, only even numbered logical VDBOXes are
* hooked up to an SFC (Scaler & Format Converter) unit.
+ * In TGL each VDBOX has access to an SFC.
*/
- if (logical_vdbox++ % 2 == 0)
+ if (IS_TIGERLAKE(dev_priv) || logical_vdbox++ % 2 == 0)
RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i);
}
DRM_DEBUG_DRIVER("vdbox enable: %04x, instances: %04lx\n",
--
2.21.0
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^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 30/39] drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (28 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 29/39] drm/i915/tgl: Report valid VDBoxes with SFC capability Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-16 8:04 ` [PATCH 31/39] drm/i915/tgl: Updated Private PAT programming Lucas De Marchi
` (12 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx; +Cc: Michel Thierry
From: Michel Thierry <michel.thierry@intel.com>
GAM registers located in the 0x4xxx range have been relocated to 0xCxxx;
this is to make space for global MOCS registers.
HSD: 399379
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h | 1 +
drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++++++--
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
index edf194d23c6b..7719fadfe785 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
@@ -81,6 +81,7 @@
#define GT_DOORBELL_ENABLE (1<<0)
#define GEN8_GTCR _MMIO(0x4274)
+#define GEN12_GTCR _MMIO(0xcee8)
#define GEN8_GTCR_INVALIDATE (1<<0)
#define GUC_ARAT_C6DIS _MMIO(0xA178)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 536eadf095fe..76af40d23f09 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -130,10 +130,14 @@ static void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
{
- struct intel_uncore *uncore = &ggtt->vm.i915->uncore;
+ struct drm_i915_private *i915 = ggtt->vm.i915;
+ struct intel_uncore *uncore = &i915->uncore;
gen6_ggtt_invalidate(ggtt);
- intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+ if (INTEL_GEN(i915) >= 12)
+ intel_uncore_write_fw(uncore, GEN12_GTCR, GEN8_GTCR_INVALIDATE);
+ else
+ intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
}
static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
--
2.21.0
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^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 31/39] drm/i915/tgl: Updated Private PAT programming
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (29 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 30/39] drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-16 8:04 ` [PATCH 32/39] drm/i915/tgl/perf: use the same oa ctx_id format as icl Lucas De Marchi
` (11 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx; +Cc: Michel Thierry
From: Michel Thierry <michel.thierry@intel.com>
Gen12 removes the target-cache and age fields from the private PAT
because MOCS now have the capability to set these itself. Only memory-type
field should be programmed in the ppat, the reminded bits are reserved.
Since now there are only 4 possible combinations, we could set only 4
PPAT and leave the reminded 4 as UC, but I left them as WB as we used
to have before.
Also these registers have been relocated to the 0x4800-0x481c range.
HSDES: 1406402661
BSpec: 31654
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 17 ++++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 76af40d23f09..b9e29afc587d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2866,6 +2866,19 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
return 0;
}
+static void tgl_setup_private_ppat(struct drm_i915_private *dev_priv)
+{
+ /* TGL doesn't support LLC or AGE settings */
+ I915_WRITE(GEN12_PAT_INDEX(0), GEN8_PPAT_WB);
+ I915_WRITE(GEN12_PAT_INDEX(1), GEN8_PPAT_WC);
+ I915_WRITE(GEN12_PAT_INDEX(2), GEN8_PPAT_WT);
+ I915_WRITE(GEN12_PAT_INDEX(3), GEN8_PPAT_UC);
+ I915_WRITE(GEN12_PAT_INDEX(4), GEN8_PPAT_WB);
+ I915_WRITE(GEN12_PAT_INDEX(5), GEN8_PPAT_WB);
+ I915_WRITE(GEN12_PAT_INDEX(6), GEN8_PPAT_WB);
+ I915_WRITE(GEN12_PAT_INDEX(7), GEN8_PPAT_WB);
+}
+
static void cnl_setup_private_ppat(struct drm_i915_private *dev_priv)
{
I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_WB | GEN8_PPAT_LLC);
@@ -2946,7 +2959,9 @@ static void setup_private_pat(struct drm_i915_private *dev_priv)
{
GEM_BUG_ON(INTEL_GEN(dev_priv) < 8);
- if (INTEL_GEN(dev_priv) >= 10)
+ if (INTEL_GEN(dev_priv) >= 12)
+ tgl_setup_private_ppat(dev_priv);
+ else if (INTEL_GEN(dev_priv) >= 10)
cnl_setup_private_ppat(dev_priv);
else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
chv_setup_private_ppat(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index eca8295aba9e..34d83e3a51a7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2501,6 +2501,7 @@ enum i915_power_well_id {
#define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0)
#define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4)
#define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4)
+#define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
#define BSD_HWS_PGA_GEN7 _MMIO(0x04180)
#define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
#define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)
--
2.21.0
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^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 32/39] drm/i915/tgl/perf: use the same oa ctx_id format as icl
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (30 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 31/39] drm/i915/tgl: Updated Private PAT programming Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-16 8:04 ` [PATCH 33/39] drm/i915/perf: add a parameter to control the size of OA buffer Lucas De Marchi
` (10 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx; +Cc: Michel Thierry
From: Michel Thierry <michel.thierry@intel.com>
Compared to Icelake, Tigerlake's MAX_CONTEXT_HW_ID is smaller by one, but
since we just use the upper 32 bits of the lrc_desc, it's guaranteed OA
will use the correct one.
v2: rebase (Umesh)
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/i915_perf.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index e42b86827d6b..2c9f46e12622 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1299,7 +1299,8 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
}
break;
- case 11: {
+ case 11:
+ case 12: {
stream->specific_ctx_id_mask =
((1U << GEN11_SW_CTX_ID_WIDTH) - 1) << (GEN11_SW_CTX_ID_SHIFT - 32) |
((1U << GEN11_ENGINE_INSTANCE_WIDTH) - 1) << (GEN11_ENGINE_INSTANCE_SHIFT - 32) |
--
2.21.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 33/39] drm/i915/perf: add a parameter to control the size of OA buffer
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (31 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 32/39] drm/i915/tgl/perf: use the same oa ctx_id format as icl Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-19 18:31 ` Umesh Nerlige Ramappa
` (2 more replies)
2019-08-16 8:04 ` [PATCH 34/39] drm/i915/tgl: Add perf support on TGL Lucas De Marchi
` (9 subsequent siblings)
42 siblings, 3 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx; +Cc: Matthew Auld
From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
The way our hardware is designed doesn't seem to let us use the
MI_RECORD_PERF_COUNT command without setting up a circular buffer.
In the case where the user didn't request OA reports to be available
through the i915 perf stream, we can set the OA buffer to the minimum
size to avoid consuming memory which won't be used by the driver.
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_perf.c | 98 +++++++++++++++++++++-----------
drivers/gpu/drm/i915/i915_reg.h | 2 +
include/uapi/drm/i915_drm.h | 7 +++
3 files changed, 74 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2c9f46e12622..9386d9c82930 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -216,13 +216,7 @@
#include "oa/i915_oa_cnl.h"
#include "oa/i915_oa_icl.h"
-/* HW requires this to be a power of two, between 128k and 16M, though driver
- * is currently generally designed assuming the largest 16M size is used such
- * that the overflow cases are unlikely in normal operation.
- */
-#define OA_BUFFER_SIZE SZ_16M
-
-#define OA_TAKEN(tail, head) ((tail - head) & (OA_BUFFER_SIZE - 1))
+#define OA_TAKEN(tail, head) (((tail) - (head)) & (stream->oa_buffer.vma->size - 1))
/**
* DOC: OA Tail Pointer Race
@@ -347,6 +341,7 @@ static const struct i915_oa_format gen8_plus_oa_formats[I915_OA_FORMAT_MAX] = {
* @oa_format: An OA unit HW report format
* @oa_periodic: Whether to enable periodic OA unit sampling
* @oa_period_exponent: The OA unit sampling period is derived from this
+ * @oa_buffer_size_exponent: The OA buffer size is derived from this
*
* As read_properties_unlocked() enumerates and validates the properties given
* to open a stream of metrics the configuration is built up in the structure
@@ -363,6 +358,7 @@ struct perf_open_properties {
int oa_format;
bool oa_periodic;
int oa_period_exponent;
+ u32 oa_buffer_size_exponent;
};
static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
@@ -531,7 +527,7 @@ static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream)
* could put the tail out of bounds...
*/
if (hw_tail >= gtt_offset &&
- hw_tail < (gtt_offset + OA_BUFFER_SIZE)) {
+ hw_tail < (gtt_offset + stream->oa_buffer.vma->size)) {
stream->oa_buffer.tails[!aged_idx].offset =
aging_tail = hw_tail;
stream->oa_buffer.aging_timestamp = now;
@@ -659,7 +655,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,
int report_size = stream->oa_buffer.format_size;
u8 *oa_buf_base = stream->oa_buffer.vaddr;
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
- u32 mask = (OA_BUFFER_SIZE - 1);
+ u32 mask = (stream->oa_buffer.vma->size - 1);
size_t start_offset = *offset;
unsigned long flags;
unsigned int aged_tail_idx;
@@ -699,8 +695,8 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,
* only be incremented by multiples of the report size (notably also
* all a power of two).
*/
- if (WARN_ONCE(head > OA_BUFFER_SIZE || head % report_size ||
- tail > OA_BUFFER_SIZE || tail % report_size,
+ if (WARN_ONCE(head > stream->oa_buffer.vma->size || head % report_size ||
+ tail > stream->oa_buffer.vma->size || tail % report_size,
"Inconsistent OA buffer pointers: head = %u, tail = %u\n",
head, tail))
return -EIO;
@@ -723,7 +719,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,
* here would imply a driver bug that would result
* in an overrun.
*/
- if (WARN_ON((OA_BUFFER_SIZE - head) < report_size)) {
+ if (WARN_ON((stream->oa_buffer.vma->size - head) < report_size)) {
DRM_ERROR("Spurious OA head ptr: non-integral report offset\n");
break;
}
@@ -881,11 +877,6 @@ static int gen8_oa_read(struct i915_perf_stream *stream,
* automatically triggered reports in this condition and so we
* have to assume that old reports are now being trampled
* over.
- *
- * Considering how we don't currently give userspace control
- * over the OA buffer size and always configure a large 16MB
- * buffer, then a buffer overflow does anyway likely indicate
- * that something has gone quite badly wrong.
*/
if (oastatus & GEN8_OASTATUS_OABUFFER_OVERFLOW) {
ret = append_oa_status(stream, buf, count, offset,
@@ -947,7 +938,7 @@ static int gen7_append_oa_reports(struct i915_perf_stream *stream,
int report_size = stream->oa_buffer.format_size;
u8 *oa_buf_base = stream->oa_buffer.vaddr;
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
- u32 mask = (OA_BUFFER_SIZE - 1);
+ u32 mask = (stream->oa_buffer.vma->size - 1);
size_t start_offset = *offset;
unsigned long flags;
unsigned int aged_tail_idx;
@@ -984,8 +975,8 @@ static int gen7_append_oa_reports(struct i915_perf_stream *stream,
* only be incremented by multiples of the report size (notably also
* all a power of two).
*/
- if (WARN_ONCE(head > OA_BUFFER_SIZE || head % report_size ||
- tail > OA_BUFFER_SIZE || tail % report_size,
+ if (WARN_ONCE(head > stream->oa_buffer.vma->size || head % report_size ||
+ tail > stream->oa_buffer.vma->size || tail % report_size,
"Inconsistent OA buffer pointers: head = %u, tail = %u\n",
head, tail))
return -EIO;
@@ -1005,7 +996,7 @@ static int gen7_append_oa_reports(struct i915_perf_stream *stream,
* here would imply a driver bug that would result
* in an overrun.
*/
- if (WARN_ON((OA_BUFFER_SIZE - head) < report_size)) {
+ if (WARN_ON((stream->oa_buffer.vma->size - head) < report_size)) {
DRM_ERROR("Spurious OA head ptr: non-integral report offset\n");
break;
}
@@ -1408,7 +1399,9 @@ static void gen7_init_oa_buffer(struct i915_perf_stream *stream)
I915_WRITE(GEN7_OABUFFER, gtt_offset);
- I915_WRITE(GEN7_OASTATUS1, gtt_offset | OABUFFER_SIZE_16M); /* tail */
+ I915_WRITE(GEN7_OASTATUS1, gtt_offset |
+ ((stream->oa_buffer.size_exponent - 17) <<
+ GEN7_OASTATUS1_BUFFER_SIZE_SHIFT)); /* tail */
/* Mark that we need updated tail pointers to read from... */
stream->oa_buffer.tails[0].offset = INVALID_TAIL_PTR;
@@ -1433,7 +1426,7 @@ static void gen7_init_oa_buffer(struct i915_perf_stream *stream)
* the assumption that new reports are being written to zeroed
* memory...
*/
- memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
+ memset(stream->oa_buffer.vaddr, 0, stream->oa_buffer.vma->size);
/* Maybe make ->pollin per-stream state if we support multiple
* concurrent streams in the future.
@@ -1464,7 +1457,9 @@ static void gen8_init_oa_buffer(struct i915_perf_stream *stream)
* bit."
*/
I915_WRITE(GEN8_OABUFFER, gtt_offset |
- OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT);
+ ((stream->oa_buffer.size_exponent - 17) <<
+ GEN8_OABUFFER_BUFFER_SIZE_SHIFT) |
+ GEN8_OABUFFER_MEM_SELECT_GGTT);
I915_WRITE(GEN8_OATAILPTR, gtt_offset & GEN8_OATAILPTR_MASK);
/* Mark that we need updated tail pointers to read from... */
@@ -1492,7 +1487,7 @@ static void gen8_init_oa_buffer(struct i915_perf_stream *stream)
* the assumption that new reports are being written to zeroed
* memory...
*/
- memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
+ memset(stream->oa_buffer.vaddr, 0, stream->oa_buffer.vma->size);
/*
* Maybe make ->pollin per-stream state if we support multiple
@@ -1501,24 +1496,25 @@ static void gen8_init_oa_buffer(struct i915_perf_stream *stream)
stream->pollin = false;
}
-static int alloc_oa_buffer(struct i915_perf_stream *stream)
+static int alloc_oa_buffer(struct i915_perf_stream *stream, int size_exponent)
{
struct drm_i915_gem_object *bo;
struct drm_i915_private *dev_priv = stream->dev_priv;
struct i915_vma *vma;
+ size_t size = 1U << size_exponent;
int ret;
if (WARN_ON(stream->oa_buffer.vma))
return -ENODEV;
+ if (WARN_ON(size < SZ_128K || size > SZ_16M))
+ return -EINVAL;
+
ret = i915_mutex_lock_interruptible(&dev_priv->drm);
if (ret)
return ret;
- BUILD_BUG_ON_NOT_POWER_OF_2(OA_BUFFER_SIZE);
- BUILD_BUG_ON(OA_BUFFER_SIZE < SZ_128K || OA_BUFFER_SIZE > SZ_16M);
-
- bo = i915_gem_object_create_shmem(dev_priv, OA_BUFFER_SIZE);
+ bo = i915_gem_object_create_shmem(dev_priv, size);
if (IS_ERR(bo)) {
DRM_ERROR("Failed to allocate OA buffer\n");
ret = PTR_ERR(bo);
@@ -1534,6 +1530,7 @@ static int alloc_oa_buffer(struct i915_perf_stream *stream)
goto err_unref;
}
stream->oa_buffer.vma = vma;
+ stream->oa_buffer.size_exponent = size_exponent;
stream->oa_buffer.vaddr =
i915_gem_object_pin_map(bo, I915_MAP_WB);
@@ -1542,9 +1539,10 @@ static int alloc_oa_buffer(struct i915_perf_stream *stream)
goto err_unpin;
}
- DRM_DEBUG_DRIVER("OA Buffer initialized, gtt offset = 0x%x, vaddr = %p\n",
+ DRM_DEBUG_DRIVER("OA Buffer initialized, gtt offset = 0x%x, vaddr = %p, size = %llu\n",
i915_ggtt_offset(stream->oa_buffer.vma),
- stream->oa_buffer.vaddr);
+ stream->oa_buffer.vaddr,
+ stream->oa_buffer.vma->size);
goto unlock;
@@ -2251,7 +2249,7 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
stream->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
- ret = alloc_oa_buffer(stream);
+ ret = alloc_oa_buffer(stream, props->oa_buffer_size_exponent);
if (ret)
goto err_oa_buf_alloc;
@@ -2823,6 +2821,26 @@ static u64 oa_exponent_to_ns(struct drm_i915_private *dev_priv, int exponent)
1000ULL * RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz);
}
+static int
+select_oa_buffer_exponent(struct drm_i915_private *i915,
+ u64 requested_size)
+{
+ int order;
+
+ /*
+ * When no size is specified, use the largest size supported by all
+ * generations.
+ */
+ if (!requested_size)
+ return order_base_2(SZ_16M);
+
+ order = order_base_2(clamp_t(u64, requested_size, SZ_128K, SZ_16M));
+ if (requested_size != (1UL << order))
+ return -EINVAL;
+
+ return order;
+}
+
/**
* read_properties_unlocked - validate + copy userspace stream open properties
* @dev_priv: i915 device instance
@@ -2950,6 +2968,14 @@ static int read_properties_unlocked(struct drm_i915_private *dev_priv,
props->oa_periodic = true;
props->oa_period_exponent = value;
break;
+ case DRM_I915_PERF_PROP_OA_BUFFER_SIZE:
+ ret = select_oa_buffer_exponent(dev_priv, value);
+ if (ret < 0) {
+ DRM_DEBUG("OA buffer size invalid %llu\n", value);
+ return ret;
+ }
+ props->oa_buffer_size_exponent = ret;
+ break;
case DRM_I915_PERF_PROP_MAX:
MISSING_CASE(id);
return -EINVAL;
@@ -2958,6 +2984,12 @@ static int read_properties_unlocked(struct drm_i915_private *dev_priv,
uprop += 2;
}
+ /* If no buffer size was requested, select the default one. */
+ if (!props->oa_buffer_size_exponent) {
+ props->oa_buffer_size_exponent =
+ select_oa_buffer_exponent(dev_priv, 0);
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 34d83e3a51a7..d35f385f8288 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -675,12 +675,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN8_OABUFFER_UDW _MMIO(0x23b4)
#define GEN8_OABUFFER _MMIO(0x2b14)
#define GEN8_OABUFFER_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
+#define GEN8_OABUFFER_BUFFER_SIZE_SHIFT 3
#define GEN7_OASTATUS1 _MMIO(0x2364)
#define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0
#define GEN7_OASTATUS1_COUNTER_OVERFLOW (1 << 2)
#define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1 << 1)
#define GEN7_OASTATUS1_REPORT_LOST (1 << 0)
+#define GEN7_OASTATUS1_BUFFER_SIZE_SHIFT 3
#define GEN7_OASTATUS2 _MMIO(0x2368)
#define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 469dc512cca3..f662c534de0a 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1873,6 +1873,13 @@ enum drm_i915_perf_property_id {
*/
DRM_I915_PERF_PROP_OA_EXPONENT,
+ /**
+ * Specify a global OA buffer size to be allocated in bytes. The size
+ * specified must be supported by HW (currently supported sizes are
+ * powers of 2 ranging from 128Kb to 16Mb).
+ */
+ DRM_I915_PERF_PROP_OA_BUFFER_SIZE,
+
DRM_I915_PERF_PROP_MAX /* non-ABI */
};
--
2.21.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 58+ messages in thread* Re: [PATCH 33/39] drm/i915/perf: add a parameter to control the size of OA buffer
2019-08-16 8:04 ` [PATCH 33/39] drm/i915/perf: add a parameter to control the size of OA buffer Lucas De Marchi
@ 2019-08-19 18:31 ` Umesh Nerlige Ramappa
2019-08-21 8:37 ` Lionel Landwerlin
2019-08-22 10:43 ` Joonas Lahtinen
2 siblings, 0 replies; 58+ messages in thread
From: Umesh Nerlige Ramappa @ 2019-08-19 18:31 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, Matthew Auld
Looks good.
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
On Fri, Aug 16, 2019 at 01:04:57AM -0700, Lucas De Marchi wrote:
>From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>
>The way our hardware is designed doesn't seem to let us use the
>MI_RECORD_PERF_COUNT command without setting up a circular buffer.
>
>In the case where the user didn't request OA reports to be available
>through the i915 perf stream, we can set the OA buffer to the minimum
>size to avoid consuming memory which won't be used by the driver.
>
>Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>Cc: Matthew Auld <matthew.auld@intel.com>
>Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>---
> drivers/gpu/drm/i915/i915_perf.c | 98 +++++++++++++++++++++-----------
> drivers/gpu/drm/i915/i915_reg.h | 2 +
> include/uapi/drm/i915_drm.h | 7 +++
> 3 files changed, 74 insertions(+), 33 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
>index 2c9f46e12622..9386d9c82930 100644
>--- a/drivers/gpu/drm/i915/i915_perf.c
>+++ b/drivers/gpu/drm/i915/i915_perf.c
>@@ -216,13 +216,7 @@
> #include "oa/i915_oa_cnl.h"
> #include "oa/i915_oa_icl.h"
>
>-/* HW requires this to be a power of two, between 128k and 16M, though driver
>- * is currently generally designed assuming the largest 16M size is used such
>- * that the overflow cases are unlikely in normal operation.
>- */
>-#define OA_BUFFER_SIZE SZ_16M
>-
>-#define OA_TAKEN(tail, head) ((tail - head) & (OA_BUFFER_SIZE - 1))
>+#define OA_TAKEN(tail, head) (((tail) - (head)) & (stream->oa_buffer.vma->size - 1))
>
> /**
> * DOC: OA Tail Pointer Race
>@@ -347,6 +341,7 @@ static const struct i915_oa_format gen8_plus_oa_formats[I915_OA_FORMAT_MAX] = {
> * @oa_format: An OA unit HW report format
> * @oa_periodic: Whether to enable periodic OA unit sampling
> * @oa_period_exponent: The OA unit sampling period is derived from this
>+ * @oa_buffer_size_exponent: The OA buffer size is derived from this
> *
> * As read_properties_unlocked() enumerates and validates the properties given
> * to open a stream of metrics the configuration is built up in the structure
>@@ -363,6 +358,7 @@ struct perf_open_properties {
> int oa_format;
> bool oa_periodic;
> int oa_period_exponent;
>+ u32 oa_buffer_size_exponent;
> };
>
> static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
>@@ -531,7 +527,7 @@ static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream)
> * could put the tail out of bounds...
> */
> if (hw_tail >= gtt_offset &&
>- hw_tail < (gtt_offset + OA_BUFFER_SIZE)) {
>+ hw_tail < (gtt_offset + stream->oa_buffer.vma->size)) {
> stream->oa_buffer.tails[!aged_idx].offset =
> aging_tail = hw_tail;
> stream->oa_buffer.aging_timestamp = now;
>@@ -659,7 +655,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,
> int report_size = stream->oa_buffer.format_size;
> u8 *oa_buf_base = stream->oa_buffer.vaddr;
> u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
>- u32 mask = (OA_BUFFER_SIZE - 1);
>+ u32 mask = (stream->oa_buffer.vma->size - 1);
> size_t start_offset = *offset;
> unsigned long flags;
> unsigned int aged_tail_idx;
>@@ -699,8 +695,8 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,
> * only be incremented by multiples of the report size (notably also
> * all a power of two).
> */
>- if (WARN_ONCE(head > OA_BUFFER_SIZE || head % report_size ||
>- tail > OA_BUFFER_SIZE || tail % report_size,
>+ if (WARN_ONCE(head > stream->oa_buffer.vma->size || head % report_size ||
>+ tail > stream->oa_buffer.vma->size || tail % report_size,
> "Inconsistent OA buffer pointers: head = %u, tail = %u\n",
> head, tail))
> return -EIO;
>@@ -723,7 +719,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,
> * here would imply a driver bug that would result
> * in an overrun.
> */
>- if (WARN_ON((OA_BUFFER_SIZE - head) < report_size)) {
>+ if (WARN_ON((stream->oa_buffer.vma->size - head) < report_size)) {
> DRM_ERROR("Spurious OA head ptr: non-integral report offset\n");
> break;
> }
>@@ -881,11 +877,6 @@ static int gen8_oa_read(struct i915_perf_stream *stream,
> * automatically triggered reports in this condition and so we
> * have to assume that old reports are now being trampled
> * over.
>- *
>- * Considering how we don't currently give userspace control
>- * over the OA buffer size and always configure a large 16MB
>- * buffer, then a buffer overflow does anyway likely indicate
>- * that something has gone quite badly wrong.
> */
> if (oastatus & GEN8_OASTATUS_OABUFFER_OVERFLOW) {
> ret = append_oa_status(stream, buf, count, offset,
>@@ -947,7 +938,7 @@ static int gen7_append_oa_reports(struct i915_perf_stream *stream,
> int report_size = stream->oa_buffer.format_size;
> u8 *oa_buf_base = stream->oa_buffer.vaddr;
> u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
>- u32 mask = (OA_BUFFER_SIZE - 1);
>+ u32 mask = (stream->oa_buffer.vma->size - 1);
> size_t start_offset = *offset;
> unsigned long flags;
> unsigned int aged_tail_idx;
>@@ -984,8 +975,8 @@ static int gen7_append_oa_reports(struct i915_perf_stream *stream,
> * only be incremented by multiples of the report size (notably also
> * all a power of two).
> */
>- if (WARN_ONCE(head > OA_BUFFER_SIZE || head % report_size ||
>- tail > OA_BUFFER_SIZE || tail % report_size,
>+ if (WARN_ONCE(head > stream->oa_buffer.vma->size || head % report_size ||
>+ tail > stream->oa_buffer.vma->size || tail % report_size,
> "Inconsistent OA buffer pointers: head = %u, tail = %u\n",
> head, tail))
> return -EIO;
>@@ -1005,7 +996,7 @@ static int gen7_append_oa_reports(struct i915_perf_stream *stream,
> * here would imply a driver bug that would result
> * in an overrun.
> */
>- if (WARN_ON((OA_BUFFER_SIZE - head) < report_size)) {
>+ if (WARN_ON((stream->oa_buffer.vma->size - head) < report_size)) {
> DRM_ERROR("Spurious OA head ptr: non-integral report offset\n");
> break;
> }
>@@ -1408,7 +1399,9 @@ static void gen7_init_oa_buffer(struct i915_perf_stream *stream)
>
> I915_WRITE(GEN7_OABUFFER, gtt_offset);
>
>- I915_WRITE(GEN7_OASTATUS1, gtt_offset | OABUFFER_SIZE_16M); /* tail */
>+ I915_WRITE(GEN7_OASTATUS1, gtt_offset |
>+ ((stream->oa_buffer.size_exponent - 17) <<
>+ GEN7_OASTATUS1_BUFFER_SIZE_SHIFT)); /* tail */
>
> /* Mark that we need updated tail pointers to read from... */
> stream->oa_buffer.tails[0].offset = INVALID_TAIL_PTR;
>@@ -1433,7 +1426,7 @@ static void gen7_init_oa_buffer(struct i915_perf_stream *stream)
> * the assumption that new reports are being written to zeroed
> * memory...
> */
>- memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
>+ memset(stream->oa_buffer.vaddr, 0, stream->oa_buffer.vma->size);
>
> /* Maybe make ->pollin per-stream state if we support multiple
> * concurrent streams in the future.
>@@ -1464,7 +1457,9 @@ static void gen8_init_oa_buffer(struct i915_perf_stream *stream)
> * bit."
> */
> I915_WRITE(GEN8_OABUFFER, gtt_offset |
>- OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT);
>+ ((stream->oa_buffer.size_exponent - 17) <<
>+ GEN8_OABUFFER_BUFFER_SIZE_SHIFT) |
>+ GEN8_OABUFFER_MEM_SELECT_GGTT);
> I915_WRITE(GEN8_OATAILPTR, gtt_offset & GEN8_OATAILPTR_MASK);
>
> /* Mark that we need updated tail pointers to read from... */
>@@ -1492,7 +1487,7 @@ static void gen8_init_oa_buffer(struct i915_perf_stream *stream)
> * the assumption that new reports are being written to zeroed
> * memory...
> */
>- memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
>+ memset(stream->oa_buffer.vaddr, 0, stream->oa_buffer.vma->size);
>
> /*
> * Maybe make ->pollin per-stream state if we support multiple
>@@ -1501,24 +1496,25 @@ static void gen8_init_oa_buffer(struct i915_perf_stream *stream)
> stream->pollin = false;
> }
>
>-static int alloc_oa_buffer(struct i915_perf_stream *stream)
>+static int alloc_oa_buffer(struct i915_perf_stream *stream, int size_exponent)
> {
> struct drm_i915_gem_object *bo;
> struct drm_i915_private *dev_priv = stream->dev_priv;
> struct i915_vma *vma;
>+ size_t size = 1U << size_exponent;
> int ret;
>
> if (WARN_ON(stream->oa_buffer.vma))
> return -ENODEV;
>
>+ if (WARN_ON(size < SZ_128K || size > SZ_16M))
>+ return -EINVAL;
>+
> ret = i915_mutex_lock_interruptible(&dev_priv->drm);
> if (ret)
> return ret;
>
>- BUILD_BUG_ON_NOT_POWER_OF_2(OA_BUFFER_SIZE);
>- BUILD_BUG_ON(OA_BUFFER_SIZE < SZ_128K || OA_BUFFER_SIZE > SZ_16M);
>-
>- bo = i915_gem_object_create_shmem(dev_priv, OA_BUFFER_SIZE);
>+ bo = i915_gem_object_create_shmem(dev_priv, size);
> if (IS_ERR(bo)) {
> DRM_ERROR("Failed to allocate OA buffer\n");
> ret = PTR_ERR(bo);
>@@ -1534,6 +1530,7 @@ static int alloc_oa_buffer(struct i915_perf_stream *stream)
> goto err_unref;
> }
> stream->oa_buffer.vma = vma;
>+ stream->oa_buffer.size_exponent = size_exponent;
>
> stream->oa_buffer.vaddr =
> i915_gem_object_pin_map(bo, I915_MAP_WB);
>@@ -1542,9 +1539,10 @@ static int alloc_oa_buffer(struct i915_perf_stream *stream)
> goto err_unpin;
> }
>
>- DRM_DEBUG_DRIVER("OA Buffer initialized, gtt offset = 0x%x, vaddr = %p\n",
>+ DRM_DEBUG_DRIVER("OA Buffer initialized, gtt offset = 0x%x, vaddr = %p, size = %llu\n",
> i915_ggtt_offset(stream->oa_buffer.vma),
>- stream->oa_buffer.vaddr);
>+ stream->oa_buffer.vaddr,
>+ stream->oa_buffer.vma->size);
>
> goto unlock;
>
>@@ -2251,7 +2249,7 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
> stream->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
> intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
>- ret = alloc_oa_buffer(stream);
>+ ret = alloc_oa_buffer(stream, props->oa_buffer_size_exponent);
> if (ret)
> goto err_oa_buf_alloc;
>
>@@ -2823,6 +2821,26 @@ static u64 oa_exponent_to_ns(struct drm_i915_private *dev_priv, int exponent)
> 1000ULL * RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz);
> }
>
>+static int
>+select_oa_buffer_exponent(struct drm_i915_private *i915,
>+ u64 requested_size)
>+{
>+ int order;
>+
>+ /*
>+ * When no size is specified, use the largest size supported by all
>+ * generations.
>+ */
>+ if (!requested_size)
>+ return order_base_2(SZ_16M);
>+
>+ order = order_base_2(clamp_t(u64, requested_size, SZ_128K, SZ_16M));
>+ if (requested_size != (1UL << order))
>+ return -EINVAL;
>+
>+ return order;
>+}
>+
> /**
> * read_properties_unlocked - validate + copy userspace stream open properties
> * @dev_priv: i915 device instance
>@@ -2950,6 +2968,14 @@ static int read_properties_unlocked(struct drm_i915_private *dev_priv,
> props->oa_periodic = true;
> props->oa_period_exponent = value;
> break;
>+ case DRM_I915_PERF_PROP_OA_BUFFER_SIZE:
>+ ret = select_oa_buffer_exponent(dev_priv, value);
>+ if (ret < 0) {
>+ DRM_DEBUG("OA buffer size invalid %llu\n", value);
>+ return ret;
>+ }
>+ props->oa_buffer_size_exponent = ret;
>+ break;
> case DRM_I915_PERF_PROP_MAX:
> MISSING_CASE(id);
> return -EINVAL;
>@@ -2958,6 +2984,12 @@ static int read_properties_unlocked(struct drm_i915_private *dev_priv,
> uprop += 2;
> }
>
>+ /* If no buffer size was requested, select the default one. */
>+ if (!props->oa_buffer_size_exponent) {
>+ props->oa_buffer_size_exponent =
>+ select_oa_buffer_exponent(dev_priv, 0);
>+ }
>+
> return 0;
> }
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 34d83e3a51a7..d35f385f8288 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -675,12 +675,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define GEN8_OABUFFER_UDW _MMIO(0x23b4)
> #define GEN8_OABUFFER _MMIO(0x2b14)
> #define GEN8_OABUFFER_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
>+#define GEN8_OABUFFER_BUFFER_SIZE_SHIFT 3
>
> #define GEN7_OASTATUS1 _MMIO(0x2364)
> #define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0
> #define GEN7_OASTATUS1_COUNTER_OVERFLOW (1 << 2)
> #define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1 << 1)
> #define GEN7_OASTATUS1_REPORT_LOST (1 << 0)
>+#define GEN7_OASTATUS1_BUFFER_SIZE_SHIFT 3
>
> #define GEN7_OASTATUS2 _MMIO(0x2368)
> #define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0
>diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
>index 469dc512cca3..f662c534de0a 100644
>--- a/include/uapi/drm/i915_drm.h
>+++ b/include/uapi/drm/i915_drm.h
>@@ -1873,6 +1873,13 @@ enum drm_i915_perf_property_id {
> */
> DRM_I915_PERF_PROP_OA_EXPONENT,
>
>+ /**
>+ * Specify a global OA buffer size to be allocated in bytes. The size
>+ * specified must be supported by HW (currently supported sizes are
>+ * powers of 2 ranging from 128Kb to 16Mb).
>+ */
>+ DRM_I915_PERF_PROP_OA_BUFFER_SIZE,
>+
> DRM_I915_PERF_PROP_MAX /* non-ABI */
> };
>
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 58+ messages in thread* Re: [PATCH 33/39] drm/i915/perf: add a parameter to control the size of OA buffer
2019-08-16 8:04 ` [PATCH 33/39] drm/i915/perf: add a parameter to control the size of OA buffer Lucas De Marchi
2019-08-19 18:31 ` Umesh Nerlige Ramappa
@ 2019-08-21 8:37 ` Lionel Landwerlin
2019-08-22 10:43 ` Joonas Lahtinen
2 siblings, 0 replies; 58+ messages in thread
From: Lionel Landwerlin @ 2019-08-21 8:37 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx; +Cc: Matthew Auld
I think this patch needs to be landed after
https://patchwork.freedesktop.org/patch/319815/?series=60916&rev=10
As recommended by Joonas.
It should also bump the revision number of the perf API so that the
application can detect this feature is available.
Thanks,
-Lionel
On 16/08/2019 10:04, Lucas De Marchi wrote:
> From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>
> The way our hardware is designed doesn't seem to let us use the
> MI_RECORD_PERF_COUNT command without setting up a circular buffer.
>
> In the case where the user didn't request OA reports to be available
> through the i915 perf stream, we can set the OA buffer to the minimum
> size to avoid consuming memory which won't be used by the driver.
>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_perf.c | 98 +++++++++++++++++++++-----------
> drivers/gpu/drm/i915/i915_reg.h | 2 +
> include/uapi/drm/i915_drm.h | 7 +++
> 3 files changed, 74 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 2c9f46e12622..9386d9c82930 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -216,13 +216,7 @@
> #include "oa/i915_oa_cnl.h"
> #include "oa/i915_oa_icl.h"
>
> -/* HW requires this to be a power of two, between 128k and 16M, though driver
> - * is currently generally designed assuming the largest 16M size is used such
> - * that the overflow cases are unlikely in normal operation.
> - */
> -#define OA_BUFFER_SIZE SZ_16M
> -
> -#define OA_TAKEN(tail, head) ((tail - head) & (OA_BUFFER_SIZE - 1))
> +#define OA_TAKEN(tail, head) (((tail) - (head)) & (stream->oa_buffer.vma->size - 1))
>
> /**
> * DOC: OA Tail Pointer Race
> @@ -347,6 +341,7 @@ static const struct i915_oa_format gen8_plus_oa_formats[I915_OA_FORMAT_MAX] = {
> * @oa_format: An OA unit HW report format
> * @oa_periodic: Whether to enable periodic OA unit sampling
> * @oa_period_exponent: The OA unit sampling period is derived from this
> + * @oa_buffer_size_exponent: The OA buffer size is derived from this
> *
> * As read_properties_unlocked() enumerates and validates the properties given
> * to open a stream of metrics the configuration is built up in the structure
> @@ -363,6 +358,7 @@ struct perf_open_properties {
> int oa_format;
> bool oa_periodic;
> int oa_period_exponent;
> + u32 oa_buffer_size_exponent;
> };
>
> static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
> @@ -531,7 +527,7 @@ static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream)
> * could put the tail out of bounds...
> */
> if (hw_tail >= gtt_offset &&
> - hw_tail < (gtt_offset + OA_BUFFER_SIZE)) {
> + hw_tail < (gtt_offset + stream->oa_buffer.vma->size)) {
> stream->oa_buffer.tails[!aged_idx].offset =
> aging_tail = hw_tail;
> stream->oa_buffer.aging_timestamp = now;
> @@ -659,7 +655,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,
> int report_size = stream->oa_buffer.format_size;
> u8 *oa_buf_base = stream->oa_buffer.vaddr;
> u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
> - u32 mask = (OA_BUFFER_SIZE - 1);
> + u32 mask = (stream->oa_buffer.vma->size - 1);
> size_t start_offset = *offset;
> unsigned long flags;
> unsigned int aged_tail_idx;
> @@ -699,8 +695,8 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,
> * only be incremented by multiples of the report size (notably also
> * all a power of two).
> */
> - if (WARN_ONCE(head > OA_BUFFER_SIZE || head % report_size ||
> - tail > OA_BUFFER_SIZE || tail % report_size,
> + if (WARN_ONCE(head > stream->oa_buffer.vma->size || head % report_size ||
> + tail > stream->oa_buffer.vma->size || tail % report_size,
> "Inconsistent OA buffer pointers: head = %u, tail = %u\n",
> head, tail))
> return -EIO;
> @@ -723,7 +719,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,
> * here would imply a driver bug that would result
> * in an overrun.
> */
> - if (WARN_ON((OA_BUFFER_SIZE - head) < report_size)) {
> + if (WARN_ON((stream->oa_buffer.vma->size - head) < report_size)) {
> DRM_ERROR("Spurious OA head ptr: non-integral report offset\n");
> break;
> }
> @@ -881,11 +877,6 @@ static int gen8_oa_read(struct i915_perf_stream *stream,
> * automatically triggered reports in this condition and so we
> * have to assume that old reports are now being trampled
> * over.
> - *
> - * Considering how we don't currently give userspace control
> - * over the OA buffer size and always configure a large 16MB
> - * buffer, then a buffer overflow does anyway likely indicate
> - * that something has gone quite badly wrong.
> */
> if (oastatus & GEN8_OASTATUS_OABUFFER_OVERFLOW) {
> ret = append_oa_status(stream, buf, count, offset,
> @@ -947,7 +938,7 @@ static int gen7_append_oa_reports(struct i915_perf_stream *stream,
> int report_size = stream->oa_buffer.format_size;
> u8 *oa_buf_base = stream->oa_buffer.vaddr;
> u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
> - u32 mask = (OA_BUFFER_SIZE - 1);
> + u32 mask = (stream->oa_buffer.vma->size - 1);
> size_t start_offset = *offset;
> unsigned long flags;
> unsigned int aged_tail_idx;
> @@ -984,8 +975,8 @@ static int gen7_append_oa_reports(struct i915_perf_stream *stream,
> * only be incremented by multiples of the report size (notably also
> * all a power of two).
> */
> - if (WARN_ONCE(head > OA_BUFFER_SIZE || head % report_size ||
> - tail > OA_BUFFER_SIZE || tail % report_size,
> + if (WARN_ONCE(head > stream->oa_buffer.vma->size || head % report_size ||
> + tail > stream->oa_buffer.vma->size || tail % report_size,
> "Inconsistent OA buffer pointers: head = %u, tail = %u\n",
> head, tail))
> return -EIO;
> @@ -1005,7 +996,7 @@ static int gen7_append_oa_reports(struct i915_perf_stream *stream,
> * here would imply a driver bug that would result
> * in an overrun.
> */
> - if (WARN_ON((OA_BUFFER_SIZE - head) < report_size)) {
> + if (WARN_ON((stream->oa_buffer.vma->size - head) < report_size)) {
> DRM_ERROR("Spurious OA head ptr: non-integral report offset\n");
> break;
> }
> @@ -1408,7 +1399,9 @@ static void gen7_init_oa_buffer(struct i915_perf_stream *stream)
>
> I915_WRITE(GEN7_OABUFFER, gtt_offset);
>
> - I915_WRITE(GEN7_OASTATUS1, gtt_offset | OABUFFER_SIZE_16M); /* tail */
> + I915_WRITE(GEN7_OASTATUS1, gtt_offset |
> + ((stream->oa_buffer.size_exponent - 17) <<
> + GEN7_OASTATUS1_BUFFER_SIZE_SHIFT)); /* tail */
>
> /* Mark that we need updated tail pointers to read from... */
> stream->oa_buffer.tails[0].offset = INVALID_TAIL_PTR;
> @@ -1433,7 +1426,7 @@ static void gen7_init_oa_buffer(struct i915_perf_stream *stream)
> * the assumption that new reports are being written to zeroed
> * memory...
> */
> - memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
> + memset(stream->oa_buffer.vaddr, 0, stream->oa_buffer.vma->size);
>
> /* Maybe make ->pollin per-stream state if we support multiple
> * concurrent streams in the future.
> @@ -1464,7 +1457,9 @@ static void gen8_init_oa_buffer(struct i915_perf_stream *stream)
> * bit."
> */
> I915_WRITE(GEN8_OABUFFER, gtt_offset |
> - OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT);
> + ((stream->oa_buffer.size_exponent - 17) <<
> + GEN8_OABUFFER_BUFFER_SIZE_SHIFT) |
> + GEN8_OABUFFER_MEM_SELECT_GGTT);
> I915_WRITE(GEN8_OATAILPTR, gtt_offset & GEN8_OATAILPTR_MASK);
>
> /* Mark that we need updated tail pointers to read from... */
> @@ -1492,7 +1487,7 @@ static void gen8_init_oa_buffer(struct i915_perf_stream *stream)
> * the assumption that new reports are being written to zeroed
> * memory...
> */
> - memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
> + memset(stream->oa_buffer.vaddr, 0, stream->oa_buffer.vma->size);
>
> /*
> * Maybe make ->pollin per-stream state if we support multiple
> @@ -1501,24 +1496,25 @@ static void gen8_init_oa_buffer(struct i915_perf_stream *stream)
> stream->pollin = false;
> }
>
> -static int alloc_oa_buffer(struct i915_perf_stream *stream)
> +static int alloc_oa_buffer(struct i915_perf_stream *stream, int size_exponent)
> {
> struct drm_i915_gem_object *bo;
> struct drm_i915_private *dev_priv = stream->dev_priv;
> struct i915_vma *vma;
> + size_t size = 1U << size_exponent;
> int ret;
>
> if (WARN_ON(stream->oa_buffer.vma))
> return -ENODEV;
>
> + if (WARN_ON(size < SZ_128K || size > SZ_16M))
> + return -EINVAL;
> +
> ret = i915_mutex_lock_interruptible(&dev_priv->drm);
> if (ret)
> return ret;
>
> - BUILD_BUG_ON_NOT_POWER_OF_2(OA_BUFFER_SIZE);
> - BUILD_BUG_ON(OA_BUFFER_SIZE < SZ_128K || OA_BUFFER_SIZE > SZ_16M);
> -
> - bo = i915_gem_object_create_shmem(dev_priv, OA_BUFFER_SIZE);
> + bo = i915_gem_object_create_shmem(dev_priv, size);
> if (IS_ERR(bo)) {
> DRM_ERROR("Failed to allocate OA buffer\n");
> ret = PTR_ERR(bo);
> @@ -1534,6 +1530,7 @@ static int alloc_oa_buffer(struct i915_perf_stream *stream)
> goto err_unref;
> }
> stream->oa_buffer.vma = vma;
> + stream->oa_buffer.size_exponent = size_exponent;
>
> stream->oa_buffer.vaddr =
> i915_gem_object_pin_map(bo, I915_MAP_WB);
> @@ -1542,9 +1539,10 @@ static int alloc_oa_buffer(struct i915_perf_stream *stream)
> goto err_unpin;
> }
>
> - DRM_DEBUG_DRIVER("OA Buffer initialized, gtt offset = 0x%x, vaddr = %p\n",
> + DRM_DEBUG_DRIVER("OA Buffer initialized, gtt offset = 0x%x, vaddr = %p, size = %llu\n",
> i915_ggtt_offset(stream->oa_buffer.vma),
> - stream->oa_buffer.vaddr);
> + stream->oa_buffer.vaddr,
> + stream->oa_buffer.vma->size);
>
> goto unlock;
>
> @@ -2251,7 +2249,7 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
> stream->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
> intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>
> - ret = alloc_oa_buffer(stream);
> + ret = alloc_oa_buffer(stream, props->oa_buffer_size_exponent);
> if (ret)
> goto err_oa_buf_alloc;
>
> @@ -2823,6 +2821,26 @@ static u64 oa_exponent_to_ns(struct drm_i915_private *dev_priv, int exponent)
> 1000ULL * RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz);
> }
>
> +static int
> +select_oa_buffer_exponent(struct drm_i915_private *i915,
> + u64 requested_size)
> +{
> + int order;
> +
> + /*
> + * When no size is specified, use the largest size supported by all
> + * generations.
> + */
> + if (!requested_size)
> + return order_base_2(SZ_16M);
> +
> + order = order_base_2(clamp_t(u64, requested_size, SZ_128K, SZ_16M));
> + if (requested_size != (1UL << order))
> + return -EINVAL;
> +
> + return order;
> +}
> +
> /**
> * read_properties_unlocked - validate + copy userspace stream open properties
> * @dev_priv: i915 device instance
> @@ -2950,6 +2968,14 @@ static int read_properties_unlocked(struct drm_i915_private *dev_priv,
> props->oa_periodic = true;
> props->oa_period_exponent = value;
> break;
> + case DRM_I915_PERF_PROP_OA_BUFFER_SIZE:
> + ret = select_oa_buffer_exponent(dev_priv, value);
> + if (ret < 0) {
> + DRM_DEBUG("OA buffer size invalid %llu\n", value);
> + return ret;
> + }
> + props->oa_buffer_size_exponent = ret;
> + break;
> case DRM_I915_PERF_PROP_MAX:
> MISSING_CASE(id);
> return -EINVAL;
> @@ -2958,6 +2984,12 @@ static int read_properties_unlocked(struct drm_i915_private *dev_priv,
> uprop += 2;
> }
>
> + /* If no buffer size was requested, select the default one. */
> + if (!props->oa_buffer_size_exponent) {
> + props->oa_buffer_size_exponent =
> + select_oa_buffer_exponent(dev_priv, 0);
> + }
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 34d83e3a51a7..d35f385f8288 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -675,12 +675,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define GEN8_OABUFFER_UDW _MMIO(0x23b4)
> #define GEN8_OABUFFER _MMIO(0x2b14)
> #define GEN8_OABUFFER_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
> +#define GEN8_OABUFFER_BUFFER_SIZE_SHIFT 3
>
> #define GEN7_OASTATUS1 _MMIO(0x2364)
> #define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0
> #define GEN7_OASTATUS1_COUNTER_OVERFLOW (1 << 2)
> #define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1 << 1)
> #define GEN7_OASTATUS1_REPORT_LOST (1 << 0)
> +#define GEN7_OASTATUS1_BUFFER_SIZE_SHIFT 3
>
> #define GEN7_OASTATUS2 _MMIO(0x2368)
> #define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 469dc512cca3..f662c534de0a 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -1873,6 +1873,13 @@ enum drm_i915_perf_property_id {
> */
> DRM_I915_PERF_PROP_OA_EXPONENT,
>
> + /**
> + * Specify a global OA buffer size to be allocated in bytes. The size
> + * specified must be supported by HW (currently supported sizes are
> + * powers of 2 ranging from 128Kb to 16Mb).
> + */
> + DRM_I915_PERF_PROP_OA_BUFFER_SIZE,
> +
> DRM_I915_PERF_PROP_MAX /* non-ABI */
> };
>
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 58+ messages in thread* Re: [PATCH 33/39] drm/i915/perf: add a parameter to control the size of OA buffer
2019-08-16 8:04 ` [PATCH 33/39] drm/i915/perf: add a parameter to control the size of OA buffer Lucas De Marchi
2019-08-19 18:31 ` Umesh Nerlige Ramappa
2019-08-21 8:37 ` Lionel Landwerlin
@ 2019-08-22 10:43 ` Joonas Lahtinen
2019-08-22 12:13 ` Lionel Landwerlin
2 siblings, 1 reply; 58+ messages in thread
From: Joonas Lahtinen @ 2019-08-22 10:43 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx; +Cc: Matthew Auld
Quoting Lucas De Marchi (2019-08-16 11:04:57)
> From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>
> The way our hardware is designed doesn't seem to let us use the
> MI_RECORD_PERF_COUNT command without setting up a circular buffer.
>
> In the case where the user didn't request OA reports to be available
> through the i915 perf stream, we can set the OA buffer to the minimum
> size to avoid consuming memory which won't be used by the driver.
>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_perf.c | 98 +++++++++++++++++++++-----------
> drivers/gpu/drm/i915/i915_reg.h | 2 +
> include/uapi/drm/i915_drm.h | 7 +++
Any patch touching i915_drm.h should have a link to the corresponding
userspace series.
Regards, Joonas
_______________________________________________
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^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 33/39] drm/i915/perf: add a parameter to control the size of OA buffer
2019-08-22 10:43 ` Joonas Lahtinen
@ 2019-08-22 12:13 ` Lionel Landwerlin
2019-08-23 8:30 ` Lucas De Marchi
0 siblings, 1 reply; 58+ messages in thread
From: Lionel Landwerlin @ 2019-08-22 12:13 UTC (permalink / raw)
To: Joonas Lahtinen, Lucas De Marchi, intel-gfx; +Cc: Matthew Auld
On 22/08/2019 12:43, Joonas Lahtinen wrote:
> Quoting Lucas De Marchi (2019-08-16 11:04:57)
>> From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>>
>> The way our hardware is designed doesn't seem to let us use the
>> MI_RECORD_PERF_COUNT command without setting up a circular buffer.
>>
>> In the case where the user didn't request OA reports to be available
>> through the i915 perf stream, we can set the OA buffer to the minimum
>> size to avoid consuming memory which won't be used by the driver.
>>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Cc: Matthew Auld <matthew.auld@intel.com>
>> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_perf.c | 98 +++++++++++++++++++++-----------
>> drivers/gpu/drm/i915/i915_reg.h | 2 +
>> include/uapi/drm/i915_drm.h | 7 +++
> Any patch touching i915_drm.h should have a link to the corresponding
> userspace series.
>
> Regards, Joonas
>
Might be worth dropping this patch from the series then.
I don't think we have anything public or any coming userspace release
making use of this.
Cheers,
-Lionel
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH 33/39] drm/i915/perf: add a parameter to control the size of OA buffer
2019-08-22 12:13 ` Lionel Landwerlin
@ 2019-08-23 8:30 ` Lucas De Marchi
0 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-23 8:30 UTC (permalink / raw)
To: Lionel Landwerlin; +Cc: Intel Graphics, Lucas De Marchi, Matthew Auld
On Fri, Aug 23, 2019 at 1:13 AM Lionel Landwerlin
<lionel.g.landwerlin@intel.com> wrote:
>
> On 22/08/2019 12:43, Joonas Lahtinen wrote:
> > Quoting Lucas De Marchi (2019-08-16 11:04:57)
> >> From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> >>
> >> The way our hardware is designed doesn't seem to let us use the
> >> MI_RECORD_PERF_COUNT command without setting up a circular buffer.
> >>
> >> In the case where the user didn't request OA reports to be available
> >> through the i915 perf stream, we can set the OA buffer to the minimum
> >> size to avoid consuming memory which won't be used by the driver.
> >>
> >> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> >> Cc: Matthew Auld <matthew.auld@intel.com>
> >> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/i915_perf.c | 98 +++++++++++++++++++++-----------
> >> drivers/gpu/drm/i915/i915_reg.h | 2 +
> >> include/uapi/drm/i915_drm.h | 7 +++
> > Any patch touching i915_drm.h should have a link to the corresponding
> > userspace series.
> >
> > Regards, Joonas
> >
> Might be worth dropping this patch from the series then.
>
> I don't think we have anything public or any coming userspace release
> making use of this.
This is dropped from v3.
Lucas De Marchi
>
>
> Cheers,
>
>
> -Lionel
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH 34/39] drm/i915/tgl: Add perf support on TGL
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (32 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 33/39] drm/i915/perf: add a parameter to control the size of OA buffer Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-16 8:04 ` [PATCH 35/39] drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support Lucas De Marchi
` (8 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx
From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
The design of the OA unit has been split into several units. We now
have a global unit (OAG) and a render specific unit (OAR). This leads
to some changes on how we program things. Some details :
OAR:
- has its own set of counter registers, they are per-context
saved/restored
- counters are not written to the circular OA buffer
- a snapshot of the counters can be acquired with
MI_RECORD_PERF_COUNT, or a single counter can be read with
MI_STORE_REGISTER_MEM.
OAG:
- has global counters that increment across context switches
- counters are written into the circular OA buffer (if requested)
BSpec: 28727, 30021
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_perf.c | 236 ++++++++++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 103 +++++++++++
drivers/gpu/drm/i915/oa/i915_oa_tgl.c | 113 ++++++++++++
drivers/gpu/drm/i915/oa/i915_oa_tgl.h | 17 ++
5 files changed, 458 insertions(+), 14 deletions(-)
create mode 100644 drivers/gpu/drm/i915/oa/i915_oa_tgl.c
create mode 100644 drivers/gpu/drm/i915/oa/i915_oa_tgl.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 45add812048b..6d9040cdf431 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -234,7 +234,8 @@ i915-y += \
oa/i915_oa_cflgt2.o \
oa/i915_oa_cflgt3.o \
oa/i915_oa_cnl.o \
- oa/i915_oa_icl.o
+ oa/i915_oa_icl.o \
+ oa/i915_oa_tgl.o
i915-y += i915_perf.o
# Post-mortem debug and GPU hang state capture
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 9386d9c82930..250061cdad5c 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -215,6 +215,7 @@
#include "oa/i915_oa_cflgt3.h"
#include "oa/i915_oa_cnl.h"
#include "oa/i915_oa_icl.h"
+#include "oa/i915_oa_tgl.h"
#define OA_TAKEN(tail, head) (((tail) - (head)) & (stream->oa_buffer.vma->size - 1))
@@ -1496,6 +1497,73 @@ static void gen8_init_oa_buffer(struct i915_perf_stream *stream)
stream->pollin = false;
}
+static void gen12_init_oa_buffer(struct i915_perf_stream *stream)
+{
+ struct drm_i915_private *dev_priv = stream->dev_priv;
+ u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
+ unsigned long flags;
+
+ spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
+
+ I915_WRITE(GEN12_OAG_OASTATUS, 0);
+ I915_WRITE(GEN12_OAG_OAHEADPTR, gtt_offset & GEN12_OAG_OAHEADPTR_MASK);
+ stream->oa_buffer.head = gtt_offset;
+
+ /*
+ * PRM says:
+ *
+ * "This MMIO must be set before the OATAILPTR
+ * register and after the OAHEADPTR register. This is
+ * to enable proper functionality of the overflow
+ * bit."
+ *
+ * On hardware that supports it, OA buffer size goes up to 128Mb by
+ * toggling a bit in the OAG_OA_DEBUG register meaning multiply base
+ * value by 8. OA buffer size is already clamped between 128K and max
+ * supported size when validating properties passed by the user, so no
+ * need to check for specific hardware here.
+ */
+ I915_WRITE(GEN12_OAG_OABUFFER, gtt_offset |
+ ((stream->oa_buffer.size_exponent - 17) <<
+ GEN12_OAG_OABUFFER_BUFFER_SIZE_SHIFT) |
+ GEN8_OABUFFER_MEM_SELECT_GGTT);
+ I915_WRITE(GEN12_OAG_OATAILPTR, gtt_offset & GEN12_OAG_OATAILPTR_MASK);
+
+ /* Mark that we need updated tail pointers to read from... */
+ stream->oa_buffer.tails[0].offset = INVALID_TAIL_PTR;
+ stream->oa_buffer.tails[1].offset = INVALID_TAIL_PTR;
+
+ /*
+ * Reset state used to recognise context switches, affecting which
+ * reports we will forward to userspace while filtering for a single
+ * context.
+ */
+ stream->oa_buffer.last_ctx_id = INVALID_CTX_ID;
+
+ spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
+
+ /*
+ * NB: although the OA buffer will initially be allocated
+ * zeroed via shmfs (and so this memset is redundant when
+ * first allocating), we may re-init the OA buffer, either
+ * when re-enabling a stream or in error/reset paths.
+ *
+ * The reason we clear the buffer for each re-init is for the
+ * sanity check in gen8_append_oa_reports() that looks at the
+ * reason field to make sure it's non-zero which relies on
+ * the assumption that new reports are being written to zeroed
+ * memory...
+ */
+ memset(stream->oa_buffer.vaddr, 0,
+ stream->oa_buffer.vma->size);
+
+ /*
+ * Maybe make ->pollin per-stream state if we support multiple
+ * concurrent streams in the future.
+ */
+ stream->pollin = false;
+}
+
static int alloc_oa_buffer(struct i915_perf_stream *stream, int size_exponent)
{
struct drm_i915_gem_object *bo;
@@ -1691,10 +1759,21 @@ gen8_update_reg_state_unlocked(struct i915_perf_stream *stream,
};
int i;
- CTX_REG(reg_state, ctx_oactxctrl, GEN8_OACTXCONTROL,
- (stream->period_exponent << GEN8_OA_TIMER_PERIOD_SHIFT) |
- (stream->periodic ? GEN8_OA_TIMER_ENABLE : 0) |
- GEN8_OA_COUNTER_RESUME);
+ if (IS_GEN(i915, 12)) {
+ u32 format = stream->oa_buffer.format;
+
+ CTX_REG(reg_state, ctx_oactxctrl, GEN12_OAR_OACONTROL,
+ (format << GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT) |
+ (oa_config ? GEN12_OAR_OACONTROL_COUNTER_ENABLE : 0));
+ } else {
+ u32 period_exponent = stream->period_exponent;
+ bool periodic = stream->periodic;
+
+ CTX_REG(reg_state, ctx_oactxctrl, GEN8_OACTXCONTROL,
+ (period_exponent << GEN8_OA_TIMER_PERIOD_SHIFT) |
+ (periodic ? GEN8_OA_TIMER_ENABLE : 0) |
+ GEN8_OA_COUNTER_RESUME);
+ }
for (i = 0; i < ARRAY_SIZE(flex_regs); i++) {
CTX_REG(reg_state, ctx_flexeu0 + i * 2, flex_regs[i],
@@ -1855,8 +1934,8 @@ static int gen8_configure_context(struct i915_gem_context *ctx,
*
* Note: it's only the RCS/Render context that has any OA state.
*/
-static int gen8_configure_all_contexts(struct i915_perf_stream *stream,
- const struct i915_oa_config *oa_config)
+static int lrc_configure_all_contexts(struct i915_perf_stream *stream,
+ const struct i915_oa_config *oa_config)
{
struct drm_i915_private *i915 = stream->dev_priv;
/* The MMIO offsets for Flex EU registers aren't contiguous */
@@ -1981,7 +2060,50 @@ static int gen8_enable_metric_set(struct i915_perf_stream *stream)
* to make sure all slices/subslices are ON before writing to NOA
* registers.
*/
- ret = gen8_configure_all_contexts(stream, oa_config);
+ ret = lrc_configure_all_contexts(stream, oa_config);
+ if (ret)
+ return ret;
+
+ config_oa_regs(dev_priv, oa_config->mux_regs, oa_config->mux_regs_len);
+
+ config_oa_regs(dev_priv, oa_config->b_counter_regs,
+ oa_config->b_counter_regs_len);
+
+ return 0;
+}
+
+static int gen12_enable_metric_set(struct i915_perf_stream *stream)
+{
+ struct drm_i915_private *dev_priv = stream->dev_priv;
+ struct i915_oa_config *oa_config = stream->oa_config;
+ bool periodic = stream->periodic;
+ u32 period_exponent = stream->period_exponent;
+ int ret;
+
+ I915_WRITE(GEN12_OAG_OA_DEBUG,
+ /* Disable clk ratio reports, like previous Gens. */
+ _MASKED_BIT_ENABLE(GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
+ GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO) |
+ /*
+ * If the user didn't require OA reports, instruct the
+ * hardware not to emit ctx switch reports.
+ */
+ (stream->sample_flags & SAMPLE_OA_REPORT) ?
+ _MASKED_BIT_ENABLE(GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS) :
+ _MASKED_BIT_DISABLE(GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS));
+
+ I915_WRITE(GEN12_OAG_OAGLBCTXCTRL,
+ periodic ?
+ (GEN12_OAG_OAGLBCTXCTRL_TIMER_ENABLE |
+ period_exponent << GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT)
+ : 0);
+
+ /*
+ * Update all contexts prior writing the mux configurations as we need
+ * to make sure all slices/subslices are ON before writing to NOA
+ * registers.
+ */
+ ret = lrc_configure_all_contexts(stream, oa_config);
if (ret)
return ret;
@@ -1999,7 +2121,7 @@ static void gen8_disable_metric_set(struct i915_perf_stream *stream)
struct drm_i915_private *dev_priv = stream->dev_priv;
/* Reset all contexts' slices/subslices configurations. */
- gen8_configure_all_contexts(stream, NULL);
+ lrc_configure_all_contexts(stream, NULL);
I915_WRITE(GDT_CHICKEN_BITS, (I915_READ(GDT_CHICKEN_BITS) &
~GT_NOA_ENABLE));
@@ -2010,7 +2132,19 @@ static void gen10_disable_metric_set(struct i915_perf_stream *stream)
struct drm_i915_private *dev_priv = stream->dev_priv;
/* Reset all contexts' slices/subslices configurations. */
- gen8_configure_all_contexts(stream, NULL);
+ lrc_configure_all_contexts(stream, NULL);
+
+ /* Make sure we disable noa to save power. */
+ I915_WRITE(RPM_CONFIG1,
+ I915_READ(RPM_CONFIG1) & ~GEN10_GT_NOA_ENABLE);
+}
+
+static void gen12_disable_metric_set(struct i915_perf_stream *stream)
+{
+ struct drm_i915_private *dev_priv = stream->dev_priv;
+
+ /* Reset all contexts' slices/subslices configurations. */
+ lrc_configure_all_contexts(stream, NULL);
/* Make sure we disable noa to save power. */
I915_WRITE(RPM_CONFIG1,
@@ -2073,6 +2207,26 @@ static void gen8_oa_enable(struct i915_perf_stream *stream)
GEN8_OA_COUNTER_ENABLE);
}
+static void gen12_oa_enable(struct i915_perf_stream *stream)
+{
+ struct drm_i915_private *dev_priv = stream->dev_priv;
+ u32 report_format = stream->oa_buffer.format;
+
+ /*
+ * If we don't want OA reports from the OA buffer, then we don't even
+ * need to program the OAG unit.
+ */
+ if (!(stream->sample_flags & SAMPLE_OA_REPORT))
+ return;
+
+ gen12_init_oa_buffer(stream);
+
+ I915_WRITE(GEN12_OAG_OACONTROL,
+ (report_format <<
+ GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT) |
+ GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE);
+}
+
/**
* i915_oa_stream_enable - handle `I915_PERF_IOCTL_ENABLE` for OA stream
* @stream: An i915 perf stream opened for OA metrics
@@ -2116,6 +2270,13 @@ static void gen8_oa_disable(struct i915_perf_stream *stream)
DRM_ERROR("wait for OA to be disabled timed out\n");
}
+static void gen12_oa_disable(struct i915_perf_stream *stream)
+{
+ struct drm_i915_private *dev_priv = stream->dev_priv;
+
+ I915_WRITE(GEN12_OAG_OACONTROL, 0);
+}
+
/**
* i915_oa_stream_disable - handle `I915_PERF_IOCTL_DISABLE` for OA stream
* @stream: An i915 perf stream opened for OA metrics
@@ -2733,16 +2894,24 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv,
* rest of the system, which we consider acceptable for a
* non-privileged client.
*
- * For Gen8+ the OA unit no longer supports clock gating off for a
+ * For Gen8->11 the OA unit no longer supports clock gating off for a
* specific context and the kernel can't securely stop the counters
* from updating as system-wide / global values. Even though we can
* filter reports based on the included context ID we can't block
* clients from seeing the raw / global counter values via
* MI_REPORT_PERF_COUNT commands and so consider it a privileged op to
* enable the OA unit by default.
+ *
+ * For Gen12+ we gain a new OAR unit that only monitors the RCS on a
+ * per context basis. So we can relax requirements there if the user
+ * doesn't request global stream access (i.e. query based sampling
+ * using MI_RECORD_PERF_COUNT.
*/
if (IS_HASWELL(dev_priv) && specific_ctx)
privileged_op = false;
+ else if (IS_GEN(dev_priv, 12) && specific_ctx &&
+ (props->sample_flags & SAMPLE_OA_REPORT) == 0)
+ privileged_op = false;
/* Similar to perf's kernel.perf_paranoid_cpu sysctl option
* we check a dev.i915.perf_stream_paranoid sysctl option
@@ -3082,7 +3251,9 @@ void i915_perf_register(struct drm_i915_private *dev_priv)
sysfs_attr_init(&dev_priv->perf.test_config.sysfs_metric_id.attr);
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (IS_GEN(dev_priv, 12)) {
+ i915_perf_load_test_config_tgl(dev_priv);
+ } else if (INTEL_GEN(dev_priv) >= 11) {
i915_perf_load_test_config_icl(dev_priv);
} else if (IS_CANNONLAKE(dev_priv)) {
i915_perf_load_test_config_cnl(dev_priv);
@@ -3228,6 +3399,26 @@ static bool chv_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr)
(addr >= 0x182300 && addr <= 0x1823A4);
}
+static bool gen12_is_valid_b_counter_addr(struct drm_i915_private *dev_priv,
+ u32 addr)
+{
+ return (addr >= i915_mmio_reg_offset(GEN12_OAG_CEC0_0) &&
+ addr <= i915_mmio_reg_offset(GEN12_OAG_CEC7_1)) ||
+ (addr >= i915_mmio_reg_offset(GEN12_OAG_SCEC0_0) &&
+ addr <= i915_mmio_reg_offset(GEN12_OAG_SCEC7_1)) ||
+ addr == i915_mmio_reg_offset(GEN12_OAA_DBG_REG) ||
+ addr == i915_mmio_reg_offset(GEN12_OAG_OA_PESS) ||
+ addr == i915_mmio_reg_offset(GEN12_OAG_SPCTR_CNF);
+}
+
+static bool gen12_is_valid_mux_addr(struct drm_i915_private *dev_priv,
+ u32 addr)
+{
+ return addr == i915_mmio_reg_offset(NOA_WRITE) ||
+ (addr >= i915_mmio_reg_offset(NOA_CONFIG(0)) &&
+ addr <= i915_mmio_reg_offset(NOA_CONFIG(8)));
+}
+
static u32 mask_reg_value(u32 reg, u32 val)
{
/* HALF_SLICE_CHICKEN2 is programmed with a the
@@ -3617,8 +3808,6 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
*/
dev_priv->perf.oa_formats = gen8_plus_oa_formats;
- dev_priv->perf.ops.oa_enable = gen8_oa_enable;
- dev_priv->perf.ops.oa_disable = gen8_oa_disable;
dev_priv->perf.ops.read = gen8_oa_read;
dev_priv->perf.ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
@@ -3635,6 +3824,8 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
chv_is_valid_mux_addr;
}
+ dev_priv->perf.ops.oa_enable = gen8_oa_enable;
+ dev_priv->perf.ops.oa_disable = gen8_oa_disable;
dev_priv->perf.ops.enable_metric_set = gen8_enable_metric_set;
dev_priv->perf.ops.disable_metric_set = gen8_disable_metric_set;
@@ -3657,6 +3848,8 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
dev_priv->perf.ops.is_valid_flex_reg =
gen8_is_valid_flex_addr;
+ dev_priv->perf.ops.oa_enable = gen8_oa_enable;
+ dev_priv->perf.ops.oa_disable = gen8_oa_disable;
dev_priv->perf.ops.enable_metric_set = gen8_enable_metric_set;
dev_priv->perf.ops.disable_metric_set = gen10_disable_metric_set;
@@ -3668,6 +3861,23 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
dev_priv->perf.ctx_flexeu0_offset = 0x78e;
}
dev_priv->perf.gen8_valid_ctx_bit = BIT(16);
+ } else if (IS_GEN(dev_priv, 12)) {
+ dev_priv->perf.ops.is_valid_b_counter_reg =
+ gen12_is_valid_b_counter_addr;
+ dev_priv->perf.ops.is_valid_mux_reg =
+ gen12_is_valid_mux_addr;
+ dev_priv->perf.ops.is_valid_flex_reg =
+ gen8_is_valid_flex_addr;
+
+ dev_priv->perf.ops.oa_enable = gen12_oa_enable;
+ dev_priv->perf.ops.oa_disable = gen12_oa_disable;
+ dev_priv->perf.ops.enable_metric_set = gen12_enable_metric_set;
+ dev_priv->perf.ops.disable_metric_set = gen12_disable_metric_set;
+
+ dev_priv->perf.ctx_oactxctrl_offset = 0x14a; /* To verify */
+ dev_priv->perf.ctx_flexeu0_offset = 0x3de; /* To verify*/
+
+ dev_priv->perf.gen8_valid_ctx_bit = (1<<16);
}
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d35f385f8288..ae4485b60b53 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -699,6 +699,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN8_OATAILPTR _MMIO(0x2B10)
#define GEN8_OATAILPTR_MASK 0xffffffc0
+
#define OABUFFER_SIZE_128K (0 << 3)
#define OABUFFER_SIZE_256K (1 << 3)
#define OABUFFER_SIZE_512K (2 << 3)
@@ -708,6 +709,44 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define OABUFFER_SIZE_8M (6 << 3)
#define OABUFFER_SIZE_16M (7 << 3)
+/* Gen12 OAR unit */
+#define GEN12_OAR_OACONTROL _MMIO(0x2960)
+#define GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT 2
+#define GEN12_OAR_OACONTROL_COUNTER_ENABLE (1 << 0)
+
+#define GEN12_OAR_OASTATUS _MMIO(0x2968)
+
+/* Gen12 OAG unit */
+#define GEN12_OAG_OAHEADPTR _MMIO(0xdb00)
+#define GEN12_OAG_OAHEADPTR_MASK 0xffffffc0
+#define GEN12_OAG_OATAILPTR _MMIO(0xdb04)
+#define GEN12_OAG_OATAILPTR_MASK 0xffffffc0
+
+#define GEN12_OAG_OABUFFER _MMIO(0xdb08)
+#define GEN12_OAG_OABUFFER_BUFFER_SIZE_MASK (0x7)
+#define GEN12_OAG_OABUFFER_BUFFER_SIZE_SHIFT (3)
+#define GEN12_OAG_OABUFFER_MEMORY_SELECT (1 << 0) /* 0: PPGTT, 1: GGTT */
+
+#define GEN12_OAG_OAGLBCTXCTRL _MMIO(0x2b28)
+#define GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT 2
+#define GEN12_OAG_OAGLBCTXCTRL_TIMER_ENABLE (1 << 1)
+#define GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME (1 << 0)
+
+#define GEN12_OAG_OACONTROL _MMIO(0xdaf4)
+#define GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT 2
+#define GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE (1 << 0)
+
+#define GEN12_OAG_OA_DEBUG _MMIO(0xdaf8)
+#define GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6)
+#define GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5)
+#define GEN12_OAG_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2)
+#define GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
+
+#define GEN12_OAG_OASTATUS _MMIO(0xdafc)
+#define GEN12_OAG_OASTATUS_COUNTER_OVERFLOW (1 << 2)
+#define GEN12_OAG_OASTATUS_BUFFER_OVERFLOW (1 << 1)
+#define GEN12_OAG_OASTATUS_REPORT_LOST (1 << 0)
+
/*
* Flexible, Aggregate EU Counter Registers.
* Note: these aren't contiguous
@@ -944,6 +983,26 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
+/* Same layout as OASTARTTRIGX */
+#define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900)
+#define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904)
+#define GEN12_OAG_OASTARTTRIG3 _MMIO(0xd908)
+#define GEN12_OAG_OASTARTTRIG4 _MMIO(0xd90c)
+#define GEN12_OAG_OASTARTTRIG5 _MMIO(0xd910)
+#define GEN12_OAG_OASTARTTRIG6 _MMIO(0xd914)
+#define GEN12_OAG_OASTARTTRIG7 _MMIO(0xd918)
+#define GEN12_OAG_OASTARTTRIG8 _MMIO(0xd91c)
+
+/* Same layout as OAREPORTTRIGX */
+#define GEN12_OAG_OAREPORTTRIG1 _MMIO(0xd920)
+#define GEN12_OAG_OAREPORTTRIG2 _MMIO(0xd924)
+#define GEN12_OAG_OAREPORTTRIG3 _MMIO(0xd928)
+#define GEN12_OAG_OAREPORTTRIG4 _MMIO(0xd92c)
+#define GEN12_OAG_OAREPORTTRIG5 _MMIO(0xd930)
+#define GEN12_OAG_OAREPORTTRIG6 _MMIO(0xd934)
+#define GEN12_OAG_OAREPORTTRIG7 _MMIO(0xd938)
+#define GEN12_OAG_OAREPORTTRIG8 _MMIO(0xd93c)
+
/* CECX_0 */
#define OACEC_COMPARE_LESS_OR_EQUAL 6
#define OACEC_COMPARE_NOT_EQUAL 5
@@ -960,6 +1019,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define OACEC_SELECT_PREV (1 << 19)
#define OACEC_SELECT_BOOLEAN (2 << 19)
+/* 11-bit array 0: pass-through, 1: negated */
+#define GEN12_OASCEC_NEGATE_MASK 0x7ff
+#define GEN12_OASCEC_NEGATE_SHIFT 21
+
/* CECX_1 */
#define OACEC_MASK_MASK 0xffff
#define OACEC_CONSIDERATIONS_MASK 0xffff
@@ -982,6 +1045,42 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define OACEC7_0 _MMIO(0x27a8)
#define OACEC7_1 _MMIO(0x27ac)
+/* Same layout as CECX_Y */
+#define GEN12_OAG_CEC0_0 _MMIO(0xd940)
+#define GEN12_OAG_CEC0_1 _MMIO(0xd944)
+#define GEN12_OAG_CEC1_0 _MMIO(0xd948)
+#define GEN12_OAG_CEC1_1 _MMIO(0xd94c)
+#define GEN12_OAG_CEC2_0 _MMIO(0xd950)
+#define GEN12_OAG_CEC2_1 _MMIO(0xd954)
+#define GEN12_OAG_CEC3_0 _MMIO(0xd958)
+#define GEN12_OAG_CEC3_1 _MMIO(0xd95c)
+#define GEN12_OAG_CEC4_0 _MMIO(0xd960)
+#define GEN12_OAG_CEC4_1 _MMIO(0xd964)
+#define GEN12_OAG_CEC5_0 _MMIO(0xd968)
+#define GEN12_OAG_CEC5_1 _MMIO(0xd96c)
+#define GEN12_OAG_CEC6_0 _MMIO(0xd970)
+#define GEN12_OAG_CEC6_1 _MMIO(0xd974)
+#define GEN12_OAG_CEC7_0 _MMIO(0xd978)
+#define GEN12_OAG_CEC7_1 _MMIO(0xd97c)
+
+/* Same layout as CECX_Y + negate 11-bit array */
+#define GEN12_OAG_SCEC0_0 _MMIO(0xdc00)
+#define GEN12_OAG_SCEC0_1 _MMIO(0xdc04)
+#define GEN12_OAG_SCEC1_0 _MMIO(0xdc08)
+#define GEN12_OAG_SCEC1_1 _MMIO(0xdc0c)
+#define GEN12_OAG_SCEC2_0 _MMIO(0xdc10)
+#define GEN12_OAG_SCEC2_1 _MMIO(0xdc14)
+#define GEN12_OAG_SCEC3_0 _MMIO(0xdc18)
+#define GEN12_OAG_SCEC3_1 _MMIO(0xdc1c)
+#define GEN12_OAG_SCEC4_0 _MMIO(0xdc20)
+#define GEN12_OAG_SCEC4_1 _MMIO(0xdc24)
+#define GEN12_OAG_SCEC5_0 _MMIO(0xdc28)
+#define GEN12_OAG_SCEC5_1 _MMIO(0xdc2c)
+#define GEN12_OAG_SCEC6_0 _MMIO(0xdc30)
+#define GEN12_OAG_SCEC6_1 _MMIO(0xdc34)
+#define GEN12_OAG_SCEC7_0 _MMIO(0xdc38)
+#define GEN12_OAG_SCEC7_1 _MMIO(0xdc3c)
+
/* OA perf counters */
#define OA_PERFCNT1_LO _MMIO(0x91B8)
#define OA_PERFCNT1_HI _MMIO(0x91BC)
@@ -1062,6 +1161,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838)
#define MICRO_BP_FIRED_ARMED _MMIO(0x983C)
+#define GEN12_OAA_DBG_REG _MMIO(0xdc44)
+#define GEN12_OAG_OA_PESS _MMIO(0x2b2c)
+#define GEN12_OAG_SPCTR_CNF _MMIO(0xdc40)
+
#define GDT_CHICKEN_BITS _MMIO(0x9840)
#define GT_NOA_ENABLE 0x00000080
diff --git a/drivers/gpu/drm/i915/oa/i915_oa_tgl.c b/drivers/gpu/drm/i915/oa/i915_oa_tgl.c
new file mode 100644
index 000000000000..d803407a799e
--- /dev/null
+++ b/drivers/gpu/drm/i915/oa/i915_oa_tgl.c
@@ -0,0 +1,113 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2018 Intel Corporation
+ *
+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
+ * DO NOT EDIT manually!
+ */
+
+#include <linux/sysfs.h>
+
+#include "i915_drv.h"
+#include "i915_oa_tgl.h"
+
+static const struct i915_oa_reg b_counter_config_test_oa[] = {
+ { _MMIO(0xd920), 0x00000000 },
+ { _MMIO(0xd900), 0x00000000 },
+ { _MMIO(0xd904), 0xf0800000 },
+ { _MMIO(0xd910), 0x00000000 },
+ { _MMIO(0xd914), 0xf0800000 },
+ { _MMIO(0xdc40), 0x00ff0000 },
+ { _MMIO(0xd940), 0x00000004 },
+ { _MMIO(0xd944), 0x0000ffff },
+ { _MMIO(0xdc00), 0x00000004 },
+ { _MMIO(0xdc04), 0x0000ffff },
+ { _MMIO(0xd948), 0x00000003 },
+ { _MMIO(0xd94c), 0x0000ffff },
+ { _MMIO(0xdc08), 0x00000003 },
+ { _MMIO(0xdc0c), 0x0000ffff },
+ { _MMIO(0xd950), 0x00000007 },
+ { _MMIO(0xd954), 0x0000ffff },
+ { _MMIO(0xdc10), 0x00000007 },
+ { _MMIO(0xdc14), 0x0000ffff },
+ { _MMIO(0xd958), 0x00100002 },
+ { _MMIO(0xd95c), 0x0000fff7 },
+ { _MMIO(0xdc18), 0x00100002 },
+ { _MMIO(0xdc1c), 0x0000fff7 },
+ { _MMIO(0xd960), 0x00100002 },
+ { _MMIO(0xd964), 0x0000ffcf },
+ { _MMIO(0xdc20), 0x00100002 },
+ { _MMIO(0xdc24), 0x0000ffcf },
+ { _MMIO(0xd968), 0x00100082 },
+ { _MMIO(0xd96c), 0x0000ffef },
+ { _MMIO(0xdc28), 0x00100082 },
+ { _MMIO(0xdc2c), 0x0000ffef },
+ { _MMIO(0xd970), 0x001000c2 },
+ { _MMIO(0xd974), 0x0000ffe7 },
+ { _MMIO(0xdc30), 0x001000c2 },
+ { _MMIO(0xdc34), 0x0000ffe7 },
+ { _MMIO(0xd978), 0x00100001 },
+ { _MMIO(0xd97c), 0x0000ffe7 },
+ { _MMIO(0xdc38), 0x00100001 },
+ { _MMIO(0xdc3c), 0x0000ffe7 },
+ { _MMIO(0x2b2c), 0x00000000 },
+ { _MMIO(0xd920), 0x00000000 },
+ { _MMIO(0xd920), 0x00000000 },
+ { _MMIO(0xd920), 0x00000000 },
+ { _MMIO(0xd920), 0x00000000 },
+};
+
+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
+};
+
+static const struct i915_oa_reg mux_config_test_oa[] = {
+ { _MMIO(0xd04), 0x00000200 },
+ { _MMIO(0x9840), 0x00000000 },
+ { _MMIO(0x9884), 0x00000003 },
+ { _MMIO(0x9888), 0x49110000 },
+ { _MMIO(0x9888), 0x5d100400 },
+ { _MMIO(0x9888), 0x1d1103a3 },
+ { _MMIO(0x9888), 0x01110000 },
+ { _MMIO(0x9888), 0x61110000 },
+ { _MMIO(0x9888), 0x17100000 },
+ { _MMIO(0x9888), 0x55100000 },
+ { _MMIO(0x9888), 0x31100000 },
+ { _MMIO(0x9884), 0x00000003 },
+ { _MMIO(0x9888), 0x65100002 },
+ { _MMIO(0x9884), 0x00000000 },
+ { _MMIO(0x9888), 0x42000001 },
+};
+
+static ssize_t
+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "1\n");
+}
+
+void
+i915_perf_load_test_config_tgl(struct drm_i915_private *dev_priv)
+{
+ strlcpy(dev_priv->perf.test_config.uuid,
+ "5338e21d-f79c-49c2-88d6-47e5b8589291",
+ sizeof(dev_priv->perf.test_config.uuid));
+ dev_priv->perf.test_config.id = 1;
+
+ dev_priv->perf.test_config.mux_regs = mux_config_test_oa;
+ dev_priv->perf.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
+
+ dev_priv->perf.test_config.b_counter_regs = b_counter_config_test_oa;
+ dev_priv->perf.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
+
+ dev_priv->perf.test_config.flex_regs = flex_eu_config_test_oa;
+ dev_priv->perf.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
+
+ dev_priv->perf.test_config.sysfs_metric.name = "5338e21d-f79c-49c2-88d6-47e5b8589291";
+ dev_priv->perf.test_config.sysfs_metric.attrs = dev_priv->perf.test_config.attrs;
+
+ dev_priv->perf.test_config.attrs[0] = &dev_priv->perf.test_config.sysfs_metric_id.attr;
+
+ dev_priv->perf.test_config.sysfs_metric_id.attr.name = "id";
+ dev_priv->perf.test_config.sysfs_metric_id.attr.mode = 0444;
+ dev_priv->perf.test_config.sysfs_metric_id.show = show_test_oa_id;
+}
diff --git a/drivers/gpu/drm/i915/oa/i915_oa_tgl.h b/drivers/gpu/drm/i915/oa/i915_oa_tgl.h
new file mode 100644
index 000000000000..64aa47ce2e55
--- /dev/null
+++ b/drivers/gpu/drm/i915/oa/i915_oa_tgl.h
@@ -0,0 +1,17 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2018 Intel Corporation
+ *
+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
+ * DO NOT EDIT manually!
+ */
+
+#ifndef __I915_OA_TGL_H__
+#define __I915_OA_TGL_H__
+
+struct drm_i915_private;
+
+extern void i915_perf_load_test_config_tgl(struct drm_i915_private *dev_priv);
+
+#endif
--
2.21.0
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^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 35/39] drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (33 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 34/39] drm/i915/tgl: Add perf support on TGL Lucas De Marchi
@ 2019-08-16 8:04 ` Lucas De Marchi
2019-08-16 8:05 ` [PATCH 36/39] drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression Lucas De Marchi
` (7 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:04 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter, Dhinakaran Pandiyan
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Yf tiling was removed in gen-12, make the necessary to changes to not
expose the modifier to user space. Gen-12 display also is incompatible with
pre-gen12 Y-tiled compression, so do not expose
I915_FORMAT_MOD_Y_TILED_CCS.
Bspec: 29650
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 73 +++++++++++++++++++--
1 file changed, 67 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index dea63be1964f..71dae3c2f9db 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2157,6 +2157,13 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
DRM_FORMAT_MOD_INVALID
};
+static const u64 gen12_plane_format_modifiers_noccs[] = {
+ I915_FORMAT_MOD_Y_TILED,
+ I915_FORMAT_MOD_X_TILED,
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_FORMAT_MOD_INVALID
+};
+
static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
@@ -2305,6 +2312,42 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
}
}
+static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
+ u32 format, u64 modifier)
+{
+ switch (modifier) {
+ case DRM_FORMAT_MOD_LINEAR:
+ case I915_FORMAT_MOD_X_TILED:
+ case I915_FORMAT_MOD_Y_TILED:
+ break;
+ default:
+ return false;
+ }
+
+ switch (format) {
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ARGB8888:
+ case DRM_FORMAT_ABGR8888:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_XRGB2101010:
+ case DRM_FORMAT_XBGR2101010:
+ case DRM_FORMAT_YUYV:
+ case DRM_FORMAT_YVYU:
+ case DRM_FORMAT_UYVY:
+ case DRM_FORMAT_VYUY:
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_C8:
+ if (modifier == DRM_FORMAT_MOD_LINEAR ||
+ modifier == I915_FORMAT_MOD_X_TILED ||
+ modifier == I915_FORMAT_MOD_Y_TILED)
+ return true;
+ /* fall through */
+ default:
+ return false;
+ }
+}
+
static const struct drm_plane_funcs g4x_sprite_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
@@ -2341,6 +2384,15 @@ static const struct drm_plane_funcs skl_plane_funcs = {
.format_mod_supported = skl_plane_format_mod_supported,
};
+static const struct drm_plane_funcs gen12_plane_funcs = {
+ .update_plane = drm_atomic_helper_update_plane,
+ .disable_plane = drm_atomic_helper_disable_plane,
+ .destroy = intel_plane_destroy,
+ .atomic_duplicate_state = intel_plane_duplicate_state,
+ .atomic_destroy_state = intel_plane_destroy_state,
+ .format_mod_supported = gen12_plane_format_mod_supported,
+};
+
static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
enum pipe pipe, enum plane_id plane_id)
{
@@ -2429,6 +2481,7 @@ struct intel_plane *
skl_universal_plane_create(struct drm_i915_private *dev_priv,
enum pipe pipe, enum plane_id plane_id)
{
+ static const struct drm_plane_funcs *plane_funcs;
struct intel_plane *plane;
enum drm_plane_type plane_type;
unsigned int supported_rotations;
@@ -2471,11 +2524,19 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
formats = skl_get_plane_formats(dev_priv, pipe,
plane_id, &num_formats);
- plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
- if (plane->has_ccs)
- modifiers = skl_plane_format_modifiers_ccs;
- else
- modifiers = skl_plane_format_modifiers_noccs;
+ if (INTEL_GEN(dev_priv) >= 12) {
+ /* TODO: Implement support for gen-12 CCS modifiers */
+ plane->has_ccs = false;
+ modifiers = gen12_plane_format_modifiers_noccs;
+ plane_funcs = &gen12_plane_funcs;
+ } else {
+ plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
+ if (plane->has_ccs)
+ modifiers = skl_plane_format_modifiers_ccs;
+ else
+ modifiers = skl_plane_format_modifiers_noccs;
+ plane_funcs = &skl_plane_funcs;
+ }
if (plane_id == PLANE_PRIMARY)
plane_type = DRM_PLANE_TYPE_PRIMARY;
@@ -2485,7 +2546,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
possible_crtcs = BIT(pipe);
ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
- possible_crtcs, &skl_plane_funcs,
+ possible_crtcs, plane_funcs,
formats, num_formats, modifiers,
plane_type,
"plane %d%c", plane_id + 1,
--
2.21.0
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^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 36/39] drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (34 preceding siblings ...)
2019-08-16 8:04 ` [PATCH 35/39] drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support Lucas De Marchi
@ 2019-08-16 8:05 ` Lucas De Marchi
2019-08-16 8:05 ` [PATCH 37/39] drm/i915/tgl: Gen-12 render decompression Lucas De Marchi
` (6 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter, Dhinakaran Pandiyan
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Gen-12 has a new compression format, add a new modifier for userspace to
indicate that.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
include/uapi/drm/drm_fourcc.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 3feeaa3f987a..fb7270bf9670 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -410,6 +410,16 @@ extern "C" {
#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
+/*
+ * Intel color control surfaces (CCS) for Gen-12 render compression.
+ *
+ * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear and
+ * at index 1. A CCS cache line corresponds to an area of 4x1 tiles in the main
+ * surface. The main surface pitch is required to be a multiple of 4 tile
+ * widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 37/39] drm/i915/tgl: Gen-12 render decompression
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (35 preceding siblings ...)
2019-08-16 8:05 ` [PATCH 36/39] drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression Lucas De Marchi
@ 2019-08-16 8:05 ` Lucas De Marchi
2019-08-16 8:05 ` [PATCH 38/39] drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression Lucas De Marchi
` (5 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter, Dhinakaran Pandiyan
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Gen-12 decompression is supported with Y-tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Gen-12 display decompression is incompatible with buffers
compressed by earlier GPUs, so make use of a new modifier to identify
gen-12 compression. Another notable change is that decompression is
supported on all planes except cursor and on all pipes. This patch adds
decompression support for [A,X]BGR888 pixel formats.
Bspec: Render Decompression (18437)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 63 +++++++++++++++++---
drivers/gpu/drm/i915/display/intel_sprite.c | 23 ++++---
2 files changed, 71 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 81c1d359edb2..89067a9f4a3c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1928,6 +1928,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
if (color_plane == 1)
return 128;
/* fall through */
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ if (color_plane == 1)
+ return cpp;
+ /* fall through */
case I915_FORMAT_MOD_Y_TILED:
if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
return 128;
@@ -2061,6 +2065,8 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
if (INTEL_GEN(dev_priv) >= 9)
return 256 * 1024;
return 0;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ return 4 * 4 * 1024;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED:
@@ -2258,7 +2264,8 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
static bool is_surface_linear(u64 modifier, int color_plane)
{
- return modifier == DRM_FORMAT_MOD_LINEAR;
+ return modifier == DRM_FORMAT_MOD_LINEAR ||
+ (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane == 1);
}
static u32 intel_adjust_aligned_offset(int *x, int *y,
@@ -2445,6 +2452,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
return I915_TILING_X;
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Y_TILED_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return I915_TILING_Y;
default:
return I915_TILING_NONE;
@@ -2465,7 +2473,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
* us a ratio of one byte in the CCS for each 8x16 pixels in the
* main surface.
*/
-static const struct drm_format_info ccs_formats[] = {
+static const struct drm_format_info skl_ccs_formats[] = {
{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
.cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
@@ -2476,6 +2484,24 @@ static const struct drm_format_info ccs_formats[] = {
.cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
};
+/*
+ * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
+ * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
+ * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
+ * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2 x 32 pixels in
+ * the main surface.
+ */
+static const struct drm_format_info gen12_ccs_formats[] = {
+ { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, },
+ { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+ { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 2, .vsub = 32, .has_alpha = true },
+};
+
static const struct drm_format_info *
lookup_format_info(const struct drm_format_info formats[],
int num_formats, u32 format)
@@ -2496,8 +2522,12 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
switch (cmd->modifier[0]) {
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
- return lookup_format_info(ccs_formats,
- ARRAY_SIZE(ccs_formats),
+ return lookup_format_info(skl_ccs_formats,
+ ARRAY_SIZE(skl_ccs_formats),
+ cmd->pixel_format);
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ return lookup_format_info(gen12_ccs_formats,
+ ARRAY_SIZE(gen12_ccs_formats),
cmd->pixel_format);
default:
return NULL;
@@ -2506,7 +2536,8 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
bool is_ccs_modifier(u64 modifier)
{
- return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
+ return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
@@ -2675,7 +2706,13 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
int main_x, main_y;
int ccs_x, ccs_y;
- intel_tile_dims(fb, i, &tile_width, &tile_height);
+ if (!is_surface_linear(fb->modifier, i)) {
+ intel_tile_dims(fb, i, &tile_width, &tile_height);
+ } else {
+ tile_width = 64/cpp;
+ tile_height = 1;
+ }
+
tile_width *= hsub;
tile_height *= vsub;
@@ -4065,6 +4102,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
case I915_FORMAT_MOD_Y_TILED:
return PLANE_CTL_TILED_Y;
case I915_FORMAT_MOD_Y_TILED_CCS:
+ /* fall through */
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
case I915_FORMAT_MOD_Yf_TILED:
return PLANE_CTL_TILED_YF;
@@ -9844,7 +9883,9 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
case PLANE_CTL_TILED_Y:
plane_config->tiling = I915_TILING_Y;
if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
- fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
+ fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
+ I915_FORMAT_MOD_Y_TILED_CCS;
else
fb->modifier = I915_FORMAT_MOD_Y_TILED;
break;
@@ -15716,6 +15757,14 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
is_ccs_modifier(fb->modifier))
stride_alignment *= 4;
+ /*
+ * The main surface pitch must be paded to a multiple of four
+ * tile widths.
+ */
+ if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS &&
+ i == 0)
+ stride_alignment *= 4;
+
if (fb->pitches[i] & (stride_alignment - 1)) {
DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n",
i, fb->pitches[i], stride_alignment);
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 71dae3c2f9db..73d32017be89 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -547,6 +547,7 @@ skl_program_plane(struct intel_plane *plane,
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
u32 surf_addr = plane_state->color_plane[color_plane].offset;
u32 stride = skl_plane_stride(plane_state, color_plane);
+ u32 aux_dist = plane_state->color_plane[1].offset - surf_addr;
u32 aux_stride = skl_plane_stride(plane_state, 1);
int crtc_x = plane_state->base.dst.x1;
int crtc_y = plane_state->base.dst.y1;
@@ -588,8 +589,10 @@ skl_program_plane(struct intel_plane *plane,
I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
- I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
- (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
+
+ if (INTEL_GEN(dev_priv) < 12)
+ aux_dist |= aux_stride;
+ I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), aux_dist);
if (icl_is_hdr_plane(dev_priv, plane_id)) {
u32 cus_ctl = 0;
@@ -1745,7 +1748,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
(fb->modifier == I915_FORMAT_MOD_Y_TILED ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
- fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
+ fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
return -EINVAL;
}
@@ -2157,7 +2161,8 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
DRM_FORMAT_MOD_INVALID
};
-static const u64 gen12_plane_format_modifiers_noccs[] = {
+static const u64 gen12_plane_format_modifiers_ccs[] = {
+ I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_LINEAR,
@@ -2319,6 +2324,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
break;
default:
return false;
@@ -2329,6 +2335,9 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_XBGR8888:
case DRM_FORMAT_ARGB8888:
case DRM_FORMAT_ABGR8888:
+ if (is_ccs_modifier(modifier))
+ return true;
+ /* fall through */
case DRM_FORMAT_RGB565:
case DRM_FORMAT_XRGB2101010:
case DRM_FORMAT_XBGR2101010:
@@ -2524,13 +2533,11 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
formats = skl_get_plane_formats(dev_priv, pipe,
plane_id, &num_formats);
+ plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
if (INTEL_GEN(dev_priv) >= 12) {
- /* TODO: Implement support for gen-12 CCS modifiers */
- plane->has_ccs = false;
- modifiers = gen12_plane_format_modifiers_noccs;
+ modifiers = gen12_plane_format_modifiers_ccs;
plane_funcs = &gen12_plane_funcs;
} else {
- plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
if (plane->has_ccs)
modifiers = skl_plane_format_modifiers_ccs;
else
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 38/39] drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (36 preceding siblings ...)
2019-08-16 8:05 ` [PATCH 37/39] drm/i915/tgl: Gen-12 render decompression Lucas De Marchi
@ 2019-08-16 8:05 ` Lucas De Marchi
2019-08-16 8:05 ` [PATCH 39/39] drm/i915/tgl: " Lucas De Marchi
` (4 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Gen-12 display can decompress surfaces compressed by the media engine, add
a new modifier as the driver needs to know the surface was compressed by
the media or render engine.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
include/uapi/drm/drm_fourcc.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index fb7270bf9670..ec8351922265 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -420,6 +420,16 @@ extern "C" {
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+/*
+ * Intel color control surfaces (CCS) for Gen-12 media compression.
+ *
+ * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear and
+ * at index 1. A CCS cache line corresponds to an area of 4x1 tiles in the main
+ * surface. The main surface pitch is required to be a multiple of 4 tile
+ * widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 58+ messages in thread* [PATCH 39/39] drm/i915/tgl: Gen-12 media compression
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (37 preceding siblings ...)
2019-08-16 8:05 ` [PATCH 38/39] drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression Lucas De Marchi
@ 2019-08-16 8:05 ` Lucas De Marchi
2019-08-16 9:37 ` ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake batch 3 Patchwork
` (3 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2019-08-16 8:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Gen-12 display can decompress surfaces compressed by the media engine.
Detect the modifier corresponding to media compression to enable
decompression for YUV and ARGB packed formats. A new modifier is added
so that the driver can distinguish between media and render compressed
buffers. Unlike render decompression, plane 6 and plane 7 do not support
media decompression.
Bspec: 29695
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 23 +++++++++++++++++---
drivers/gpu/drm/i915/display/intel_sprite.c | 20 +++++++++++++----
drivers/gpu/drm/i915/i915_reg.h | 1 +
3 files changed, 37 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 89067a9f4a3c..42f9c480222c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1929,6 +1929,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
return 128;
/* fall through */
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
if (color_plane == 1)
return cpp;
/* fall through */
@@ -2066,6 +2067,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
return 256 * 1024;
return 0;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return 4 * 4 * 1024;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -2264,8 +2266,15 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
static bool is_surface_linear(u64 modifier, int color_plane)
{
- return modifier == DRM_FORMAT_MOD_LINEAR ||
- (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS && color_plane == 1);
+ switch (modifier) {
+ case DRM_FORMAT_MOD_LINEAR:
+ return true;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ return color_plane == 1;
+ default:
+ return false;
+ }
}
static u32 intel_adjust_aligned_offset(int *x, int *y,
@@ -2453,6 +2462,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return I915_TILING_Y;
default:
return I915_TILING_NONE;
@@ -2526,6 +2536,7 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
ARRAY_SIZE(skl_ccs_formats),
cmd->pixel_format);
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return lookup_format_info(gen12_ccs_formats,
ARRAY_SIZE(gen12_ccs_formats),
cmd->pixel_format);
@@ -2537,6 +2548,7 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
bool is_ccs_modifier(u64 modifier)
{
return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
@@ -4105,6 +4117,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
/* fall through */
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
case I915_FORMAT_MOD_Yf_TILED:
return PLANE_CTL_TILED_YF;
case I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -9886,6 +9900,8 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
fb->modifier = INTEL_GEN(dev_priv) >= 12 ?
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
I915_FORMAT_MOD_Y_TILED_CCS;
+ else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
+ fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
else
fb->modifier = I915_FORMAT_MOD_Y_TILED;
break;
@@ -15761,7 +15777,8 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
* The main surface pitch must be paded to a multiple of four
* tile widths.
*/
- if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS &&
+ if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS) &&
i == 0)
stride_alignment *= 4;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 73d32017be89..5df3a899068e 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -1749,7 +1749,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
- fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS)) {
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) {
DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
return -EINVAL;
}
@@ -2163,6 +2164,7 @@ static const u64 skl_plane_format_modifiers_ccs[] = {
static const u64 gen12_plane_format_modifiers_ccs[] = {
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+ I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_LINEAR,
@@ -2320,7 +2322,13 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
+ struct intel_plane *plane = to_intel_plane(_plane);
+
switch (modifier) {
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ if (plane->id >= PLANE_SPRITE4)
+ return false;
+ /* fall through */
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
@@ -2338,14 +2346,18 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
if (is_ccs_modifier(modifier))
return true;
/* fall through */
- case DRM_FORMAT_RGB565:
- case DRM_FORMAT_XRGB2101010:
- case DRM_FORMAT_XBGR2101010:
case DRM_FORMAT_YUYV:
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
+ if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
+ return true;
+ /* fall through */
+ /* TODO: Media decompression does support NV12 */
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_XRGB2101010:
+ case DRM_FORMAT_XBGR2101010:
case DRM_FORMAT_C8:
if (modifier == DRM_FORMAT_MOD_LINEAR ||
modifier == I915_FORMAT_MOD_X_TILED ||
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ae4485b60b53..205cf6f45f65 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6853,6 +6853,7 @@ enum {
#define PLANE_CTL_TILED_Y (4 << 10)
#define PLANE_CTL_TILED_YF (5 << 10)
#define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
+#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
#define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
#define PLANE_CTL_ALPHA_DISABLE (0 << 4)
#define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4)
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 58+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake batch 3
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (38 preceding siblings ...)
2019-08-16 8:05 ` [PATCH 39/39] drm/i915/tgl: " Lucas De Marchi
@ 2019-08-16 9:37 ` Patchwork
2019-08-16 9:51 ` ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
42 siblings, 0 replies; 58+ messages in thread
From: Patchwork @ 2019-08-16 9:37 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Tiger Lake batch 3
URL : https://patchwork.freedesktop.org/series/65290/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2f6d4ad3eda1 drm/i915/tgl: do not use DDIC
c0c2c6e584ca drm/i915/psr: Make PSR registers relative to transcoders
-:427: WARNING:LONG_LINE_COMMENT: line over 100 characters
#427: FILE: drivers/gpu/drm/i915/i915_reg.h:4311:
+#define EDP_PSR_AUX_DATA(tran, i) _MMIO(_PSR_ADJ(tran, _SRD_AUX_DATA_A) + (i) + 4) /* 5 registers */
total: 0 errors, 1 warnings, 0 checks, 393 lines checked
7cfc49277b02 drm/i915: Add transcoder restriction to PSR2
39b89150c6cd drm/i915: Do not unmask PSR interruption in IRQ postinstall
d626b231f0fb drm/i915/psr: Only handle interruptions of the transcoder in use
-:229: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'trans' - possible side-effects?
#229: FILE: drivers/gpu/drm/i915/i915_reg.h:4292:
+#define _EDP_PSR_TRANS_SHIFT(trans) (trans == TRANSCODER_EDP ? 0 : (trans + 1) * 8)
-:229: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'trans' may be better as '(trans)' to avoid precedence issues
#229: FILE: drivers/gpu/drm/i915/i915_reg.h:4292:
+#define _EDP_PSR_TRANS_SHIFT(trans) (trans == TRANSCODER_EDP ? 0 : (trans + 1) * 8)
total: 0 errors, 0 warnings, 2 checks, 203 lines checked
451e5d5e655b drm/i915/bdw+: Enable PSR in any eDP port
-:28: ERROR:CODE_INDENT: code indent should use tabs where possible
#28: FILE: drivers/gpu/drm/i915/display/intel_psr.c:581:
+ * BDW+ platforms with DDI implementation of PSR have different$
total: 1 errors, 0 warnings, 0 checks, 14 lines checked
2b396b0fd3a0 drm/i915: Guard and warn if more than one eDP panel is present
83d401588ff1 drm/i915/tgl: Change PSR2 transcoder restriction
d822292eb833 drm/i915: Do not read PSR2 register in transcoders without PSR2
3e0a6b536020 drm/i915/tgl: PSR link standby is not supported anymore
6a5a43b3886e drm/i915/tgl: Access the right register when handling PSR interruptions
09bfdb8f1220 drm/i915/tgl: Add maximum resolution supported by PSR2 HW
3c79bc060462 drm/i915/mst: Do not hardcoded the crtcs that encoder can connect
a74e4acb4ff7 drm/i915: Add for_each_new_intel_connector_in_state()
-:22: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#22: FILE: drivers/gpu/drm/i915/display/intel_display.h:414:
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->base.num_connector; \
+ (__i)++) \
+ for_each_if ((__state)->base.connectors[__i].ptr && \
+ ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+ (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
-:22: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible side-effects?
#22: FILE: drivers/gpu/drm/i915/display/intel_display.h:414:
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->base.num_connector; \
+ (__i)++) \
+ for_each_if ((__state)->base.connectors[__i].ptr && \
+ ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+ (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
-:22: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#22: FILE: drivers/gpu/drm/i915/display/intel_display.h:414:
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+ for ((__i) = 0; \
+ (__i) < (__state)->base.num_connector; \
+ (__i)++) \
+ for_each_if ((__state)->base.connectors[__i].ptr && \
+ ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+ (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
-:26: WARNING:SPACING: space prohibited between function name and open parenthesis '('
#26: FILE: drivers/gpu/drm/i915/display/intel_display.h:418:
+ for_each_if ((__state)->base.connectors[__i].ptr && \
-:27: WARNING:LONG_LINE: line over 100 characters
#27: FILE: drivers/gpu/drm/i915/display/intel_display.h:419:
+ ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
-:28: WARNING:LONG_LINE: line over 100 characters
#28: FILE: drivers/gpu/drm/i915/display/intel_display.h:420:
+ (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
total: 1 errors, 3 warnings, 2 checks, 14 lines checked
be1c98132963 drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
-:25: CHECK:LINE_SPACING: Please don't use multiple blank lines
#25: FILE: drivers/gpu/drm/i915/display/intel_display.h:414:
+
-:33: WARNING:LONG_LINE: line over 100 characters
#33: FILE: drivers/gpu/drm/i915/display/intel_display.h:423:
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
-:33: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible side-effects?
#33: FILE: drivers/gpu/drm/i915/display/intel_display.h:423:
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+ for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
+ (__i) >= 0 && \
+ ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+ (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+ (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+ (__i)--) \
+ for_each_if(crtc)
-:33: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'crtc' - possible side-effects?
#33: FILE: drivers/gpu/drm/i915/display/intel_display.h:423:
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+ for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
+ (__i) >= 0 && \
+ ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+ (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+ (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+ (__i)--) \
+ for_each_if(crtc)
-:33: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#33: FILE: drivers/gpu/drm/i915/display/intel_display.h:423:
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+ for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
+ (__i) >= 0 && \
+ ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+ (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+ (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+ (__i)--) \
+ for_each_if(crtc)
total: 0 errors, 1 warnings, 4 checks, 22 lines checked
e4f1a7b7ac7d drm/i915: Disable pipes in reverse order
31a881d23902 drm/i915/tgl: Select master transcoder in DP MST
646b03f0618a drm/i915/tgl: Introduce initial Tiger Lake workarounds
e0b3f8f95c79 drm/i915/tgl: Implement Wa_1406941453
c9ba1d70c006 drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
71de6cdc0cfe drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards
-:11: WARNING:BAD_SIGN_OFF: Duplicate signature
#11:
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
total: 0 errors, 1 warnings, 0 checks, 8 lines checked
9f588da30621 drm/i915/tgl: implement WaProgramMgsrForCorrectSliceSpecificMmioReads
df2f2dd03b35 drm/i915/tgl: Register state context definition for Gen12
-:16: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#16:
the gen8 path), fix length of first LRI for non-rcs to include the semaphore
total: 0 errors, 1 warnings, 0 checks, 240 lines checked
19e7d157eeab drm/i915/tgl: move DP_TP_* to transcoder
9a5fcbcdce67 drm/i915/tgl: Implement TGL DisplayPort training sequence
02738cff2fc6 HACK: drm/i915/tgl: Gen12 render context size
6ffd68d96f23 drm/i915/tgl: add Gen12 default indirect ctx offset
06ab10d9acec drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID
5fb45b0f331a drm/i915/tgl: Report valid VDBoxes with SFC capability
9a45d563be0c drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
f5852b6a5343 drm/i915/tgl: Updated Private PAT programming
d07f569dbdfc drm/i915/tgl/perf: use the same oa ctx_id format as icl
812b8979deb4 drm/i915/perf: add a parameter to control the size of OA buffer
cc1d225b2d89 drm/i915/tgl: Add perf support on TGL
-:398: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#398: FILE: drivers/gpu/drm/i915/i915_perf.c:3880:
+ dev_priv->perf.gen8_valid_ctx_bit = (1<<16);
^
-:410: CHECK:LINE_SPACING: Please don't use multiple blank lines
#410: FILE: drivers/gpu/drm/i915/i915_reg.h:702:
+
-:552: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#552:
new file mode 100644
-:557: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#557: FILE: drivers/gpu/drm/i915/oa/i915_oa_tgl.c:1:
+/*
-:558: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead
#558: FILE: drivers/gpu/drm/i915/oa/i915_oa_tgl.c:2:
+ * SPDX-License-Identifier: MIT
-:676: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#676: FILE: drivers/gpu/drm/i915/oa/i915_oa_tgl.h:1:
+/*
-:677: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead
#677: FILE: drivers/gpu/drm/i915/oa/i915_oa_tgl.h:2:
+ * SPDX-License-Identifier: MIT
-:690: CHECK:AVOID_EXTERNS: extern prototypes should be avoided in .h files
#690: FILE: drivers/gpu/drm/i915/oa/i915_oa_tgl.h:15:
+extern void i915_perf_load_test_config_tgl(struct drm_i915_private *dev_priv);
total: 0 errors, 5 warnings, 3 checks, 619 lines checked
ec3736e13a4b drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
a8f121f6224c drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression
94f0008b78ce drm/i915/tgl: Gen-12 render decompression
-:134: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#134: FILE: drivers/gpu/drm/i915/display/intel_display.c:2712:
+ tile_width = 64/cpp;
^
total: 0 errors, 0 warnings, 1 checks, 203 lines checked
ad1ee48f6561 drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression
5390f66e9174 drm/i915/tgl: Gen-12 media compression
-:50: WARNING:TABSTOP: Statements should start on a tabstop
#50: FILE: drivers/gpu/drm/i915/display/intel_display.c:2271:
+ return true;
-:53: WARNING:TABSTOP: Statements should start on a tabstop
#53: FILE: drivers/gpu/drm/i915/display/intel_display.c:2274:
+ return color_plane == 1;
-:55: WARNING:TABSTOP: Statements should start on a tabstop
#55: FILE: drivers/gpu/drm/i915/display/intel_display.c:2276:
+ return false;
-:72: WARNING:MISSING_BREAK: Possible switch case/default not preceded by break or fallthrough comment
#72: FILE: drivers/gpu/drm/i915/display/intel_display.c:2539:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
total: 0 errors, 4 warnings, 0 checks, 134 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 58+ messages in thread* ✗ Fi.CI.SPARSE: warning for Tiger Lake batch 3
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (39 preceding siblings ...)
2019-08-16 9:37 ` ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake batch 3 Patchwork
@ 2019-08-16 9:51 ` Patchwork
2019-08-16 9:57 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-16 21:26 ` ✓ Fi.CI.IGT: " Patchwork
42 siblings, 0 replies; 58+ messages in thread
From: Patchwork @ 2019-08-16 9:51 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Tiger Lake batch 3
URL : https://patchwork.freedesktop.org/series/65290/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/tgl: do not use DDIC
Okay!
Commit: drm/i915/psr: Make PSR registers relative to transcoders
Okay!
Commit: drm/i915: Add transcoder restriction to PSR2
Okay!
Commit: drm/i915: Do not unmask PSR interruption in IRQ postinstall
Okay!
Commit: drm/i915/psr: Only handle interruptions of the transcoder in use
Okay!
Commit: drm/i915/bdw+: Enable PSR in any eDP port
Okay!
Commit: drm/i915: Guard and warn if more than one eDP panel is present
Okay!
Commit: drm/i915/tgl: Change PSR2 transcoder restriction
Okay!
Commit: drm/i915: Do not read PSR2 register in transcoders without PSR2
Okay!
Commit: drm/i915/tgl: PSR link standby is not supported anymore
Okay!
Commit: drm/i915/tgl: Access the right register when handling PSR interruptions
Okay!
Commit: drm/i915/tgl: Add maximum resolution supported by PSR2 HW
Okay!
Commit: drm/i915/mst: Do not hardcoded the crtcs that encoder can connect
Okay!
Commit: drm/i915: Add for_each_new_intel_connector_in_state()
Okay!
Commit: drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
Okay!
Commit: drm/i915: Disable pipes in reverse order
Okay!
Commit: drm/i915/tgl: Select master transcoder in DP MST
Okay!
Commit: drm/i915/tgl: Introduce initial Tiger Lake workarounds
Okay!
Commit: drm/i915/tgl: Implement Wa_1406941453
Okay!
Commit: drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
Okay!
Commit: drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards
Okay!
Commit: drm/i915/tgl: implement WaProgramMgsrForCorrectSliceSpecificMmioReads
Okay!
Commit: drm/i915/tgl: Register state context definition for Gen12
Okay!
Commit: drm/i915/tgl: move DP_TP_* to transcoder
Okay!
Commit: drm/i915/tgl: Implement TGL DisplayPort training sequence
Okay!
Commit: HACK: drm/i915/tgl: Gen12 render context size
Okay!
Commit: drm/i915/tgl: add Gen12 default indirect ctx offset
Okay!
Commit: drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID
Okay!
Commit: drm/i915/tgl: Report valid VDBoxes with SFC capability
Okay!
Commit: drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
Okay!
Commit: drm/i915/tgl: Updated Private PAT programming
Okay!
Commit: drm/i915/tgl/perf: use the same oa ctx_id format as icl
Okay!
Commit: drm/i915/perf: add a parameter to control the size of OA buffer
-O:drivers/gpu/drm/i915/i915_perf.c:1436:15: warning: memset with byte count of 16777216
-O:drivers/gpu/drm/i915/i915_perf.c:1495:15: warning: memset with byte count of 16777216
Commit: drm/i915/tgl: Add perf support on TGL
Okay!
Commit: drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 58+ messages in thread* ✓ Fi.CI.BAT: success for Tiger Lake batch 3
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (40 preceding siblings ...)
2019-08-16 9:51 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2019-08-16 9:57 ` Patchwork
2019-08-16 21:26 ` ✓ Fi.CI.IGT: " Patchwork
42 siblings, 0 replies; 58+ messages in thread
From: Patchwork @ 2019-08-16 9:57 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Tiger Lake batch 3
URL : https://patchwork.freedesktop.org/series/65290/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6716 -> Patchwork_14046
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/
Known issues
------------
Here are the changes found in Patchwork_14046 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@read_all_entries:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-icl-u3/igt@debugfs_test@read_all_entries.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/fi-icl-u3/igt@debugfs_test@read_all_entries.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: [PASS][5] -> [SKIP][6] ([fdo#109271] / [fdo#109278]) +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-kbl-7567u/igt@kms_busy@basic-flip-a.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/fi-kbl-7567u/igt@kms_busy@basic-flip-a.html
#### Possible fixes ####
* igt@gem_exec_reloc@basic-write-gtt:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-icl-u3/igt@gem_exec_reloc@basic-write-gtt.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/fi-icl-u3/igt@gem_exec_reloc@basic-write-gtt.html
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [DMESG-FAIL][9] ([fdo#111108]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
- fi-bwr-2160: [DMESG-WARN][11] ([fdo#111115]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-bwr-2160/igt@i915_selftest@live_execlists.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/fi-bwr-2160/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_hangcheck:
- fi-bwr-2160: [DMESG-FAIL][13] ([fdo#111115]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-bwr-2160/igt@i915_selftest@live_hangcheck.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/fi-bwr-2160/igt@i915_selftest@live_hangcheck.html
* igt@i915_selftest@live_requests:
- fi-byt-j1900: [INCOMPLETE][15] ([fdo#102657]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-byt-j1900/igt@i915_selftest@live_requests.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/fi-byt-j1900/igt@i915_selftest@live_requests.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-icl-u2: [DMESG-WARN][17] ([fdo#102505] / [fdo#110390]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#102657]: https://bugs.freedesktop.org/show_bug.cgi?id=102657
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#110390]: https://bugs.freedesktop.org/show_bug.cgi?id=110390
[fdo#111108]: https://bugs.freedesktop.org/show_bug.cgi?id=111108
[fdo#111115]: https://bugs.freedesktop.org/show_bug.cgi?id=111115
Participating hosts (54 -> 45)
------------------------------
Additional (1): fi-cfl-8700k
Missing (10): fi-kbl-soraka fi-ilk-m540 fi-bdw-5557u fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6716 -> Patchwork_14046
CI-20190529: 20190529
CI_DRM_6716: 64ecd8f88d7b55de82ff414784ae4daca93d0577 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5138: b9abe0bf6c478c4f6cac56bff286d6926ad8c0ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14046: 5390f66e917426e5dc5c169cc45c04935ab9ca00 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
5390f66e9174 drm/i915/tgl: Gen-12 media compression
ad1ee48f6561 drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression
94f0008b78ce drm/i915/tgl: Gen-12 render decompression
a8f121f6224c drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression
ec3736e13a4b drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
cc1d225b2d89 drm/i915/tgl: Add perf support on TGL
812b8979deb4 drm/i915/perf: add a parameter to control the size of OA buffer
d07f569dbdfc drm/i915/tgl/perf: use the same oa ctx_id format as icl
f5852b6a5343 drm/i915/tgl: Updated Private PAT programming
9a45d563be0c drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
5fb45b0f331a drm/i915/tgl: Report valid VDBoxes with SFC capability
06ab10d9acec drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID
6ffd68d96f23 drm/i915/tgl: add Gen12 default indirect ctx offset
02738cff2fc6 HACK: drm/i915/tgl: Gen12 render context size
9a5fcbcdce67 drm/i915/tgl: Implement TGL DisplayPort training sequence
19e7d157eeab drm/i915/tgl: move DP_TP_* to transcoder
df2f2dd03b35 drm/i915/tgl: Register state context definition for Gen12
9f588da30621 drm/i915/tgl: implement WaProgramMgsrForCorrectSliceSpecificMmioReads
71de6cdc0cfe drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards
c9ba1d70c006 drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
e0b3f8f95c79 drm/i915/tgl: Implement Wa_1406941453
646b03f0618a drm/i915/tgl: Introduce initial Tiger Lake workarounds
31a881d23902 drm/i915/tgl: Select master transcoder in DP MST
e4f1a7b7ac7d drm/i915: Disable pipes in reverse order
be1c98132963 drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
a74e4acb4ff7 drm/i915: Add for_each_new_intel_connector_in_state()
3c79bc060462 drm/i915/mst: Do not hardcoded the crtcs that encoder can connect
09bfdb8f1220 drm/i915/tgl: Add maximum resolution supported by PSR2 HW
6a5a43b3886e drm/i915/tgl: Access the right register when handling PSR interruptions
3e0a6b536020 drm/i915/tgl: PSR link standby is not supported anymore
d822292eb833 drm/i915: Do not read PSR2 register in transcoders without PSR2
83d401588ff1 drm/i915/tgl: Change PSR2 transcoder restriction
2b396b0fd3a0 drm/i915: Guard and warn if more than one eDP panel is present
451e5d5e655b drm/i915/bdw+: Enable PSR in any eDP port
d626b231f0fb drm/i915/psr: Only handle interruptions of the transcoder in use
39b89150c6cd drm/i915: Do not unmask PSR interruption in IRQ postinstall
7cfc49277b02 drm/i915: Add transcoder restriction to PSR2
c0c2c6e584ca drm/i915/psr: Make PSR registers relative to transcoders
2f6d4ad3eda1 drm/i915/tgl: do not use DDIC
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 58+ messages in thread* ✓ Fi.CI.IGT: success for Tiger Lake batch 3
2019-08-16 8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
` (41 preceding siblings ...)
2019-08-16 9:57 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-08-16 21:26 ` Patchwork
42 siblings, 0 replies; 58+ messages in thread
From: Patchwork @ 2019-08-16 21:26 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Tiger Lake batch 3
URL : https://patchwork.freedesktop.org/series/65290/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6716_full -> Patchwork_14046_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_14046_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@rcs0-s3:
- shard-kbl: [PASS][1] -> [INCOMPLETE][2] ([fdo#103665])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-kbl3/igt@gem_ctx_isolation@rcs0-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-kbl3/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_exec_schedule@pi-ringfull-bsd:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-iclb7/igt@gem_exec_schedule@pi-ringfull-bsd.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-iclb2/igt@gem_exec_schedule@pi-ringfull-bsd.html
* igt@i915_pm_rpm@fences:
- shard-iclb: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713] / [fdo#108840])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-iclb8/igt@i915_pm_rpm@fences.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-iclb2/igt@i915_pm_rpm@fences.html
* igt@i915_selftest@live_hugepages:
- shard-snb: [PASS][7] -> [INCOMPLETE][8] ([fdo#105411])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-snb7/igt@i915_selftest@live_hugepages.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-snb6/igt@i915_selftest@live_hugepages.html
* igt@kms_cursor_crc@pipe-c-cursor-128x128-random:
- shard-skl: [PASS][9] -> [FAIL][10] ([fdo#103232]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-skl3/igt@kms_cursor_crc@pipe-c-cursor-128x128-random.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-skl7/igt@kms_cursor_crc@pipe-c-cursor-128x128-random.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-skl: [PASS][11] -> [INCOMPLETE][12] ([fdo#110741])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-skl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-skl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
- shard-apl: [PASS][13] -> [DMESG-WARN][14] ([fdo#108566]) +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-apl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-apl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [PASS][15] -> [FAIL][16] ([fdo#104873])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_flip@plain-flip-fb-recreate:
- shard-kbl: [PASS][17] -> [FAIL][18] ([fdo#100368])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-kbl3/igt@kms_flip@plain-flip-fb-recreate.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-kbl1/igt@kms_flip@plain-flip-fb-recreate.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
- shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +5 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [fdo#110403])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109441]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-iclb6/igt@kms_psr@psr2_no_drrs.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109276]) +14 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-iclb1/igt@prime_vgem@fence-wait-bsd2.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-iclb5/igt@prime_vgem@fence-wait-bsd2.html
#### Possible fixes ####
* igt@gem_exec_schedule@preempt-bsd:
- shard-iclb: [SKIP][29] ([fdo#111325]) -> [PASS][30] +4 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-iclb4/igt@gem_exec_schedule@preempt-bsd.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-iclb6/igt@gem_exec_schedule@preempt-bsd.html
* igt@gem_exec_schedule@preempt-contexts-bsd2:
- shard-iclb: [SKIP][31] ([fdo#109276]) -> [PASS][32] +9 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-iclb5/igt@gem_exec_schedule@preempt-contexts-bsd2.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-iclb1/igt@gem_exec_schedule@preempt-contexts-bsd2.html
* igt@gem_linear_blits@normal:
- shard-iclb: [INCOMPLETE][33] ([fdo#107713]) -> [PASS][34] +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-iclb7/igt@gem_linear_blits@normal.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-iclb2/igt@gem_linear_blits@normal.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [DMESG-WARN][35] ([fdo#108566]) -> [PASS][36] +9 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-apl6/igt@i915_suspend@sysfs-reader.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-apl8/igt@i915_suspend@sysfs-reader.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [FAIL][37] ([fdo#102670]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [FAIL][39] ([fdo#105363]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-skl: [INCOMPLETE][41] ([fdo#109507]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-skl7/igt@kms_flip@flip-vs-suspend-interruptible.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-skl5/igt@kms_flip@flip-vs-suspend-interruptible.html
- shard-kbl: [DMESG-WARN][43] ([fdo#103313]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-iclb: [FAIL][45] ([fdo#103167]) -> [PASS][46] +6 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-pwrite:
- shard-skl: [FAIL][47] ([fdo#103167]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-skl9/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-pwrite.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-skl3/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-pwrite.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][49] ([fdo#108145]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [SKIP][51] ([fdo#109642] / [fdo#111068]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-iclb8/igt@kms_psr2_su@page_flip.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-iclb2/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_sprite_mmap_cpu:
- shard-iclb: [SKIP][53] ([fdo#109441]) -> [PASS][54] +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-iclb8/igt@kms_psr@psr2_sprite_mmap_cpu.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_cpu.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][55] ([fdo#99912]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-apl1/igt@kms_setmode@basic.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-apl1/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-kbl: [INCOMPLETE][57] ([fdo#103665]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-kbl6/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-kbl1/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-skl: [INCOMPLETE][59] ([fdo#104108]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-skl3/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-skl8/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-rc6-bsd2:
- shard-iclb: [FAIL][61] ([fdo#111330]) -> [SKIP][62] ([fdo#109276])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-iclb2/igt@gem_mocs_settings@mocs-rc6-bsd2.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-iclb3/igt@gem_mocs_settings@mocs-rc6-bsd2.html
* igt@gem_mocs_settings@mocs-reset-bsd2:
- shard-iclb: [SKIP][63] ([fdo#109276]) -> [FAIL][64] ([fdo#111330])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-iclb8/igt@gem_mocs_settings@mocs-reset-bsd2.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-iclb2/igt@gem_mocs_settings@mocs-reset-bsd2.html
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#102670]: https://bugs.freedesktop.org/show_bug.cgi?id=102670
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103313]: https://bugs.freedesktop.org/show_bug.cgi?id=103313
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#110741]: https://bugs.freedesktop.org/show_bug.cgi?id=110741
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6716 -> Patchwork_14046
CI-20190529: 20190529
CI_DRM_6716: 64ecd8f88d7b55de82ff414784ae4daca93d0577 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5138: b9abe0bf6c478c4f6cac56bff286d6926ad8c0ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14046: 5390f66e917426e5dc5c169cc45c04935ab9ca00 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/
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