* [PATCH 1/9] drm/i915: Use variable for debugfs device status
2019-08-19 21:49 [PATCH 0/9] Refactor to expand subslice mask (rev 2) Stuart Summers
@ 2019-08-19 21:49 ` Stuart Summers
2019-08-19 21:49 ` [PATCH 2/9] drm/i915: Add function to set SSEU info per platform Stuart Summers
` (11 subsequent siblings)
12 siblings, 0 replies; 29+ messages in thread
From: Stuart Summers @ 2019-08-19 21:49 UTC (permalink / raw)
To: intel-gfx
Use a local variable to find SSEU runtime information
in various debugfs functions.
v2: Remove extra line breaks per feedback from Chris
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_debugfs.c | 26 +++++++++++---------------
1 file changed, 11 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index b39226d7f8d2..b52c04f44f32 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3844,8 +3844,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
if (IS_GEN9_BC(dev_priv))
- sseu->subslice_mask[s] =
- RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s];
+ sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
@@ -3872,25 +3871,22 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
{
+ const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
int s;
sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
if (sseu->slice_mask) {
- sseu->eu_per_subslice =
- RUNTIME_INFO(dev_priv)->sseu.eu_per_subslice;
- for (s = 0; s < fls(sseu->slice_mask); s++) {
- sseu->subslice_mask[s] =
- RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s];
- }
+ sseu->eu_per_subslice = info->sseu.eu_per_subslice;
+ for (s = 0; s < fls(sseu->slice_mask); s++)
+ sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
sseu->eu_total = sseu->eu_per_subslice *
intel_sseu_subslice_total(sseu);
/* subtract fused off EU(s) from enabled slice(s) */
for (s = 0; s < fls(sseu->slice_mask); s++) {
- u8 subslice_7eu =
- RUNTIME_INFO(dev_priv)->sseu.subslice_7eu[s];
+ u8 subslice_7eu = info->sseu.subslice_7eu[s];
sseu->eu_total -= hweight8(subslice_7eu);
}
@@ -3937,6 +3933,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
static int i915_sseu_status(struct seq_file *m, void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
struct sseu_dev_info sseu;
intel_wakeref_t wakeref;
@@ -3944,14 +3941,13 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
return -ENODEV;
seq_puts(m, "SSEU Device Info\n");
- i915_print_sseu_info(m, true, &RUNTIME_INFO(dev_priv)->sseu);
+ i915_print_sseu_info(m, true, &info->sseu);
seq_puts(m, "SSEU Device Status\n");
memset(&sseu, 0, sizeof(sseu));
- sseu.max_slices = RUNTIME_INFO(dev_priv)->sseu.max_slices;
- sseu.max_subslices = RUNTIME_INFO(dev_priv)->sseu.max_subslices;
- sseu.max_eus_per_subslice =
- RUNTIME_INFO(dev_priv)->sseu.max_eus_per_subslice;
+ sseu.max_slices = info->sseu.max_slices;
+ sseu.max_subslices = info->sseu.max_subslices;
+ sseu.max_eus_per_subslice = info->sseu.max_eus_per_subslice;
with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
if (IS_CHERRYVIEW(dev_priv))
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 2/9] drm/i915: Add function to set SSEU info per platform
2019-08-19 21:49 [PATCH 0/9] Refactor to expand subslice mask (rev 2) Stuart Summers
2019-08-19 21:49 ` [PATCH 1/9] drm/i915: Use variable for debugfs device status Stuart Summers
@ 2019-08-19 21:49 ` Stuart Summers
2019-08-20 7:44 ` Mika Kuoppala
2019-08-19 21:49 ` [PATCH 3/9] drm/i915: Add subslice stride runtime parameter Stuart Summers
` (10 subsequent siblings)
12 siblings, 1 reply; 29+ messages in thread
From: Stuart Summers @ 2019-08-19 21:49 UTC (permalink / raw)
To: intel-gfx
Add a new function to allow each platform to set maximum
slice, subslice, and EU information to reduce code duplication.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 8 +++++
drivers/gpu/drm/i915/gt/intel_sseu.h | 3 ++
drivers/gpu/drm/i915/i915_debugfs.c | 6 ++--
drivers/gpu/drm/i915/intel_device_info.c | 39 +++++++++---------------
4 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 6bf2d87da109..6727079eb9b6 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -8,6 +8,14 @@
#include "intel_lrc_reg.h"
#include "intel_sseu.h"
+void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
+ u8 max_subslices, u8 max_eus_per_subslice)
+{
+ sseu->max_slices = max_slices;
+ sseu->max_subslices = max_subslices;
+ sseu->max_eus_per_subslice = max_eus_per_subslice;
+}
+
unsigned int
intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index b50d0401a4e2..64e47dad07be 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -63,6 +63,9 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
return value;
}
+void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
+ u8 max_subslices, u8 max_eus_per_subslice);
+
unsigned int
intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index b52c04f44f32..abf0f6ba213c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3945,9 +3945,9 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
seq_puts(m, "SSEU Device Status\n");
memset(&sseu, 0, sizeof(sseu));
- sseu.max_slices = info->sseu.max_slices;
- sseu.max_subslices = info->sseu.max_subslices;
- sseu.max_eus_per_subslice = info->sseu.max_eus_per_subslice;
+ intel_sseu_set_info(&sseu, info->sseu.max_slices,
+ info->sseu.max_subslices,
+ info->sseu.max_eus_per_subslice);
with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
if (IS_CHERRYVIEW(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index f99c9fd497b2..9a79d9d547c5 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -191,15 +191,10 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
u8 eu_en;
int s;
- if (IS_ELKHARTLAKE(dev_priv)) {
- sseu->max_slices = 1;
- sseu->max_subslices = 4;
- sseu->max_eus_per_subslice = 8;
- } else {
- sseu->max_slices = 1;
- sseu->max_subslices = 8;
- sseu->max_eus_per_subslice = 8;
- }
+ if (IS_ELKHARTLAKE(dev_priv))
+ intel_sseu_set_info(sseu, 1, 4, 8);
+ else
+ intel_sseu_set_info(sseu, 1, 8, 8);
s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
@@ -236,11 +231,10 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
const int eu_mask = 0xff;
u32 subslice_mask, eu_en;
+ intel_sseu_set_info(sseu, 6, 4, 8);
+
sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
GEN10_F2_S_ENA_SHIFT;
- sseu->max_slices = 6;
- sseu->max_subslices = 4;
- sseu->max_eus_per_subslice = 8;
subslice_mask = (1 << 4) - 1;
subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
@@ -314,9 +308,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
fuse = I915_READ(CHV_FUSE_GT);
sseu->slice_mask = BIT(0);
- sseu->max_slices = 1;
- sseu->max_subslices = 2;
- sseu->max_eus_per_subslice = 8;
+ intel_sseu_set_info(sseu, 1, 2, 8);
if (!(fuse & CHV_FGT_DISABLE_SS0)) {
u8 disabled_mask =
@@ -372,9 +364,8 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
/* BXT has a single slice and at most 3 subslices. */
- sseu->max_slices = IS_GEN9_LP(dev_priv) ? 1 : 3;
- sseu->max_subslices = IS_GEN9_LP(dev_priv) ? 3 : 4;
- sseu->max_eus_per_subslice = 8;
+ intel_sseu_set_info(sseu, IS_GEN9_LP(dev_priv) ? 1 : 3,
+ IS_GEN9_LP(dev_priv) ? 3 : 4, 8);
/*
* The subslice disable field is global, i.e. it applies
@@ -473,9 +464,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
fuse2 = I915_READ(GEN8_FUSE2);
sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
- sseu->max_slices = 3;
- sseu->max_subslices = 3;
- sseu->max_eus_per_subslice = 8;
+ intel_sseu_set_info(sseu, 3, 3, 8);
/*
* The subslice disable field is global, i.e. it applies
@@ -577,9 +566,6 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
break;
}
- sseu->max_slices = hweight8(sseu->slice_mask);
- sseu->max_subslices = hweight8(sseu->subslice_mask[0]);
-
fuse1 = I915_READ(HSW_PAVP_FUSE1);
switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) {
default:
@@ -596,7 +582,10 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
sseu->eu_per_subslice = 6;
break;
}
- sseu->max_eus_per_subslice = sseu->eu_per_subslice;
+
+ intel_sseu_set_info(sseu, hweight8(sseu->slice_mask),
+ hweight8(sseu->subslice_mask[0]),
+ sseu->eu_per_subslice);
for (s = 0; s < sseu->max_slices; s++) {
for (ss = 0; ss < sseu->max_subslices; ss++) {
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 2/9] drm/i915: Add function to set SSEU info per platform
2019-08-19 21:49 ` [PATCH 2/9] drm/i915: Add function to set SSEU info per platform Stuart Summers
@ 2019-08-20 7:44 ` Mika Kuoppala
0 siblings, 0 replies; 29+ messages in thread
From: Mika Kuoppala @ 2019-08-20 7:44 UTC (permalink / raw)
To: Stuart Summers, intel-gfx
Stuart Summers <stuart.summers@intel.com> writes:
> Add a new function to allow each platform to set maximum
> slice, subslice, and EU information to reduce code duplication.
>
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_sseu.c | 8 +++++
> drivers/gpu/drm/i915/gt/intel_sseu.h | 3 ++
> drivers/gpu/drm/i915/i915_debugfs.c | 6 ++--
> drivers/gpu/drm/i915/intel_device_info.c | 39 +++++++++---------------
> 4 files changed, 28 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
> index 6bf2d87da109..6727079eb9b6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> @@ -8,6 +8,14 @@
> #include "intel_lrc_reg.h"
> #include "intel_sseu.h"
>
> +void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
> + u8 max_subslices, u8 max_eus_per_subslice)
> +{
> + sseu->max_slices = max_slices;
> + sseu->max_subslices = max_subslices;
> + sseu->max_eus_per_subslice = max_eus_per_subslice;
> +}
> +
> unsigned int
> intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
> {
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
> index b50d0401a4e2..64e47dad07be 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> @@ -63,6 +63,9 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
> return value;
> }
>
> +void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
> + u8 max_subslices, u8 max_eus_per_subslice);
> +
> unsigned int
> intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index b52c04f44f32..abf0f6ba213c 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -3945,9 +3945,9 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
>
> seq_puts(m, "SSEU Device Status\n");
> memset(&sseu, 0, sizeof(sseu));
> - sseu.max_slices = info->sseu.max_slices;
> - sseu.max_subslices = info->sseu.max_subslices;
> - sseu.max_eus_per_subslice = info->sseu.max_eus_per_subslice;
> + intel_sseu_set_info(&sseu, info->sseu.max_slices,
> + info->sseu.max_subslices,
> + info->sseu.max_eus_per_subslice);
>
> with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
> if (IS_CHERRYVIEW(dev_priv))
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index f99c9fd497b2..9a79d9d547c5 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -191,15 +191,10 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
> u8 eu_en;
> int s;
>
> - if (IS_ELKHARTLAKE(dev_priv)) {
> - sseu->max_slices = 1;
> - sseu->max_subslices = 4;
> - sseu->max_eus_per_subslice = 8;
> - } else {
> - sseu->max_slices = 1;
> - sseu->max_subslices = 8;
> - sseu->max_eus_per_subslice = 8;
> - }
> + if (IS_ELKHARTLAKE(dev_priv))
> + intel_sseu_set_info(sseu, 1, 4, 8);
> + else
> + intel_sseu_set_info(sseu, 1, 8, 8);
>
> s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
> ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
> @@ -236,11 +231,10 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
> const int eu_mask = 0xff;
> u32 subslice_mask, eu_en;
>
> + intel_sseu_set_info(sseu, 6, 4, 8);
> +
> sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
> GEN10_F2_S_ENA_SHIFT;
> - sseu->max_slices = 6;
> - sseu->max_subslices = 4;
> - sseu->max_eus_per_subslice = 8;
>
> subslice_mask = (1 << 4) - 1;
> subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
> @@ -314,9 +308,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
> fuse = I915_READ(CHV_FUSE_GT);
>
> sseu->slice_mask = BIT(0);
> - sseu->max_slices = 1;
> - sseu->max_subslices = 2;
> - sseu->max_eus_per_subslice = 8;
> + intel_sseu_set_info(sseu, 1, 2, 8);
>
> if (!(fuse & CHV_FGT_DISABLE_SS0)) {
> u8 disabled_mask =
> @@ -372,9 +364,8 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
> sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
>
> /* BXT has a single slice and at most 3 subslices. */
> - sseu->max_slices = IS_GEN9_LP(dev_priv) ? 1 : 3;
> - sseu->max_subslices = IS_GEN9_LP(dev_priv) ? 3 : 4;
> - sseu->max_eus_per_subslice = 8;
> + intel_sseu_set_info(sseu, IS_GEN9_LP(dev_priv) ? 1 : 3,
> + IS_GEN9_LP(dev_priv) ? 3 : 4, 8);
>
> /*
> * The subslice disable field is global, i.e. it applies
> @@ -473,9 +464,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
>
> fuse2 = I915_READ(GEN8_FUSE2);
> sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
> - sseu->max_slices = 3;
> - sseu->max_subslices = 3;
> - sseu->max_eus_per_subslice = 8;
> + intel_sseu_set_info(sseu, 3, 3, 8);
>
> /*
> * The subslice disable field is global, i.e. it applies
> @@ -577,9 +566,6 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
> break;
> }
>
> - sseu->max_slices = hweight8(sseu->slice_mask);
> - sseu->max_subslices = hweight8(sseu->subslice_mask[0]);
> -
> fuse1 = I915_READ(HSW_PAVP_FUSE1);
> switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) {
> default:
> @@ -596,7 +582,10 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
> sseu->eu_per_subslice = 6;
> break;
> }
> - sseu->max_eus_per_subslice = sseu->eu_per_subslice;
> +
> + intel_sseu_set_info(sseu, hweight8(sseu->slice_mask),
> + hweight8(sseu->subslice_mask[0]),
> + sseu->eu_per_subslice);
>
> for (s = 0; s < sseu->max_slices; s++) {
> for (ss = 0; ss < sseu->max_subslices; ss++) {
> --
> 2.22.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 3/9] drm/i915: Add subslice stride runtime parameter
2019-08-19 21:49 [PATCH 0/9] Refactor to expand subslice mask (rev 2) Stuart Summers
2019-08-19 21:49 ` [PATCH 1/9] drm/i915: Use variable for debugfs device status Stuart Summers
2019-08-19 21:49 ` [PATCH 2/9] drm/i915: Add function to set SSEU info per platform Stuart Summers
@ 2019-08-19 21:49 ` Stuart Summers
2019-08-20 10:46 ` Chris Wilson
2019-08-19 21:49 ` [PATCH 4/9] drm/i915: Add EU " Stuart Summers
` (9 subsequent siblings)
12 siblings, 1 reply; 29+ messages in thread
From: Stuart Summers @ 2019-08-19 21:49 UTC (permalink / raw)
To: intel-gfx
Add a new parameter, ss_stride, to the runtime info
structure. This is used to mirror the userspace concept
of subslice stride, which is a range of subslices per slice.
This patch simply adds the definition and updates usage
in the QUERY_TOPOLOGY_INFO handler.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 2 ++
drivers/gpu/drm/i915/gt/intel_sseu.h | 2 ++
drivers/gpu/drm/i915/i915_query.c | 5 ++---
3 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 6727079eb9b6..5b8246138020 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -14,6 +14,8 @@ void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
sseu->max_slices = max_slices;
sseu->max_subslices = max_subslices;
sseu->max_eus_per_subslice = max_eus_per_subslice;
+
+ sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
}
unsigned int
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 64e47dad07be..b0101e1c69bd 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -33,6 +33,8 @@ struct sseu_dev_info {
u8 max_subslices;
u8 max_eus_per_subslice;
+ u8 ss_stride;
+
/* We don't have more than 8 eus per subslice at the moment and as we
* store eus enabled using bits, no need to multiply by eus per
* subslice.
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index ad9240a0817a..d8e25dcf5f0b 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -37,7 +37,6 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
- u8 subslice_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
u8 eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
int ret;
@@ -50,7 +49,7 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
slice_length = sizeof(sseu->slice_mask);
- subslice_length = sseu->max_slices * subslice_stride;
+ subslice_length = sseu->max_slices * sseu->ss_stride;
eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
total_length = sizeof(topo) + slice_length + subslice_length +
eu_length;
@@ -69,7 +68,7 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
topo.max_eus_per_subslice = sseu->max_eus_per_subslice;
topo.subslice_offset = slice_length;
- topo.subslice_stride = subslice_stride;
+ topo.subslice_stride = sseu->ss_stride;
topo.eu_offset = slice_length + subslice_length;
topo.eu_stride = eu_stride;
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 4/9] drm/i915: Add EU stride runtime parameter
2019-08-19 21:49 [PATCH 0/9] Refactor to expand subslice mask (rev 2) Stuart Summers
` (2 preceding siblings ...)
2019-08-19 21:49 ` [PATCH 3/9] drm/i915: Add subslice stride runtime parameter Stuart Summers
@ 2019-08-19 21:49 ` Stuart Summers
2019-08-20 10:47 ` Chris Wilson
2019-08-19 21:49 ` [PATCH 5/9] drm/i915: Add function to set subslices Stuart Summers
` (8 subsequent siblings)
12 siblings, 1 reply; 29+ messages in thread
From: Stuart Summers @ 2019-08-19 21:49 UTC (permalink / raw)
To: intel-gfx
Add a new SSEU runtime parameter, eu_stride, which is
used to mirror the userspace concept of a range of EUs
per subslice.
This patch simply adds the parameter and updates usage
in the QUERY_TOPOLOGY_INFO handler.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 1 +
drivers/gpu/drm/i915/gt/intel_sseu.h | 1 +
drivers/gpu/drm/i915/i915_query.c | 5 ++---
drivers/gpu/drm/i915/intel_device_info.c | 9 ++++-----
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 5b8246138020..3a5c0f7b5a08 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -16,6 +16,7 @@ void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
sseu->max_eus_per_subslice = max_eus_per_subslice;
sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
+ sseu->eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
}
unsigned int
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index b0101e1c69bd..fe22d5b18e67 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -34,6 +34,7 @@ struct sseu_dev_info {
u8 max_eus_per_subslice;
u8 ss_stride;
+ u8 eu_stride;
/* We don't have more than 8 eus per subslice at the moment and as we
* store eus enabled using bits, no need to multiply by eus per
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index d8e25dcf5f0b..abac5042da2b 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -37,7 +37,6 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
- u8 eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
int ret;
if (query_item->flags != 0)
@@ -50,7 +49,7 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
slice_length = sizeof(sseu->slice_mask);
subslice_length = sseu->max_slices * sseu->ss_stride;
- eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
+ eu_length = sseu->max_slices * sseu->max_subslices * sseu->eu_stride;
total_length = sizeof(topo) + slice_length + subslice_length +
eu_length;
@@ -70,7 +69,7 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
topo.subslice_offset = slice_length;
topo.subslice_stride = sseu->ss_stride;
topo.eu_offset = slice_length + subslice_length;
- topo.eu_stride = eu_stride;
+ topo.eu_stride = sseu->eu_stride;
if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr),
&topo, sizeof(topo)))
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 9a79d9d547c5..7de7b7b540cb 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -118,10 +118,9 @@ void intel_device_info_dump_runtime(const struct intel_runtime_info *info,
static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice,
int subslice)
{
- int subslice_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
- int slice_stride = sseu->max_subslices * subslice_stride;
+ int slice_stride = sseu->max_subslices * sseu->eu_stride;
- return slice * slice_stride + subslice * subslice_stride;
+ return slice * slice_stride + subslice * sseu->eu_stride;
}
static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
@@ -130,7 +129,7 @@ static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
int i, offset = sseu_eu_idx(sseu, slice, subslice);
u16 eu_mask = 0;
- for (i = 0; i < GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); i++) {
+ for (i = 0; i < sseu->eu_stride; i++) {
eu_mask |= ((u16)sseu->eu_mask[offset + i]) <<
(i * BITS_PER_BYTE);
}
@@ -143,7 +142,7 @@ static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice,
{
int i, offset = sseu_eu_idx(sseu, slice, subslice);
- for (i = 0; i < GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); i++) {
+ for (i = 0; i < sseu->eu_stride; i++) {
sseu->eu_mask[offset + i] =
(eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
}
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 5/9] drm/i915: Add function to set subslices
2019-08-19 21:49 [PATCH 0/9] Refactor to expand subslice mask (rev 2) Stuart Summers
` (3 preceding siblings ...)
2019-08-19 21:49 ` [PATCH 4/9] drm/i915: Add EU " Stuart Summers
@ 2019-08-19 21:49 ` Stuart Summers
2019-08-20 10:51 ` Chris Wilson
2019-08-19 21:50 ` [PATCH 6/9] drm/i915: Add function to determine if a slice has a subslice Stuart Summers
` (7 subsequent siblings)
12 siblings, 1 reply; 29+ messages in thread
From: Stuart Summers @ 2019-08-19 21:49 UTC (permalink / raw)
To: intel-gfx
Add a new function to set a range of subslices for a
specified slice based on a given mask.
v2: Use local variable for subslice_mask on HSW and
clean up a few other subslice_mask local variable
changes
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 10 ++++
drivers/gpu/drm/i915/gt/intel_sseu.h | 3 ++
drivers/gpu/drm/i915/intel_device_info.c | 59 +++++++++++++-----------
3 files changed, 46 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 3a5c0f7b5a08..f5ee43a034bd 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -30,6 +30,16 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
return total;
}
+void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
+ u32 ss_mask)
+{
+ int i, offset = slice * sseu->ss_stride;
+
+ for (i = 0; i < sseu->ss_stride; i++)
+ sseu->subslice_mask[offset + i] =
+ (ss_mask >> (BITS_PER_BYTE * i)) & 0xff;
+}
+
unsigned int
intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index fe22d5b18e67..2261d4e7d98b 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -75,6 +75,9 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
unsigned int
intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
+void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
+ u32 ss_mask);
+
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
const struct intel_sseu *req_sseu);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 7de7b7b540cb..2320613a51ac 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -206,7 +206,10 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
int ss;
sseu->slice_mask |= BIT(s);
- sseu->subslice_mask[s] = (ss_en >> ss_idx) & ss_en_mask;
+
+ intel_sseu_set_subslices(sseu, s, (ss_en >> ss_idx) &
+ ss_en_mask);
+
for (ss = 0; ss < sseu->max_subslices; ss++) {
if (sseu->subslice_mask[s] & BIT(ss))
sseu_set_eus(sseu, s, ss, eu_en);
@@ -235,18 +238,6 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
GEN10_F2_S_ENA_SHIFT;
- subslice_mask = (1 << 4) - 1;
- subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
- GEN10_F2_SS_DIS_SHIFT);
-
- /*
- * Slice0 can have up to 3 subslices, but there are only 2 in
- * slice1/2.
- */
- sseu->subslice_mask[0] = subslice_mask;
- for (s = 1; s < sseu->max_slices; s++)
- sseu->subslice_mask[s] = subslice_mask & 0x3;
-
/* Slice0 */
eu_en = ~I915_READ(GEN8_EU_DISABLE0);
for (ss = 0; ss < sseu->max_subslices; ss++)
@@ -270,14 +261,25 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
eu_en = ~I915_READ(GEN10_EU_DISABLE3);
sseu_set_eus(sseu, 5, 1, eu_en & eu_mask);
- /* Do a second pass where we mark the subslices disabled if all their
- * eus are off.
- */
+ subslice_mask = (1 << 4) - 1;
+ subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
+ GEN10_F2_SS_DIS_SHIFT);
+
for (s = 0; s < sseu->max_slices; s++) {
+ u32 subslice_mask_with_eus = subslice_mask;
+
for (ss = 0; ss < sseu->max_subslices; ss++) {
if (sseu_get_eus(sseu, s, ss) == 0)
- sseu->subslice_mask[s] &= ~BIT(ss);
+ subslice_mask_with_eus &= ~BIT(ss);
}
+
+ /*
+ * Slice0 can have up to 3 subslices, but there are only 2 in
+ * slice1/2.
+ */
+ intel_sseu_set_subslices(sseu, s, s == 0 ?
+ subslice_mask_with_eus :
+ subslice_mask_with_eus & 0x3);
}
sseu->eu_total = compute_eu_total(sseu);
@@ -303,6 +305,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
{
struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
u32 fuse;
+ u8 subslice_mask = 0;
fuse = I915_READ(CHV_FUSE_GT);
@@ -316,7 +319,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
(((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
- sseu->subslice_mask[0] |= BIT(0);
+ subslice_mask |= BIT(0);
sseu_set_eus(sseu, 0, 0, ~disabled_mask);
}
@@ -327,10 +330,12 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
(((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
- sseu->subslice_mask[0] |= BIT(1);
+ subslice_mask |= BIT(1);
sseu_set_eus(sseu, 0, 1, ~disabled_mask);
}
+ intel_sseu_set_subslices(sseu, 0, subslice_mask);
+
sseu->eu_total = compute_eu_total(sseu);
/*
@@ -383,7 +388,7 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
/* skip disabled slice */
continue;
- sseu->subslice_mask[s] = subslice_mask;
+ intel_sseu_set_subslices(sseu, s, subslice_mask);
eu_disable = I915_READ(GEN9_EU_DISABLE(s));
for (ss = 0; ss < sseu->max_subslices; ss++) {
@@ -490,7 +495,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
/* skip disabled slice */
continue;
- sseu->subslice_mask[s] = subslice_mask;
+ intel_sseu_set_subslices(sseu, s, subslice_mask);
for (ss = 0; ss < sseu->max_subslices; ss++) {
u8 eu_disabled_mask;
@@ -540,6 +545,7 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
{
struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
u32 fuse1;
+ u8 subslice_mask = 0;
int s, ss;
/*
@@ -552,16 +558,15 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
/* fall through */
case 1:
sseu->slice_mask = BIT(0);
- sseu->subslice_mask[0] = BIT(0);
+ subslice_mask = BIT(0);
break;
case 2:
sseu->slice_mask = BIT(0);
- sseu->subslice_mask[0] = BIT(0) | BIT(1);
+ subslice_mask = BIT(0) | BIT(1);
break;
case 3:
sseu->slice_mask = BIT(0) | BIT(1);
- sseu->subslice_mask[0] = BIT(0) | BIT(1);
- sseu->subslice_mask[1] = BIT(0) | BIT(1);
+ subslice_mask = BIT(0) | BIT(1);
break;
}
@@ -583,10 +588,12 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
}
intel_sseu_set_info(sseu, hweight8(sseu->slice_mask),
- hweight8(sseu->subslice_mask[0]),
+ hweight8(subslice_mask),
sseu->eu_per_subslice);
for (s = 0; s < sseu->max_slices; s++) {
+ intel_sseu_set_subslices(sseu, s, subslice_mask);
+
for (ss = 0; ss < sseu->max_subslices; ss++) {
sseu_set_eus(sseu, s, ss,
(1UL << sseu->eu_per_subslice) - 1);
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 5/9] drm/i915: Add function to set subslices
2019-08-19 21:49 ` [PATCH 5/9] drm/i915: Add function to set subslices Stuart Summers
@ 2019-08-20 10:51 ` Chris Wilson
0 siblings, 0 replies; 29+ messages in thread
From: Chris Wilson @ 2019-08-20 10:51 UTC (permalink / raw)
To: Stuart Summers, intel-gfx
Quoting Stuart Summers (2019-08-19 22:49:59)
> Add a new function to set a range of subslices for a
> specified slice based on a given mask.
>
> v2: Use local variable for subslice_mask on HSW and
> clean up a few other subslice_mask local variable
> changes
>
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_sseu.c | 10 ++++
> drivers/gpu/drm/i915/gt/intel_sseu.h | 3 ++
> drivers/gpu/drm/i915/intel_device_info.c | 59 +++++++++++++-----------
> 3 files changed, 46 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
> index 3a5c0f7b5a08..f5ee43a034bd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> @@ -30,6 +30,16 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
> return total;
> }
>
> +void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
> + u32 ss_mask)
> +{
> + int i, offset = slice * sseu->ss_stride;
> +
Some sort of
GEM_BUG_ON(sseu->ss_stride > 32);
to detect UB ?
> + for (i = 0; i < sseu->ss_stride; i++)
> + sseu->subslice_mask[offset + i] =
> + (ss_mask >> (BITS_PER_BYTE * i)) & 0xff;
This is a non-trivial transformation :|
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 6/9] drm/i915: Add function to determine if a slice has a subslice
2019-08-19 21:49 [PATCH 0/9] Refactor to expand subslice mask (rev 2) Stuart Summers
` (4 preceding siblings ...)
2019-08-19 21:49 ` [PATCH 5/9] drm/i915: Add function to set subslices Stuart Summers
@ 2019-08-19 21:50 ` Stuart Summers
2019-08-20 10:53 ` Chris Wilson
2019-08-19 21:50 ` [PATCH 7/9] drm/i915: Refactor instdone loops on new subslice functions Stuart Summers
` (6 subsequent siblings)
12 siblings, 1 reply; 29+ messages in thread
From: Stuart Summers @ 2019-08-19 21:50 UTC (permalink / raw)
To: intel-gfx
Add a new function to determine whether a particular slice
has a given subslice.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 10 ++++++++++
drivers/gpu/drm/i915/intel_device_info.c | 9 ++++-----
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 2261d4e7d98b..0ecc1c35a7a1 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -66,6 +66,16 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
return value;
}
+static inline bool
+intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice,
+ int subslice)
+{
+ u8 mask = sseu->subslice_mask[slice * sseu->ss_stride +
+ subslice / BITS_PER_BYTE];
+
+ return mask & BIT(subslice % BITS_PER_BYTE);
+}
+
void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
u8 max_subslices, u8 max_eus_per_subslice);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 2320613a51ac..ff3d6508fd17 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -210,10 +210,9 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
intel_sseu_set_subslices(sseu, s, (ss_en >> ss_idx) &
ss_en_mask);
- for (ss = 0; ss < sseu->max_subslices; ss++) {
- if (sseu->subslice_mask[s] & BIT(ss))
+ for (ss = 0; ss < sseu->max_subslices; ss++)
+ if (intel_sseu_has_subslice(sseu, s, ss))
sseu_set_eus(sseu, s, ss, eu_en);
- }
}
}
sseu->eu_per_subslice = hweight8(eu_en);
@@ -395,7 +394,7 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
int eu_per_ss;
u8 eu_disabled_mask;
- if (!(sseu->subslice_mask[s] & BIT(ss)))
+ if (!intel_sseu_has_subslice(sseu, s, ss))
/* skip disabled subslice */
continue;
@@ -501,7 +500,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
u8 eu_disabled_mask;
u32 n_disabled;
- if (!(sseu->subslice_mask[s] & BIT(ss)))
+ if (!intel_sseu_has_subslice(sseu, s, ss))
/* skip disabled subslice */
continue;
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 6/9] drm/i915: Add function to determine if a slice has a subslice
2019-08-19 21:50 ` [PATCH 6/9] drm/i915: Add function to determine if a slice has a subslice Stuart Summers
@ 2019-08-20 10:53 ` Chris Wilson
2019-08-20 19:01 ` Summers, Stuart
0 siblings, 1 reply; 29+ messages in thread
From: Chris Wilson @ 2019-08-20 10:53 UTC (permalink / raw)
To: Stuart Summers, intel-gfx
Quoting Stuart Summers (2019-08-19 22:50:00)
> Add a new function to determine whether a particular slice
> has a given subslice.
>
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_sseu.h | 10 ++++++++++
> drivers/gpu/drm/i915/intel_device_info.c | 9 ++++-----
> 2 files changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
> index 2261d4e7d98b..0ecc1c35a7a1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> @@ -66,6 +66,16 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
> return value;
> }
>
> +static inline bool
> +intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice,
> + int subslice)
> +{
> + u8 mask = sseu->subslice_mask[slice * sseu->ss_stride +
> + subslice / BITS_PER_BYTE];
> +
Suggestion:
GEM_BUG_ON(subslice >= sseu->ss_slice);
> + return mask & BIT(subslice % BITS_PER_BYTE);
> +}
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 6/9] drm/i915: Add function to determine if a slice has a subslice
2019-08-20 10:53 ` Chris Wilson
@ 2019-08-20 19:01 ` Summers, Stuart
2019-08-20 19:20 ` Chris Wilson
0 siblings, 1 reply; 29+ messages in thread
From: Summers, Stuart @ 2019-08-20 19:01 UTC (permalink / raw)
To: intel-gfx, chris
[-- Attachment #1.1: Type: text/plain, Size: 1581 bytes --]
On Tue, 2019-08-20 at 11:53 +0100, Chris Wilson wrote:
> Quoting Stuart Summers (2019-08-19 22:50:00)
> > Add a new function to determine whether a particular slice
> > has a given subslice.
> >
> > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_sseu.h | 10 ++++++++++
> > drivers/gpu/drm/i915/intel_device_info.c | 9 ++++-----
> > 2 files changed, 14 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
> > b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > index 2261d4e7d98b..0ecc1c35a7a1 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > @@ -66,6 +66,16 @@ intel_sseu_from_device_info(const struct
> > sseu_dev_info *sseu)
> > return value;
> > }
> >
> > +static inline bool
> > +intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int
> > slice,
> > + int subslice)
> > +{
> > + u8 mask = sseu->subslice_mask[slice * sseu->ss_stride +
> > + subslice / BITS_PER_BYTE];
> > +
>
> Suggestion:
>
> GEM_BUG_ON(subslice >= sseu->ss_slice);
Thanks Chris and makes sense. I think this should instead be (ss /
BITS_PER_BYTE >= ss_stride).
I'll post an update hopefully today on this. Let me know if you'd like
me to drop your R-B with the above change.
Thanks,
Stuart
>
> > + return mask & BIT(subslice % BITS_PER_BYTE);
> > +}
>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> -Chris
[-- Attachment #1.2: smime.p7s --]
[-- Type: application/x-pkcs7-signature, Size: 3270 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 6/9] drm/i915: Add function to determine if a slice has a subslice
2019-08-20 19:01 ` Summers, Stuart
@ 2019-08-20 19:20 ` Chris Wilson
0 siblings, 0 replies; 29+ messages in thread
From: Chris Wilson @ 2019-08-20 19:20 UTC (permalink / raw)
To: Summers, Stuart, intel-gfx
Quoting Summers, Stuart (2019-08-20 20:01:05)
> On Tue, 2019-08-20 at 11:53 +0100, Chris Wilson wrote:
> > Quoting Stuart Summers (2019-08-19 22:50:00)
> > > Add a new function to determine whether a particular slice
> > > has a given subslice.
> > >
> > > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/gt/intel_sseu.h | 10 ++++++++++
> > > drivers/gpu/drm/i915/intel_device_info.c | 9 ++++-----
> > > 2 files changed, 14 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
> > > b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > > index 2261d4e7d98b..0ecc1c35a7a1 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> > > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > > @@ -66,6 +66,16 @@ intel_sseu_from_device_info(const struct
> > > sseu_dev_info *sseu)
> > > return value;
> > > }
> > >
> > > +static inline bool
> > > +intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int
> > > slice,
> > > + int subslice)
> > > +{
> > > + u8 mask = sseu->subslice_mask[slice * sseu->ss_stride +
> > > + subslice / BITS_PER_BYTE];
> > > +
> >
> > Suggestion:
> >
> > GEM_BUG_ON(subslice >= sseu->ss_slice);
>
> Thanks Chris and makes sense. I think this should instead be (ss /
> BITS_PER_BYTE >= ss_stride).
Don't assume I put more thought into than dropping a hint to catch
programmer errors that would lead to UB. :)
> I'll post an update hopefully today on this. Let me know if you'd like
> me to drop your R-B with the above change.
If CI doesn't explode, keep the r-b ;)
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 7/9] drm/i915: Refactor instdone loops on new subslice functions
2019-08-19 21:49 [PATCH 0/9] Refactor to expand subslice mask (rev 2) Stuart Summers
` (5 preceding siblings ...)
2019-08-19 21:50 ` [PATCH 6/9] drm/i915: Add function to determine if a slice has a subslice Stuart Summers
@ 2019-08-19 21:50 ` Stuart Summers
2019-08-19 21:50 ` [PATCH 8/9] drm/i915: Add new function to copy subslices for a slice Stuart Summers
` (5 subsequent siblings)
12 siblings, 0 replies; 29+ messages in thread
From: Stuart Summers @ 2019-08-19 21:50 UTC (permalink / raw)
To: intel-gfx
Refactor instdone loops to use the new intel_sseu_has_subslice
function.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 31 ++++++++++----------
drivers/gpu/drm/i915/gt/intel_hangcheck.c | 3 +-
drivers/gpu/drm/i915/i915_debugfs.c | 5 ++--
drivers/gpu/drm/i915/i915_gpu_error.c | 5 ++--
5 files changed, 25 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index ba457c1c7dc0..a91ddda656e2 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -947,6 +947,7 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine,
struct intel_instdone *instdone)
{
struct drm_i915_private *i915 = engine->i915;
+ const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
struct intel_uncore *uncore = engine->uncore;
u32 mmio_base = engine->mmio_base;
int slice;
@@ -964,7 +965,7 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine,
instdone->slice_common =
intel_uncore_read(uncore, GEN7_SC_INSTDONE);
- for_each_instdone_slice_subslice(i915, slice, subslice) {
+ for_each_instdone_slice_subslice(i915, sseu, slice, subslice) {
instdone->sampler[slice][subslice] =
read_subslice_reg(engine, slice, subslice,
GEN7_SAMPLER_INSTDONE);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index a82cea95c2f2..99bee06cdbdb 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -576,20 +576,19 @@ intel_engine_is_virtual(const struct intel_engine_cs *engine)
return engine->flags & I915_ENGINE_IS_VIRTUAL;
}
-#define instdone_slice_mask(dev_priv__) \
- (IS_GEN(dev_priv__, 7) ? \
- 1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)
-
-#define instdone_subslice_mask(dev_priv__) \
- (IS_GEN(dev_priv__, 7) ? \
- 1 : RUNTIME_INFO(dev_priv__)->sseu.subslice_mask[0])
-
-#define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
- for ((slice__) = 0, (subslice__) = 0; \
- (slice__) < I915_MAX_SLICES; \
- (subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ? (subslice__) + 1 : 0, \
- (slice__) += ((subslice__) == 0)) \
- for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) && \
- (BIT(subslice__) & instdone_subslice_mask(dev_priv__)))
-
+#define instdone_has_slice(dev_priv___, sseu___, slice___) \
+ ((IS_GEN(dev_priv___, 7) ? 1 : ((sseu___)->slice_mask)) & \
+ BIT(slice___))
+
+#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
+ (IS_GEN(dev_priv__, 7) ? (1 & BIT(subslice__)) : \
+ intel_sseu_has_subslice(sseu__, 0, subslice__))
+
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+ for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+ (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \
+ (slice_) += ((subslice_) == 0)) \
+ for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \
+ (instdone_has_subslice(dev_priv_, sseu_, slice_, \
+ subslice_)))
#endif /* __INTEL_ENGINE_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_hangcheck.c b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
index 05d042cdefe2..40f62f780be5 100644
--- a/drivers/gpu/drm/i915/gt/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
@@ -53,6 +53,7 @@ static bool instdone_unchanged(u32 current_instdone, u32 *old_instdone)
static bool subunits_stuck(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
+ const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
struct intel_instdone instdone;
struct intel_instdone *accu_instdone = &engine->hangcheck.instdone;
bool stuck;
@@ -71,7 +72,7 @@ static bool subunits_stuck(struct intel_engine_cs *engine)
stuck &= instdone_unchanged(instdone.slice_common,
&accu_instdone->slice_common);
- for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
+ for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice) {
stuck &= instdone_unchanged(instdone.sampler[slice][subslice],
&accu_instdone->sampler[slice][subslice]);
stuck &= instdone_unchanged(instdone.row[slice][subslice],
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index abf0f6ba213c..8c5eca72ff5e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -995,6 +995,7 @@ static void i915_instdone_info(struct drm_i915_private *dev_priv,
struct seq_file *m,
struct intel_instdone *instdone)
{
+ const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
int slice;
int subslice;
@@ -1010,11 +1011,11 @@ static void i915_instdone_info(struct drm_i915_private *dev_priv,
if (INTEL_GEN(dev_priv) <= 6)
return;
- for_each_instdone_slice_subslice(dev_priv, slice, subslice)
+ for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice)
seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
slice, subslice, instdone->sampler[slice][subslice]);
- for_each_instdone_slice_subslice(dev_priv, slice, subslice)
+ for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice)
seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
slice, subslice, instdone->row[slice][subslice]);
}
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index e284bd76fa86..4aff342b8944 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -421,6 +421,7 @@ static void err_compression_marker(struct drm_i915_error_state_buf *m)
static void error_print_instdone(struct drm_i915_error_state_buf *m,
const struct drm_i915_error_engine *ee)
{
+ const struct sseu_dev_info *sseu = &RUNTIME_INFO(m->i915)->sseu;
int slice;
int subslice;
@@ -436,12 +437,12 @@ static void error_print_instdone(struct drm_i915_error_state_buf *m,
if (INTEL_GEN(m->i915) <= 6)
return;
- for_each_instdone_slice_subslice(m->i915, slice, subslice)
+ for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
slice, subslice,
ee->instdone.sampler[slice][subslice]);
- for_each_instdone_slice_subslice(m->i915, slice, subslice)
+ for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n",
slice, subslice,
ee->instdone.row[slice][subslice]);
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 8/9] drm/i915: Add new function to copy subslices for a slice
2019-08-19 21:49 [PATCH 0/9] Refactor to expand subslice mask (rev 2) Stuart Summers
` (6 preceding siblings ...)
2019-08-19 21:50 ` [PATCH 7/9] drm/i915: Refactor instdone loops on new subslice functions Stuart Summers
@ 2019-08-19 21:50 ` Stuart Summers
2019-08-19 21:50 ` [PATCH 9/9] drm/i915: Expand subslice mask Stuart Summers
` (4 subsequent siblings)
12 siblings, 0 replies; 29+ messages in thread
From: Stuart Summers @ 2019-08-19 21:50 UTC (permalink / raw)
To: intel-gfx
Add a new function to copy subslices for a specified slice
between intel_sseu structures for the purpose of determining
power-gate status.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 17 ++++++++++++++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 8c5eca72ff5e..e975cad03e39 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3721,6 +3721,15 @@ i915_cache_sharing_set(void *data, u64 val)
return 0;
}
+static void
+intel_sseu_copy_subslices(const struct sseu_dev_info *sseu, int slice,
+ u8 *to_mask)
+{
+ int offset = slice * sseu->ss_stride;
+
+ memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride);
+}
+
DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
i915_cache_sharing_get, i915_cache_sharing_set,
"%llu\n");
@@ -3794,7 +3803,7 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
continue;
sseu->slice_mask |= BIT(s);
- sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
+ intel_sseu_copy_subslices(&info->sseu, s, sseu->subslice_mask);
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
@@ -3845,7 +3854,8 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
if (IS_GEN9_BC(dev_priv))
- sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
+ intel_sseu_copy_subslices(&info->sseu, s,
+ sseu->subslice_mask);
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
@@ -3881,7 +3891,8 @@ static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
if (sseu->slice_mask) {
sseu->eu_per_subslice = info->sseu.eu_per_subslice;
for (s = 0; s < fls(sseu->slice_mask); s++)
- sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
+ intel_sseu_copy_subslices(&info->sseu, s,
+ sseu->subslice_mask);
sseu->eu_total = sseu->eu_per_subslice *
intel_sseu_subslice_total(sseu);
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 9/9] drm/i915: Expand subslice mask
2019-08-19 21:49 [PATCH 0/9] Refactor to expand subslice mask (rev 2) Stuart Summers
` (7 preceding siblings ...)
2019-08-19 21:50 ` [PATCH 8/9] drm/i915: Add new function to copy subslices for a slice Stuart Summers
@ 2019-08-19 21:50 ` Stuart Summers
2019-08-19 21:55 ` ✗ Fi.CI.CHECKPATCH: warning for Refactor to expand subslice mask (rev 2) Patchwork
` (3 subsequent siblings)
12 siblings, 0 replies; 29+ messages in thread
From: Stuart Summers @ 2019-08-19 21:50 UTC (permalink / raw)
To: intel-gfx
Currently, the subslice_mask runtime parameter is stored as an
array of subslices per slice. Expand the subslice mask array to
better match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
slice * subslice stride + subslice index / 8
v2: Fix 32-bit build
v3: Use new helper function in SSEU workaround warning message
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 27 ++++++++++++++++++++-
drivers/gpu/drm/i915/gt/intel_sseu.h | 5 +++-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 ++--
drivers/gpu/drm/i915/i915_debugfs.c | 5 +++-
drivers/gpu/drm/i915/intel_device_info.c | 8 +++---
5 files changed, 40 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index f5ee43a034bd..b956d5f08e2d 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -30,6 +30,31 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
return total;
}
+u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
+{
+ int i, offset = slice * sseu->ss_stride;
+ u32 mask = 0;
+
+ if (slice >= sseu->max_slices) {
+ DRM_ERROR("%s: invalid slice %d, max: %d\n",
+ __func__, slice, sseu->max_slices);
+ return 0;
+ }
+
+ if (sseu->ss_stride > sizeof(mask)) {
+ DRM_ERROR("%s: invalid subslice stride %d, max: %u\n",
+ __func__, sseu->ss_stride,
+ (unsigned int)sizeof(mask));
+ return 0;
+ }
+
+ for (i = 0; i < sseu->ss_stride; i++)
+ mask |= (u32)sseu->subslice_mask[offset + i] <<
+ i * BITS_PER_BYTE;
+
+ return mask;
+}
+
void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
u32 ss_mask)
{
@@ -43,7 +68,7 @@ void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
unsigned int
intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
{
- return hweight8(sseu->subslice_mask[slice]);
+ return hweight32(intel_sseu_get_subslices(sseu, slice));
}
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 0ecc1c35a7a1..2291764b7db5 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -15,10 +15,11 @@ struct drm_i915_private;
#define GEN_MAX_SLICES (6) /* CNL upper bound */
#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
+#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
struct sseu_dev_info {
u8 slice_mask;
- u8 subslice_mask[GEN_MAX_SLICES];
+ u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
u16 eu_total;
u8 eu_per_subslice;
u8 min_eu_in_pool;
@@ -85,6 +86,8 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
unsigned int
intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
+u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice);
+
void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
u32 ss_mask);
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 704ace01e7f5..5bfae7f71b83 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -794,11 +794,10 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
}
slice = fls(sseu->slice_mask) - 1;
- GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
- subslice = fls(l3_en & sseu->subslice_mask[slice]);
+ subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice));
if (!subslice) {
DRM_WARN("No common index found between subslice mask %x and L3 bank mask %x!\n",
- sseu->subslice_mask[slice], l3_en);
+ intel_sseu_get_subslices(sseu, slice), l3_en);
subslice = fls(l3_en);
WARN_ON(!subslice);
}
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index e975cad03e39..112c8a305971 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3859,13 +3859,16 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
+ u8 ss_idx = s * info->sseu.ss_stride +
+ ss / BITS_PER_BYTE;
if (IS_GEN9_LP(dev_priv)) {
if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
/* skip disabled subslice */
continue;
- sseu->subslice_mask[s] |= BIT(ss);
+ sseu->subslice_mask[ss_idx] |=
+ BIT(ss % BITS_PER_BYTE);
}
eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index ff3d6508fd17..8eef34e72c0b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -93,9 +93,9 @@ static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
hweight8(sseu->slice_mask), sseu->slice_mask);
drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu));
for (s = 0; s < sseu->max_slices; s++) {
- drm_printf(p, "slice%d: %u subslices, mask=%04x\n",
+ drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
s, intel_sseu_subslices_per_slice(sseu, s),
- sseu->subslice_mask[s]);
+ intel_sseu_get_subslices(sseu, s));
}
drm_printf(p, "EU total: %u\n", sseu->eu_total);
drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
@@ -159,9 +159,9 @@ void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
}
for (s = 0; s < sseu->max_slices; s++) {
- drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n",
+ drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
s, intel_sseu_subslices_per_slice(sseu, s),
- sseu->subslice_mask[s]);
+ intel_sseu_get_subslices(sseu, s));
for (ss = 0; ss < sseu->max_subslices; ss++) {
u16 enabled_eus = sseu_get_eus(sseu, s, ss);
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for Refactor to expand subslice mask (rev 2)
2019-08-19 21:49 [PATCH 0/9] Refactor to expand subslice mask (rev 2) Stuart Summers
` (8 preceding siblings ...)
2019-08-19 21:50 ` [PATCH 9/9] drm/i915: Expand subslice mask Stuart Summers
@ 2019-08-19 21:55 ` Patchwork
2019-08-19 22:39 ` ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
12 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2019-08-19 21:55 UTC (permalink / raw)
To: Stuart Summers; +Cc: intel-gfx
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/65437/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f217c83c161f drm/i915: Use variable for debugfs device status
ebb026770255 drm/i915: Add function to set SSEU info per platform
601868f2e0ab drm/i915: Add subslice stride runtime parameter
31c31e79301a drm/i915: Add EU stride runtime parameter
d3c72e5f28e1 drm/i915: Add function to set subslices
f834cf717197 drm/i915: Add function to determine if a slice has a subslice
eb90555f7bb3 drm/i915: Refactor instdone loops on new subslice functions
-:60: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'subslice__' - possible side-effects?
#60: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:583:
+#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
+ (IS_GEN(dev_priv__, 7) ? (1 & BIT(subslice__)) : \
+ intel_sseu_has_subslice(sseu__, 0, subslice__))
-:64: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv_' - possible side-effects?
#64: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:587:
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+ for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+ (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \
+ (slice_) += ((subslice_) == 0)) \
+ for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \
+ (instdone_has_subslice(dev_priv_, sseu_, slice_, \
+ subslice_)))
-:64: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'sseu_' - possible side-effects?
#64: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:587:
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+ for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+ (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \
+ (slice_) += ((subslice_) == 0)) \
+ for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \
+ (instdone_has_subslice(dev_priv_, sseu_, slice_, \
+ subslice_)))
-:64: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'slice_' - possible side-effects?
#64: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:587:
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+ for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+ (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \
+ (slice_) += ((subslice_) == 0)) \
+ for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \
+ (instdone_has_subslice(dev_priv_, sseu_, slice_, \
+ subslice_)))
-:64: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'subslice_' - possible side-effects?
#64: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:587:
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+ for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+ (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \
+ (slice_) += ((subslice_) == 0)) \
+ for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \
+ (instdone_has_subslice(dev_priv_, sseu_, slice_, \
+ subslice_)))
total: 0 errors, 0 warnings, 5 checks, 106 lines checked
41990ed2780c drm/i915: Add new function to copy subslices for a slice
974b8ca59175 drm/i915: Expand subslice mask
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread* ✓ Fi.CI.BAT: success for Refactor to expand subslice mask (rev 2)
2019-08-19 21:49 [PATCH 0/9] Refactor to expand subslice mask (rev 2) Stuart Summers
` (9 preceding siblings ...)
2019-08-19 21:55 ` ✗ Fi.CI.CHECKPATCH: warning for Refactor to expand subslice mask (rev 2) Patchwork
@ 2019-08-19 22:39 ` Patchwork
2019-08-20 10:44 ` ✓ Fi.CI.IGT: " Patchwork
2019-08-20 11:10 ` Patchwork
12 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2019-08-19 22:39 UTC (permalink / raw)
To: Stuart Summers; +Cc: intel-gfx
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/65437/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6741 -> Patchwork_14089
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/
Known issues
------------
Here are the changes found in Patchwork_14089 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][1] ([fdo#107718]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
* igt@gem_sync@basic-store-each:
- fi-cfl-8109u: [INCOMPLETE][3] ([fdo#111427]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/fi-cfl-8109u/igt@gem_sync@basic-store-each.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/fi-cfl-8109u/igt@gem_sync@basic-store-each.html
* igt@i915_selftest@live_execlists:
- {fi-icl-guc}: [INCOMPLETE][5] ([fdo#107713]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/fi-icl-guc/igt@i915_selftest@live_execlists.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/fi-icl-guc/igt@i915_selftest@live_execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#111427]: https://bugs.freedesktop.org/show_bug.cgi?id=111427
Participating hosts (55 -> 46)
------------------------------
Missing (9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-u3 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6741 -> Patchwork_14089
CI-20190529: 20190529
CI_DRM_6741: 0db9333be821acadbf8c476e13b160522d252d77 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5141: 7102b417fedc2a1ea6f72d768a9f1bd100a34f13 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14089: 974b8ca59175df1e480372d134a39187f42cd060 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
974b8ca59175 drm/i915: Expand subslice mask
41990ed2780c drm/i915: Add new function to copy subslices for a slice
eb90555f7bb3 drm/i915: Refactor instdone loops on new subslice functions
f834cf717197 drm/i915: Add function to determine if a slice has a subslice
d3c72e5f28e1 drm/i915: Add function to set subslices
31c31e79301a drm/i915: Add EU stride runtime parameter
601868f2e0ab drm/i915: Add subslice stride runtime parameter
ebb026770255 drm/i915: Add function to set SSEU info per platform
f217c83c161f drm/i915: Use variable for debugfs device status
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread* ✓ Fi.CI.IGT: success for Refactor to expand subslice mask (rev 2)
2019-08-19 21:49 [PATCH 0/9] Refactor to expand subslice mask (rev 2) Stuart Summers
` (10 preceding siblings ...)
2019-08-19 22:39 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-08-20 10:44 ` Patchwork
2019-08-20 11:10 ` Patchwork
12 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2019-08-20 10:44 UTC (permalink / raw)
To: Summers, Stuart; +Cc: intel-gfx
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/65437/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6741_full -> Patchwork_14089_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_14089_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_blt@dumb-buf:
- shard-apl: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927]) +2 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-apl1/igt@gem_exec_blt@dumb-buf.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-apl7/igt@gem_exec_blt@dumb-buf.html
* igt@gem_exec_schedule@in-order-bsd2:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +14 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb1/igt@gem_exec_schedule@in-order-bsd2.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb3/igt@gem_exec_schedule@in-order-bsd2.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +7 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb7/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb4/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@i915_pm_rpm@system-suspend:
- shard-skl: [PASS][7] -> [INCOMPLETE][8] ([fdo#104108] / [fdo#107807])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl3/igt@i915_pm_rpm@system-suspend.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-skl2/igt@i915_pm_rpm@system-suspend.html
* igt@kms_flip@2x-modeset-vs-vblank-race:
- shard-glk: [PASS][9] -> [FAIL][10] ([fdo#103060])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-glk1/igt@kms_flip@2x-modeset-vs-vblank-race.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-glk5/igt@kms_flip@2x-modeset-vs-vblank-race.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
- shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +2 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [PASS][13] -> [DMESG-WARN][14] ([fdo#108566]) +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-apl2/igt@kms_frontbuffer_tracking@fbc-suspend.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-apl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109642] / [fdo#111068])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb1/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@no_drrs:
- shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#108341])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb2/igt@kms_psr@no_drrs.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb1/igt@kms_psr@no_drrs.html
* igt@perf_pmu@busy-accuracy-2-bcs0:
- shard-iclb: [PASS][21] -> [INCOMPLETE][22] ([fdo#107713])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb8/igt@perf_pmu@busy-accuracy-2-bcs0.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb1/igt@perf_pmu@busy-accuracy-2-bcs0.html
#### Possible fixes ####
* igt@gem_exec_schedule@promotion-bsd:
- shard-iclb: [SKIP][23] ([fdo#111325]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb1/igt@gem_exec_schedule@promotion-bsd.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb3/igt@gem_exec_schedule@promotion-bsd.html
* igt@gem_mmap_gtt@forked-big-copy:
- shard-apl: [INCOMPLETE][25] ([fdo#103927]) -> [PASS][26] +2 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-apl4/igt@gem_mmap_gtt@forked-big-copy.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-apl8/igt@gem_mmap_gtt@forked-big-copy.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [DMESG-WARN][27] ([fdo#108566]) -> [PASS][28] +3 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-apl3/igt@i915_suspend@sysfs-reader.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-apl8/igt@i915_suspend@sysfs-reader.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
- shard-hsw: [FAIL][29] ([fdo#103355]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-hsw1/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [FAIL][31] ([fdo#102670]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [FAIL][33] ([fdo#105363]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt:
- shard-iclb: [FAIL][35] ([fdo#103167]) -> [PASS][36] +3 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-skl: [INCOMPLETE][37] ([fdo#104108]) -> [PASS][38] +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-skl10/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][39] ([fdo#108145] / [fdo#110403]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [FAIL][41] ([fdo#103166]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-y.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][43] ([fdo#109441]) -> [PASS][44] +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb1/igt@kms_psr@psr2_no_drrs.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
* igt@perf@blocking:
- shard-skl: [FAIL][45] ([fdo#110728]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl5/igt@perf@blocking.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-skl8/igt@perf@blocking.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [SKIP][47] ([fdo#109276]) -> [PASS][48] +15 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb7/igt@prime_vgem@fence-wait-bsd2.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-settings-bsd2:
- shard-iclb: [SKIP][49] ([fdo#109276]) -> [FAIL][50] ([fdo#111330])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb3/igt@gem_mocs_settings@mocs-settings-bsd2.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb4/igt@gem_mocs_settings@mocs-settings-bsd2.html
[fdo#102670]: https://bugs.freedesktop.org/show_bug.cgi?id=102670
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6741 -> Patchwork_14089
CI-20190529: 20190529
CI_DRM_6741: 0db9333be821acadbf8c476e13b160522d252d77 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5141: 7102b417fedc2a1ea6f72d768a9f1bd100a34f13 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14089: 974b8ca59175df1e480372d134a39187f42cd060 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread* ✓ Fi.CI.IGT: success for Refactor to expand subslice mask (rev 2)
2019-08-19 21:49 [PATCH 0/9] Refactor to expand subslice mask (rev 2) Stuart Summers
` (11 preceding siblings ...)
2019-08-20 10:44 ` ✓ Fi.CI.IGT: " Patchwork
@ 2019-08-20 11:10 ` Patchwork
12 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2019-08-20 11:10 UTC (permalink / raw)
To: Summers, Stuart; +Cc: intel-gfx
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/65437/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6741_full -> Patchwork_14089_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_14089_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_blt@dumb-buf:
- shard-apl: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927]) +2 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-apl1/igt@gem_exec_blt@dumb-buf.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-apl7/igt@gem_exec_blt@dumb-buf.html
* igt@gem_exec_schedule@in-order-bsd2:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +14 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb1/igt@gem_exec_schedule@in-order-bsd2.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb3/igt@gem_exec_schedule@in-order-bsd2.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +7 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb7/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb4/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@i915_pm_rpm@system-suspend:
- shard-skl: [PASS][7] -> [INCOMPLETE][8] ([fdo#104108] / [fdo#107807])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl3/igt@i915_pm_rpm@system-suspend.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-skl2/igt@i915_pm_rpm@system-suspend.html
* igt@kms_flip@2x-modeset-vs-vblank-race:
- shard-glk: [PASS][9] -> [FAIL][10] ([fdo#103060])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-glk1/igt@kms_flip@2x-modeset-vs-vblank-race.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-glk5/igt@kms_flip@2x-modeset-vs-vblank-race.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
- shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +2 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [PASS][13] -> [DMESG-WARN][14] ([fdo#108566]) +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-apl2/igt@kms_frontbuffer_tracking@fbc-suspend.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-apl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109642] / [fdo#111068])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb1/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@no_drrs:
- shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#108341])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb2/igt@kms_psr@no_drrs.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb1/igt@kms_psr@no_drrs.html
* igt@perf_pmu@busy-accuracy-2-bcs0:
- shard-iclb: [PASS][21] -> [INCOMPLETE][22] ([fdo#107713])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb8/igt@perf_pmu@busy-accuracy-2-bcs0.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb1/igt@perf_pmu@busy-accuracy-2-bcs0.html
#### Possible fixes ####
* igt@gem_exec_schedule@promotion-bsd:
- shard-iclb: [SKIP][23] ([fdo#111325]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb1/igt@gem_exec_schedule@promotion-bsd.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb3/igt@gem_exec_schedule@promotion-bsd.html
* igt@gem_mmap_gtt@forked-big-copy:
- shard-apl: [INCOMPLETE][25] ([fdo#103927]) -> [PASS][26] +2 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-apl4/igt@gem_mmap_gtt@forked-big-copy.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-apl8/igt@gem_mmap_gtt@forked-big-copy.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [DMESG-WARN][27] ([fdo#108566]) -> [PASS][28] +3 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-apl3/igt@i915_suspend@sysfs-reader.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-apl8/igt@i915_suspend@sysfs-reader.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
- shard-hsw: [FAIL][29] ([fdo#103355]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-hsw1/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [FAIL][31] ([fdo#102670]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [FAIL][33] ([fdo#105363]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt:
- shard-iclb: [FAIL][35] ([fdo#103167]) -> [PASS][36] +3 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-skl: [INCOMPLETE][37] ([fdo#104108]) -> [PASS][38] +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-skl10/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][39] ([fdo#108145] / [fdo#110403]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [FAIL][41] ([fdo#103166]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-y.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][43] ([fdo#109441]) -> [PASS][44] +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb1/igt@kms_psr@psr2_no_drrs.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
* igt@perf@blocking:
- shard-skl: [FAIL][45] ([fdo#110728]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl5/igt@perf@blocking.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-skl8/igt@perf@blocking.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [SKIP][47] ([fdo#109276]) -> [PASS][48] +15 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb7/igt@prime_vgem@fence-wait-bsd2.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-settings-bsd2:
- shard-iclb: [SKIP][49] ([fdo#109276]) -> [FAIL][50] ([fdo#111330])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb3/igt@gem_mocs_settings@mocs-settings-bsd2.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb4/igt@gem_mocs_settings@mocs-settings-bsd2.html
[fdo#102670]: https://bugs.freedesktop.org/show_bug.cgi?id=102670
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6741 -> Patchwork_14089
CI-20190529: 20190529
CI_DRM_6741: 0db9333be821acadbf8c476e13b160522d252d77 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5141: 7102b417fedc2a1ea6f72d768a9f1bd100a34f13 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14089: 974b8ca59175df1e480372d134a39187f42cd060 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread