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From: Will Deacon <will@kernel.org>
To: Robin Murphy <robin.murphy@arm.com>
Cc: iommu@lists.linux-foundation.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 4/4] iommu/io-pgtable-arm: Prepare for TTBR1 usage
Date: Tue, 20 Aug 2019 16:58:24 +0100	[thread overview]
Message-ID: <20190820155823.ptn2rfvnmkd4v632@willie-the-truck> (raw)
In-Reply-To: <469dc66a-2532-5f7f-cd8d-3fe13f6c279a@arm.com>

On Tue, Aug 20, 2019 at 03:51:45PM +0100, Robin Murphy wrote:
> On 20/08/2019 11:30, Will Deacon wrote:
> > On Mon, Aug 19, 2019 at 07:19:31PM +0100, Robin Murphy wrote:
> > > Now that callers are free to use a given table for TTBR1 if they wish
> > > (all they need do is shift the provided attributes when constructing
> > > their final TCR value), the only remaining impediment is the address
> > > validation on map/unmap. The fact that the LPAE address space split is
> > > symmetric makes this easy to accommodate - by simplifying the current
> > > range checks into explicit tests that address bits above IAS are all
> > > zero, it then follows straightforwardly to add the inverse test to
> > > allow the all-ones case as well.
> > > 
> > > Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> > > ---
> > >   drivers/iommu/io-pgtable-arm.c | 7 ++++---
> > >   1 file changed, 4 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
> > > index 09cb20671fbb..f39c50356351 100644
> > > --- a/drivers/iommu/io-pgtable-arm.c
> > > +++ b/drivers/iommu/io-pgtable-arm.c
> > > @@ -475,13 +475,13 @@ static int arm_lpae_map(struct io_pgtable_ops *ops, unsigned long iova,
> > >   	arm_lpae_iopte *ptep = data->pgd;
> > >   	int ret, lvl = ARM_LPAE_START_LVL(data);
> > >   	arm_lpae_iopte prot;
> > > +	long iaext = (long)iova >> data->iop.cfg.ias;
> > >   	/* If no access, then nothing to do */
> > >   	if (!(iommu_prot & (IOMMU_READ | IOMMU_WRITE)))
> > >   		return 0;
> > > -	if (WARN_ON(iova >= (1ULL << data->iop.cfg.ias) ||
> > > -		    paddr >= (1ULL << data->iop.cfg.oas)))
> > > +	if (WARN_ON((iaext && ~iaext) || paddr >> data->iop.cfg.oas))
> > 
> > I had to read that '&&' twice, but I see what you're doing now :)
> > 
> > >   		return -ERANGE;
> > 
> > This doesn't seem sufficient to prevent a mixture of TTBR1 and TTBR0
> > addresses from being mapped in the same TTBR. Perhaps we need a quirk for
> > TTBR1, which could then take care of setting EPDx appropriately?
> 
> Right, that's the one downside of going for the minimalist "io-pgtable
> doesn't even have to know" approach. On reflection, though, in that paradigm
> it should probably be the caller's responsibility to convert TTBR1 addresses
> to preserve the "as if TTBR0" illusion anyway :/

Right, and I'd rather not push stuff into the caller for the common case.
It's not exactly onerous to support this in io-pgtable. It's also why I'd
still like to keep the EPDx in there, because the callers that care can
rewrite the stuff, but at least we provided a default.

> The advantage of not having a quirk is that it allows split address spaces
> to fit more closely with the aux_domain idea, i.e. we could allocate and
> initialise a domain without having to assume, or even care, whether it will
> end up attached as a primary or aux domain. It *might* even be potentially
> useful to have a domain attached to TTBR0 of one device's context and TTBR1
> of another's at the same time, although that's pretty niche.

That sounds pretty theoretical to me at the moment.

Will
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu

WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will@kernel.org>
To: Robin Murphy <robin.murphy@arm.com>
Cc: robdclark@gmail.com, joro@8bytes.org, jcrouse@codeaurora.org,
	iommu@lists.linux-foundation.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 4/4] iommu/io-pgtable-arm: Prepare for TTBR1 usage
Date: Tue, 20 Aug 2019 16:58:24 +0100	[thread overview]
Message-ID: <20190820155823.ptn2rfvnmkd4v632@willie-the-truck> (raw)
In-Reply-To: <469dc66a-2532-5f7f-cd8d-3fe13f6c279a@arm.com>

On Tue, Aug 20, 2019 at 03:51:45PM +0100, Robin Murphy wrote:
> On 20/08/2019 11:30, Will Deacon wrote:
> > On Mon, Aug 19, 2019 at 07:19:31PM +0100, Robin Murphy wrote:
> > > Now that callers are free to use a given table for TTBR1 if they wish
> > > (all they need do is shift the provided attributes when constructing
> > > their final TCR value), the only remaining impediment is the address
> > > validation on map/unmap. The fact that the LPAE address space split is
> > > symmetric makes this easy to accommodate - by simplifying the current
> > > range checks into explicit tests that address bits above IAS are all
> > > zero, it then follows straightforwardly to add the inverse test to
> > > allow the all-ones case as well.
> > > 
> > > Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> > > ---
> > >   drivers/iommu/io-pgtable-arm.c | 7 ++++---
> > >   1 file changed, 4 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
> > > index 09cb20671fbb..f39c50356351 100644
> > > --- a/drivers/iommu/io-pgtable-arm.c
> > > +++ b/drivers/iommu/io-pgtable-arm.c
> > > @@ -475,13 +475,13 @@ static int arm_lpae_map(struct io_pgtable_ops *ops, unsigned long iova,
> > >   	arm_lpae_iopte *ptep = data->pgd;
> > >   	int ret, lvl = ARM_LPAE_START_LVL(data);
> > >   	arm_lpae_iopte prot;
> > > +	long iaext = (long)iova >> data->iop.cfg.ias;
> > >   	/* If no access, then nothing to do */
> > >   	if (!(iommu_prot & (IOMMU_READ | IOMMU_WRITE)))
> > >   		return 0;
> > > -	if (WARN_ON(iova >= (1ULL << data->iop.cfg.ias) ||
> > > -		    paddr >= (1ULL << data->iop.cfg.oas)))
> > > +	if (WARN_ON((iaext && ~iaext) || paddr >> data->iop.cfg.oas))
> > 
> > I had to read that '&&' twice, but I see what you're doing now :)
> > 
> > >   		return -ERANGE;
> > 
> > This doesn't seem sufficient to prevent a mixture of TTBR1 and TTBR0
> > addresses from being mapped in the same TTBR. Perhaps we need a quirk for
> > TTBR1, which could then take care of setting EPDx appropriately?
> 
> Right, that's the one downside of going for the minimalist "io-pgtable
> doesn't even have to know" approach. On reflection, though, in that paradigm
> it should probably be the caller's responsibility to convert TTBR1 addresses
> to preserve the "as if TTBR0" illusion anyway :/

Right, and I'd rather not push stuff into the caller for the common case.
It's not exactly onerous to support this in io-pgtable. It's also why I'd
still like to keep the EPDx in there, because the callers that care can
rewrite the stuff, but at least we provided a default.

> The advantage of not having a quirk is that it allows split address spaces
> to fit more closely with the aux_domain idea, i.e. we could allocate and
> initialise a domain without having to assume, or even care, whether it will
> end up attached as a primary or aux domain. It *might* even be potentially
> useful to have a domain attached to TTBR0 of one device's context and TTBR1
> of another's at the same time, although that's pretty niche.

That sounds pretty theoretical to me at the moment.

Will

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2019-08-20 15:58 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-19 18:19 [PATCH 0/4] iommu/io-pgtable: Cleanup and prep for split tables Robin Murphy
2019-08-19 18:19 ` Robin Murphy
2019-08-19 18:19 ` [PATCH 1/4] iommu/io-pgtable-arm: Rationalise MAIR handling Robin Murphy
2019-08-19 18:19   ` Robin Murphy
2019-08-19 18:19 ` [PATCH 2/4] iommu/io-pgtable-arm: Rationalise TTBRn handling Robin Murphy
2019-08-19 18:19   ` Robin Murphy
2019-08-20 10:19   ` Will Deacon
2019-08-20 10:19     ` Will Deacon
2019-08-20 14:17     ` Robin Murphy
2019-08-20 14:17       ` Robin Murphy
2019-08-20 15:50       ` Will Deacon
2019-08-20 15:50         ` Will Deacon
2019-08-19 18:19 ` [PATCH 3/4] iommu/io-pgtable-arm: Rationalise TCR handling Robin Murphy
2019-08-19 18:19   ` Robin Murphy
2019-08-20 10:31   ` Will Deacon
2019-08-20 10:31     ` Will Deacon
2019-08-20 15:25     ` Robin Murphy
2019-08-20 15:25       ` Robin Murphy
2019-08-20 16:07       ` Will Deacon
2019-08-20 16:07         ` Will Deacon
2019-08-20 18:41         ` Robin Murphy
2019-08-20 18:41           ` Robin Murphy
2019-08-21 12:11           ` Will Deacon
2019-08-21 12:11             ` Will Deacon
2019-08-21 12:56             ` Robin Murphy
2019-08-21 12:56               ` Robin Murphy
2019-10-03 17:33               ` Jordan Crouse
2019-10-03 17:33                 ` Jordan Crouse
2019-10-24 10:51                 ` Will Deacon
2019-10-24 10:51                   ` Will Deacon
2019-10-24 11:23                   ` Robin Murphy
2019-10-24 11:23                     ` Robin Murphy
2019-10-24 11:40                     ` Will Deacon
2019-10-24 11:40                       ` Will Deacon
2019-08-20 16:23       ` Jordan Crouse
2019-08-20 16:23         ` Jordan Crouse
2019-08-19 18:19 ` [PATCH 4/4] iommu/io-pgtable-arm: Prepare for TTBR1 usage Robin Murphy
2019-08-19 18:19   ` Robin Murphy
2019-08-19 22:34   ` Jordan Crouse
2019-08-19 22:34     ` Jordan Crouse
2019-08-20 13:51     ` Robin Murphy
2019-08-20 13:51       ` Robin Murphy
2019-08-20 10:30   ` Will Deacon
2019-08-20 10:30     ` Will Deacon
2019-08-20 14:51     ` Robin Murphy
2019-08-20 14:51       ` Robin Murphy
2019-08-20 15:58       ` Will Deacon [this message]
2019-08-20 15:58         ` Will Deacon

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