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From: "hch@infradead.org" <hch@infradead.org>
To: Anup Patel <anup@brainfault.org>
Cc: "hch@infradead.org" <hch@infradead.org>,
	Alan Kao <alankao@andestech.com>,
	Atish Patra <Atish.Patra@wdc.com>,
	"aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>,
	"palmer@sifive.com" <palmer@sifive.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"schwab@linux-m68k.org" <schwab@linux-m68k.org>,
	"paul.walmsley@sifive.com" <paul.walmsley@sifive.com>,
	"linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
	"allison@lohutok.net" <allison@lohutok.net>
Subject: Re: [v2 PATCH] RISC-V: Optimize tlb flush path.
Date: Wed, 21 Aug 2019 00:18:55 -0700	[thread overview]
Message-ID: <20190821071855.GA32145@infradead.org> (raw)
In-Reply-To: <CAAhSdy0GX9BbayYScsm2_Mvi0hDH-y0UVvTWFGLbKY-rE8TfZQ@mail.gmail.com>

On Wed, Aug 21, 2019 at 09:22:48AM +0530, Anup Patel wrote:
> I agree that IPI mechanism should be standardized for RISC-V but I
> don't support the idea of mandating CLINT as part of the UNIX
> platform spec. For example, the AndesTech SOC does not use CLINT
> instead they have PLMT for per-HART timer and PLICSW for per-HART
> IPIs.

The point is not really mandating a CLINT as know right now.  The
point is to mandate one way to issue IPIs from S-mode to S-mode,
one way to read the time counter and one way to write the timer
threshold.

WARNING: multiple messages have this Message-ID (diff)
From: "hch@infradead.org" <hch@infradead.org>
To: Anup Patel <anup@brainfault.org>
Cc: "aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>,
	Alan Kao <alankao@andestech.com>,
	"palmer@sifive.com" <palmer@sifive.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"hch@infradead.org" <hch@infradead.org>,
	Atish Patra <Atish.Patra@wdc.com>,
	"schwab@linux-m68k.org" <schwab@linux-m68k.org>,
	"paul.walmsley@sifive.com" <paul.walmsley@sifive.com>,
	"linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
	"allison@lohutok.net" <allison@lohutok.net>
Subject: Re: [v2 PATCH] RISC-V: Optimize tlb flush path.
Date: Wed, 21 Aug 2019 00:18:55 -0700	[thread overview]
Message-ID: <20190821071855.GA32145@infradead.org> (raw)
In-Reply-To: <CAAhSdy0GX9BbayYScsm2_Mvi0hDH-y0UVvTWFGLbKY-rE8TfZQ@mail.gmail.com>

On Wed, Aug 21, 2019 at 09:22:48AM +0530, Anup Patel wrote:
> I agree that IPI mechanism should be standardized for RISC-V but I
> don't support the idea of mandating CLINT as part of the UNIX
> platform spec. For example, the AndesTech SOC does not use CLINT
> instead they have PLMT for per-HART timer and PLICSW for per-HART
> IPIs.

The point is not really mandating a CLINT as know right now.  The
point is to mandate one way to issue IPIs from S-mode to S-mode,
one way to read the time counter and one way to write the timer
threshold.

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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2019-08-21  7:19 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-20  0:47 [v2 PATCH] RISC-V: Optimize tlb flush path Atish Patra
2019-08-20  0:47 ` Atish Patra
2019-08-20  3:06 ` hch
2019-08-20  3:06   ` hch
2019-08-20  7:14   ` Andreas Schwab
2019-08-20  7:14     ` Andreas Schwab
2019-08-20  7:16     ` hch
2019-08-20  7:16       ` hch
2019-08-20  7:46 ` Andreas Schwab
2019-08-20  7:46   ` Andreas Schwab
2019-08-20  8:42   ` Atish Patra
2019-08-20  8:42     ` Atish Patra
2019-08-20  8:51     ` Andreas Schwab
2019-08-20  8:51       ` Andreas Schwab
2019-08-20  9:22     ` hch
2019-08-20  9:22       ` hch
2019-08-20 20:28       ` Atish Patra
2019-08-20 20:28         ` Atish Patra
2019-08-20 22:18         ` hch
2019-08-20 22:18           ` hch
2019-08-20 22:24           ` Atish Patra
2019-08-20 22:24             ` Atish Patra
2019-08-21  1:29         ` Alan Kao
2019-08-21  1:29           ` Alan Kao
2019-08-21  1:40           ` hch
2019-08-21  1:40             ` hch
2019-08-21  3:52             ` Anup Patel
2019-08-21  3:52               ` Anup Patel
2019-08-21  7:18               ` hch [this message]
2019-08-21  7:18                 ` hch
2019-08-20  8:51 ` Anup Patel
2019-08-20  8:51   ` Anup Patel
2019-08-20 20:29   ` Atish Patra
2019-08-20 20:29     ` Atish Patra
2019-08-21 14:41     ` hch
2019-08-21 14:41       ` hch
2019-08-21 14:45 ` hch
2019-08-21 14:45   ` hch
2019-08-21 17:36   ` Atish Patra
2019-08-21 17:36     ` Atish Patra

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