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From: Animesh Manna <animesh.manna@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Michel Thierry <michel.thierry@intel.com>,
	Jani Nikula <jani.nikula@intel.com>
Subject: [PATCH v4 06/10] drm/i915/dsb: functions to enable/disable DSB engine.
Date: Fri, 30 Aug 2019 18:15:29 +0530	[thread overview]
Message-ID: <20190830124533.26573-7-animesh.manna@intel.com> (raw)
In-Reply-To: <20190830124533.26573-1-animesh.manna@intel.com>

DSB will be used for performance improvement for some special scenario.
DSB engine will be enabled based on need and after completion of its work
will be disabled. Api added for enable/disable operation by using DSB_CTRL
register.

v1: Initial version.
v2: POSTING_READ added after writing control register. (Shashank)

Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsb.c | 42 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h          |  1 +
 2 files changed, 43 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 1022b5720d17..485748e63a94 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -26,6 +26,48 @@ static inline bool is_dsb_busy(struct intel_dsb *dsb)
 	return DSB_STATUS & I915_READ(DSB_CTRL(pipe, dsb->id));
 }
 
+static inline bool intel_dsb_enable_engine(struct intel_dsb *dsb)
+{
+	struct intel_crtc *crtc = dsb->crtc;
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
+	u32 dsb_ctrl;
+
+	dsb_ctrl = I915_READ(DSB_CTRL(pipe, dsb->id));
+
+	if (DSB_STATUS & dsb_ctrl) {
+		DRM_DEBUG_KMS("DSB engine is busy.\n");
+		return false;
+	}
+
+	dsb_ctrl |= DSB_ENABLE;
+	I915_WRITE(DSB_CTRL(pipe, dsb->id), dsb_ctrl);
+
+	POSTING_READ(DSB_CTRL(pipe, dsb->id));
+	return true;
+}
+
+static inline bool intel_dsb_disable_engine(struct intel_dsb *dsb)
+{
+	struct intel_crtc *crtc = dsb->crtc;
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
+	u32 dsb_ctrl;
+
+	dsb_ctrl = I915_READ(DSB_CTRL(pipe, dsb->id));
+
+	if (DSB_STATUS & dsb_ctrl) {
+		DRM_DEBUG_KMS("DSB engine is busy.\n");
+		return false;
+	}
+
+	dsb_ctrl &= ~DSB_ENABLE;
+	I915_WRITE(DSB_CTRL(pipe, dsb->id), dsb_ctrl);
+
+	POSTING_READ(DSB_CTRL(pipe, dsb->id));
+	return true;
+}
+
 struct intel_dsb *
 intel_dsb_get(struct intel_crtc *crtc)
 {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3e35d7a4d2c4..067f86d3a9de 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11675,6 +11675,7 @@ enum skl_power_gate {
 #define DSBSL_INSTANCE(pipe, id)	(_DSBSL_INSTANCE_BASE + \
 					 (pipe) * 0x1000 + (id) * 100)
 #define DSB_CTRL(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
+#define   DSB_ENABLE			(1 << 31)
 #define   DSB_STATUS			(1 << 0)
 
 #endif /* _I915_REG_H_ */
-- 
2.22.0

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  parent reply	other threads:[~2019-08-30 12:53 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-30 12:45 [PATCH v4 00/10] DSB enablement Animesh Manna
2019-08-30 12:45 ` [PATCH v4 01/10] drm/i915/dsb: feature flag added for display state buffer Animesh Manna
2019-08-30 12:45 ` [PATCH v4 02/10] drm/i915/dsb: DSB context creation Animesh Manna
2019-08-30 13:35   ` Jani Nikula
2019-09-03  3:55     ` Sharma, Shashank
2019-09-03 10:45     ` Animesh Manna
2019-09-03 11:22       ` Jani Nikula
2019-08-30 12:45 ` [PATCH v4 03/10] drm/i915/dsb: single register write function for DSB Animesh Manna
2019-08-30 12:45 ` [PATCH v4 04/10] drm/i915/dsb: Indexed " Animesh Manna
2019-08-30 12:45 ` [PATCH v4 05/10] drm/i915/dsb: Check DSB engine status Animesh Manna
2019-08-30 12:45 ` Animesh Manna [this message]
2019-08-30 12:45 ` [PATCH v4 07/10] drm/i915/dsb: function to trigger workload execution of DSB Animesh Manna
2019-08-30 12:45 ` [PATCH v4 08/10] drm/i915/dsb: Enable gamma lut programming using DSB Animesh Manna
2019-08-30 13:32   ` Jani Nikula
2019-09-03  4:00     ` Sharma, Shashank
     [not found]       ` <8736hd6c9g.fsf@intel.com>
2019-09-03  8:02         ` Sharma, Shashank
2019-09-03  8:08     ` Jani Nikula
2019-09-03 11:05       ` Animesh Manna
2019-09-03 11:14         ` Jani Nikula
2019-09-04 10:30     ` Animesh Manna
2019-08-30 12:45 ` [PATCH v4 09/10] drm/i915/dsb: Enable DSB for gen12 Animesh Manna
2019-08-30 12:45 ` [PATCH v4 10/10] drm/i915/dsb: Documentation for DSB Animesh Manna
2019-08-30 12:59 ` ✗ Fi.CI.CHECKPATCH: warning for DSB enablement. (rev4) Patchwork
2019-08-30 13:00 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-08-30 13:46 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-31  9:02 ` ✓ Fi.CI.IGT: " Patchwork

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