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From: Animesh Manna <animesh.manna@intel.com>
To: Jani Nikula <jani.nikula@intel.com>, intel-gfx@lists.freedesktop.org
Cc: Michel Thierry <michel.thierry@intel.com>
Subject: Re: [PATCH v4 02/10] drm/i915/dsb: DSB context creation.
Date: Tue, 3 Sep 2019 16:15:30 +0530	[thread overview]
Message-ID: <4191e8f9-dfeb-7ed8-9a06-be79947ca1f6@intel.com> (raw)
In-Reply-To: <875zme6ais.fsf@intel.com>

Hi,


On 8/30/2019 7:05 PM, Jani Nikula wrote:
> On Fri, 30 Aug 2019, Animesh Manna <animesh.manna@intel.com> wrote:
>> This patch adds a function, which will internally get the gem buffer
>> for DSB engine. The GEM buffer is from global GTT, and is mapped into
>> CPU domain, contains the data + opcode to be feed to DSB engine.
>>
>> v1: Initial version.
>>
>> v2:
>> - removed some unwanted code. (Chris)
>> - Used i915_gem_object_create_internal instead of _shmem. (Chris)
>> - cmd_buf_tail removed and can be derived through vma object. (Chris)
>>
>> v3: vma realeased if i915_gem_object_pin_map() failed. (Shashank)
>>
>> Cc: Imre Deak <imre.deak@intel.com>
>> Cc: Michel Thierry <michel.thierry@intel.com>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>> ---
>>   drivers/gpu/drm/i915/Makefile                 |  1 +
>>   .../drm/i915/display/intel_display_types.h    |  3 +
>>   drivers/gpu/drm/i915/display/intel_dsb.c      | 83 +++++++++++++++++++
>>   drivers/gpu/drm/i915/display/intel_dsb.h      | 31 +++++++
>>   drivers/gpu/drm/i915/i915_drv.h               |  1 +
>>   5 files changed, 119 insertions(+)
>>   create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.c
>>   create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.h
>>
>> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
>> index 658b930d34a8..6313e7b4bd78 100644
>> --- a/drivers/gpu/drm/i915/Makefile
>> +++ b/drivers/gpu/drm/i915/Makefile
>> @@ -172,6 +172,7 @@ i915-y += \
>>   	display/intel_display_power.o \
>>   	display/intel_dpio_phy.o \
>>   	display/intel_dpll_mgr.o \
>> +	display/intel_dsb.o \
>>   	display/intel_fbc.o \
>>   	display/intel_fifo_underrun.o \
>>   	display/intel_frontbuffer.o \
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index 61277a87dbe7..da36867189cb 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1033,6 +1033,9 @@ struct intel_crtc {
>>   
>>   	/* scalers available on this crtc */
>>   	int num_scalers;
>> +
>> +	/* per pipe DSB related info */
>> +	struct intel_dsb dsb[MAX_DSB_PER_PIPE];
>>   };
>>   
>>   struct intel_plane {
>> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
>> new file mode 100644
>> index 000000000000..007ef13481d5
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
>> @@ -0,0 +1,83 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright © 2019 Intel Corporation
>> + *
>> + */
>> +
>> +#include "i915_drv.h"
>> +#include "intel_display_types.h"
>> +
>> +#define DSB_BUF_SIZE    (2 * PAGE_SIZE)
>> +
>> +struct intel_dsb *
>> +intel_dsb_get(struct intel_crtc *crtc)
>> +{
>> +	struct drm_device *dev = crtc->base.dev;
>> +	struct drm_i915_private *i915 = to_i915(dev);
>> +	struct drm_i915_gem_object *obj;
>> +	struct i915_vma *vma;
>> +	struct intel_dsb *dsb;
>> +	intel_wakeref_t wakeref;
>> +	int i;
>> +
>> +	for (i = 0; i < MAX_DSB_PER_PIPE; i++)
>> +		if (!crtc->dsb[i].cmd_buf)
>> +			break;
>> +
>> +	if (WARN_ON(i == MAX_DSB_PER_PIPE))
>> +		return NULL;
>> +
>> +	dsb = &crtc->dsb[i];
>> +	dsb->id = i;
>> +	dsb->crtc = crtc;
>> +	if (!HAS_DSB(i915))
>> +		return dsb;
> Why do you go through any of the trouble if there is no DSB? Just early
> return NULL, and make the write functions handle NULL dsb pointer.

Handing NULL dsb pointer in write function is easy, but getting dev_priv 
which is needed for I915_WRITE is tricky with the following function 
prototypes which were agreed (I can understand  it was discussed long 
back, so added below). Good to get your suggestion here.

struct intel_dsb * intel_dsb_get(struct intel_crtc *crtc);
void intel_dsb_put(struct intel_dsb *dsb);
void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg, 
u32 val);
void intel_dsb_commit(struct intel_dsb *dsb);

Regards,
Animesh


>
>> +
>> +	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
>> +
>> +	obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
>> +	if (IS_ERR(obj))
>> +		goto err;
>> +
>> +	mutex_lock(&i915->drm.struct_mutex);
>> +	vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
>> +	mutex_unlock(&i915->drm.struct_mutex);
>> +	if (IS_ERR(vma)) {
>> +		DRM_ERROR("Vma creation failed.\n");
>> +		i915_gem_object_put(obj);
>> +		goto err;
>> +	}
>> +
>> +	dsb->cmd_buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
>> +	if (IS_ERR(dsb->cmd_buf)) {
>> +		DRM_ERROR("Command buffer creation failed.\n");
>> +		i915_vma_unpin_and_release(&vma, 0);
>> +		dsb->cmd_buf = NULL;
>> +		goto err;
>> +	}
>> +	dsb->vma = vma;
>> +
>> +err:
>> +	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
>> +	return dsb;
>> +}
>> +
>> +void intel_dsb_put(struct intel_dsb *dsb)
>> +{
>> +	struct intel_crtc *crtc;
>> +	struct drm_i915_private *i915;
>> +
>> +	if (!dsb)
>> +		return;
>> +
>> +	crtc = dsb->crtc;
>> +	i915 = to_i915(crtc->base.dev);
>> +
>> +	if (dsb->cmd_buf) {
>> +		mutex_lock(&i915->drm.struct_mutex);
>> +		i915_gem_object_unpin_map(dsb->vma->obj);
>> +		i915_vma_unpin_and_release(&dsb->vma, 0);
>> +		dsb->cmd_buf = NULL;
>> +		mutex_unlock(&i915->drm.struct_mutex);
>> +	}
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
>> new file mode 100644
>> index 000000000000..4a4091cadc1e
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/display/intel_dsb.h
>> @@ -0,0 +1,31 @@
>> +/* SPDX-License-Identifier: MIT
>> + *
>> + * Copyright © 2019 Intel Corporation
>> + */
>> +
>> +#ifndef _INTEL_DSB_H
>> +#define _INTEL_DSB_H
>> +
>> +struct intel_crtc;
>> +struct i915_vma;
>> +
>> +enum dsb_id {
>> +	INVALID_DSB = -1,
>> +	DSB1,
>> +	DSB2,
>> +	DSB3,
>> +	MAX_DSB_PER_PIPE
>> +};
>> +
>> +struct intel_dsb {
>> +	struct intel_crtc *crtc;
>> +	enum dsb_id id;
>> +	u32 *cmd_buf;
>> +	struct i915_vma *vma;
>> +};
>> +
>> +struct intel_dsb *
>> +intel_dsb_get(struct intel_crtc *crtc);
>> +void intel_dsb_put(struct intel_dsb *dsb);
>> +
>> +#endif
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 804bfe7aec2b..7aa11e3dd413 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -67,6 +67,7 @@
>>   #include "display/intel_display.h"
>>   #include "display/intel_display_power.h"
>>   #include "display/intel_dpll_mgr.h"
>> +#include "display/intel_dsb.h"
>>   #include "display/intel_frontbuffer.h"
>>   #include "display/intel_gmbus.h"
>>   #include "display/intel_opregion.h"

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  parent reply	other threads:[~2019-09-03 10:45 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-30 12:45 [PATCH v4 00/10] DSB enablement Animesh Manna
2019-08-30 12:45 ` [PATCH v4 01/10] drm/i915/dsb: feature flag added for display state buffer Animesh Manna
2019-08-30 12:45 ` [PATCH v4 02/10] drm/i915/dsb: DSB context creation Animesh Manna
2019-08-30 13:35   ` Jani Nikula
2019-09-03  3:55     ` Sharma, Shashank
2019-09-03 10:45     ` Animesh Manna [this message]
2019-09-03 11:22       ` Jani Nikula
2019-08-30 12:45 ` [PATCH v4 03/10] drm/i915/dsb: single register write function for DSB Animesh Manna
2019-08-30 12:45 ` [PATCH v4 04/10] drm/i915/dsb: Indexed " Animesh Manna
2019-08-30 12:45 ` [PATCH v4 05/10] drm/i915/dsb: Check DSB engine status Animesh Manna
2019-08-30 12:45 ` [PATCH v4 06/10] drm/i915/dsb: functions to enable/disable DSB engine Animesh Manna
2019-08-30 12:45 ` [PATCH v4 07/10] drm/i915/dsb: function to trigger workload execution of DSB Animesh Manna
2019-08-30 12:45 ` [PATCH v4 08/10] drm/i915/dsb: Enable gamma lut programming using DSB Animesh Manna
2019-08-30 13:32   ` Jani Nikula
2019-09-03  4:00     ` Sharma, Shashank
     [not found]       ` <8736hd6c9g.fsf@intel.com>
2019-09-03  8:02         ` Sharma, Shashank
2019-09-03  8:08     ` Jani Nikula
2019-09-03 11:05       ` Animesh Manna
2019-09-03 11:14         ` Jani Nikula
2019-09-04 10:30     ` Animesh Manna
2019-08-30 12:45 ` [PATCH v4 09/10] drm/i915/dsb: Enable DSB for gen12 Animesh Manna
2019-08-30 12:45 ` [PATCH v4 10/10] drm/i915/dsb: Documentation for DSB Animesh Manna
2019-08-30 12:59 ` ✗ Fi.CI.CHECKPATCH: warning for DSB enablement. (rev4) Patchwork
2019-08-30 13:00 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-08-30 13:46 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-31  9:02 ` ✓ Fi.CI.IGT: " Patchwork

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