* [PATCH 1/6] drm/i915/psr: Only handle interruptions of the transcoder in use
2019-09-04 21:34 [PATCH 0/6] Tiger Lake batch 3.5 v2 José Roberto de Souza
@ 2019-09-04 21:34 ` José Roberto de Souza
2019-09-04 21:34 ` [PATCH 2/6] drm/i915/tgl: Access the right register when handling PSR interruptions José Roberto de Souza
` (7 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: José Roberto de Souza @ 2019-09-04 21:34 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Dhinakaran Pandiyan
It was enabling and checking PSR interruptions in every transcoder
while it should keep the interruptions on the non-used transcoders
masked.
While doing this it gives us trouble on Tiger Lake if we are
reading/writing to registers of disabled transcoders since from gen12
onwards the registers are relative to the transcoder. Instead of forcing
them ON to access those registers, just avoid the accesses as they are
not needed.
v2 (Lucas):
- Explain why we can't keep accessing all transcoders
- Remove TODO about extending the irq handling to multiple instances:
when/if implementing multiple instances it's pretty clear by the
singleton psr that it needs to be extended
- Fix intel_psr_debug_set() calling psr_irq_control() with
psr.transcoder not set yet (from Imre). Now we only set the debug
register right away if psr is already enabled. Otherwise we just
record the value to be set when enabling the source.
- Do not depend on the value of TRANSCODER_A. Just be relative to it
(from Imre)
- handle psr error last so we don't schedule the work before handling
the other flags
v3:
- Adding a warning about setting reserverd bits on EDP_PSR_IMR
Cc: Imre Deak <imre.deak@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 142 +++++++++--------------
drivers/gpu/drm/i915/i915_reg.h | 13 +--
2 files changed, 60 insertions(+), 95 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 629b8b98a97f..1d99ffeaa36a 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -88,48 +88,20 @@ static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
}
}
-static int edp_psr_shift(enum transcoder cpu_transcoder)
+static void psr_irq_control(struct drm_i915_private *dev_priv)
{
- switch (cpu_transcoder) {
- case TRANSCODER_A:
- return EDP_PSR_TRANSCODER_A_SHIFT;
- case TRANSCODER_B:
- return EDP_PSR_TRANSCODER_B_SHIFT;
- case TRANSCODER_C:
- return EDP_PSR_TRANSCODER_C_SHIFT;
- default:
- MISSING_CASE(cpu_transcoder);
- /* fallthrough */
- case TRANSCODER_EDP:
- return EDP_PSR_TRANSCODER_EDP_SHIFT;
- }
-}
-
-static void psr_irq_control(struct drm_i915_private *dev_priv, u32 debug)
-{
- u32 debug_mask, mask;
- enum transcoder cpu_transcoder;
- u32 transcoders = BIT(TRANSCODER_EDP);
-
- if (INTEL_GEN(dev_priv) >= 8)
- transcoders |= BIT(TRANSCODER_A) |
- BIT(TRANSCODER_B) |
- BIT(TRANSCODER_C);
-
- debug_mask = 0;
- mask = 0;
- for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
- int shift = edp_psr_shift(cpu_transcoder);
-
- mask |= EDP_PSR_ERROR(shift);
- debug_mask |= EDP_PSR_POST_EXIT(shift) |
- EDP_PSR_PRE_ENTRY(shift);
- }
-
- if (debug & I915_PSR_DEBUG_IRQ)
- mask |= debug_mask;
-
- I915_WRITE(EDP_PSR_IMR, ~mask);
+ enum transcoder trans = dev_priv->psr.transcoder;
+ u32 val, mask;
+
+ mask = EDP_PSR_ERROR(trans);
+ if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ)
+ mask |= EDP_PSR_POST_EXIT(trans) | EDP_PSR_PRE_ENTRY(trans);
+
+ /* Warning: it is masking/setting reserved bits too */
+ val = I915_READ(EDP_PSR_IMR);
+ val &= ~EDP_PSR_TRANS_MASK(trans);
+ val |= ~mask;
+ I915_WRITE(EDP_PSR_IMR, val);
}
static void psr_event_print(u32 val, bool psr2_enabled)
@@ -171,60 +143,48 @@ static void psr_event_print(u32 val, bool psr2_enabled)
void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
{
- u32 transcoders = BIT(TRANSCODER_EDP);
- enum transcoder cpu_transcoder;
+ enum transcoder cpu_transcoder = dev_priv->psr.transcoder;
ktime_t time_ns = ktime_get();
- u32 mask = 0;
-
- if (INTEL_GEN(dev_priv) >= 8)
- transcoders |= BIT(TRANSCODER_A) |
- BIT(TRANSCODER_B) |
- BIT(TRANSCODER_C);
-
- for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
- int shift = edp_psr_shift(cpu_transcoder);
- if (psr_iir & EDP_PSR_ERROR(shift)) {
- DRM_WARN("[transcoder %s] PSR aux error\n",
- transcoder_name(cpu_transcoder));
+ if (psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder)) {
+ dev_priv->psr.last_entry_attempt = time_ns;
+ DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
+ transcoder_name(cpu_transcoder));
+ }
- dev_priv->psr.irq_aux_error = true;
+ if (psr_iir & EDP_PSR_POST_EXIT(cpu_transcoder)) {
+ dev_priv->psr.last_exit = time_ns;
+ DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
+ transcoder_name(cpu_transcoder));
- /*
- * If this interruption is not masked it will keep
- * interrupting so fast that it prevents the scheduled
- * work to run.
- * Also after a PSR error, we don't want to arm PSR
- * again so we don't care about unmask the interruption
- * or unset irq_aux_error.
- */
- mask |= EDP_PSR_ERROR(shift);
- }
+ if (INTEL_GEN(dev_priv) >= 9) {
+ u32 val = I915_READ(PSR_EVENT(cpu_transcoder));
+ bool psr2_enabled = dev_priv->psr.psr2_enabled;
- if (psr_iir & EDP_PSR_PRE_ENTRY(shift)) {
- dev_priv->psr.last_entry_attempt = time_ns;
- DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
- transcoder_name(cpu_transcoder));
+ I915_WRITE(PSR_EVENT(cpu_transcoder), val);
+ psr_event_print(val, psr2_enabled);
}
+ }
- if (psr_iir & EDP_PSR_POST_EXIT(shift)) {
- dev_priv->psr.last_exit = time_ns;
- DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
- transcoder_name(cpu_transcoder));
+ if (psr_iir & EDP_PSR_ERROR(cpu_transcoder)) {
+ u32 val;
- if (INTEL_GEN(dev_priv) >= 9) {
- u32 val = I915_READ(PSR_EVENT(cpu_transcoder));
- bool psr2_enabled = dev_priv->psr.psr2_enabled;
+ DRM_WARN("[transcoder %s] PSR aux error\n",
+ transcoder_name(cpu_transcoder));
- I915_WRITE(PSR_EVENT(cpu_transcoder), val);
- psr_event_print(val, psr2_enabled);
- }
- }
- }
+ dev_priv->psr.irq_aux_error = true;
- if (mask) {
- mask |= I915_READ(EDP_PSR_IMR);
- I915_WRITE(EDP_PSR_IMR, mask);
+ /*
+ * If this interruption is not masked it will keep
+ * interrupting so fast that it prevents the scheduled
+ * work to run.
+ * Also after a PSR error, we don't want to arm PSR
+ * again so we don't care about unmask the interruption
+ * or unset irq_aux_error.
+ */
+ val = I915_READ(EDP_PSR_IMR);
+ val |= EDP_PSR_ERROR(cpu_transcoder);
+ I915_WRITE(EDP_PSR_IMR, val);
schedule_work(&dev_priv->psr.work);
}
@@ -747,7 +707,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
I915_WRITE(EDP_PSR_DEBUG(dev_priv->psr.transcoder), mask);
- psr_irq_control(dev_priv, dev_priv->psr.debug);
+ psr_irq_control(dev_priv);
}
static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
@@ -772,7 +732,7 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
* to avoid any rendering problems.
*/
val = I915_READ(EDP_PSR_IIR);
- val &= EDP_PSR_ERROR(edp_psr_shift(dev_priv->psr.transcoder));
+ val &= EDP_PSR_ERROR(dev_priv->psr.transcoder);
if (val) {
dev_priv->psr.sink_not_reliable = true;
DRM_DEBUG_KMS("PSR interruption error set, not enabling PSR\n");
@@ -1120,7 +1080,13 @@ int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 val)
old_mode = dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK;
dev_priv->psr.debug = val;
- psr_irq_control(dev_priv, dev_priv->psr.debug);
+
+ /*
+ * Do it right away if it's already enabled, otherwise it will be done
+ * when enabling the source.
+ */
+ if (dev_priv->psr.enabled)
+ psr_irq_control(dev_priv);
mutex_unlock(&dev_priv->psr.lock);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 45ed96d7c599..81f68455d492 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4225,13 +4225,12 @@ enum {
/* Bspec claims those aren't shifted but stay at 0x64800 */
#define EDP_PSR_IMR _MMIO(0x64834)
#define EDP_PSR_IIR _MMIO(0x64838)
-#define EDP_PSR_ERROR(shift) (1 << ((shift) + 2))
-#define EDP_PSR_POST_EXIT(shift) (1 << ((shift) + 1))
-#define EDP_PSR_PRE_ENTRY(shift) (1 << (shift))
-#define EDP_PSR_TRANSCODER_C_SHIFT 24
-#define EDP_PSR_TRANSCODER_B_SHIFT 16
-#define EDP_PSR_TRANSCODER_A_SHIFT 8
-#define EDP_PSR_TRANSCODER_EDP_SHIFT 0
+#define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \
+ 0 : ((trans) - TRANSCODER_A + 1) * 8)
+#define EDP_PSR_TRANS_MASK(trans) (0x7 << _EDP_PSR_TRANS_SHIFT(trans))
+#define EDP_PSR_ERROR(trans) (0x4 << _EDP_PSR_TRANS_SHIFT(trans))
+#define EDP_PSR_POST_EXIT(trans) (0x2 << _EDP_PSR_TRANS_SHIFT(trans))
+#define EDP_PSR_PRE_ENTRY(trans) (0x1 << _EDP_PSR_TRANS_SHIFT(trans))
#define _SRD_AUX_CTL_A 0x60810
#define _SRD_AUX_CTL_EDP 0x6f810
--
2.23.0
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^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 2/6] drm/i915/tgl: Access the right register when handling PSR interruptions
2019-09-04 21:34 [PATCH 0/6] Tiger Lake batch 3.5 v2 José Roberto de Souza
2019-09-04 21:34 ` [PATCH 1/6] drm/i915/psr: Only handle interruptions of the transcoder in use José Roberto de Souza
@ 2019-09-04 21:34 ` José Roberto de Souza
2019-09-04 21:34 ` [PATCH 3/6] drm/i915: protect access to DP_TP_* on non-dp José Roberto de Souza
` (6 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: José Roberto de Souza @ 2019-09-04 21:34 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Dhinakaran Pandiyan
For older gens PSR IIR and IMR have fixed addresses. From TGL onwards those
registers moved to each transcoder offset. The bits for the registers
are defined without an offset per transcoder as right now we have one
register per transcoder. So add a fake "trans_shift" when calculating
the bits offsets: it will be 0 for gen12+ and psr.transcoder otherwise.
v2 (Lucas): change the implementation to use trans_shift instead of
getting each bit value with a different macro
Cc: Imre Deak <imre.deak@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 60 ++++++++++++++++++------
drivers/gpu/drm/i915/i915_irq.c | 51 +++++++++++++++++---
drivers/gpu/drm/i915/i915_reg.h | 10 +++-
3 files changed, 99 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 1d99ffeaa36a..b3c7eef53bf3 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -90,18 +90,33 @@ static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
static void psr_irq_control(struct drm_i915_private *dev_priv)
{
- enum transcoder trans = dev_priv->psr.transcoder;
- u32 val, mask;
+ enum transcoder trans_shift;
+ u32 mask, val;
+ i915_reg_t imr_reg;
- mask = EDP_PSR_ERROR(trans);
+ /*
+ * gen12+ has registers relative to transcoder and one per transcoder
+ * using the same bit definition: handle it as TRANSCODER_EDP to force
+ * 0 shift in bit definition
+ */
+ if (INTEL_GEN(dev_priv) >= 12) {
+ trans_shift = 0;
+ imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder);
+ } else {
+ trans_shift = dev_priv->psr.transcoder;
+ imr_reg = EDP_PSR_IMR;
+ }
+
+ mask = EDP_PSR_ERROR(trans_shift);
if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ)
- mask |= EDP_PSR_POST_EXIT(trans) | EDP_PSR_PRE_ENTRY(trans);
+ mask |= EDP_PSR_POST_EXIT(trans_shift) |
+ EDP_PSR_PRE_ENTRY(trans_shift);
/* Warning: it is masking/setting reserved bits too */
- val = I915_READ(EDP_PSR_IMR);
- val &= ~EDP_PSR_TRANS_MASK(trans);
+ val = I915_READ(imr_reg);
+ val &= ~EDP_PSR_TRANS_MASK(trans_shift);
val |= ~mask;
- I915_WRITE(EDP_PSR_IMR, val);
+ I915_WRITE(imr_reg, val);
}
static void psr_event_print(u32 val, bool psr2_enabled)
@@ -144,15 +159,25 @@ static void psr_event_print(u32 val, bool psr2_enabled)
void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
{
enum transcoder cpu_transcoder = dev_priv->psr.transcoder;
+ enum transcoder trans_shift;
+ i915_reg_t imr_reg;
ktime_t time_ns = ktime_get();
- if (psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder)) {
+ if (INTEL_GEN(dev_priv) >= 12) {
+ trans_shift = 0;
+ imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder);
+ } else {
+ trans_shift = dev_priv->psr.transcoder;
+ imr_reg = EDP_PSR_IMR;
+ }
+
+ if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) {
dev_priv->psr.last_entry_attempt = time_ns;
DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",
transcoder_name(cpu_transcoder));
}
- if (psr_iir & EDP_PSR_POST_EXIT(cpu_transcoder)) {
+ if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) {
dev_priv->psr.last_exit = time_ns;
DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",
transcoder_name(cpu_transcoder));
@@ -166,7 +191,7 @@ void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
}
}
- if (psr_iir & EDP_PSR_ERROR(cpu_transcoder)) {
+ if (psr_iir & EDP_PSR_ERROR(trans_shift)) {
u32 val;
DRM_WARN("[transcoder %s] PSR aux error\n",
@@ -182,9 +207,9 @@ void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)
* again so we don't care about unmask the interruption
* or unset irq_aux_error.
*/
- val = I915_READ(EDP_PSR_IMR);
- val |= EDP_PSR_ERROR(cpu_transcoder);
- I915_WRITE(EDP_PSR_IMR, val);
+ val = I915_READ(imr_reg);
+ val |= EDP_PSR_ERROR(trans_shift);
+ I915_WRITE(imr_reg, val);
schedule_work(&dev_priv->psr.work);
}
@@ -731,8 +756,13 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
* first time that PSR HW tries to activate so lets keep PSR disabled
* to avoid any rendering problems.
*/
- val = I915_READ(EDP_PSR_IIR);
- val &= EDP_PSR_ERROR(dev_priv->psr.transcoder);
+ if (INTEL_GEN(dev_priv) >= 12) {
+ val = I915_READ(TRANS_PSR_IIR(dev_priv->psr.transcoder));
+ val &= EDP_PSR_ERROR(0);
+ } else {
+ val = I915_READ(EDP_PSR_IIR);
+ val &= EDP_PSR_ERROR(dev_priv->psr.transcoder);
+ }
if (val) {
dev_priv->psr.sink_not_reliable = true;
DRM_DEBUG_KMS("PSR interruption error set, not enabling PSR\n");
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 135c9ee55e07..ae7228032d2c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2613,11 +2613,21 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
}
if (iir & GEN8_DE_EDP_PSR) {
- u32 psr_iir = I915_READ(EDP_PSR_IIR);
+ u32 psr_iir;
+ i915_reg_t iir_reg;
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ iir_reg = TRANS_PSR_IIR(dev_priv->psr.transcoder);
+ else
+ iir_reg = EDP_PSR_IIR;
+
+ psr_iir = I915_READ(iir_reg);
+ I915_WRITE(iir_reg, psr_iir);
+
+ if (psr_iir)
+ found = true;
intel_psr_irq_handler(dev_priv, psr_iir);
- I915_WRITE(EDP_PSR_IIR, psr_iir);
- found = true;
}
if (!found)
@@ -3233,8 +3243,23 @@ static void gen11_irq_reset(struct drm_i915_private *dev_priv)
intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);
- intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
- intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
+ if (INTEL_GEN(dev_priv) >= 12) {
+ enum transcoder trans;
+
+ for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) {
+ enum intel_display_power_domain domain;
+
+ domain = POWER_DOMAIN_TRANSCODER(trans);
+ if (!intel_display_power_is_enabled(dev_priv, domain))
+ continue;
+
+ intel_uncore_write(uncore, TRANS_PSR_IMR(trans), 0xffffffff);
+ intel_uncore_write(uncore, TRANS_PSR_IIR(trans), 0xffffffff);
+ }
+ } else {
+ intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
+ intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
+ }
for_each_pipe(dev_priv, pipe)
if (intel_display_power_is_enabled(dev_priv,
@@ -3740,7 +3765,21 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
else if (IS_BROADWELL(dev_priv))
de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
- gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
+ if (INTEL_GEN(dev_priv) >= 12) {
+ enum transcoder trans;
+
+ for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) {
+ enum intel_display_power_domain domain;
+
+ domain = POWER_DOMAIN_TRANSCODER(trans);
+ if (!intel_display_power_is_enabled(dev_priv, domain))
+ continue;
+
+ gen3_assert_iir_is_zero(uncore, TRANS_PSR_IIR(trans));
+ }
+ } else {
+ gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
+ }
for_each_pipe(dev_priv, pipe) {
dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 81f68455d492..de9e679e90bb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4222,9 +4222,17 @@ enum {
#define EDP_PSR_TP1_TIME_0us (3 << 4)
#define EDP_PSR_IDLE_FRAME_SHIFT 0
-/* Bspec claims those aren't shifted but stay at 0x64800 */
+/*
+ * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative
+ * to transcoder and bits defined for each one as if using no shift (i.e. as if
+ * it was for TRANSCODER_EDP)
+ */
#define EDP_PSR_IMR _MMIO(0x64834)
#define EDP_PSR_IIR _MMIO(0x64838)
+#define _PSR_IMR_A 0x60814
+#define _PSR_IIR_A 0x60818
+#define TRANS_PSR_IMR(tran) _MMIO_TRANS2(tran, _PSR_IMR_A)
+#define TRANS_PSR_IIR(tran) _MMIO_TRANS2(tran, _PSR_IIR_A)
#define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \
0 : ((trans) - TRANSCODER_A + 1) * 8)
#define EDP_PSR_TRANS_MASK(trans) (0x7 << _EDP_PSR_TRANS_SHIFT(trans))
--
2.23.0
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^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 3/6] drm/i915: protect access to DP_TP_* on non-dp
2019-09-04 21:34 [PATCH 0/6] Tiger Lake batch 3.5 v2 José Roberto de Souza
2019-09-04 21:34 ` [PATCH 1/6] drm/i915/psr: Only handle interruptions of the transcoder in use José Roberto de Souza
2019-09-04 21:34 ` [PATCH 2/6] drm/i915/tgl: Access the right register when handling PSR interruptions José Roberto de Souza
@ 2019-09-04 21:34 ` José Roberto de Souza
2019-09-04 21:39 ` Matt Roper
2019-09-04 21:34 ` [PATCH 4/6] drm/i915/tgl: move DP_TP_* to transcoder José Roberto de Souza
` (5 subsequent siblings)
8 siblings, 1 reply; 12+ messages in thread
From: José Roberto de Souza @ 2019-09-04 21:34 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Lucas De Marchi <lucas.demarchi@intel.com>
DP_TP_{CTL,STATUS} should only be programmed when the encoder is intel_dp.
Checking its current usages intel_disable_ddi_buf() is the only
offender, with other places being protected by checks like
pipe_config->fec_enable that is only set by intel_dp.
v3 (José):
- Using intel_crtc_has_dp_encoder() instead of intel_encoder_is_dp()
(Ville)
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 1fe0bf01e580..ec132cd6add8 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3465,10 +3465,12 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
wait = true;
}
- val = I915_READ(DP_TP_CTL(port));
- val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
- val |= DP_TP_CTL_LINK_TRAIN_PAT1;
- I915_WRITE(DP_TP_CTL(port), val);
+ if (intel_crtc_has_dp_encoder(crtc_state)) {
+ val = I915_READ(DP_TP_CTL(port));
+ val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
+ val |= DP_TP_CTL_LINK_TRAIN_PAT1;
+ I915_WRITE(DP_TP_CTL(port), val);
+ }
/* Disable FEC in DP Sink */
intel_ddi_disable_fec_state(encoder, crtc_state);
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 3/6] drm/i915: protect access to DP_TP_* on non-dp
2019-09-04 21:34 ` [PATCH 3/6] drm/i915: protect access to DP_TP_* on non-dp José Roberto de Souza
@ 2019-09-04 21:39 ` Matt Roper
0 siblings, 0 replies; 12+ messages in thread
From: Matt Roper @ 2019-09-04 21:39 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx, Lucas De Marchi
On Wed, Sep 04, 2019 at 02:34:16PM -0700, José Roberto de Souza wrote:
> From: Lucas De Marchi <lucas.demarchi@intel.com>
>
> DP_TP_{CTL,STATUS} should only be programmed when the encoder is intel_dp.
> Checking its current usages intel_disable_ddi_buf() is the only
> offender, with other places being protected by checks like
> pipe_config->fec_enable that is only set by intel_dp.
>
> v3 (José):
> - Using intel_crtc_has_dp_encoder() instead of intel_encoder_is_dp()
> (Ville)
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 1fe0bf01e580..ec132cd6add8 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3465,10 +3465,12 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
> wait = true;
> }
>
> - val = I915_READ(DP_TP_CTL(port));
> - val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
> - val |= DP_TP_CTL_LINK_TRAIN_PAT1;
> - I915_WRITE(DP_TP_CTL(port), val);
> + if (intel_crtc_has_dp_encoder(crtc_state)) {
> + val = I915_READ(DP_TP_CTL(port));
> + val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
> + val |= DP_TP_CTL_LINK_TRAIN_PAT1;
> + I915_WRITE(DP_TP_CTL(port), val);
> + }
>
> /* Disable FEC in DP Sink */
> intel_ddi_disable_fec_state(encoder, crtc_state);
> --
> 2.23.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 4/6] drm/i915/tgl: move DP_TP_* to transcoder
2019-09-04 21:34 [PATCH 0/6] Tiger Lake batch 3.5 v2 José Roberto de Souza
` (2 preceding siblings ...)
2019-09-04 21:34 ` [PATCH 3/6] drm/i915: protect access to DP_TP_* on non-dp José Roberto de Souza
@ 2019-09-04 21:34 ` José Roberto de Souza
2019-09-04 21:34 ` [PATCH 5/6] drm/i915/tgl: disable SAGV temporarily José Roberto de Souza
` (4 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: José Roberto de Souza @ 2019-09-04 21:34 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Lucas De Marchi <lucas.demarchi@intel.com>
Gen 12 onwards moves the DP_TP_* registers to be transcoder-based rather
than port-based. This adds the new register addresses and changes all
the callers to use the register saved in intel_dp->regs.*. This is
filled out when preparing to enable the port so we take into account if
we should use the transcoder or the port.
v2: reimplement by stashing the registers we want to access under
intel_dp->reg. Now they are initialized when enabling the port.
Ville suggested to store the transcoder to be used exclusively
by TGL+. After implementing I thought just storing the register directly
made it cleaner.
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 43 ++++++++++++-------
.../drm/i915/display/intel_display_types.h | 9 ++++
drivers/gpu/drm/i915/display/intel_dp.c | 13 +++---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 ++--
drivers/gpu/drm/i915/i915_reg.h | 4 ++
5 files changed, 51 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index ec132cd6add8..3e6394139964 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3167,17 +3167,18 @@ static void intel_ddi_enable_fec(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum port port = encoder->port;
+ struct intel_dp *intel_dp;
u32 val;
if (!crtc_state->fec_enable)
return;
- val = I915_READ(DP_TP_CTL(port));
+ intel_dp = enc_to_intel_dp(&encoder->base);
+ val = I915_READ(intel_dp->regs.dp_tp_ctl);
val |= DP_TP_CTL_FEC_ENABLE;
- I915_WRITE(DP_TP_CTL(port), val);
+ I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
- if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
+ if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
DP_TP_STATUS_FEC_ENABLE_LIVE, 1))
DRM_ERROR("Timed out waiting for FEC Enable Status\n");
}
@@ -3186,16 +3187,17 @@ static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum port port = encoder->port;
+ struct intel_dp *intel_dp;
u32 val;
if (!crtc_state->fec_enable)
return;
- val = I915_READ(DP_TP_CTL(port));
+ intel_dp = enc_to_intel_dp(&encoder->base);
+ val = I915_READ(intel_dp->regs.dp_tp_ctl);
val &= ~DP_TP_CTL_FEC_ENABLE;
- I915_WRITE(DP_TP_CTL(port), val);
- POSTING_READ(DP_TP_CTL(port));
+ I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
+ POSTING_READ(intel_dp->regs.dp_tp_ctl);
}
static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
@@ -3208,10 +3210,14 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
int level = intel_ddi_dp_level(intel_dp);
+ enum transcoder transcoder = crtc_state->cpu_transcoder;
intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
crtc_state->lane_count, is_mst);
+ intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
+ intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
+
/* 1.a got on intel_atomic_commit_tail() */
/* 2. */
@@ -3300,6 +3306,9 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder,
intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
crtc_state->lane_count, is_mst);
+ intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
+ intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
+
intel_edp_panel_on(intel_dp);
intel_ddi_clk_select(encoder, crtc_state);
@@ -3466,10 +3475,12 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
}
if (intel_crtc_has_dp_encoder(crtc_state)) {
- val = I915_READ(DP_TP_CTL(port));
+ struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+
+ val = I915_READ(intel_dp->regs.dp_tp_ctl);
val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
val |= DP_TP_CTL_LINK_TRAIN_PAT1;
- I915_WRITE(DP_TP_CTL(port), val);
+ I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
}
/* Disable FEC in DP Sink */
@@ -3898,7 +3909,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
u32 val;
bool wait = false;
- if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
+ if (I915_READ(intel_dp->regs.dp_tp_ctl) & DP_TP_CTL_ENABLE) {
val = I915_READ(DDI_BUF_CTL(port));
if (val & DDI_BUF_CTL_ENABLE) {
val &= ~DDI_BUF_CTL_ENABLE;
@@ -3906,11 +3917,11 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
wait = true;
}
- val = I915_READ(DP_TP_CTL(port));
+ val = I915_READ(intel_dp->regs.dp_tp_ctl);
val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
val |= DP_TP_CTL_LINK_TRAIN_PAT1;
- I915_WRITE(DP_TP_CTL(port), val);
- POSTING_READ(DP_TP_CTL(port));
+ I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
+ POSTING_READ(intel_dp->regs.dp_tp_ctl);
if (wait)
intel_wait_ddi_buf_idle(dev_priv, port);
@@ -3925,8 +3936,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
}
- I915_WRITE(DP_TP_CTL(port), val);
- POSTING_READ(DP_TP_CTL(port));
+ I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
+ POSTING_READ(intel_dp->regs.dp_tp_ctl);
intel_dp->DP |= DDI_BUF_CTL_ENABLE;
I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 61277a87dbe7..d5cc4b810d9e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1218,6 +1218,15 @@ struct intel_dp {
bool can_mst; /* this port supports mst */
bool is_mst;
int active_mst_links;
+
+ /*
+ * DP_TP_* registers may be either on port or transcoder register space.
+ */
+ struct {
+ i915_reg_t dp_tp_ctl;
+ i915_reg_t dp_tp_status;
+ } regs;
+
/* connector directly attached - won't be use for modeset in mst world */
struct intel_connector *attached_connector;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 5673ed75e428..d09133a958e1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2297,6 +2297,9 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
intel_crtc_has_type(pipe_config,
INTEL_OUTPUT_DP_MST));
+ intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
+ intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
+
/*
* There are four kinds of DP registers:
*
@@ -3253,7 +3256,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
dp_train_pat & train_pat_mask);
if (HAS_DDI(dev_priv)) {
- u32 temp = I915_READ(DP_TP_CTL(port));
+ u32 temp = I915_READ(intel_dp->regs.dp_tp_ctl);
if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
@@ -3279,7 +3282,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
break;
}
- I915_WRITE(DP_TP_CTL(port), temp);
+ I915_WRITE(intel_dp->regs.dp_tp_ctl, temp);
} else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
(HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
@@ -3980,10 +3983,10 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
if (!HAS_DDI(dev_priv))
return;
- val = I915_READ(DP_TP_CTL(port));
+ val = I915_READ(intel_dp->regs.dp_tp_ctl);
val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
val |= DP_TP_CTL_LINK_TRAIN_IDLE;
- I915_WRITE(DP_TP_CTL(port), val);
+ I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
/*
* Until TGL on PORT_A we can have only eDP in SST mode. There the only
@@ -3995,7 +3998,7 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
if (port == PORT_A && INTEL_GEN(dev_priv) < 12)
return;
- if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
+ if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
DP_TP_STATUS_IDLE_DONE, 1))
DRM_ERROR("Timed out waiting for DP idle patterns\n");
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 37366f81255b..3f9cdbaab95e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -295,7 +295,6 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
struct intel_digital_port *intel_dig_port = intel_mst->primary;
struct intel_dp *intel_dp = &intel_dig_port->dp;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum port port = intel_dig_port->base.port;
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
int ret;
@@ -326,8 +325,8 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
DRM_ERROR("failed to allocate vcpi\n");
intel_dp->active_mst_links++;
- temp = I915_READ(DP_TP_STATUS(port));
- I915_WRITE(DP_TP_STATUS(port), temp);
+ temp = I915_READ(intel_dp->regs.dp_tp_status);
+ I915_WRITE(intel_dp->regs.dp_tp_status, temp);
ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr);
@@ -342,11 +341,10 @@ static void intel_mst_enable_dp(struct intel_encoder *encoder,
struct intel_digital_port *intel_dig_port = intel_mst->primary;
struct intel_dp *intel_dp = &intel_dig_port->dp;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum port port = intel_dig_port->base.port;
DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
- if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
+ if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
DP_TP_STATUS_ACT_SENT, 1))
DRM_ERROR("Timed out waiting for ACT sent\n");
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index de9e679e90bb..006cffd56be2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9546,7 +9546,9 @@ enum skl_power_gate {
/* DisplayPort Transport Control */
#define _DP_TP_CTL_A 0x64040
#define _DP_TP_CTL_B 0x64140
+#define _TGL_DP_TP_CTL_A 0x60540
#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
+#define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A)
#define DP_TP_CTL_ENABLE (1 << 31)
#define DP_TP_CTL_FEC_ENABLE (1 << 30)
#define DP_TP_CTL_MODE_SST (0 << 27)
@@ -9566,7 +9568,9 @@ enum skl_power_gate {
/* DisplayPort Transport Status */
#define _DP_TP_STATUS_A 0x64044
#define _DP_TP_STATUS_B 0x64144
+#define _TGL_DP_TP_STATUS_A 0x60544
#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
+#define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A)
#define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28)
#define DP_TP_STATUS_IDLE_DONE (1 << 25)
#define DP_TP_STATUS_ACT_SENT (1 << 24)
--
2.23.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 5/6] drm/i915/tgl: disable SAGV temporarily
2019-09-04 21:34 [PATCH 0/6] Tiger Lake batch 3.5 v2 José Roberto de Souza
` (3 preceding siblings ...)
2019-09-04 21:34 ` [PATCH 4/6] drm/i915/tgl: move DP_TP_* to transcoder José Roberto de Souza
@ 2019-09-04 21:34 ` José Roberto de Souza
2019-09-04 21:34 ` [PATCH 6/6] drm/i915/tgl: add gen12 to stolen initialization José Roberto de Souza
` (3 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: José Roberto de Souza @ 2019-09-04 21:34 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Lucas De Marchi <lucas.demarchi@intel.com>
SAGV is not currently working for Tiger Lake. We better disable it until
the implementation is stabilized and we can enable it.
HSDES: 1409542895 2208191909
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4fa9bc83c8b4..7294fcf05323 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3654,6 +3654,10 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
static bool
intel_has_sagv(struct drm_i915_private *dev_priv)
{
+ /* HACK! */
+ if (IS_GEN(dev_priv, 12))
+ return false;
+
return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
}
--
2.23.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 6/6] drm/i915/tgl: add gen12 to stolen initialization
2019-09-04 21:34 [PATCH 0/6] Tiger Lake batch 3.5 v2 José Roberto de Souza
` (4 preceding siblings ...)
2019-09-04 21:34 ` [PATCH 5/6] drm/i915/tgl: disable SAGV temporarily José Roberto de Souza
@ 2019-09-04 21:34 ` José Roberto de Souza
2019-09-04 21:59 ` ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake batch 3.5 (rev2) Patchwork
` (2 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: José Roberto de Souza @ 2019-09-04 21:34 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Lucas De Marchi <lucas.demarchi@intel.com>
Add case for gen == 12 and add MISSING_CASE() for future gens. We were
already handling gen12 as the default, so this doesn't change the
current behavior.
BSpec: 19481 and 44980
Cc: CQ Tang <cq.tang@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index aa533b4ab5f5..7ce5259d73d6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -425,8 +425,11 @@ int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
bdw_get_stolen_reserved(dev_priv,
&reserved_base, &reserved_size);
break;
- case 11:
default:
+ MISSING_CASE(INTEL_GEN(dev_priv));
+ /* fall-through */
+ case 11:
+ case 12:
icl_get_stolen_reserved(dev_priv, &reserved_base,
&reserved_size);
break;
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake batch 3.5 (rev2)
2019-09-04 21:34 [PATCH 0/6] Tiger Lake batch 3.5 v2 José Roberto de Souza
` (5 preceding siblings ...)
2019-09-04 21:34 ` [PATCH 6/6] drm/i915/tgl: add gen12 to stolen initialization José Roberto de Souza
@ 2019-09-04 21:59 ` Patchwork
2019-09-04 22:22 ` ✓ Fi.CI.BAT: success " Patchwork
2019-09-04 23:35 ` ✓ Fi.CI.IGT: " Patchwork
8 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-09-04 21:59 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Tiger Lake batch 3.5 (rev2)
URL : https://patchwork.freedesktop.org/series/65982/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ef543edfad30 drm/i915/psr: Only handle interruptions of the transcoder in use
-:250: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'trans' - possible side-effects?
#250: FILE: drivers/gpu/drm/i915/i915_reg.h:4228:
+#define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \
+ 0 : ((trans) - TRANSCODER_A + 1) * 8)
total: 0 errors, 0 warnings, 1 checks, 202 lines checked
d22eb1bcc53a drm/i915/tgl: Access the right register when handling PSR interruptions
8c8ae5031338 drm/i915: protect access to DP_TP_* on non-dp
ea764a30c1a9 drm/i915/tgl: move DP_TP_* to transcoder
2976ddd465c0 drm/i915/tgl: disable SAGV temporarily
4a408e5fdb8e drm/i915/tgl: add gen12 to stolen initialization
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* ✓ Fi.CI.BAT: success for Tiger Lake batch 3.5 (rev2)
2019-09-04 21:34 [PATCH 0/6] Tiger Lake batch 3.5 v2 José Roberto de Souza
` (6 preceding siblings ...)
2019-09-04 21:59 ` ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake batch 3.5 (rev2) Patchwork
@ 2019-09-04 22:22 ` Patchwork
2019-09-04 23:35 ` ✓ Fi.CI.IGT: " Patchwork
8 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-09-04 22:22 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Tiger Lake batch 3.5 (rev2)
URL : https://patchwork.freedesktop.org/series/65982/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6837 -> Patchwork_14277
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14277:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_close_race@basic-process:
- {fi-tgl-u}: NOTRUN -> [DMESG-FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/fi-tgl-u/igt@gem_close_race@basic-process.html
* igt@gem_exec_suspend@basic-s3:
- {fi-tgl-u}: NOTRUN -> [FAIL][2] +19 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/fi-tgl-u/igt@gem_exec_suspend@basic-s3.html
* igt@gem_render_linear_blits@basic:
- {fi-tgl-u}: NOTRUN -> [SKIP][3] +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/fi-tgl-u/igt@gem_render_linear_blits@basic.html
Known issues
------------
Here are the changes found in Patchwork_14277 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_create@basic:
- fi-icl-u3: [PASS][4] -> [DMESG-WARN][5] ([fdo#107724])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/fi-icl-u3/igt@gem_ctx_create@basic.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/fi-icl-u3/igt@gem_ctx_create@basic.html
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [PASS][6] -> [INCOMPLETE][7] ([fdo#103927] / [fdo#111381])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [PASS][8] -> [FAIL][9] ([fdo#109483])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
- fi-kbl-7500u: [PASS][10] -> [FAIL][11] ([fdo#111096])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_flip@basic-flip-vs-dpms:
- fi-hsw-4770r: [PASS][12] -> [DMESG-WARN][13] ([fdo#105602])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/fi-hsw-4770r/igt@kms_flip@basic-flip-vs-dpms.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/fi-hsw-4770r/igt@kms_flip@basic-flip-vs-dpms.html
#### Possible fixes ####
* igt@gem_ctx_create@basic-files:
- fi-icl-u3: [INCOMPLETE][14] ([fdo#107713] / [fdo#109100]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/fi-icl-u3/igt@gem_ctx_create@basic-files.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/fi-icl-u3/igt@gem_ctx_create@basic-files.html
* igt@gem_ctx_switch@legacy-render:
- fi-apl-guc: [INCOMPLETE][16] ([fdo#103927] / [fdo#111381]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/fi-apl-guc/igt@gem_ctx_switch@legacy-render.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/fi-apl-guc/igt@gem_ctx_switch@legacy-render.html
- {fi-icl-u4}: [INCOMPLETE][18] ([fdo#107713] / [fdo#111381]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/fi-icl-u4/igt@gem_ctx_switch@legacy-render.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/fi-icl-u4/igt@gem_ctx_switch@legacy-render.html
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [DMESG-FAIL][20] ([fdo#111108]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [FAIL][22] ([fdo#103167]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111108]: https://bugs.freedesktop.org/show_bug.cgi?id=111108
[fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
Participating hosts (53 -> 44)
------------------------------
Missing (9): fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-bsw-n3050 fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6837 -> Patchwork_14277
CI-20190529: 20190529
CI_DRM_6837: 87a611a0243c69c24f5bd6a1fd3d7bfefbb00ecb @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5171: 1911564805fe454919e8a5846534a0c1ef376a33 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14277: 4a408e5fdb8ecde5871a76430d0dc699c59eb5b3 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4a408e5fdb8e drm/i915/tgl: add gen12 to stolen initialization
2976ddd465c0 drm/i915/tgl: disable SAGV temporarily
ea764a30c1a9 drm/i915/tgl: move DP_TP_* to transcoder
8c8ae5031338 drm/i915: protect access to DP_TP_* on non-dp
d22eb1bcc53a drm/i915/tgl: Access the right register when handling PSR interruptions
ef543edfad30 drm/i915/psr: Only handle interruptions of the transcoder in use
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* ✓ Fi.CI.IGT: success for Tiger Lake batch 3.5 (rev2)
2019-09-04 21:34 [PATCH 0/6] Tiger Lake batch 3.5 v2 José Roberto de Souza
` (7 preceding siblings ...)
2019-09-04 22:22 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-09-04 23:35 ` Patchwork
2019-09-05 0:13 ` Souza, Jose
8 siblings, 1 reply; 12+ messages in thread
From: Patchwork @ 2019-09-04 23:35 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Tiger Lake batch 3.5 (rev2)
URL : https://patchwork.freedesktop.org/series/65982/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6837_full -> Patchwork_14277_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_14277_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@bcs0-s3:
- shard-skl: [PASS][1] -> [INCOMPLETE][2] ([fdo#104108])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-skl10/igt@gem_ctx_isolation@bcs0-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-skl3/igt@gem_ctx_isolation@bcs0-s3.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +6 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-iclb5/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-iclb4/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_exec_suspend@basic-s4-devices:
- shard-hsw: [PASS][5] -> [FAIL][6] ([fdo#111550])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-hsw7/igt@gem_exec_suspend@basic-s4-devices.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-hsw2/igt@gem_exec_suspend@basic-s4-devices.html
* igt@i915_pm_rpm@system-suspend:
- shard-hsw: [PASS][7] -> [FAIL][8] ([fdo#111548]) +4 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-hsw5/igt@i915_pm_rpm@system-suspend.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-hsw2/igt@i915_pm_rpm@system-suspend.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +6 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-apl3/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@i915_suspend@forcewake:
- shard-snb: [PASS][11] -> [FAIL][12] ([fdo#103375]) +2 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-snb6/igt@i915_suspend@forcewake.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-snb6/igt@i915_suspend@forcewake.html
- shard-hsw: [PASS][13] -> [FAIL][14] ([fdo#103375]) +4 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-hsw5/igt@i915_suspend@forcewake.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-hsw2/igt@i915_suspend@forcewake.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [PASS][15] -> [FAIL][16] ([fdo#105363]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-skl9/igt@kms_flip@flip-vs-expired-vblank.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-skl5/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
- shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +4 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff:
- shard-skl: [PASS][19] -> [FAIL][20] ([fdo#103167])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-skl9/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-skl: [PASS][21] -> [FAIL][22] ([fdo#103166])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-skl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-skl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145] / [fdo#110403])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-iclb7/igt@kms_psr@psr2_cursor_render.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109276]) +18 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-iclb1/igt@prime_vgem@fence-wait-bsd2.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-iclb6/igt@prime_vgem@fence-wait-bsd2.html
#### Possible fixes ####
* igt@gem_eio@reset-stress:
- shard-glk: [FAIL][31] ([fdo#109661]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-glk1/igt@gem_eio@reset-stress.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-glk6/igt@gem_eio@reset-stress.html
* igt@gem_exec_schedule@independent-bsd2:
- shard-iclb: [SKIP][33] ([fdo#109276]) -> [PASS][34] +21 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-iclb3/igt@gem_exec_schedule@independent-bsd2.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-iclb2/igt@gem_exec_schedule@independent-bsd2.html
* igt@gem_exec_schedule@pi-ringfull-vebox:
- shard-apl: [FAIL][35] ([fdo#111547]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-apl6/igt@gem_exec_schedule@pi-ringfull-vebox.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-apl6/igt@gem_exec_schedule@pi-ringfull-vebox.html
* igt@gem_exec_schedule@preempt-self-bsd:
- shard-iclb: [SKIP][37] ([fdo#111325]) -> [PASS][38] +4 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-iclb1/igt@gem_exec_schedule@preempt-self-bsd.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-iclb6/igt@gem_exec_schedule@preempt-self-bsd.html
* igt@i915_suspend@sysfs-reader:
- shard-iclb: [INCOMPLETE][39] ([fdo#107713]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-iclb1/igt@i915_suspend@sysfs-reader.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-iclb6/igt@i915_suspend@sysfs-reader.html
* igt@kms_flip@dpms-vs-vblank-race:
- shard-apl: [INCOMPLETE][41] ([fdo#103927]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-apl4/igt@kms_flip@dpms-vs-vblank-race.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-apl8/igt@kms_flip@dpms-vs-vblank-race.html
* igt@kms_flip@plain-flip-fb-recreate:
- shard-skl: [FAIL][43] ([fdo#100368]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-skl4/igt@kms_flip@plain-flip-fb-recreate.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-skl6/igt@kms_flip@plain-flip-fb-recreate.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [FAIL][45] ([fdo#103167]) -> [PASS][46] +4 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-snb: [FAIL][47] ([fdo#103375]) -> [PASS][48] +2 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-snb1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-snb2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-skl: [INCOMPLETE][49] ([fdo#104108]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-skl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-skl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-apl: [DMESG-WARN][51] ([fdo#108566]) -> [PASS][52] +1 similar issue
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [FAIL][53] ([fdo#108145]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr@no_drrs:
- shard-iclb: [FAIL][55] ([fdo#108341]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-iclb1/igt@kms_psr@no_drrs.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-iclb8/igt@kms_psr@no_drrs.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [SKIP][57] ([fdo#109441]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-iclb3/igt@kms_psr@psr2_sprite_mmap_gtt.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_setmode@basic:
- shard-hsw: [FAIL][59] ([fdo#99912]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-hsw6/igt@kms_setmode@basic.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-hsw8/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-apl: [FAIL][61] ([fdo#103375]) -> [PASS][62] +3 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-apl6/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-apl6/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* igt@perf@polling:
- shard-skl: [FAIL][63] ([fdo#110728]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-skl9/igt@perf@polling.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-skl5/igt@perf@polling.html
* igt@perf_pmu@enable-race-vecs0:
- shard-apl: [TIMEOUT][65] ([fdo#111545]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-apl6/igt@perf_pmu@enable-race-vecs0.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-apl6/igt@perf_pmu@enable-race-vecs0.html
* igt@perf_pmu@init-wait-rcs0:
- shard-apl: [FAIL][67] ([fdo#111545]) -> [PASS][68] +7 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-apl6/igt@perf_pmu@init-wait-rcs0.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-apl6/igt@perf_pmu@init-wait-rcs0.html
* igt@prime_busy@hang-vebox:
- shard-hsw: [INCOMPLETE][69] ([fdo#103540]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-hsw5/igt@prime_busy@hang-vebox.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-hsw4/igt@prime_busy@hang-vebox.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-settings-bsd2:
- shard-iclb: [FAIL][71] ([fdo#111330]) -> [SKIP][72] ([fdo#109276]) +2 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-iclb1/igt@gem_mocs_settings@mocs-settings-bsd2.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-iclb8/igt@gem_mocs_settings@mocs-settings-bsd2.html
* igt@gem_softpin@noreloc-s3:
- shard-skl: [INCOMPLETE][73] ([fdo#104108]) -> [INCOMPLETE][74] ([fdo#104108] / [fdo#107773])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-skl6/igt@gem_softpin@noreloc-s3.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-skl8/igt@gem_softpin@noreloc-s3.html
* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- shard-hsw: [SKIP][75] ([fdo#109271]) -> [FAIL][76] ([fdo#111548])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-hsw6/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-hsw2/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [DMESG-WARN][77] ([fdo#107724]) -> [SKIP][78] ([fdo#109349])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-iclb7/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@perf_pmu@cpu-hotplug:
- shard-hsw: [INCOMPLETE][79] ([fdo#103540]) -> [TIMEOUT][80] ([fdo#111546])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6837/shard-hsw4/igt@perf_pmu@cpu-hotplug.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/shard-hsw2/igt@perf_pmu@cpu-hotplug.html
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[fdo#111545]: https://bugs.freedesktop.org/show_bug.cgi?id=111545
[fdo#111546]: https://bugs.freedesktop.org/show_bug.cgi?id=111546
[fdo#111547]: https://bugs.freedesktop.org/show_bug.cgi?id=111547
[fdo#111548]: https://bugs.freedesktop.org/show_bug.cgi?id=111548
[fdo#111550]: https://bugs.freedesktop.org/show_bug.cgi?id=111550
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6837 -> Patchwork_14277
CI-20190529: 20190529
CI_DRM_6837: 87a611a0243c69c24f5bd6a1fd3d7bfefbb00ecb @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5171: 1911564805fe454919e8a5846534a0c1ef376a33 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14277: 4a408e5fdb8ecde5871a76430d0dc699c59eb5b3 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14277/
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Intel-gfx@lists.freedesktop.org
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