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From: Vignesh Raghavendra <vigneshr@ti.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/2] spi-nor: spi-nor-ids: Merge "n25q512a" and "mt25qu512a" entries
Date: Tue, 10 Sep 2019 22:36:20 +0530	[thread overview]
Message-ID: <20190910170621.2064-1-vigneshr@ti.com> (raw)

mt25qu512a is just a rebranded name for n25q512a. All the 6 bytes of JEDEC
ID bytes are same for mt25qu512a and n25q512a.
Commit 8385520f2931 ("mtd: spi: Add flash property for Micron mt25qu512a")
added new entry for mt25qu512a before n25q512a entry. So on older boards
with n25q512a "sf probe" now shows flash name as mt25qu512a. This creates
confusion with users who used to seeing n25q512a and are not aware of
the fact that both flashes are the same. Therefore fix this by renaming
name to "mt25qu512a (n25q512a)" so as to make it clear that flash
detected may be either of them.

With that we can have single entry for n25q512a and mt25qu512a.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
 drivers/mtd/spi/spi-nor-ids.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index a3920ba520e0..f32a6c7d464b 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -163,9 +163,7 @@ const struct flash_info spi_nor_ids[] = {
 	{ INFO("n25q128a13",  0x20ba18, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_QUAD_READ) },
 	{ INFO("n25q256a",    0x20ba19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
 	{ INFO("n25q256ax1",  0x20bb19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
-	{ INFO6("mt25qu512a",  0x20bb20, 0x104400, 64 * 1024, 1024,
-		 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
-	{ INFO("n25q512a",    0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mt25qu512a (n25q512a)",    0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
 	{ INFO("n25q512ax3",  0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
 	{ INFO("n25q00",      0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 	{ INFO("n25q00a",     0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
-- 
2.23.0

             reply	other threads:[~2019-09-10 17:06 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-10 17:06 Vignesh Raghavendra [this message]
2019-09-10 17:06 ` [U-Boot] [PATCH 2/2] spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256* Vignesh Raghavendra
2019-09-10 19:18   ` Simon Goldschmidt
2019-09-11  8:49   ` [U-Boot] [EXT] " Ashish Kumar
2019-09-11  9:41     ` Simon Goldschmidt
2019-09-11 10:07       ` Vignesh Raghavendra
2019-09-23  9:07         ` Ashish Kumar
2019-09-23 10:37           ` Vignesh Raghavendra
2019-09-23  9:30         ` Simon Goldschmidt
2019-09-23  9:38           ` Tudor.Ambarus at microchip.com
2019-09-23 10:49             ` Simon Goldschmidt
2019-09-24  9:26               ` Simon Goldschmidt
2019-09-24 11:36           ` Tudor.Ambarus at microchip.com
2019-09-24 11:45             ` Simon Goldschmidt
2019-09-24 11:53               ` Vignesh Raghavendra
2019-09-24 12:08                 ` Simon Goldschmidt
2019-09-25 11:07                   ` Simon Goldschmidt
2019-09-25 11:24                     ` Vignesh Raghavendra

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