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From: Vignesh Raghavendra <vigneshr@ti.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [EXT] [PATCH 2/2] spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256*
Date: Tue, 24 Sep 2019 17:23:59 +0530	[thread overview]
Message-ID: <b3de969f-9109-b377-8875-f9a72b46b1f5@ti.com> (raw)
In-Reply-To: <CAAh8qsyzxdobNzJAbGiqbH1cWOA7zVK7aR5WMfnLmpkdkuA=bw@mail.gmail.com>

Simon,

On 24-Sep-19 5:15 PM, Simon Goldschmidt wrote:
> Hi Tudor,
> 
> On Tue, Sep 24, 2019 at 1:36 PM <Tudor.Ambarus@microchip.com> wrote:
>>
[...]

>>>>
>>>> Simon,
>>>> Could you provide dump of SFDP tables and all the 6 bytes READ ID of the
>>>> flash that you have?
>>>
>>> I have a n251256a with JEDEC ID 20, ba, 19, 10, 44, 00.
>>
>> Is this a n25q256a or a MT25QL256ABA? We want to check if there are n25q256a
>> flashes that have the 6th bit of the Extended Device Id set to one or not.
>> According to n25q256a datasheet the bit 6 is reserved (which probably translates
>> to being zero), while on MT25QL256ABA is set to one.
> 
> Right, this really is a MT25QL256ABA, I guess. I'm not quite familiar with the
> print on the housing, sorry. We had both and here, it's probably the MT, not
> the nq.
> 

But, do you have access to n25q variants? And does that support 4 Byte
addressing opcode? What does its JEDEC ID read?

> I also wasn't really aware of the differences between those two, sorry.
> 
> Regards,
> Simon
> 
>>
>> Cheers,
>> ta
>>

  reply	other threads:[~2019-09-24 11:53 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-10 17:06 [U-Boot] [PATCH 1/2] spi-nor: spi-nor-ids: Merge "n25q512a" and "mt25qu512a" entries Vignesh Raghavendra
2019-09-10 17:06 ` [U-Boot] [PATCH 2/2] spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256* Vignesh Raghavendra
2019-09-10 19:18   ` Simon Goldschmidt
2019-09-11  8:49   ` [U-Boot] [EXT] " Ashish Kumar
2019-09-11  9:41     ` Simon Goldschmidt
2019-09-11 10:07       ` Vignesh Raghavendra
2019-09-23  9:07         ` Ashish Kumar
2019-09-23 10:37           ` Vignesh Raghavendra
2019-09-23  9:30         ` Simon Goldschmidt
2019-09-23  9:38           ` Tudor.Ambarus at microchip.com
2019-09-23 10:49             ` Simon Goldschmidt
2019-09-24  9:26               ` Simon Goldschmidt
2019-09-24 11:36           ` Tudor.Ambarus at microchip.com
2019-09-24 11:45             ` Simon Goldschmidt
2019-09-24 11:53               ` Vignesh Raghavendra [this message]
2019-09-24 12:08                 ` Simon Goldschmidt
2019-09-25 11:07                   ` Simon Goldschmidt
2019-09-25 11:24                     ` Vignesh Raghavendra

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