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From: "Cédric Le Goater" <clg@kaod.org>
To: David Gibson <david@gibson.dropbear.id.au>
Cc: "Cédric Le Goater" <clg@kaod.org>,
	qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
	"Greg Kurz" <groug@kaod.org>
Subject: [Qemu-devel] [PATCH v4 01/25] ppc/xive: Introduce a XivePresenter interface
Date: Wed, 18 Sep 2019 18:06:21 +0200	[thread overview]
Message-ID: <20190918160645.25126-2-clg@kaod.org> (raw)
In-Reply-To: <20190918160645.25126-1-clg@kaod.org>

When the XIVE IVRE sub-engine (XiveRouter) looks for a Notification
Virtual Target (NVT) to notify, it broadcasts a message on the
PowerBUS to find an XIVE IVPE sub-engine (Presenter) with the NVT
dispatched on one of its HW threads, and then forwards the
notification if any response was received.

The current XIVE presenter model is sufficient for the pseries machine
because it has a single interrupt controller device, but the PowerNV
machine can have multiple chips each having its own interrupt
controller. In this case, the XIVE presenter model is too simple and
the CAM line matching should scan all chips of the system.

To start fixing this issue, we first extend the XIVE Router model with
a new XivePresenter QOM interface representing the XIVE IVPE
sub-engine. This interface exposes a 'match_nvt' handler which the
sPAPR and PowerNV XIVE Router models will need to implement to perform
the CAM line matching.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/ppc/xive.h | 32 ++++++++++++++++++++++++++++++++
 hw/intc/xive.c        | 26 +++++++++++++++++---------
 2 files changed, 49 insertions(+), 9 deletions(-)

diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index 6d38755f8459..39de45b87cb9 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -367,6 +367,38 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
 XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs);
 void xive_router_notify(XiveNotifier *xn, uint32_t lisn);
 
+/*
+ * XIVE Presenter
+ */
+
+typedef struct XiveTCTXMatch {
+    XiveTCTX *tctx;
+    uint8_t ring;
+} XiveTCTXMatch;
+
+typedef struct XivePresenter XivePresenter;
+
+#define TYPE_XIVE_PRESENTER "xive-presenter"
+#define XIVE_PRESENTER(obj)                                     \
+    INTERFACE_CHECK(XivePresenter, (obj), TYPE_XIVE_PRESENTER)
+#define XIVE_PRESENTER_CLASS(klass)                                     \
+    OBJECT_CLASS_CHECK(XivePresenterClass, (klass), TYPE_XIVE_PRESENTER)
+#define XIVE_PRESENTER_GET_CLASS(obj)                                   \
+    OBJECT_GET_CLASS(XivePresenterClass, (obj), TYPE_XIVE_PRESENTER)
+
+typedef struct XivePresenterClass {
+    InterfaceClass parent;
+    int (*match_nvt)(XivePresenter *xptr, uint8_t format,
+                     uint8_t nvt_blk, uint32_t nvt_idx,
+                     bool cam_ignore, uint8_t priority,
+                     uint32_t logic_serv, XiveTCTXMatch *match);
+} XivePresenterClass;
+
+int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
+                              uint8_t format,
+                              uint8_t nvt_blk, uint32_t nvt_idx,
+                              bool cam_ignore, uint32_t logic_serv);
+
 /*
  * XIVE END ESBs
  */
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index b7417210d817..aa45ac2e06cb 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1316,9 +1316,10 @@ static uint32_t xive_tctx_hw_cam_line(XiveTCTX *tctx)
 /*
  * The thread context register words are in big-endian format.
  */
-static int xive_presenter_tctx_match(XiveTCTX *tctx, uint8_t format,
-                                     uint8_t nvt_blk, uint32_t nvt_idx,
-                                     bool cam_ignore, uint32_t logic_serv)
+int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
+                              uint8_t format,
+                              uint8_t nvt_blk, uint32_t nvt_idx,
+                              bool cam_ignore, uint32_t logic_serv)
 {
     uint32_t cam = xive_nvt_cam_line(nvt_blk, nvt_idx);
     uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]);
@@ -1375,11 +1376,6 @@ static int xive_presenter_tctx_match(XiveTCTX *tctx, uint8_t format,
     return -1;
 }
 
-typedef struct XiveTCTXMatch {
-    XiveTCTX *tctx;
-    uint8_t ring;
-} XiveTCTXMatch;
-
 static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format,
                                  uint8_t nvt_blk, uint32_t nvt_idx,
                                  bool cam_ignore, uint8_t priority,
@@ -1405,7 +1401,8 @@ static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format,
          * Check the thread context CAM lines and record matches. We
          * will handle CPU exception delivery later
          */
-        ring = xive_presenter_tctx_match(tctx, format, nvt_blk, nvt_idx,
+        ring = xive_presenter_tctx_match(XIVE_PRESENTER(xrtr), tctx, format,
+                                         nvt_blk, nvt_idx,
                                          cam_ignore, logic_serv);
         /*
          * Save the context and follow on to catch duplicates, that we
@@ -1692,6 +1689,7 @@ static const TypeInfo xive_router_info = {
     .class_init    = xive_router_class_init,
     .interfaces    = (InterfaceInfo[]) {
         { TYPE_XIVE_NOTIFIER },
+        { TYPE_XIVE_PRESENTER },
         { }
     }
 };
@@ -1863,10 +1861,20 @@ static const TypeInfo xive_notifier_info = {
     .class_size = sizeof(XiveNotifierClass),
 };
 
+/*
+ * XIVE Presenter
+ */
+static const TypeInfo xive_presenter_info = {
+    .name = TYPE_XIVE_PRESENTER,
+    .parent = TYPE_INTERFACE,
+    .class_size = sizeof(XivePresenterClass),
+};
+
 static void xive_register_types(void)
 {
     type_register_static(&xive_source_info);
     type_register_static(&xive_notifier_info);
+    type_register_static(&xive_presenter_info);
     type_register_static(&xive_router_info);
     type_register_static(&xive_end_source_info);
     type_register_static(&xive_tctx_info);
-- 
2.21.0



  reply	other threads:[~2019-09-18 17:16 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-18 16:06 [Qemu-devel] [PATCH v4 00/25] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
2019-09-18 16:06 ` Cédric Le Goater [this message]
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 02/25] ppc/xive: Implement the XivePresenter interface Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 03/25] ppc/pnv: Introduce a PNV_CHIP_CPU_FOREACH() helper Cédric Le Goater
2019-10-03  1:50   ` David Gibson
2019-10-03  9:42     ` Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 04/25] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper Cédric Le Goater
2019-10-03  1:51   ` David Gibson
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 05/25] ppc/xive: Introduce a XiveFabric interface Cédric Le Goater
2019-10-03  1:54   ` David Gibson
2019-10-03  9:46     ` Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 06/25] ppc/pnv: Implement the " Cédric Le Goater
2019-10-03  1:55   ` David Gibson
2019-10-03  9:47     ` Cédric Le Goater
2019-10-04  9:05   ` Greg Kurz
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 07/25] ppc/spapr: " Cédric Le Goater
2019-10-03  1:58   ` David Gibson
2019-10-03  9:50     ` Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 08/25] ppc/xive: Use the XiveFabric and XivePresenter interfaces Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 09/25] ppc/xive: Extend the TIMA operation with a XivePresenter parameter Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 10/25] ppc/pnv: Clarify how the TIMA is accessed on a multichip system Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 11/25] ppc/xive: Move the TIMA operations to the controller model Cédric Le Goater
2019-10-03  2:08   ` David Gibson
2019-10-03 10:57     ` Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 12/25] ppc/xive: Remove the get_tctx() XiveRouter handler Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 13/25] ppc/xive: Introduce a xive_tctx_ipb_update() helper Cédric Le Goater
2019-10-03  2:11   ` David Gibson
2019-10-03  9:30     ` Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 14/25] ppc/xive: Introduce helpers for the NVT id Cédric Le Goater
2019-10-03  2:12   ` David Gibson
2019-10-03  9:23     ` Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 15/25] ppc/xive: Synthesize interrupt from the saved IPB in the NVT Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 16/25] ppc/pnv: Remove pnv_xive_vst_size() routine Cédric Le Goater
2019-10-03  2:20   ` David Gibson
2019-10-03  9:12     ` Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 17/25] ppc/pnv: Dump the XIVE NVT table Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 18/25] ppc/pnv: Skip empty slots of " Cédric Le Goater
2019-10-03  2:22   ` David Gibson
2019-10-03  8:46     ` Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 19/25] ppc/pnv: Introduce a pnv_xive_block_id() helper Cédric Le Goater
2019-10-03  2:25   ` David Gibson
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 20/25] ppc/pnv: Extend XiveRouter with a get_block_id() handler Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 21/25] ppc/pnv: Quiesce some XIVE errors Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 22/25] ppc/xive: Introduce a xive_os_cam_decode() helper Cédric Le Goater
2019-10-03  2:34   ` David Gibson
2019-10-03  8:39     ` Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 23/25] ppc/xive: Check V bit in TM_PULL_POOL_CTX Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 24/25] ppc/pnv: Improve trigger data definition Cédric Le Goater
2019-10-03  2:41   ` David Gibson
2019-10-03  8:30     ` Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 25/25] ppc/pnv: Use the EAS trigger bit when triggering an interrupt from PSI Cédric Le Goater

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