All of lore.kernel.org
 help / color / mirror / Atom feed
From: Greg Kurz <groug@kaod.org>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
	David Gibson <david@gibson.dropbear.id.au>
Subject: Re: [PATCH v4 06/25] ppc/pnv: Implement the XiveFabric interface
Date: Fri, 4 Oct 2019 11:05:15 +0200	[thread overview]
Message-ID: <20191004110515.0896565c@bahia.lan> (raw)
In-Reply-To: <20190918160645.25126-7-clg@kaod.org>

On Wed, 18 Sep 2019 18:06:26 +0200
Cédric Le Goater <clg@kaod.org> wrote:

> The CAM line matching on the PowerNV machine now scans all chips of
> the system and all CPUs of a chip to find a dispatched NVT in the
> thread contexts.
> 
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
>  hw/ppc/pnv.c | 32 ++++++++++++++++++++++++++++++++
>  1 file changed, 32 insertions(+)
> 
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 77a86c6a2301..ca24dd62df23 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -1378,6 +1378,35 @@ static void pnv_pic_print_info(InterruptStatsProvider *obj,
>      }
>  }
>  
> +static int pnv_xive_match_nvt(XiveFabric *xfb, uint8_t format,
> +                               uint8_t nvt_blk, uint32_t nvt_idx,
> +                               bool cam_ignore, uint8_t priority,
> +                               uint32_t logic_serv,
> +                               XiveTCTXMatch *match)

Hmm, patch 2 already introduces a function with the same name:

--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -392,6 +392,45 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t blk, uint32_t idx,
     return pnv_xive_vst_read(xive, VST_TSEL_IVT, blk, idx, eas);
 }
 
+static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format,
+                              uint8_t nvt_blk, uint32_t nvt_idx,
+                              bool cam_ignore, uint8_t priority,
+                              uint32_t logic_serv, XiveTCTXMatch *match)
+{

This is valid because both are static functions in different compilation
units, but it usually better to avoid naming collisions (for an easier
gdb experience for example).

Anyway, I guess this isn't a problem if we reparent TM contexts to the
XIVE router, since we wouldn't need patches 1 to 3 anymore if I get it
right.

> +{
> +    PnvMachineState *pnv = PNV_MACHINE(xfb);
> +    int total_count = 0;
> +    int i;
> +
> +    for (i = 0; i < pnv->num_chips; i++) {
> +        Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]);
> +        XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive);
> +        XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
> +        int count;
> +
> +        count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
> +                               priority, logic_serv, match);
> +
> +        if (count < 0) {
> +            return count;
> +        }
> +
> +        total_count += count;
> +    }
> +
> +    return total_count;
> +}
> +
>  static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name,
>                                void *opaque, Error **errp)
>  {
> @@ -1441,9 +1470,11 @@ static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
>  static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
>  {
>      MachineClass *mc = MACHINE_CLASS(oc);
> +    XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
>  
>      mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
>      mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
> +    xfc->match_nvt = pnv_xive_match_nvt;
>  
>      mc->alias = "powernv";
>  }
> @@ -1495,6 +1526,7 @@ static void pnv_machine_class_init(ObjectClass *oc, void *data)
>          .interfaces = (InterfaceInfo[]) {               \
>              { TYPE_XICS_FABRIC },                       \
>              { TYPE_INTERRUPT_STATS_PROVIDER },          \
> +            { TYPE_XIVE_FABRIC },                       \
>              { },                                        \
>          },                                              \
>      }



  parent reply	other threads:[~2019-10-04  9:06 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-18 16:06 [Qemu-devel] [PATCH v4 00/25] ppc/pnv: add XIVE support for KVM guests Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 01/25] ppc/xive: Introduce a XivePresenter interface Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 02/25] ppc/xive: Implement the " Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 03/25] ppc/pnv: Introduce a PNV_CHIP_CPU_FOREACH() helper Cédric Le Goater
2019-10-03  1:50   ` David Gibson
2019-10-03  9:42     ` Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 04/25] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper Cédric Le Goater
2019-10-03  1:51   ` David Gibson
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 05/25] ppc/xive: Introduce a XiveFabric interface Cédric Le Goater
2019-10-03  1:54   ` David Gibson
2019-10-03  9:46     ` Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 06/25] ppc/pnv: Implement the " Cédric Le Goater
2019-10-03  1:55   ` David Gibson
2019-10-03  9:47     ` Cédric Le Goater
2019-10-04  9:05   ` Greg Kurz [this message]
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 07/25] ppc/spapr: " Cédric Le Goater
2019-10-03  1:58   ` David Gibson
2019-10-03  9:50     ` Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 08/25] ppc/xive: Use the XiveFabric and XivePresenter interfaces Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 09/25] ppc/xive: Extend the TIMA operation with a XivePresenter parameter Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 10/25] ppc/pnv: Clarify how the TIMA is accessed on a multichip system Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 11/25] ppc/xive: Move the TIMA operations to the controller model Cédric Le Goater
2019-10-03  2:08   ` David Gibson
2019-10-03 10:57     ` Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 12/25] ppc/xive: Remove the get_tctx() XiveRouter handler Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 13/25] ppc/xive: Introduce a xive_tctx_ipb_update() helper Cédric Le Goater
2019-10-03  2:11   ` David Gibson
2019-10-03  9:30     ` Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 14/25] ppc/xive: Introduce helpers for the NVT id Cédric Le Goater
2019-10-03  2:12   ` David Gibson
2019-10-03  9:23     ` Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 15/25] ppc/xive: Synthesize interrupt from the saved IPB in the NVT Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 16/25] ppc/pnv: Remove pnv_xive_vst_size() routine Cédric Le Goater
2019-10-03  2:20   ` David Gibson
2019-10-03  9:12     ` Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 17/25] ppc/pnv: Dump the XIVE NVT table Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 18/25] ppc/pnv: Skip empty slots of " Cédric Le Goater
2019-10-03  2:22   ` David Gibson
2019-10-03  8:46     ` Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 19/25] ppc/pnv: Introduce a pnv_xive_block_id() helper Cédric Le Goater
2019-10-03  2:25   ` David Gibson
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 20/25] ppc/pnv: Extend XiveRouter with a get_block_id() handler Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 21/25] ppc/pnv: Quiesce some XIVE errors Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 22/25] ppc/xive: Introduce a xive_os_cam_decode() helper Cédric Le Goater
2019-10-03  2:34   ` David Gibson
2019-10-03  8:39     ` Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 23/25] ppc/xive: Check V bit in TM_PULL_POOL_CTX Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 24/25] ppc/pnv: Improve trigger data definition Cédric Le Goater
2019-10-03  2:41   ` David Gibson
2019-10-03  8:30     ` Cédric Le Goater
2019-09-18 16:06 ` [Qemu-devel] [PATCH v4 25/25] ppc/pnv: Use the EAS trigger bit when triggering an interrupt from PSI Cédric Le Goater

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20191004110515.0896565c@bahia.lan \
    --to=groug@kaod.org \
    --cc=clg@kaod.org \
    --cc=david@gibson.dropbear.id.au \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.