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From: Vignesh Raghavendra <vigneshr@ti.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH RFT 1/3] spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256*
Date: Tue, 24 Sep 2019 11:26:15 +0530	[thread overview]
Message-ID: <20190924055617.20397-2-vigneshr@ti.com> (raw)
In-Reply-To: <20190924055617.20397-1-vigneshr@ti.com>

Older variants of n25q256* and n25q512* do not support 4 Byte stateless
addressing opcodes. Therefore drop SPI_NOR_4B_OPCODES flag from these
entries.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
 drivers/mtd/spi/spi-nor-ids.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index a3920ba520e0..6f7386db4226 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -161,12 +161,12 @@ const struct flash_info spi_nor_ids[] = {
 	{ INFO("n25q064a",    0x20bb17, 0, 64 * 1024,  128, SECT_4K | SPI_NOR_QUAD_READ) },
 	{ INFO("n25q128a11",  0x20bb18, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_QUAD_READ) },
 	{ INFO("n25q128a13",  0x20ba18, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_QUAD_READ) },
-	{ INFO("n25q256a",    0x20ba19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
-	{ INFO("n25q256ax1",  0x20bb19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("n25q256a",    0x20ba19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ INFO("n25q256ax1",  0x20bb19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ) },
 	{ INFO6("mt25qu512a",  0x20bb20, 0x104400, 64 * 1024, 1024,
 		 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
-	{ INFO("n25q512a",    0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
-	{ INFO("n25q512ax3",  0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("n25q512a",    0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
+	{ INFO("n25q512ax3",  0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
 	{ INFO("n25q00",      0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 	{ INFO("n25q00a",     0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 	{ INFO("mt25qu02g",   0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
-- 
2.23.0

  reply	other threads:[~2019-09-24  5:56 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-24  5:56 [U-Boot] [PATCH RFT 0/3] spi-nor: spi-nor-ids: Fix 4 Byte addressing for n25q256 and n25q512* Vignesh Raghavendra
2019-09-24  5:56 ` Vignesh Raghavendra [this message]
2019-09-24  5:56 ` [U-Boot] [PATCH RFT 2/3] spi-nor: spi-nor-ids: Rename mt25qu512a entry Vignesh Raghavendra
2019-09-24  5:56 ` [U-Boot] [PATCH RFT 3/3] spi-nor: spi-nor-ids: Add entries for newer variants of n25q256* and n25q512* Vignesh Raghavendra
2019-09-24 11:47   ` Simon Goldschmidt
2019-09-24 11:49     ` Simon Goldschmidt
2019-09-24 12:24     ` Tudor.Ambarus at microchip.com
2019-09-25  8:21       ` Vignesh Raghavendra
2019-09-25  8:27         ` Simon Goldschmidt
2019-09-25  9:09           ` Vignesh Raghavendra
2019-09-24  7:02 ` [U-Boot] [PATCH RFT 0/3] spi-nor: spi-nor-ids: Fix 4 Byte addressing for n25q256 " Simon Goldschmidt
2019-09-24  8:00   ` Vignesh Raghavendra
2019-09-24  8:43     ` Simon Goldschmidt
2019-09-24  9:17       ` Vignesh Raghavendra
2019-09-24  9:23         ` Simon Goldschmidt
2019-09-24  9:23   ` Tudor.Ambarus at microchip.com
2019-09-24  9:27     ` Simon Goldschmidt
2019-09-24 17:23 ` Eugeniy Paltsev
2019-09-25  8:11   ` Vignesh Raghavendra
2019-10-07 14:46     ` Eugeniy Paltsev
2019-10-09 11:48       ` Vignesh Raghavendra

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